Lines Matching +full:3 +full:gbps
261 /* 3 tries is assumed to be enough to read successfully */ in __intel_cx0_read()
262 for (i = 0; i < 3; i++) { in __intel_cx0_read()
352 /* 3 tries is assumed to be enough to write successfully */ in __intel_cx0_write()
353 for (i = 0; i < 3; i++) { in __intel_cx0_write()
480 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CMN(3), in intel_cx0_phy_set_signal_levels()
539 .pll[3] = 0x1,
565 .pll[3] = 0x1,
591 .pll[3] = 0x1,
617 .pll[3] = 0x0,
643 .pll[3] = 0x1,
669 .pll[3] = 0x1,
695 .pll[3] = 0,
721 .pll[3] = 0x1,
747 .pll[3] = 0x1,
890 .clock = 1000000, /* 10 Gbps */
914 .clock = 1350000, /* 13.5 Gbps */
939 .clock = 2000000, /* 20 Gbps */
1116 .clock = 1350000, /* 13.5 Gbps */
1177 .pll[3] = 0,
1203 .pll[3] = 0,
1229 .pll[3] = 0,
1255 .pll[3] = 0,
1281 .pll[3] = 0,
1305 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1315 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] = 0x00,
1325 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] = 0x00,
1335 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] = 0x00,
1345 .pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] = 0x00,
1355 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1365 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1375 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] = 0x00,
1385 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] = 0x00,
1395 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1405 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] = 0x00,
1415 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] = 0x00,
1425 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1435 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] = 0x00,
1445 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] = 0x00,
1455 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] = 0x00,
1465 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] = 0x00,
1475 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] = 0x00,
1485 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1495 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1505 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] = 0x00,
1515 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] = 0x00,
1525 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] = 0x00,
1535 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] = 0x00,
1545 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1555 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] = 0x00,
1565 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] = 0x00,
1575 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] = 0x00,
1585 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1595 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1605 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] = 0x00,
1615 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] = 0x00,
1625 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] = 0x00,
1635 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00,
1645 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1655 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1665 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1675 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] = 0x00,
1685 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1695 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
2182 multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 | in intel_c10pll_dump_hw_state()
2197 i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]); in intel_c10pll_dump_hw_state()
2229 tx_misc = 3; in intel_c20_hdmi_tmds_tx_cgf_1()
2285 pll_state->cmn[3] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2294 pll_state->mpllb[3] = (V2I(V2I_2) | in intel_c20_compute_hdmi_tmds_pll()
2503 "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2504 hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); in intel_c20pll_dump_hw_state()
2529 case 162000: /* 1.62 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2531 case 270000: /* 2.7 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2533 case 540000: /* 5.4 Gbps DP 1.4 */ in intel_c20_get_dp_rate()
2535 case 810000: /* 8.1 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2536 return 3; in intel_c20_get_dp_rate()
2537 case 216000: /* 2.16 Gbps eDP */ in intel_c20_get_dp_rate()
2539 case 243000: /* 2.43 Gbps eDP */ in intel_c20_get_dp_rate()
2541 case 324000: /* 3.24 Gbps eDP */ in intel_c20_get_dp_rate()
2543 case 432000: /* 4.32 Gbps eDP */ in intel_c20_get_dp_rate()
2545 case 1000000: /* 10 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2547 case 1350000: /* 13.5 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2549 case 2000000: /* 20 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2551 case 648000: /* 6.48 Gbps eDP*/ in intel_c20_get_dp_rate()
2553 case 675000: /* 6.75 Gbps eDP*/ in intel_c20_get_dp_rate()
2567 case 300000: /* 3 Gbps */ in intel_c20_get_hdmi_rate()
2568 case 600000: /* 6 Gbps */ in intel_c20_get_hdmi_rate()
2569 case 1200000: /* 12 Gbps */ in intel_c20_get_hdmi_rate()
2571 case 800000: /* 8 Gbps */ in intel_c20_get_hdmi_rate()
2573 case 1000000: /* 10 Gbps */ in intel_c20_get_hdmi_rate()
2574 return 3; in intel_c20_get_hdmi_rate()
2593 case 300000: /* 3 Gbps */ in is_hdmi_frl()
2594 case 600000: /* 6 Gbps */ in is_hdmi_frl()
2595 case 800000: /* 8 Gbps */ in is_hdmi_frl()
2596 case 1000000: /* 10 Gbps */ in is_hdmi_frl()
2597 case 1200000: /* 12 Gbps */ in is_hdmi_frl()
2646 /* 3. Write SRAM configuration context. If A in use, write configuration to B context */ in intel_c20_pll_program()
2740 multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 | in intel_c10pll_calc_port_clock()
2960 disables = REG_GENMASK8(3, 0) >> lane_count; in intel_cx0_program_phy_lane()
2962 disables = REG_GENMASK8(3, 0) << lane_count; in intel_cx0_program_phy_lane()
3033 * 3. Change Phy power state to Ready. in __intel_cx0pll_enable()
3190 * 3. Follow the Display Voltage Frequency Switching - Sequence in intel_mtl_tbt_pll_enable()
3303 * 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK> in intel_cx0pll_disable()
3364 /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */ in intel_mtl_tbt_pll_disable()