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/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
46 #define MT_TX_FREE_PAIR BIT(31)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
56 #define MT_TXD1_TGID BIT(30)
57 #define MT_TXD1_OWN_MAC GENMASK(29, 24)
58 #define MT_TXD1_AMSDU BIT(23)
63 #define MT_TXD1_ETH_802_3 BIT(15)
64 #define MT_TXD1_VTA BIT(10)
67 #define MT_TXD2_FIX_RATE BIT(31)
68 #define MT_TXD2_FIXED_RATE BIT(30)
[all …]
H A Dmt76_connac3_mac.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_RXD0_MESH BIT(18)
29 #define MT_RXD0_MHCP BIT(19)
38 #define MT_RXD1_NORMAL_GROUP_1 BIT(16)
39 #define MT_RXD1_NORMAL_GROUP_2 BIT(17)
40 #define MT_RXD1_NORMAL_GROUP_3 BIT(18)
41 #define MT_RXD1_NORMAL_GROUP_4 BIT(19)
42 #define MT_RXD1_NORMAL_GROUP_5 BIT(20)
44 #define MT_RXD1_NORMAL_CM BIT(23)
45 #define MT_RXD1_NORMAL_CLM BIT(24)
[all …]
H A Dmt76x02_dma.h1 /* SPDX-License-Identifier: ISC */
13 #define MT_TXD_INFO_NEXT_VLD BIT(16)
14 #define MT_TXD_INFO_TX_BURST BIT(17)
15 #define MT_TXD_INFO_80211 BIT(19)
16 #define MT_TXD_INFO_TSO BIT(20)
17 #define MT_TXD_INFO_CSO BIT(21)
18 #define MT_TXD_INFO_WIV BIT(24)
20 #define MT_TXD_INFO_DPORT GENMASK(29, 27)
24 #define MT_RX_FCE_INFO_SELF_GEN BIT(15)
27 #define MT_RX_FCE_INFO_PCIE_INTR BIT(24)
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
[all …]
H A Dregs.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
[all …]
/freebsd/contrib/netbsd-tests/include/
H A Dd_bitstring_32.out34 29 3 32 4
39 be: 0 -1 00000000000000000000000000000000
40 is: 0 -1 00000000000000000000000000000000
81 29 0
86 be: 0 -1 00000000000000000000000000000000
87 is: 0 -1 00000000000000000000000000000000
94 be: 0 -1 00000000000000000000000000000000
95 is: 0 -1 00000000000000000000000000000000
98 be: 0 -1 00000000000000000000000000000000
99 is: 0 -1 00000000000000000000000000000000
[all …]
H A Dd_bitstring_49.out34 29 3 32 4
56 be: 0 -1 0000000000000000000000000000000000000000000000000
57 is: 0 -1 0000000000000000000000000000000000000000000000000
98 29 0
120 be: 0 -1 0000000000000000000000000000000000000000000000000
121 is: 0 -1 0000000000000000000000000000000000000000000000000
128 be: 0 -1 0000000000000000000000000000000000000000000000000
129 is: 0 -1 0000000000000000000000000000000000000000000000000
132 be: 0 -1 0000000000000000000000000000000000000000000000000
133 is: 0 -1 0000000000000000000000000000000000000000000000000
[all …]
H A Dd_bitstring_67.out34 29 3 32 4
74 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000
75 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000
116 29 0
156 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000
157 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000
164 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000
165 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000
168 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000
169 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000
[all …]
H A Dd_bitstring_64.out34 29 3 32 4
71 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000
72 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000
113 29 0
150 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000
151 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000
158 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000
159 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000
162 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000
163 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Dtxrx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
28 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_rate_mode()
41 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_ht_mcs()
49 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_mcs()
62 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_nss()
71 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23)
72 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22)
73 #define RTW89_TXWD_BODY0_FW_DL BIT(20)
76 #define RTW89_TXWD_BODY0_STF_MODE BIT(10)
77 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7)
[all …]
H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
9 #define B_AX_AUTOLOAD_SUS BIT(5)
13 #define B_AX_PWC_EV2EF_B15 BIT(15)
14 #define B_AX_PWC_EV2EF_B14 BIT(14)
15 #define B_AX_ISO_EB2CORE BIT(8)
18 #define B_AX_FEN_BB_GLB_RSTN BIT(1)
19 #define B_AX_FEN_BBRSTB BIT(0)
22 #define B_AX_SOP_ASWRM BIT(31)
23 #define B_AX_SOP_PWMM_DSWR BIT(29)
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_inline.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
19 #define ADF_C4XXX_SADB_SIZE_BIT BIT(24)
21 ((accel_dev)->aram_info->sadb_region_size / 32)
24 /* SADB CTRL register bit offsets */
39 #define ADF_C4XXX_STATS_REQUEST_ENABLED BIT(16)
40 #define ADF_C4XXX_STATS_REQUEST_DISABLED ~BIT(16)
45 #define ADF_C4XXX_MAC_STATS_READY BIT(0)
48 #define ADF_C4XXX_MAC_ERROR_TX_UNDERRUN BIT(6)
49 #define ADF_C4XXX_MAC_ERROR_TX_FCS BIT(7)
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrFormats.td1 //===-- R600InstrFormats.td - R600 Instruction Encodings ------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 def isR600 : Predicate<"Subtarget->getGeneration() <= AMDGPUSubtarget::R700">;
16 "Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS">;
27 bit Trig = 0;
28 bit Op3 = 0;
29 bit isVector = 0;
31 bit Op1 = 0;
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Drtw8812a.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
26 rx_pwr_all = -94 + 2 * (27 - vga_idx); in rtw8812a_cck_rx_pwr()
28 rx_pwr_all = -94; in rtw8812a_cck_rx_pwr()
31 rx_pwr_all = -42 + 2 * (2 - vga_idx); in rtw8812a_cck_rx_pwr()
34 rx_pwr_all = -36 + 2 * (7 - vga_idx); in rtw8812a_cck_rx_pwr()
37 rx_pwr_all = -30 + 2 * (7 - vga_idx); in rtw8812a_cck_rx_pwr()
40 rx_pwr_all = -18 + 2 * (7 - vga_idx); in rtw8812a_cck_rx_pwr()
43 rx_pwr_all = 2 * (5 - vga_idx); in rtw8812a_cck_rx_pwr()
46 rx_pwr_all = 14 - 2 * vga_idx; in rtw8812a_cck_rx_pwr()
49 rx_pwr_all = 20 - 2 * vga_idx; in rtw8812a_cck_rx_pwr()
[all …]
H A Drtw8723d.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
22 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
9 #define BIT_FEN_EN_25_1 BIT(13)
10 #define BIT_FEN_ELDR BIT(12)
11 #define BIT_FEN_PCIEA BIT(6)
12 #define BIT_FEN_CPUEN BIT(2)
13 #define BIT_FEN_USBA BIT(2)
14 #define BIT_FEN_BB_GLB_RST BIT(1)
15 #define BIT_FEN_BB_RSTB BIT(0)
16 #define BIT_R_DIS_PRST BIT(6)
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsV.td1 //===-- RISCVInstrFormatsV.td - RISC-V V Instruction Formats -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the RISC-V V extension instruction formats.
11 //===----------------------------------------------------------------------===//
65 let Inst{29-20} = vtypei{9-0};
66 let Inst{19-15} = uimm;
67 let Inst{14-12} = OPCFG.Value;
68 let Inst{11-7} = rd;
69 let Inst{6-0} = OPC_OP_V.Value;
[all …]
/freebsd/secure/lib/libcrypto/man/man3/
H A DOPENSSL_ia32cap.31 .\" -*- mode: troff; coding: utf-8 -*-
58 .TH OPENSSL_IA32CAP 3ossl 2025-09-30 3.5.4 OpenSSL
64 OPENSSL_ia32cap \- the x86[_64] processor capabilities vector
74 stored internally as ten 32\-bit capability vectors and for simplicity
75 represented logically below as five 64\-bit vectors. This logical
81 environment variable capability bit modifications are applied. After toolkit
94 .IP "bit #0+4 denoting presence of Time-Stamp Counter;" 4
95 .IX Item "bit #0+4 denoting presence of Time-Stamp Counter;"
97 .IP "bit #0+19 denoting availability of CLFLUSH instruction;" 4
98 .IX Item "bit #0+19 denoting availability of CLFLUSH instruction;"
[all …]
/freebsd/sys/dev/ice/
H A Dice_hw_autogen.h1 /* SPDX-License-Identifier: BSD-3-Clause */
37 #define PRTMAC_CTL_TX_PAUSE_ENABLE_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_TX_PAUSE_ENABLE : E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE)
38 #define PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_S_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_S : E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_S)
39 #define PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_M : E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_M)
40 #define PRTMAC_CTL_RX_PAUSE_ENABLE_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_RX_PAUSE_ENABLE : E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE)
41 #define PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_S_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_S : E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_S)
42 #define PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_M_BY_MAC(hw) ((hw)->mac_typ
[all...]
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Dnvidia,tegra186-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <treding@nvidia.com>
13 The Tegra timer provides 29-bit timer counters and a 32-bit timestamp
16 programmed to generate one-shot, periodic, or watchdog interrupts.
22 - const: nvidia,tegra186-timer
24 The Tegra186 timer provides ten 29-bit timer counters.
25 - const: nvidia,tegra234-timer
[all …]
H A Dnvidia,tegra-timer.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Warren <swarren@nvidia.com>
13 - if:
17 const: nvidia,tegra210-timer
27 - if:
31 - items:
32 - enum:
[all …]
/freebsd/sys/contrib/device-tree/include/dt-bindings/mfd/
H A Dstm32f4-rcc.h1 /* SPDX-License-Identifier: GPL-2.0 */
31 #define STM32F4_RCC_AHB1_OTGHS 29
34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
77 #define STM32F4_RCC_APB1_DAC 29
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
[all …]
H A Dstm32f7-rcc.h1 /* SPDX-License-Identifier: GPL-2.0 */
31 #define STM32F7_RCC_AHB1_OTGHS 29
34 #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit) argument
45 #define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8)) argument
46 #define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20) argument
52 #define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8)) argument
53 #define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40) argument
83 #define STM32F7_RCC_APB1_DAC 29
87 #define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8)) argument
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dregs.h1 /* SPDX-License-Identifier: ISC */
126 #define __REG(id) (dev->reg.reg_rev[(id)])
127 #define __OFFS(id) (dev->reg.offs_rev[(id)])
140 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
141 #define MT_MCU_INT_EVENT_DMA_INIT BIT(1)
142 #define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2)
143 #define MT_MCU_INT_EVENT_RESET_DONE BIT(3)
150 #define MT_PLE_HOST_RPT0_TX_LATENCY BIT(3)
175 #define MT_MDP_DCR0_DAMSDU_EN BIT(15)
176 #define MT_MDP_DCR0_RX_HDR_TRANS_EN BIT(19)
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