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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dlpc1850-creg-clk.txt5 32 kHz oscillator driver with power up/down and clock gating. Next
6 is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
9 The 32 kHz can also be routed to other peripherals to enable low
19 Shall have value <1>.
21 Shall contain a phandle to the fixed 32 kHz crystal.
28 0 1 kHz clock
29 1 3
[all...]
H A Damlogic,gxbb-aoclkc.txt19 * "ext-32k-0" : external 32kHz reference #0 if any (optional)
20 * "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only)
21 * "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only)
23 - #clock-cells: should be 1.
30 - #reset-cells: should be 1.
49 #clock-cells = <1>;
50 #reset-cells = <1>;
61 interrupts = <0 90 1>;
H A Dmaxim,max77686.txt10 The MAX77686 contains three 32.768khz clock outputs that can be controlled
15 The MAX77802 contains two 32.768khz clock outputs that can be controlled
19 The MAX77686 contains one 32.768khz clock outputs that can be controlled
27 - #clock-cells: from common clock binding; shall be set to 1.
35 - 1: 32khz_cp clock (max77686, max77802),
43 1. With MAX77686:
54 #clock-cells = <1>;
79 #clock-cells = <1>;
103 #clock-cells = <1>;
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dti,j721e-cpb-ivi-audio.yaml23 In order to support 48KHz and 44.1KHz family of sampling rates the parent clock
24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
25 44.1KHz). The same PLLs are used for McASP0's AUXCLK clock via different
30 Clocking setup for 48KHz family:
37 Clocking setup for 44.1KHz family:
76 - description: Parent for CPB_McASP auxclk (for 48KHz)
77 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
79 - description: Parent for CPB_SCKI clock (for 48KHz)
80 - description: Parent for CPB_SCKI clock (for 44.1KHz)
[all...]
H A Dti,j721e-cpb-audio.yaml18 In order to support 48KHz and 44.1KHz family of sampling rates the parent
19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
20 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
24 48KHz family:
28 44.1KHz family:
33 48KHz family:
85 - description: Parent for CPB_McASP auxclk (for 48KHz)
86 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
88 - description: Parent for CPB_SCKI clock (for 48KHz)
89 - description: Parent for CPB_SCKI clock (for 44.1KHz)
[all …]
H A Dst,stm32-sai.yaml28 minItems: 1
31 maxItems: 1
34 maxItems: 1
37 maxItems: 1
40 const: 1
43 const: 1
77 maxItems: 1
83 minItems: 1
89 minItems: 1
92 maxItems: 1
[all...]
/freebsd/contrib/file/magic/scripts/
H A Dcreate_filemagic_flac6 ## >>17 belong&0xfffff0 0x2ee000 \b, 192 kHz
15 ## (16384 kHz = 32 kHz * 512 = 32 * 2^9)
17 ## (22579.2 kHz = 44.1kHz * 512 = 44.1 * 2^9)
20 ## (24576 kHz = 48 kHz * 512 = 48 * 2^9)
43 while [[ ${n} -ge 1 ]]; do
53 ## use bc with sed to convert and format Hz to kHz
58 printf -v line ">>17\tbelong&%#-15x\t%#08x\t%s, %s kHz\n" \
/freebsd/contrib/file/magic/Magdir/
H A Daudio4 # audio: file(1) magic for sound formats (see also "iff")
12 >12 belong 1 8-bit ISDN mu-law,
42 >20 belong 1 mono,
50 >12 lelong 1 8-bit ISDN mu-law,
80 >20 lelong 1 mono,
90 >10 beshort >1 \bs
91 >12 beshort&0x7fff x at 1/%d
116 >83 byte 1 (song)
169 >14 string >/0 ultratracker V1.%.1s module sound data
259 >14 beshort =1 single song,
[all …]
H A Danimation4 # animation: file(1) magic for animation/movie formats
52 # Section 8.1.1, corresponds to a, b, c
75 >>11 byte 1 \b, Release %d (non existent)
179 >8 string J2P1 \b, JPEG2000 Profile 1
182 >8 string JP2 \b, JPEG 2000 Image (.JP2) [ISO 15444-1 ?]
217 >8 string mp41 \b, MP4 v1 [ISO 14496-1:ch13]
350 >>4 byte 1 \b, simple @ L1
424 >>>16 byte&0x0F 1 \b HP
443 >>>>>144 byte&0x0F 1 \b HP
460 >>>80 byte&0x0F 1 \b HP
[all …]
H A Ddolby13 >4 byte&0xc0 = 0x00 48 kHz,
14 >4 byte&0xc0 = 0x40 44.1 kHz,
15 >4 byte&0xc0 = 0x80 32 kHz,
16 # is this one used for 96 kHz?
29 >6 byte&0xe0 = 0x00 1+1 front,
31 >6 byte&0xe0 = 0x20 1 front/0 rear,
42 >6 byte&0xe0 = 0x80 2 front/1 rear,
44 >6 byte&0xe0 = 0xa0 3 front/1 rear,
/freebsd/share/man/man4/
H A Dsnd_hdsp.48 .\" 1. Redistributions of source code must retain the above copyright
69 (32kHz-48kHz) and 4 channels at double speed (64kHz-96kHz).
70 Only the HDSP 9632 can operate at quad speed (128kHz-192kHz), ADAT is
81 If set to 1, all physical ports are combined into one unified pcm device.
H A Dsnd_hdspe.47 .\" 1. Redistributions of source code must retain the above copyright
68 (32kHz-48kHz), 4 channels at double speed (64kHz-96kHz), and 2 channels at
69 quad speed (128kHz-192kHz).
79 If set to 1, all physical ports are combined into one unified pcm device.
H A Dsnd_emu10kx.48 .\" 1. Redistributions of source code must retain the above copyright
78 PCM support is limited to 48kHz/16 bit stereo (192kHz/24 bit part
83 to 48kHz/16 bit stereo (192kHz/24 bit part of this chipset is not supported).
138 you will get one more DSP device that is rate-locked to 48kHz/16bit/mono.
139 This is actually 48kHz/16bit/32 channels on SB Live! cards and
140 48kHz/16bit/64channels on Audigy cards, but the current implementation of
232 .Xr kenv 1
249 .It 1
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6q-cm-fx6.dts145 fsl,audmux-port = <1>;
159 IMX_AUDMUX_V2_PTCR_TFSEL(1) |
161 IMX_AUDMUX_V2_PTCR_RCSEL(1 | 0x8) |
163 IMX_AUDMUX_V2_PTCR_TCSEL(1))
164 IMX_AUDMUX_V2_PDCR_RXDSEL(1)
176 /* kHz uV */
183 /* ARM kHz SOC-PU uV */
198 /* kHz uV */
205 /* ARM kHz SOC-PU uV */
220 /* kHz u
[all...]
H A Dimx6q.dtsi16 #address-cells = <1>;
25 /* kHz uV */
33 /* ARM kHz SOC-PU uV */
56 cpu1: cpu@1 {
59 reg = <1>;
62 /* kHz uV */
70 /* ARM kHz SOC-PU uV */
97 /* kHz uV */
105 /* ARM kHz SOC-PU uV */
132 /* kHz uV */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/calxeda/
H A Dhighbank.dts14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
29 /* kHz ignored */
48 /* kHz ignored */
67 /* kHz ignored */
86 /* kHz ignored */
116 interrupts = <1 13 0xf01>;
123 interrupts = <1 14 0xf01>;
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dr8a779g0-white-hawk-ard-audio-da7212.dtso55 * 44.1kHz groups sound is available by default.
56 * You need to update audio_clkin settings to switch to 48kHz groups sound.
88 /* 44.1kHz groups [(C) clock] */
92 /* 48 kHz groups [(C) clock] */
124 #address-cells = <1>;
127 codec@1a {
163 clock-frequency = <5644800>; /* 44.1kHz groups [(C) clock] */
164 // clock-frequency = <6144000>; /* 48 kHz groups [(C) clock] */
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dmax77620.txt22 system power, see [1] for more details.
24 [1] Documentation/devicetree/bindings/power/power-controller.txt
36 with internal regulators. 32KHz clock can be programmed to be part of a
46 Each regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power
54 When FPS event cleared (set to LOW), regulators, GPIOs and 32KHz
58 and 32KHz clock get disabled at
68 regulators, GPIOs and 32kHz clocks are provided in their respective
117 1: Enables POK(Power OK) to control nRST_IO and GPIO1
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Drichtek,rt6245-regulator.yaml26 maxItems: 1
32 maxItems: 1
36 enum: [0, 1, 2, 3]
44 enum: [0, 1, 2]
52 enum: [0, 1, 2, 3]
61 enum: [0, 1, 2]
63 Buck switch frequency selection. Each respective value means 400KHz,
64 800KHz, 1200KHz. If this property is missing then keep in chip default.
75 #address-cells = <1>;
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-ocores.txt19 - #address-cells : should be <1>
25 Defaults to 100 KHz when the property is not specified
27 - reg-io-width : io register width in bytes (1, 2 or 4)
37 frequency is fixed at 100 KHz.
46 #address-cells = <1>;
54 reg-io-width = <1>; /* 8 bit read/write */
63 #address-cells = <1>;
69 clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
72 reg-io-width = <1>; /* 8 bit read/write */
/freebsd/sys/dev/ath/ath_hal/ar5312/
H A Dar5312_misc.c92 * If 32KHz clock exists, use it to lower power consumption during sleep
94 * Note: If clock is set to 32 KHz, delays on accessing certain
114 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1); in ar5312SetupClock()
115 OS_REG_WRITE(ah, AR_TSF_PARM, 61); /* 32 KHz TSF incr */ in ar5312SetupClock()
118 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */ in ar5312SetupClock()
139 * If 32KHz clock exists, turn it off and turn back on the 32Mhz
146 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */ in ar5312RestoreClock()
/freebsd/sys/contrib/device-tree/Bindings/pwm/
H A Dkontron,sl28cpld-pwm.yaml17 frequencies (250Hz, 500Hz, 1kHz, 2kHz).
27 maxItems: 1
/freebsd/sys/dev/sound/pci/
H A Denvy24ht.h11 * 1. Redistributions of source code must retain the above copyright
62 /* 00: 24.576MHz(96kHz*256) */
63 /* 01: 49.152MHz(192kHz*256) */
64 /* 1x: Reserved */
65 #define ENVY24HT_CCSM_SCFG_MPU 0x20 /* 0(not implemented)/1(1) MPU-401 UART */
66 #define ENVY24HT_CCSM_SCFG_ADC 0x0c /* 1-2 stereo ADC connected, S/PDIF receiver connected */
67 #define ENVY24HT_CCSM_SCFG_DAC 0x03 /* 1-4 stereo DAC connected */
70 #define ENVY24HT_CCSM_ACL_MTC 0x80 /* Multi-track converter type: 0:AC'97 1:I2S */
71 #define ENVY24HT_CCSM_ACL_OMODE 0x02 /* AC 97 codec SDATA_OUT 0:split 1:packed */
75 #define ENVY24HT_CCSM_I2S_96KHZ 0x40 /* I2S converter 96kHz sampling rate support */
[all …]
/freebsd/sys/dev/iicbus/controller/twsi/
H A Dmv_twsi.c10 * 1. Redistributions of source code must retain the above copyright
80 #define TWSI_BAUD_RATE_RAW(C,M,N) ((C)/((10*(M+1))<<(N+1)))
81 #define TWSI_BAUD_RATE_SLOW 50000 /* 50kHz */
82 #define TWSI_BAUD_RATE_FAST 100000 /* 100kHz */
120 MODULE_DEPEND(twsi, iicbus, 1, 1, 1);
197 if (clk_get_by_ofw_index(dev, 0, 1, &sc->clk_reg) == 0) { in mv_twsi_attach()
209 " %" PRIu32 " kHz (M=%d, N=%d) for slow,\n" in mv_twsi_attach()
210 " %" PRIu32 " kHz (M=%d, N=%d) for fast.\n", in mv_twsi_attach()
/freebsd/sys/contrib/device-tree/Bindings/input/
H A Diqs626a.yaml26 maxItems: 1
29 maxItems: 1
32 const: 1
39 enum: [0, 1, 2, 3]
44 1: Low power (all sensing at a reduced reporting rate)
60 enum: [0, 1, 2, 3, 4, 5, 6, 7]
66 1: 13
84 enum: [0, 1, 2, 3, 4, 5, 6, 7]
85 default: 1
90 1: ULP channel
[all …]

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