1*c66ec88fSEmmanuel VadotMAX77620 Power management IC from Maxim Semiconductor. 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotRequired properties: 4*c66ec88fSEmmanuel Vadot------------------- 5*c66ec88fSEmmanuel Vadot- compatible: Must be one of 6*c66ec88fSEmmanuel Vadot "maxim,max77620" 7*c66ec88fSEmmanuel Vadot "maxim,max20024" 8*c66ec88fSEmmanuel Vadot "maxim,max77663" 9*c66ec88fSEmmanuel Vadot- reg: I2C device address. 10*c66ec88fSEmmanuel Vadot 11*c66ec88fSEmmanuel VadotOptional properties: 12*c66ec88fSEmmanuel Vadot------------------- 13*c66ec88fSEmmanuel Vadot- interrupts: The interrupt on the parent the controller is 14*c66ec88fSEmmanuel Vadot connected to. 15*c66ec88fSEmmanuel Vadot- interrupt-controller: Marks the device node as an interrupt controller. 16*c66ec88fSEmmanuel Vadot- #interrupt-cells: is <2> and their usage is compliant to the 2 cells 17*c66ec88fSEmmanuel Vadot variant of <../interrupt-controller/interrupts.txt> 18*c66ec88fSEmmanuel Vadot IRQ numbers for different interrupt source of MAX77620 19*c66ec88fSEmmanuel Vadot are defined at dt-bindings/mfd/max77620.h. 20*c66ec88fSEmmanuel Vadot 21*c66ec88fSEmmanuel Vadot- system-power-controller: Indicates that this PMIC is controlling the 22*c66ec88fSEmmanuel Vadot system power, see [1] for more details. 23*c66ec88fSEmmanuel Vadot 24*c66ec88fSEmmanuel Vadot[1] Documentation/devicetree/bindings/power/power-controller.txt 25*c66ec88fSEmmanuel Vadot 26*c66ec88fSEmmanuel VadotOptional subnodes and their properties: 27*c66ec88fSEmmanuel Vadot======================================= 28*c66ec88fSEmmanuel Vadot 29*c66ec88fSEmmanuel VadotFlexible power sequence configurations: 30*c66ec88fSEmmanuel Vadot-------------------------------------- 31*c66ec88fSEmmanuel VadotThe Flexible Power Sequencer (FPS) allows each regulator to power up under 32*c66ec88fSEmmanuel Vadothardware or software control. Additionally, each regulator can power on 33*c66ec88fSEmmanuel Vadotindependently or among a group of other regulators with an adjustable power-up 34*c66ec88fSEmmanuel Vadotand power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can be programmed 35*c66ec88fSEmmanuel Vadotto be part of a sequence allowing external regulators to be sequenced along 36*c66ec88fSEmmanuel Vadotwith internal regulators. 32KHz clock can be programmed to be part of a 37*c66ec88fSEmmanuel Vadotsequence. 38*c66ec88fSEmmanuel Vadot 39*c66ec88fSEmmanuel VadotThe flexible sequencing structure consists of two hardware enable inputs 40*c66ec88fSEmmanuel Vadot(EN0, EN1), and 3 master sequencing timers called FPS0, FPS1 and FPS2. 41*c66ec88fSEmmanuel VadotEach master sequencing timer is programmable through its configuration 42*c66ec88fSEmmanuel Vadotregister to have a hardware enable source (EN1 or EN2) or a software enable 43*c66ec88fSEmmanuel Vadotsource (SW). When enabled/disabled, the master sequencing timer generates 44*c66ec88fSEmmanuel Vadoteight sequencing events on different time periods called slots. The time 45*c66ec88fSEmmanuel Vadotperiod between each event is programmable within the configuration register. 46*c66ec88fSEmmanuel VadotEach regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power 47*c66ec88fSEmmanuel Vadotsequence slave register which allows its enable source to be specified as 48*c66ec88fSEmmanuel Vadota flexible power sequencer timer or a software bit. When a FPS source of 49*c66ec88fSEmmanuel Vadotregulators, GPIOs and clocks specifies the enable source to be a flexible 50*c66ec88fSEmmanuel Vadotpower sequencer, the power up and power down delays can be specified in 51*c66ec88fSEmmanuel Vadotthe regulators, GPIOs and clocks flexible power sequencer configuration 52*c66ec88fSEmmanuel Vadotregisters. 53*c66ec88fSEmmanuel Vadot 54*c66ec88fSEmmanuel VadotWhen FPS event cleared (set to LOW), regulators, GPIOs and 32KHz 55*c66ec88fSEmmanuel Vadotclock are set into following state at the sequencing event that 56*c66ec88fSEmmanuel Vadotcorresponds to its flexible sequencer configuration register. 57*c66ec88fSEmmanuel Vadot Sleep state: In this state, regulators, GPIOs 58*c66ec88fSEmmanuel Vadot and 32KHz clock get disabled at 59*c66ec88fSEmmanuel Vadot the sequencing event. 60*c66ec88fSEmmanuel Vadot Global Low Power Mode (GLPM): In this state, regulators are set in 61*c66ec88fSEmmanuel Vadot low power mode at the sequencing event. 62*c66ec88fSEmmanuel Vadot 63*c66ec88fSEmmanuel VadotThe configuration parameters of FPS is provided through sub-node "fps" 64*c66ec88fSEmmanuel Vadotand their child for FPS specific. The child node name for FPS are "fps0", 65*c66ec88fSEmmanuel Vadot"fps1", and "fps2" for FPS0, FPS1 and FPS2 respectively. 66*c66ec88fSEmmanuel Vadot 67*c66ec88fSEmmanuel VadotThe FPS configurations like FPS source, power up and power down slots for 68*c66ec88fSEmmanuel Vadotregulators, GPIOs and 32kHz clocks are provided in their respective 69*c66ec88fSEmmanuel Vadotconfiguration nodes which is explained in respective sub-system DT 70*c66ec88fSEmmanuel Vadotbinding document. 71*c66ec88fSEmmanuel Vadot 72*c66ec88fSEmmanuel VadotThere is need for different FPS configuration parameters based on system 73*c66ec88fSEmmanuel Vadotstate like when system state changed from active to suspend or active to 74*c66ec88fSEmmanuel Vadotpower off (shutdown). 75*c66ec88fSEmmanuel Vadot 76*c66ec88fSEmmanuel VadotOptional properties: 77*c66ec88fSEmmanuel Vadot------------------- 78*c66ec88fSEmmanuel Vadot-maxim,fps-event-source: u32, FPS event source like external 79*c66ec88fSEmmanuel Vadot hardware input to PMIC i.e. EN0, EN1 or 80*c66ec88fSEmmanuel Vadot software (SW). 81*c66ec88fSEmmanuel Vadot The macros are defined on 82*c66ec88fSEmmanuel Vadot dt-bindings/mfd/max77620.h 83*c66ec88fSEmmanuel Vadot for different control source. 84*c66ec88fSEmmanuel Vadot - MAX77620_FPS_EVENT_SRC_EN0 85*c66ec88fSEmmanuel Vadot for hardware input pin EN0. 86*c66ec88fSEmmanuel Vadot - MAX77620_FPS_EVENT_SRC_EN1 87*c66ec88fSEmmanuel Vadot for hardware input pin EN1. 88*c66ec88fSEmmanuel Vadot - MAX77620_FPS_EVENT_SRC_SW 89*c66ec88fSEmmanuel Vadot for software control. 90*c66ec88fSEmmanuel Vadot 91*c66ec88fSEmmanuel Vadot-maxim,shutdown-fps-time-period-us: u32, FPS time period in microseconds 92*c66ec88fSEmmanuel Vadot when system enters in to shutdown 93*c66ec88fSEmmanuel Vadot state. 94*c66ec88fSEmmanuel Vadot 95*c66ec88fSEmmanuel Vadot-maxim,suspend-fps-time-period-us: u32, FPS time period in microseconds 96*c66ec88fSEmmanuel Vadot when system enters in to suspend state. 97*c66ec88fSEmmanuel Vadot 98*c66ec88fSEmmanuel Vadot-maxim,device-state-on-disabled-event: u32, describe the PMIC state when FPS 99*c66ec88fSEmmanuel Vadot event cleared (set to LOW) whether it 100*c66ec88fSEmmanuel Vadot should go to sleep state or low-power 101*c66ec88fSEmmanuel Vadot state. Following are valid values: 102*c66ec88fSEmmanuel Vadot - MAX77620_FPS_INACTIVE_STATE_SLEEP 103*c66ec88fSEmmanuel Vadot to set the PMIC state to sleep. 104*c66ec88fSEmmanuel Vadot - MAX77620_FPS_INACTIVE_STATE_LOW_POWER 105*c66ec88fSEmmanuel Vadot to set the PMIC state to low 106*c66ec88fSEmmanuel Vadot power. 107*c66ec88fSEmmanuel Vadot Absence of this property or other value 108*c66ec88fSEmmanuel Vadot will not change device state when FPS 109*c66ec88fSEmmanuel Vadot event get cleared. 110*c66ec88fSEmmanuel Vadot 111*c66ec88fSEmmanuel VadotHere supported time periods by device in microseconds are as follows: 112*c66ec88fSEmmanuel VadotMAX77620 supports 40, 80, 160, 320, 640, 1280, 2560 and 5120 microseconds. 113*c66ec88fSEmmanuel VadotMAX20024 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds. 114*c66ec88fSEmmanuel VadotMAX77663 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds. 115*c66ec88fSEmmanuel Vadot 116*c66ec88fSEmmanuel Vadot-maxim,power-ok-control: configure map power ok bit 117*c66ec88fSEmmanuel Vadot 1: Enables POK(Power OK) to control nRST_IO and GPIO1 118*c66ec88fSEmmanuel Vadot POK function. 119*c66ec88fSEmmanuel Vadot 0: Disables POK control. 120*c66ec88fSEmmanuel Vadot if property missing, do not configure MPOK bit. 121*c66ec88fSEmmanuel Vadot If POK mapping is enabled for GPIO1/nRST_IO then, 122*c66ec88fSEmmanuel Vadot GPIO1/nRST_IO pins are HIGH only if all rails 123*c66ec88fSEmmanuel Vadot that have POK control enabled are HIGH. 124*c66ec88fSEmmanuel Vadot If any of the rails goes down(which are enabled for POK 125*c66ec88fSEmmanuel Vadot control) then, GPIO1/nRST_IO goes LOW. 126*c66ec88fSEmmanuel Vadot this property is valid for max20024 only. 127*c66ec88fSEmmanuel Vadot 128*c66ec88fSEmmanuel VadotFor DT binding details of different sub modules like GPIO, pincontrol, 129*c66ec88fSEmmanuel Vadotregulator, power, please refer respective device-tree binding document 130*c66ec88fSEmmanuel Vadotunder their respective sub-system directories. 131*c66ec88fSEmmanuel Vadot 132*c66ec88fSEmmanuel VadotExample: 133*c66ec88fSEmmanuel Vadot-------- 134*c66ec88fSEmmanuel Vadot#include <dt-bindings/mfd/max77620.h> 135*c66ec88fSEmmanuel Vadot 136*c66ec88fSEmmanuel Vadotmax77620@3c { 137*c66ec88fSEmmanuel Vadot compatible = "maxim,max77620"; 138*c66ec88fSEmmanuel Vadot reg = <0x3c>; 139*c66ec88fSEmmanuel Vadot 140*c66ec88fSEmmanuel Vadot interrupt-parent = <&intc>; 141*c66ec88fSEmmanuel Vadot interrupts = <0 86 IRQ_TYPE_NONE>; 142*c66ec88fSEmmanuel Vadot 143*c66ec88fSEmmanuel Vadot interrupt-controller; 144*c66ec88fSEmmanuel Vadot #interrupt-cells = <2>; 145*c66ec88fSEmmanuel Vadot 146*c66ec88fSEmmanuel Vadot fps { 147*c66ec88fSEmmanuel Vadot fps0 { 148*c66ec88fSEmmanuel Vadot maxim,shutdown-fps-time-period-us = <1280>; 149*c66ec88fSEmmanuel Vadot maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; 150*c66ec88fSEmmanuel Vadot }; 151*c66ec88fSEmmanuel Vadot 152*c66ec88fSEmmanuel Vadot fps1 { 153*c66ec88fSEmmanuel Vadot maxim,shutdown-fps-time-period-us = <1280>; 154*c66ec88fSEmmanuel Vadot maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 155*c66ec88fSEmmanuel Vadot }; 156*c66ec88fSEmmanuel Vadot 157*c66ec88fSEmmanuel Vadot fps2 { 158*c66ec88fSEmmanuel Vadot maxim,shutdown-fps-time-period-us = <1280>; 159*c66ec88fSEmmanuel Vadot maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_SW>; 160*c66ec88fSEmmanuel Vadot }; 161*c66ec88fSEmmanuel Vadot }; 162*c66ec88fSEmmanuel Vadot}; 163