Lines Matching +full:1 +full:khz
11 * 1. Redistributions of source code must retain the above copyright
62 /* 00: 24.576MHz(96kHz*256) */
63 /* 01: 49.152MHz(192kHz*256) */
64 /* 1x: Reserved */
65 #define ENVY24HT_CCSM_SCFG_MPU 0x20 /* 0(not implemented)/1(1) MPU-401 UART */
66 #define ENVY24HT_CCSM_SCFG_ADC 0x0c /* 1-2 stereo ADC connected, S/PDIF receiver connected */
67 #define ENVY24HT_CCSM_SCFG_DAC 0x03 /* 1-4 stereo DAC connected */
70 #define ENVY24HT_CCSM_ACL_MTC 0x80 /* Multi-track converter type: 0:AC'97 1:I2S */
71 #define ENVY24HT_CCSM_ACL_OMODE 0x02 /* AC 97 codec SDATA_OUT 0:split 1:packed */
75 #define ENVY24HT_CCSM_I2S_96KHZ 0x40 /* I2S converter 96kHz sampling rate support */
76 #define ENVY24HT_CCSM_I2S_192KHZ 0x08 /* I2S converter 192kHz sampling rate support */
127 #define ENVY24HT_MT_PCTL_RSTART 0x02 /* 1: Record start; 0: Record stop */
128 #define ENVY24HT_MT_PCTL_PSTART 0x01 /* 1: Playback start; 0: Playback stop */
156 #define ENVY24HT_CHAN_NUM 11 /* Play * 5 + Record * 5 + Mix * 1 */
159 #define ENVY24HT_CHAN_PLAY_DAC2 1
178 #define BUS_SPACE_MAXSIZE_ENVY24 0x3fffc /* 64k x 4byte(1dword) */