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/linux/arch/arm/include/asm/
H A Darch_gicv3.h18 #define ICC_EOIR1 __ACCESS_CP15(c12, 0, c12, 1)
19 #define ICC_DIR __ACCESS_CP15(c12, 0, c11, 1)
20 #define ICC_IAR1 __ACCESS_CP15(c12, 0, c12, 0)
21 #define ICC_SGI1R __ACCESS_CP15_64(0, c12)
23 #define ICC_CTLR __ACCESS_CP15(c12, 0, c12, 4)
24 #define ICC_SRE __ACCESS_CP15(c12, 0, c12, 5)
25 #define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7)
26 #define ICC_BPR1 __ACCESS_CP15(c12, 0, c12, 3)
27 #define ICC_RPR __ACCESS_CP15(c12, 0, c11, 3)
29 #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x)
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H A Darm_pmuv3.h14 #define PMCR __ACCESS_CP15(c9, 0, c12, 0)
15 #define PMCNTENSET __ACCESS_CP15(c9, 0, c12, 1)
16 #define PMCNTENCLR __ACCESS_CP15(c9, 0, c12, 2)
17 #define PMOVSR __ACCESS_CP15(c9, 0, c12, 3)
18 #define PMSELR __ACCESS_CP15(c9, 0, c12, 5)
19 #define PMCEID0 __ACCESS_CP15(c9, 0, c12, 6)
20 #define PMCEID1 __ACCESS_CP15(c9, 0, c12, 7)
21 #define PMXEVTYPER __ACCESS_CP15(c9, 0, c13, 1)
24 #define PMINTENSET __ACCESS_CP15(c9, 0, c14, 1)
32 #define PMEVCNTR1 __ACCESS_CP15(c14, 0, c8, 1)
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/linux/arch/arm/include/asm/hardware/
H A Dcp14.h35 * Available only in DBGv7.1
69 #define RCP14_DBGBVR12() MRC14(0, c0, c12, 4)
85 #define RCP14_DBGBCR12() MRC14(0, c0, c12, 5)
101 #define RCP14_DBGWVR12() MRC14(0, c0, c12, 6)
117 #define RCP14_DBGWCR12() MRC14(0, c0, c12, 7)
122 #define RCP14_DBGBXVR0() MRC14(0, c1, c0, 1)
123 #define RCP14_DBGBXVR1() MRC14(0, c1, c1, 1)
124 #define RCP14_DBGBXVR2() MRC14(0, c1, c2, 1)
125 #define RCP14_DBGBXVR3() MRC14(0, c1, c3, 1)
126 #define RCP14_DBGBXVR4() MRC14(0, c1, c4, 1)
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/linux/arch/arm/kernel/
H A Dhyp-stub.S116 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR)
124 THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE
125 ARM_BE8(orr r7, r7, #(1 << 25)) @ HSCTLR.EE
128 mrc p15, 4, r7, c1, c1, 1 @ HDCR
130 mcr p15, 4, r7, c1, c1, 1 @ HDCR
134 orr r7, #(1 << 5) @ CP15 barriers enabled
147 mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1
150 beq 1f
158 mrc p15, 0, r7, c14, c3, 1 @ CNTV_CTL
159 bic r7, #1 @ Clear ENABLE
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/linux/drivers/perf/
H A Darm_v6_pmu.c119 asm volatile("mrc p15, 0, %0, c15, c12, 0" : "=r"(val)); in armv6_pmcr_read()
126 asm volatile("mcr p15, 0, %0, c15, c12, 0" : : "r"(val)); in armv6_pmcr_write()
129 #define ARMV6_PMCR_ENABLE (1 << 0)
130 #define ARMV6_PMCR_CTR01_RESET (1 << 1)
131 #define ARMV6_PMCR_CCOUNT_RESET (1 << 2)
132 #define ARMV6_PMCR_CCOUNT_DIV (1 << 3)
133 #define ARMV6_PMCR_COUNT0_IEN (1 << 4)
134 #define ARMV6_PMCR_COUNT1_IEN (1 << 5)
135 #define ARMV6_PMCR_CCOUNT_IEN (1 << 6)
136 #define ARMV6_PMCR_COUNT0_OVERFLOW (1 << 8)
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H A Darm_v7_pmu.c661 #define ARMV7_PMNC_E (1 << 0) /* Enable all counters */
662 #define ARMV7_PMNC_P (1 << 1) /* Reset all counters */
663 #define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */
664 #define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */
665 #define ARMV7_PMNC_X (1 << 4) /* Export to ETM */
666 #define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
693 #define ARMV7_SDER_SUNIDEN BIT(1) /* Permit non-invasive debug */
698 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val)); in armv7_pmnc_read()
706 asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); in armv7_pmnc_write()
726 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (idx)); in armv7_pmnc_select_counter()
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/linux/drivers/iio/pressure/
H A Dmpl115.c21 #define MPL115_B2 0x08 /* 1 bit integer, 14 bit fraction */
30 s16 c12; member
70 a1 = data->b1 + ((data->c12 * tadc) >> 11); in mpl115_comp_pressure()
74 pcomp = (y1 + ((data->b2 * (int) tadc) >> 1)) >> 9; in mpl115_comp_pressure()
198 data->c12 = ret; in mpl115_probe()
234 gpiod_set_value(data->shutdown, 1); in mpl115_runtime_suspend()
/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_csc.c59 * y' = c10 * (x + d0) + c11 * (y + d1) + c12 * (z + d2) + const1
69 * c10 c11 c12 [d1 const1]
128 if ((i & 3) == 1) in sun8i_csc_set_coefficients()
129 base_reg = SUN8I_CSC_COEFF(base, i + 1); in sun8i_csc_set_coefficients()
131 base_reg = SUN8I_CSC_COEFF(base, i - 1); in sun8i_csc_set_coefficients()
161 if ((i & 3) == 1) in sun8i_de3_ccsc_set_coefficients()
164 i + 1); in sun8i_de3_ccsc_set_coefficients()
168 i - 1); in sun8i_de3_ccsc_set_coefficients()
/linux/drivers/pinctrl/aspeed/
H A Dpinctrl-aspeed-g4.c44 #define SCU80 0x80 /* Multi-function Pin Control #1 */
78 #define B5 1
79 SSSF_PIN_DECL(B5, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1));
224 #define SD2_DESC SIG_DESC_SET(SCU90, 1)
436 SSSF_PIN_DECL(E13, GPIOG1, SGPSLD, SIG_DESC_SET(SCU84, 1));
445 SIG_EXPR_LIST_DECL_SINGLE(B13, OSCCLK, OSCCLK, SIG_DESC_SET(SCU2C, 1));
469 #define BOOT_SRC_NOR { ASPEED_IP_SCU, HW_STRAP1, GENMASK(1, 0), 0, 0 }
530 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
690 #define VPI18_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 }
898 #define Y3_DESC SIG_DESC_SET(SCU88, 1)
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H A Dpinctrl-aspeed-g5.c45 #define SCU80 0x80 /* Multi-function Pin Control #1 */
60 #define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
69 #define D14 1
70 SSSF_PIN_DECL(D14, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1));
149 #define C12 16 macro
151 SIG_EXPR_LIST_DECL_SINGLE(C12, SD1CLK, SD1, SD1_DESC);
152 SIG_EXPR_LIST_DECL_SINGLE(C12, SCL10, I2C10, I2C10_DESC);
153 PIN_DECL_2(C12, GPIOC0, SD1CLK, SCL10);
160 FUNC_GROUP_DECL(I2C10, C12, A12);
200 FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11);
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H A Dpinctrl-aspeed-g6.c20 #define SCU400 0x400 /* Multi-function Pin Control #1 */
40 #define SCU500 0x500 /* Hardware Strap 1 */
43 #define SCU614 0x614 /* Disable GPIO Internal Pull-Down #1 */
62 #define M25 1
63 SIG_EXPR_LIST_DECL_SESG(M25, MDIO3, MDIO3, SIG_DESC_SET(SCU410, 1));
64 SIG_EXPR_LIST_DECL_SESG(M25, SDA11, I2C11, SIG_DESC_SET(SCU4B0, 1));
259 SIG_DESC_SET(SCU510, 1));
261 SIG_DESC_CLEAR(SCU510, 1));
268 SIG_DESC_SET(SCU510, 1));
270 SIG_DESC_CLEAR(SCU510, 1));
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/linux/drivers/gpu/drm/tidss/
H A Dtidss_dispc.c79 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
82 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
93 .num_vps = 1,
106 .num_planes = 1,
155 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
158 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
182 /* note: vid is plane_id 0 and vidl1 is plane_id 1 */
185 .vid_order = { 1, 0 },
244 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
247 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
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/linux/drivers/memory/
H A Djedec_ddr.h15 #define DDR_DENSITY_64Mb 1
27 #define DDR_TYPE_DDR2 1
35 #define DDR_IO_WIDTH_4 1
56 #define C12 12 macro
60 #define B2 1
80 #define DDR_MR1 1
103 #define MR4_TUF_MASK (1 << 7)
115 #define LPDDR2_MANID_SAMSUNG 1
132 #define LPDDR2_TYPE_S2 1
/linux/net/atm/
H A Dlec.h58 * 1. Dix Ethernet EtherType frames encoded by placing EtherType
104 * vcc will be torn down (C12)
/linux/arch/arm/mm/
H A Dnommu.c54 asm("mcr p15, 0, %0, c12, c0, 0" : : "r" (val) : "cc"); in set_vbar()
109 memblock_reserve(0, 1); in arm_mm_memblock_reserve()
149 high_memory = __va(end - 1) + 1; in adjust_lowmem_bounds()
/linux/Documentation/input/devices/
H A Dxpad.rst89 work UNLESS you set "dpad_to_buttons" to 1 in the module configuration.
122 can be found on the net ([1]_, [2]_, [3]_).
141 D: Ver= 1.10 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=32 #Cfgs= 1
143 C:* #Ifs= 1 Cfg#= 1 Atr=80 MxPwr=100mA
152 D: Ver= 1.10 Cls=00(>ifc ) Sub=00 Prot=00 MxPS= 8 #Cfgs= 1
153 P: Vendor=0c12 ProdID=8809 Rev= 0.01
155 C:* #Ifs= 1 Cfg#= 1 Atr=80 MxPwr=100mA
218 .. [1] http://euc.jp/periphs/xbox-controller.ja.html (ITO Takayuki) citation in References
/linux/arch/arm/mach-omap2/
H A Dsram242x.S38 mov r3, #0x1 @ value for 1x operation
48 cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
94 * wait for it to finish, use 32k sync counter, 1tick=31uS.
132 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
151 moveq r5, r5, lsr #1 @ divide by 2 if to half
152 movne r5, r5, lsl #1 @ mult by 2 if to full
154 add r5, r5, #0x1 @ turn on burst of 1
160 str r3, [r4] @ set new state (pll/x, x=1 or 2)
189 * wait for it to finish, use 32k sync counter, 1tick=31uS.
235 mcrr p15, 1, r8, r4, c12 @ preload into icache
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H A Dsram243x.S38 mov r3, #0x1 @ value for 1x operation
48 cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
94 * wait for it to finish, use 32k sync counter, 1tick=31uS.
132 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
151 moveq r5, r5, lsr #1 @ divide by 2 if to half
152 movne r5, r5, lsl #1 @ mult by 2 if to full
154 add r5, r5, #0x1 @ turn on burst of 1
160 str r3, [r4] @ set new state (pll/x, x=1 or 2)
189 * wait for it to finish, use 32k sync counter, 1tick=31uS.
235 mcrr p15, 1, r8, r4, c12 @ preload into icache
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/linux/drivers/gpu/drm/vc4/
H A Dvc4_hvs.c86 readl((u32 __iomem *)hvs->dlist + i + 1), in vc4_hvs_dump_state()
164 c9, c10, c11, c12, c13, c14, c15) \ argument
169 VC4_PPF_FILTER_WORD(c12, c13, c14), \
173 #define VC4_KERNEL_DWORDS (VC4_LINEAR_PHASE_KERNEL_DWORDS * 2 - 1)
175 /* Recommended B=1/3, C=1/3 filter choice from Mitchell/Netravali.
207 writel(kernel[VC4_KERNEL_DWORDS - i - 1], in vc4_hvs_upload_linear_kernel()
280 case 1: in vc4_hvs_get_fifo_frame_count()
316 case 1: in vc4_hvs_get_fifo_from_output()
317 return 1; in vc4_hvs_get_fifo_from_output()
465 * 1:1 with connectors.) in vc4_hvs_atomic_check()
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/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-pocketbeagle.dts131 "[USR LED 1]",
152 "[SYSBOOT 1]",
196 "P1.33 [PRU0.1]",
417 …AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE5)/* (C12) mcasp0_ahclkr.pr1…
482 ti,adc-channels = <0 1 2 3 4 5 6 7>;
H A Dam335x-boneblue.dts322 #address-cells = <1>;
323 #size-cells = <1>;
345 #address-cells = <1>;
366 interrupts = <0>, <1>;
390 dmas = <&edma_xbar 12 0 1
402 #address-cells = <1>;
415 ti,adc-channels = <0 1 2 3 4 5 6 7>;
569 "GPIO3_17", /* C12 */
/linux/drivers/staging/media/ipu3/include/uapi/
H A Dintel-ipu3.h19 #define V4L2_CID_INTEL_IPU3_MODE (V4L2_CID_INTEL_IPU3_BASE + 1)
26 #define IPU3_UAPI_GRID_START_MASK ((1 << 12) - 1)
27 #define IPU3_UAPI_GRID_Y_START_EN (1 << 15)
30 #define IPU3_UAPI_AWB_RGBS_THR_B_EN (1 << 14)
31 #define IPU3_UAPI_AWB_RGBS_THR_B_INCL_SAT (1 << 15)
182 * 1: write normally.
183 * @rst_hist_array: write 1 to trigger histogram array reset.
200 __u8 ae_en:1;
201 __u8 rst_hist_array:1;
202 __u8 done_rst_hist_array:1;
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c82 "C11 C12 C13 C14 " in dcn30_log_color_state()
104 ((s.pre_dgam_select == 1) ? "Gamma 2.2" : in dcn30_log_color_state()
112 ((s.gamcor_mode == 1) ? "RAM A" : in dcn30_log_color_state()
114 (s.shaper_lut_mode == 1) ? "RAM A" : in dcn30_log_color_state()
117 (s.lut3d_mode == 1) ? "RAM A" : in dcn30_log_color_state()
123 ((s.rgam_lut_mode == 1) ? "RAM A" : in dcn30_log_color_state()
126 ((s.gamut_remap.gamut_adjust_type == 1) ? "HW" : in dcn30_log_color_state()
129 s.gamut_remap.temperature_matrix[1].value, in dcn30_log_color_state()
165 "C11 C12 C13 C14 " in dcn30_log_color_state()
184 (s.shaper_lut_mode == 1) ? "RAM A" : in dcn30_log_color_state()
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/linux/arch/powerpc/crypto/
H A Dchacha-p10le-8x.S14 # 1. a += b; d ^= a; d <<<= 16;
33 # a12 b12 c12 d12
80 std 0, 16(1)
81 stdu 1,-752(1)
83 SAVE_GPR 14, 112, 1
84 SAVE_GPR 15, 120, 1
85 SAVE_GPR 16, 128, 1
86 SAVE_GPR 17, 136, 1
87 SAVE_GPR 18, 144, 1
88 SAVE_GPR 19, 152, 1
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/linux/drivers/pinctrl/
H A Dpinctrl-ep93xx.c120 PINCTRL_PIN(1, "CSn[7]"),
124 PINCTRL_PIN(5, "CSn[1]"),
136 PINCTRL_PIN(17, "SDCSn[1]"),
142 PINCTRL_PIN(23, "DQMn[1]"),
165 PINCTRL_PIN(46, "AD[1]"),
191 PINCTRL_PIN(72, "DA[1]"),
202 PINCTRL_PIN(83, "BOOT[1]"),
221 PINCTRL_PIN(102, "INT[1]"),
229 PINCTRL_PIN(110, "RXD[1]"),
233 PINCTRL_PIN(114, "TXD[1]"),
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