Lines Matching +full:1 +full:c12
45 #define SCU80 0x80 /* Multi-function Pin Control #1 */
60 #define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
69 #define D14 1
70 SSSF_PIN_DECL(D14, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1));
149 #define C12 16 macro
151 SIG_EXPR_LIST_DECL_SINGLE(C12, SD1CLK, SD1, SD1_DESC);
152 SIG_EXPR_LIST_DECL_SINGLE(C12, SCL10, I2C10, I2C10_DESC);
153 PIN_DECL_2(C12, GPIOC0, SD1CLK, SCL10);
160 FUNC_GROUP_DECL(I2C10, C12, A12);
200 FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11);
202 #define SD2_DESC SIG_DESC_SET(SCU90, 1)
432 SIG_EXPR_LIST_DECL_SINGLE(E19, SGPS1LD, SGPS1, COND1, SIG_DESC_SET(SCU84, 1));
516 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
695 #define VPIOFF1_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 }
813 #define W2_DESC SIG_DESC_SET(SCU88, 1)
990 SSSF_PIN_DECL(B10, GPIOQ6, OSCCLK, SIG_DESC_SET(SCU2C, 1));
1023 #define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
1024 #define VPO_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 }
1025 #define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 }
1026 #define VPOOFF2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 }
1045 #define U19_DESC SIG_DESC_SET(SCU8C, 1)
1148 SIG_EXPR_LIST_DECL_SINGLE(E9, GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1));
1370 SIG_EXPR_LIST_DECL_SINGLE(G3, GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1));
1544 #define CRT_DVO_DD_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 1, 1 }
1755 #define T21_DESC SIG_DESC_SET(SCUA8, 1)
1812 SIG_EXPR_LIST_DECL_SINGLE(G20, LAD1, LAD1, SIG_DESC_SET(SCUAC, 1));
1868 #define USB2BD_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 1, 0 }
1900 /* Pins, groups and functions are sort(1):ed alphabetically for sanity */
1960 ASPEED_PINCTRL_PIN(C12),
2491 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C12, B11, SCU8C, 18),
2492 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C12, B11, SCU8C, 18),
2556 /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
2655 "aspeed,external-nodes", 1); in aspeed_g5_acquire_regmap()
2701 return 1; in aspeed_g5_sig_expr_eval()
2794 { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)},
2795 { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
2796 { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
2798 { PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)},