Lines Matching +full:1 +full:c12

119 	asm volatile("mrc   p15, 0, %0, c15, c12, 0" : "=r"(val));  in armv6_pmcr_read()
126 	asm volatile("mcr   p15, 0, %0, c15, c12, 0" : : "r"(val));  in armv6_pmcr_write()
129 #define ARMV6_PMCR_ENABLE		(1 << 0)
130 #define ARMV6_PMCR_CTR01_RESET		(1 << 1)
131 #define ARMV6_PMCR_CCOUNT_RESET		(1 << 2)
132 #define ARMV6_PMCR_CCOUNT_DIV		(1 << 3)
133 #define ARMV6_PMCR_COUNT0_IEN		(1 << 4)
134 #define ARMV6_PMCR_COUNT1_IEN		(1 << 5)
135 #define ARMV6_PMCR_CCOUNT_IEN		(1 << 6)
136 #define ARMV6_PMCR_COUNT0_OVERFLOW	(1 << 8)
137 #define ARMV6_PMCR_COUNT1_OVERFLOW	(1 << 9)
138 #define ARMV6_PMCR_CCOUNT_OVERFLOW	(1 << 10)
167 		WARN_ONCE(1, "invalid counter number (%d)\n", counter);  in armv6_pmcr_counter_has_overflowed()
179 		asm volatile("mrc   p15, 0, %0, c15, c12, 1" : "=r"(value));  in armv6pmu_read_counter()
181 		asm volatile("mrc   p15, 0, %0, c15, c12, 2" : "=r"(value));  in armv6pmu_read_counter()
183 		asm volatile("mrc   p15, 0, %0, c15, c12, 3" : "=r"(value));  in armv6pmu_read_counter()
185 		WARN_ONCE(1, "invalid counter number (%d)\n", counter);  in armv6pmu_read_counter()
196 		asm volatile("mcr   p15, 0, %0, c15, c12, 1" : : "r"(value));  in armv6pmu_write_counter()
198 		asm volatile("mcr   p15, 0, %0, c15, c12, 2" : : "r"(value));  in armv6pmu_write_counter()
200 		asm volatile("mcr   p15, 0, %0, c15, c12, 3" : : "r"(value));  in armv6pmu_write_counter()
202 		WARN_ONCE(1, "invalid counter number (%d)\n", counter);  in armv6pmu_write_counter()
223 		WARN_ONCE(1, "invalid counter number (%d)\n", idx);  in armv6pmu_enable_event()
362 		WARN_ONCE(1, "invalid counter number (%d)\n", idx);  in armv6pmu_disable_event()