Lines Matching +full:1 +full:c12
20 #define SCU400 0x400 /* Multi-function Pin Control #1 */
40 #define SCU500 0x500 /* Hardware Strap 1 */
43 #define SCU614 0x614 /* Disable GPIO Internal Pull-Down #1 */
62 #define M25 1
63 SIG_EXPR_LIST_DECL_SESG(M25, MDIO3, MDIO3, SIG_DESC_SET(SCU410, 1));
64 SIG_EXPR_LIST_DECL_SESG(M25, SDA11, I2C11, SIG_DESC_SET(SCU4B0, 1));
259 SIG_DESC_SET(SCU510, 1));
261 SIG_DESC_CLEAR(SCU510, 1));
268 SIG_DESC_SET(SCU510, 1));
270 SIG_DESC_CLEAR(SCU510, 1));
277 SIG_DESC_SET(SCU510, 1));
279 SIG_DESC_CLEAR(SCU510, 1));
286 SIG_DESC_SET(SCU510, 1));
288 SIG_DESC_CLEAR(SCU510, 1));
295 SIG_DESC_SET(SCU510, 1));
300 SIG_EXPR_LIST_DECL_SESG(D24, NRTS3, NRTS3, SIG_DESC_SET(SCU414, 1));
301 SIG_EXPR_LIST_DECL_SESG(D24, RGMII4TXD3, RGMII4, SIG_DESC_SET(SCU4B4, 1),
302 SIG_DESC_SET(SCU510, 1));
309 SIG_DESC_SET(SCU510, 1));
311 SIG_DESC_CLEAR(SCU510, 1));
318 SIG_DESC_SET(SCU510, 1));
325 SIG_DESC_SET(SCU510, 1));
327 SIG_DESC_CLEAR(SCU510, 1));
334 SIG_DESC_SET(SCU510, 1));
336 SIG_DESC_CLEAR(SCU510, 1));
343 SIG_DESC_SET(SCU510, 1));
345 SIG_DESC_CLEAR(SCU510, 1));
352 SIG_DESC_SET(SCU510, 1));
354 SIG_DESC_CLEAR(SCU510, 1));
417 SIG_DESC_SET(SCU450, 1));
425 SIG_DESC_SET(SCU450, 1));
436 SIG_DESC_SET(SCU450, 1));
445 SIG_DESC_SET(SCU450, 1));
456 SIG_DESC_SET(SCU450, 1));
465 SIG_DESC_SET(SCU450, 1));
476 SIG_DESC_SET(SCU450, 1));
485 SIG_DESC_SET(SCU450, 1));
544 SIG_EXPR_LIST_DECL_SESG(A16, MTDI, JTAGM, SIG_DESC_SET(SCU418, 1));
545 SIG_EXPR_LIST_DECL_SEMG(A16, RXD12, UART12G0, UART12, SIG_DESC_SET(SCU4B8, 1));
713 SSSF_PIN_DECL(B13, GPIOM1, NDCD1, SIG_DESC_SET(SCU41C, 1));
724 #define C12 101 macro
725 SSSF_PIN_DECL(C12, GPIOM5, NRTS1, SIG_DESC_SET(SCU41C, 5));
852 SSSF_PIN_DECL(AB25, GPIOQ1, TACH1, SIG_DESC_SET(SCU430, 1));
1002 SIG_EXPR_LIST_DECL_SEMG(AA17, SALT10, SALT10G1, SALT10, SIG_DESC_SET(SCU434, 1),
1004 SIG_EXPR_LIST_DECL_SESG(AA17, GPIU1, GPIU1, SIG_DESC_SET(SCU434, 1),
1222 SIG_EXPR_LIST_DECL_SESG(AD12, SALT6, SALT6, SIG_DESC_SET(SCU438, 1));
1223 SIG_EXPR_LIST_DECL_SESG(AD12, WDTRST2, WDTRST2, SIG_DESC_SET(SCU4D8, 1));
1310 SIG_EXPR_LIST_DECL_SESG(D6, RGMII1TXCTL, RGMII1, SIG_DESC_SET(SCU400, 1),
1312 SIG_EXPR_LIST_DECL_SESG(D6, RMII1TXEN, RMII1, SIG_DESC_SET(SCU400, 1),
1508 SIG_EXPR_LIST_DECL_SEMG(Y2, EMMCDAT5, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 1));
1587 #define USB2AD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 1, 0 }
1591 #define USB2BD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 1, 0 }
1639 /* Pins, groups and functions are sort(1):ed alphabetically for sanity */
1769 ASPEED_PINCTRL_PIN(C12),
2431 ASPEED_PULL_DOWN_PINCONF(A16, SCU618, 1),
2491 ASPEED_PULL_DOWN_PINCONF(C12, SCU61C, 5),
2499 ASPEED_PULL_DOWN_PINCONF(B13, SCU61C, 1),
2598 ASPEED_PULL_DOWN_PINCONF(AD12, SCU638, 1),
2617 { PIN_CONFIG_DRIVE_STRENGTH, { H24, E26 }, SCU458, GENMASK(1, 0)},
2632 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B2, D3, SCU40C, 1),
2633 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B2, D3, SCU40C, 1),
2678 * The strapping registers implement write-1-clear in aspeed_g6_sig_expr_set()
2707 { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)},
2708 { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
2709 { PIN_CONFIG_BIAS_PULL_UP, 0, 1, BIT_MASK(0)},
2710 { PIN_CONFIG_BIAS_PULL_UP, -1, 0, BIT_MASK(0)},
2711 { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
2712 { PIN_CONFIG_DRIVE_STRENGTH, 4, 0, GENMASK(1, 0)},
2713 { PIN_CONFIG_DRIVE_STRENGTH, 8, 1, GENMASK(1, 0)},
2714 { PIN_CONFIG_DRIVE_STRENGTH, 12, 2, GENMASK(1, 0)},
2715 { PIN_CONFIG_DRIVE_STRENGTH, 16, 3, GENMASK(1, 0)},
2717 { PIN_CONFIG_POWER_SOURCE, 1800, 1, BIT_MASK(0)},