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/linux/drivers/power/supply/
H A Dbd99954-charger.h1 /* SPDX-License-Identifier: GPL-2.0-only */
482 [F_PREV_CHGSTM_STATE] = REG_FIELD(CHGSTM_STATUS, 8, 14),
498 [F_VRBOOST_TRIG] = REG_FIELD(VIN_CTRL_SET, 14, 14),
508 [F_SDP_500_SEL] = REG_FIELD(CHGOP_SET1, 14, 14),
517 [F_ILIM_RESET_EN] = REG_FIELD(CHGOP_SET2, 14, 14),
528 [F_VBUSCLPS_TH_SET] = REG_FIELD(VBUSCLPS_TH_SET, 7, 14),
529 [F_VCCCLPS_TH_SET] = REG_FIELD(VCCCLPS_TH_SET, 7, 14),
534 [F_VSYSREG_SET] = REG_FIELD(VSYSREG_SET, 6, 14),
535 [F_VSYSVAL_THH_SET] = REG_FIELD(VSYSVAL_THH_SET, 6, 14),
536 [F_VSYSVAL_THL_SET] = REG_FIELD(VSYSVAL_THL_SET, 6, 14),
[all …]
/linux/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-lite-reg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include "fimc-lite.h"
15 #define FLITE_REG_CISRCSIZE_ORDER422_IN_YCBYCR (0 << 14)
16 #define FLITE_REG_CISRCSIZE_ORDER422_IN_YCRYCB (1 << 14)
17 #define FLITE_REG_CISRCSIZE_ORDER422_IN_CBYCRY (2 << 14)
18 #define FLITE_REG_CISRCSIZE_ORDER422_IN_CRYCBY (3 << 14)
19 #define FLITE_REG_CISRCSIZE_ORDER422_MASK (0x3 << 14)
30 #define FLITE_REG_CIGCTRL_USER(x) ((0x30 + x - 1) << 24)
32 #define FLITE_REG_CIGCTRL_SHADOWMASK_DISABLE BIT(21)
33 #define FLITE_REG_CIGCTRL_ODMA_DISABLE BIT(20)
[all …]
H A Dfimc-reg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
13 #include "fimc-core.h"
17 #define FIMC_REG_CISRCFMT_ITU601_8BIT BIT(31)
18 #define FIMC_REG_CISRCFMT_ITU601_16BIT BIT(29)
19 #define FIMC_REG_CISRCFMT_ORDER422_YCBYCR (0 << 14)
20 #define FIMC_REG_CISRCFMT_ORDER422_YCRYCB (1 << 14)
21 #define FIMC_REG_CISRCFMT_ORDER422_CBYCRY (2 << 14)
22 #define FIMC_REG_CISRCFMT_ORDER422_CRYCBY (3 << 14)
26 #define FIMC_REG_CIWDOFST_OFF_EN BIT(31)
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/linux/drivers/comedi/drivers/
H A Dni_tio_internal.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * COMEDI - Linux Control and Measurement Device Interface
17 #define GI_ARM BIT(0)
18 #define GI_SAVE_TRACE BIT(1)
19 #define GI_LOAD BIT(2)
20 #define GI_DISARM BIT(4)
23 #define GI_WRITE_SWITCH BIT(7)
24 #define GI_SYNC_GATE BIT(8)
25 #define GI_LITTLE_BIG_ENDIAN BIT(9)
26 #define GI_BANK_SWITCH_START BIT(10)
[all …]
H A Dni_stc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
28 #define NISTC_INTA_ACK_AI_STOP BIT(12)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
41 #define MT_TX_FREE_WLAN_ID GENMASK(23, 14)
44 #define MT_TX_FREE_STATUS GENMASK(14, 13)
46 #define MT_TX_FREE_PAIR BIT(31)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
56 #define MT_TXD1_TGID BIT(30)
58 #define MT_TXD1_AMSDU BIT(23)
63 #define MT_TXD1_ETH_802_3 BIT(15)
64 #define MT_TXD1_VTA BIT(10)
67 #define MT_TXD2_FIX_RATE BIT(31)
[all …]
H A Dmt76_connac3_mac.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_RXD0_MESH BIT(18)
29 #define MT_RXD0_MHCP BIT(19)
38 #define MT_RXD1_NORMAL_GROUP_1 BIT(16)
39 #define MT_RXD1_NORMAL_GROUP_2 BIT(17)
40 #define MT_RXD1_NORMAL_GROUP_3 BIT(18)
41 #define MT_RXD1_NORMAL_GROUP_4 BIT(19)
42 #define MT_RXD1_NORMAL_GROUP_5 BIT(20)
44 #define MT_RXD1_NORMAL_CM BIT(23)
45 #define MT_RXD1_NORMAL_CLM BIT(24)
[all …]
/linux/drivers/media/platform/samsung/s3c-camif/
H A Dcamif-regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include "camif-core.h"
15 #include <media/drv-intf/s3c_camif.h>
19 * id = 0 - codec (FIMC C), 1 - preview (FIMC P).
24 #define CISRCFMT_ITU601_8BIT BIT(31)
26 #define CISRCFMT_ORDER422_YCBYCR (0 << 14)
27 #define CISRCFMT_ORDER422_YCRYCB (1 << 14)
28 #define CISRCFMT_ORDER422_CBYCRY (2 << 14)
29 #define CISRCFMT_ORDER422_CRYCBY (3 << 14)
30 #define CISRCFMT_ORDER422_MASK (3 << 14)
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/linux/drivers/net/wireless/realtek/rtw89/
H A Dtxrx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
28 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_rate_mode()
41 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_ht_mcs()
49 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_mcs()
62 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_nss()
71 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23)
72 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22)
73 #define RTW89_TXWD_BODY0_FW_DL BIT(20)
76 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7)
77 #define RTW89_TXWD_BODY0_HW_AMSDU BIT(5)
[all …]
H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
9 #define B_AX_AUTOLOAD_SUS BIT(5)
12 #define B_AX_PWC_EV2EF_MASK GENMASK(15, 14)
13 #define B_AX_PWC_EV2EF_B15 BIT(15)
14 #define B_AX_PWC_EV2EF_B14 BIT(14)
15 #define B_AX_ISO_EB2CORE BIT(8)
18 #define B_AX_FEN_BB_GLB_RSTN BIT(1)
19 #define B_AX_FEN_BBRSTB BIT(0)
22 #define B_AX_SOP_ASWRM BIT(31)
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/linux/drivers/staging/sm750fb/
H A Dddk750_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
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/linux/tools/arch/arm64/include/asm/
H A Dsysreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #include <asm/gpr-num.h>
21 * [20-19] : Op0
22 * [18-16] : Op1
23 * [15-12] : CRn
24 * [11-8] : CRm
25 * [7-5] : Op2
82 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
122 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
123 #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)
[all …]
/linux/drivers/net/ethernet/amazon/ena/
H A Dena_eth_io_defs.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
24 /* 15:0 : length - Buffer length in bytes, must
26 * to update like End-to-End CRC, Authentication GMAC
29 * the 4-byte added in the end for 802.3 Ethernet FCS
30 * 21:16 : req_id_hi - Request ID[15:10]
31 * 22 : reserved22 - MBZ
32 * 23 : meta_desc - MBZ
34 * 25 : reserved1 - MBZ
35 * 26 : first - Indicates first descriptor in
[all …]
/linux/drivers/net/ethernet/asix/
H A Dax88796c_main.h1 /* SPDX-License-Identifier: GPL-2.0-only */
25 #define AX88796C_PHY_REGDUMP_LEN 14
121 #define AX_FC_RX BIT(0)
122 #define AX_FC_TX BIT(1)
123 #define AX_FC_ANEG BIT(2)
126 #define AX_CAP_COMP BIT(0)
153 #define PSR_DEV_READY BIT(7)
155 #define PSR_RESET_CLR BIT(15)
158 #define FER_IPALM BIT(0)
159 #define FER_DCRC BIT(1)
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/linux/drivers/iio/imu/
H A Dadis16400.c1 // SPDX-License-Identifier: GPL-2.0-only
31 #define ADIS16400_XGYRO_OUT 0x04 /* X-axis gyroscope output */
32 #define ADIS16400_YGYRO_OUT 0x06 /* Y-axis gyroscope output */
33 #define ADIS16400_ZGYRO_OUT 0x08 /* Z-axis gyroscope output */
34 #define ADIS16400_XACCL_OUT 0x0A /* X-axis accelerometer output */
35 #define ADIS16400_YACCL_OUT 0x0C /* Y-axis accelerometer output */
36 #define ADIS16400_ZACCL_OUT 0x0E /* Z-axis accelerometer output */
37 #define ADIS16400_XMAGN_OUT 0x10 /* X-axis magnetometer measurement */
38 #define ADIS16400_YMAGN_OUT 0x12 /* Y-axis magnetometer measurement */
39 #define ADIS16400_ZMAGN_OUT 0x14 /* Z-axis magnetometer measurement */
[all …]
/linux/include/soc/mscc/
H A Docelot_ana.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14 #define ANA_ANAGEFIL_PID_EN BIT(19)
15 #define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14))
16 #define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14)
17 #define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14)
18 #define ANA_ANAGEFIL_VID_EN BIT(13)
27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
[all …]
/linux/drivers/phy/mediatek/
H A Dphy-mtk-hdmi-mt8195.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/clk-provider.h>
28 #define RG_HDMITX21_DRV_IBIAS_D0 GENMASK(19, 14)
34 #define RG_HDMITX21_VREF_SEL BIT(4)
35 #define RG_HDMITX21_BIAS_PE_VREF_SELB BIT(10)
37 #define RG_HDMITX21_BG_PWD BIT(20)
41 #define RG_HDMITX21_DRV_IMP_D1_EN1 GENMASK(19, 14)
46 #define RG_HDMITX21_CKLDO_EN BIT(3)
47 #define RG_HDMITX21_SLDOLPF_EN BIT(7)
51 #define RG_HDMITX21_D2_DRV_OP_EN BIT(8)
[all …]
/linux/drivers/net/phy/mscc/
H A Dmscc_macsec.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
17 #define CONTROL_IV0 BIT(5)
18 #define CONTROL_IV1 BIT(6)
19 #define CONTROL_IV2 BIT(7)
20 #define CONTROL_UPDATE_SEQ BIT(13)
21 #define CONTROL_IV_IN_SEQ BIT(14)
22 #define CONTROL_ENCRYPT_AUTH BIT(15)
23 #define CONTROL_KEY_IN_CTX BIT(16)
33 #define CONTROL_SEQ_MASK BIT(30)
34 #define CONTROL_CONTEXT_ID BIT(31)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
34 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
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/linux/drivers/mmc/host/
H A Dmeson-mx-sdhc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
15 #define MESON_SDHC_SEND_CMD_HAS_RESP BIT(6)
16 #define MESON_SDHC_SEND_CMD_HAS_DATA BIT(7)
17 #define MESON_SDHC_SEND_RESP_LEN BIT(8)
18 #define MESON_SDHC_SEND_RESP_NO_CRC BIT(9)
19 #define MESON_SDHC_SEND_DATA_DIR BIT(10)
20 #define MESON_SDHC_SEND_DATA_STOP BIT(11)
21 #define MESON_SDHC_SEND_R1B BIT(12)
26 #define MESON_SDHC_CTRL_DDR_MODE BIT(2)
27 #define MESON_SDHC_CTRL_TX_CRC_NOCHECK BIT(3)
[all …]
/linux/arch/parisc/include/asm/
H A Delf.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */
29 #define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */
30 #define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */
60 #define R_PARISC_DIR32 1 /* Direct 32-bit reference. */
64 #define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */
65 #define R_PARISC_PCREL32 9 /* 32-bit rel. address. */
69 #define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */
71 #define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */
72 #define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */
[all …]
/linux/drivers/media/platform/amlogic/meson-ge2d/
H A Dge2d-regs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 #define GE2D_DST_BYTEMASK_ONLY BIT(31)
17 #define GE2D_DST_BITMASK_EN BIT(30)
18 #define GE2D_SRC2_KEY_EN BIT(29)
19 #define GE2D_SRC2_KEY_MODE BIT(28)
20 #define GE2D_SRC1_KEY_EN BIT(27)
21 #define GE2D_SRC1_KEY_MODE BIT(26)
23 #define GE2D_DST_CLIP_MODE BIT(23)
25 #define GE2D_SRC2_FILL_MODE BIT(14)
27 #define GE2D_SRC2_X_YC_RATIO BIT(11)
[all …]
/linux/drivers/iio/accel/
H A Dadis16209.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ADIS16209 Dual-Axis Digital Inclinometer and Accelerometer
27 /* Output, +/- 90 degrees X-axis inclination */
30 /* Output, +/-180 vertical rotational position */
57 #define ADIS16209_MSC_CTRL_PWRUP_SELF_TEST BIT(10)
58 #define ADIS16209_MSC_CTRL_SELF_TEST_EN BIT(8)
59 #define ADIS16209_MSC_CTRL_DATA_RDY_EN BIT(2)
60 /* Data-ready polarity: 1 = active high, 0 = active low */
61 #define ADIS16209_MSC_CTRL_ACTIVE_HIGH BIT(1)
62 #define ADIS16209_MSC_CTRL_DATA_RDY_DIO2 BIT(0)
[all …]
/linux/drivers/net/ipa/reg/
H A Dipa_reg-v5.0.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
22 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
23 [GSI_SNOC_BYPASS_DIS] = BIT(1),
24 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
25 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
26 /* Bit 4 reserved */
27 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
28 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
29 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[all …]
H A Dipa_reg-v5.5.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
22 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
23 [GSI_SNOC_BYPASS_DIS] = BIT(1),
24 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
25 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
26 /* Bit 4 reserved */
27 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
28 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
29 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[all …]

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