Lines Matching +full:14 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include "fimc-lite.h"
15 #define FLITE_REG_CISRCSIZE_ORDER422_IN_YCBYCR (0 << 14)
16 #define FLITE_REG_CISRCSIZE_ORDER422_IN_YCRYCB (1 << 14)
17 #define FLITE_REG_CISRCSIZE_ORDER422_IN_CBYCRY (2 << 14)
18 #define FLITE_REG_CISRCSIZE_ORDER422_IN_CRYCBY (3 << 14)
19 #define FLITE_REG_CISRCSIZE_ORDER422_MASK (0x3 << 14)
30 #define FLITE_REG_CIGCTRL_USER(x) ((0x30 + x - 1) << 24)
32 #define FLITE_REG_CIGCTRL_SHADOWMASK_DISABLE BIT(21)
33 #define FLITE_REG_CIGCTRL_ODMA_DISABLE BIT(20)
34 #define FLITE_REG_CIGCTRL_SWRST_REQ BIT(19)
35 #define FLITE_REG_CIGCTRL_SWRST_RDY BIT(18)
36 #define FLITE_REG_CIGCTRL_SWRST BIT(17)
37 #define FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR BIT(15)
38 #define FLITE_REG_CIGCTRL_INVPOLPCLK BIT(14)
39 #define FLITE_REG_CIGCTRL_INVPOLVSYNC BIT(13)
40 #define FLITE_REG_CIGCTRL_INVPOLHREF BIT(12)
42 #define FLITE_REG_CIGCTRL_IRQ_LASTEN BIT(8)
43 #define FLITE_REG_CIGCTRL_IRQ_ENDEN BIT(7)
44 #define FLITE_REG_CIGCTRL_IRQ_STARTEN BIT(6)
45 #define FLITE_REG_CIGCTRL_IRQ_OVFEN BIT(5)
47 #define FLITE_REG_CIGCTRL_SELCAM_MIPI BIT(3)
51 #define FLITE_REG_CIIMGCPT_IMGCPTEN BIT(31)
52 #define FLITE_REG_CIIMGCPT_CPT_FREN BIT(25)
61 #define FLITE_REG_CIWDOFST_WINOFSEN BIT(31)
62 #define FLITE_REG_CIWDOFST_CLROVIY BIT(31)
63 #define FLITE_REG_CIWDOFST_CLROVFICB BIT(15)
64 #define FLITE_REG_CIWDOFST_CLROVFICR BIT(14)
72 #define FLITE_REG_CIODMAFMT_RAW_CON BIT(15)
73 #define FLITE_REG_CIODMAFMT_PACK12 BIT(14)
93 #define FLITE_REG_CISTATUS_MIPI_VVALID BIT(22)
94 #define FLITE_REG_CISTATUS_MIPI_HVALID BIT(21)
95 #define FLITE_REG_CISTATUS_MIPI_DVALID BIT(20)
96 #define FLITE_REG_CISTATUS_ITU_VSYNC BIT(14)
97 #define FLITE_REG_CISTATUS_ITU_HREFF BIT(13)
98 #define FLITE_REG_CISTATUS_OVFIY BIT(10)
99 #define FLITE_REG_CISTATUS_OVFICB BIT(9)
100 #define FLITE_REG_CISTATUS_OVFICR BIT(8)
101 #define FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW BIT(7)
102 #define FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND BIT(6)
103 #define FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART BIT(5)
104 #define FLITE_REG_CISTATUS_IRQ_SRC_FRMEND BIT(4)
105 #define FLITE_REG_CISTATUS_IRQ_CAM BIT(0)
110 #define FLITE_REG_CISTATUS2_LASTCAPEND BIT(1)
111 #define FLITE_REG_CISTATUS2_FRMEND BIT(0)
115 #define FLITE_REG_CITHOLD_W_QOS_EN BIT(30)
119 /* b0: 1 - camera B, 0 - camera A */
120 #define FLITE_REG_CIGENERAL_CAM_B BIT(0)
125 /* ----------------------------------------------------------------------------
150 writel(mask, dev->regs + FLITE_REG_CIFCNTSEQ); in flite_hw_set_dma_buf_mask()