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Searched +full:10 +full:base (Results 1 – 25 of 1507) sorted by relevance

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/linux/tools/perf/tests/shell/
H A Ddaemon.sh9 local base=$3
30 if [ "${base}" != "${line_base}" ]; then
31 echo "FAILED: wrong base"
56 local base=$4
87 if [ "${base}" != "${line_base}" ]; then
88 echo "FAILED: wrong base"
163 local base
164 base=$(mktemp -d /tmp/perf.daemon.base.XXX)
168 base=BASE
171 run = -e cpu-clock -m 1 sleep 10
[all …]
/linux/arch/arm/mach-rpc/
H A Dirq.c18 0, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10,
19 12, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10,
20 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
21 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
22 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10,
23 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10,
24 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
25 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
26 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10,
27 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10,
[all …]
/linux/drivers/rtc/
H A Drtc-renesas-rtca3.c106 * @ten_sec: PPB per cycle in 10 seconds adjutment mode
116 * @base: base address
126 void __iomem *base; member
140 tmp = readb(priv->base + off); in rtca3_byte_update_bits()
143 writeb(tmp, priv->base + off); in rtca3_byte_update_bits()
150 val = readb(priv->base + RTCA3_RSR); in rtca3_alarm_handler_helper()
152 writeb(val & ~pending, priv->base + RTCA3_RSR); in rtca3_alarm_handler_helper()
179 val = readb(priv->base + RTCA3_RSR); in rtca3_periodic_handler()
183 writeb(val & ~pending, priv->base + RTCA3_RSR); in rtca3_periodic_handler()
196 readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, val, in rtca3_periodic_handler()
[all …]
/linux/include/uapi/linux/
H A Dmii.h23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
37 #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
52 #define BMCR_SPEED10 0x0000 /* Select 10Mbps */
63 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
64 #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
65 #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
66 #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
74 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
75 #define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
[all …]
/linux/arch/x86/kernel/cpu/mtrr/
H A Dcleanup.c53 unsigned long base, size; in x86_get_mtrr_mem_range() local
61 base = range_state[i].base_pfn; in x86_get_mtrr_mem_range()
64 base, base + size); in x86_get_mtrr_mem_range()
81 base = range_state[i].base_pfn; in x86_get_mtrr_mem_range()
82 if (base < (1<<(20-PAGE_SHIFT)) && mtrr_state.have_fixed && in x86_get_mtrr_mem_range()
87 if (base + size <= (1<<(20-PAGE_SHIFT))) in x86_get_mtrr_mem_range()
89 size -= (1<<(20-PAGE_SHIFT)) - base; in x86_get_mtrr_mem_range()
90 base = 1<<(20-PAGE_SHIFT); in x86_get_mtrr_mem_range()
92 subtract_range(range, RANGE_NUM, base, base + size); in x86_get_mtrr_mem_range()
153 u64 base, mask; in set_var_mtrr() local
[all …]
/linux/sound/i2c/other/
H A Dpt2258.c24 0x80, 0x90, /* channel 1: -10dB, -1dB */
25 0x40, 0x50, /* channel 2: -10dB, -1dB */
26 0x00, 0x10, /* channel 3: -10dB, -1dB */
27 0x20, 0x30, /* channel 4: -10dB, -1dB */
28 0x60, 0x70, /* channel 5: -10dB, -1dB */
29 0xa0, 0xb0 /* channel 6: -10dB, -1dB */
84 int base = kcontrol->private_value; in pt2258_stereo_volume_get() local
87 ucontrol->value.integer.value[0] = 79 - pt->volume[base]; in pt2258_stereo_volume_get()
88 ucontrol->value.integer.value[1] = 79 - pt->volume[base + 1]; in pt2258_stereo_volume_get()
96 int base = kcontrol->private_value; in pt2258_stereo_volume_put() local
[all …]
/linux/arch/powerpc/boot/
H A Dstdlib.c12 /* Not currently supported: leading whitespace, sign, 0x prefix, zero base */
13 unsigned long long int strtoull(const char *ptr, char **end, int base) in strtoull() argument
17 if (base > 36) in strtoull()
23 if (*ptr >= '0' && *ptr <= '9' && *ptr < '0' + base) in strtoull()
25 else if (*ptr >= 'A' && *ptr < 'A' + base - 10) in strtoull()
26 digit = *ptr - 'A' + 10; in strtoull()
27 else if (*ptr >= 'a' && *ptr < 'a' + base - 10) in strtoull()
28 digit = *ptr - 'a' + 10; in strtoull()
32 ret *= base; in strtoull()
/linux/drivers/net/phy/
H A DKconfig92 These are C45 PHYs 10G that require all a generic firmware.
121 - ADIN1200 - Robust,Industrial, Low Power 10/100 Ethernet PHY
122 - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
130 - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY
197 Currently supports the BCM8706 and BCM8727 10G Ethernet PHYs.
224 tristate "Cortina EDC CDR 10G Ethernet PHY"
262 tristate "Marvell Alaska 10Gbit PHYs"
270 Support for the Marvell 88Q2XXX 100/1000BASE-T1 Automotive Ethernet
294 physical interface for 10/100/1000 Mbps Ethernet connections
309 tristate "Microchip 10BASE-T1S Ethernet PHYs"
[all …]
/linux/drivers/scsi/
H A Dnsp32_debug.c28 /* 23-28 */ unknown, unknown, "Read Capacity", unknown, unknown, "Read (10)",
29 /* 29-2d */ unknown, "Write (10)", "Seek (10)", unknown, unknown,
41 /* 49-4f */ "Play Track Relative(10)(cd)", unknown, "Pause/Resume(cd)", "Log Select", "Log Sense", …
42 /* 50-55 */ unknown, unknown, unknown, unknown, unknown, "Mode Select (10)",
43 /* 56-5b */ unknown, unknown, unknown, unknown, "Mode Sense (10)", unknown,
112 case 10: in print_commandk()
228 static void nsp32_print_register(int base) in nsp32_print_register() argument
233 printk("Phase=0x%x, ", nsp32_read1(base, SCSI_BUS_MONITOR)); in nsp32_print_register()
234 printk("OldPhase=0x%x, ", nsp32_index_read1(base, OLD_SCSI_PHASE)); in nsp32_print_register()
235 printk("syncreg=0x%x, ", nsp32_read1(base, SYNC_REG)); in nsp32_print_register()
[all …]
H A Dnsp32.h81 #define IRQ_CONTROL 0x00 /* BASE+00, W, W */
82 #define IRQ_STATUS 0x00 /* BASE+00, W, R */
93 # define IRQSTATUS_BMCNTERR_IRQ BIT(10)
112 #define TRANSFER_CONTROL 0x02 /* BASE+02, W, W */
113 #define TRANSFER_STATUS 0x02 /* BASE+02, W, R */
123 # define ADVANCED_BM_WRITE BIT(10)
130 #define INDEX_REG 0x04 /* BASE+04, Byte(R/W), Word(R) */
132 #define TIMER_SET 0x06 /* BASE+06, W, R/W */
136 #define DATA_REG_LOW 0x08 /* BASE+08, LowW, R/W */
137 #define DATA_REG_HI 0x0a /* BASE+0a, Hi-W, R/W */
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx6sll.c82 void __iomem *base; in imx6sll_clocks_init() local
102 base = of_iomap(np, 0); in imx6sll_clocks_init()
104 WARN_ON(!base); in imx6sll_clocks_init()
107 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x0)); in imx6sll_clocks_init()
108 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x10)); in imx6sll_clocks_init()
109 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x20)); in imx6sll_clocks_init()
110 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x30)); in imx6sll_clocks_init()
111 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x70)); in imx6sll_clocks_init()
112 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xa0)); in imx6sll_clocks_init()
113 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xe0)); in imx6sll_clocks_init()
[all …]
H A Dclk-imx6ul.c77 { .val = 1, .div = 10, },
131 void __iomem *base; in imx6ul_clocks_init() local
151 base = of_iomap(np, 0); in imx6ul_clocks_init()
153 WARN_ON(!base); in imx6ul_clocks_init()
155 …hws[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
156 …hws[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
157 …hws[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
158 …hws[IMX6UL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
159 …hws[IMX6UL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
160 …hws[IMX6UL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
[all …]
/linux/lib/
H A Dtest-kstrtox.c10 unsigned int base; member
19 unsigned int base; \
36 rv = fn(t->str, t->base, &tmp); \
38 WARN(1, "str '%s', base %u, expected -E, got %d/" fmt "\n", \
39 t->str, t->base, rv, tmp); \
54 rv = fn(t->str, t->base, &res); \
56 WARN(1, "str '%s', base %u, expected 0/" fmt ", got %d\n", \
57 t->str, t->base, t->expected_res, rv); \
61 WARN(1, "str '%s', base %u, expected " fmt ", got " fmt "\n", \
62 t->str, t->base, t->expected_res, res); \
[all …]
/linux/drivers/gpu/drm/atmel-hlcdc/
H A Datmel_hlcdc_crtc.c31 * @base: base CRTC state
36 struct drm_crtc_state base; member
44 return container_of(state, struct atmel_hlcdc_crtc_state, base); in drm_crtc_state_to_atmel_hlcdc_crtc_state()
50 * @base: base DRM CRTC structure
56 struct drm_crtc base; member
65 return container_of(crtc, struct atmel_hlcdc_crtc, base); in drm_crtc_to_atmel_hlcdc_crtc()
138 /* The divider ended up too big, try a lower base rate. */ in atmel_hlcdc_crtc_mode_set_nofb()
148 (10 * (prate / div_low - mode_rate) < in atmel_hlcdc_crtc_mode_set_nofb()
151 * At least 10 times better when using a higher in atmel_hlcdc_crtc_mode_set_nofb()
217 10, 1000)) in atmel_hlcdc_crtc_atomic_disable()
[all …]
/linux/Documentation/ABI/testing/
H A Ddebugfs-intel-iommu13 IOMMU: dmar0 Register Base Address: 26be37000
24 IOMMU: dmar1 Register Base Address: fed90000
35 IOMMU: dmar2 Register Base Address: fed91000
131 Base: 0x10022e000 Head: 20 Tail: 20
145 Base: 0x10026e000 Head: 32 Tail: 32
191 IOMMU: dmar0 Register Base Address: 26be37000
192 <0.1us 0.1us-1us 1us-10us 10us-100us 100us-1ms
195 1ms-10ms >=10ms min(us) max(us) average(us)
200 IOMMU: dmar2 Register Base Address: fed91000
201 <0.1us 0.1us-1us 1us-10us 10us-100us 100us-1ms
[all …]
/linux/arch/mips/include/asm/
H A Dasmmacro.h136 bgez \tmp, 10f
138 10:
195 bgez \tmp, 10f # 16 register mode?
198 10:
240 insn32_if_mm 0x0000000E | (\rt << 21) | (\rs << 16) | (\u << 10) | (\sel << 4)
245 insn32_if_mm 0x00000006 | (\rt << 21) | (\rs << 16) | (\u << 10) | (\sel << 4)
267 .macro ld_b wd, off, base
272 ld.b $w\wd, \off(\base)
276 .macro ld_h wd, off, base
281 ld.h $w\wd, \off(\base)
[all …]
/linux/drivers/gpu/drm/amd/display/dc/sspl/
H A Ddc_spl.c293 * In the following two diagrams, user applied 10% overscan adjustment in spl_calculate_recout()
1287 fmt.mantissa_bits = 10; in spl_calculate_c0_c3_hdr()
1364 dscl_prog_data->easf_v_bf1_pwl_in_seg0 = 0x600; // S0.10, BF1 PWL Segment 0 = -512 in spl_set_easf_data()
1365 dscl_prog_data->easf_v_bf1_pwl_base_seg0 = 0; // U0.6, BF1 Base PWL Segment 0 in spl_set_easf_data()
1367 dscl_prog_data->easf_v_bf1_pwl_in_seg1 = 0x7EC; // S0.10, BF1 PWL Segment 1 = -20 in spl_set_easf_data()
1368 dscl_prog_data->easf_v_bf1_pwl_base_seg1 = 12; // U0.6, BF1 Base PWL Segment 1 in spl_set_easf_data()
1370 dscl_prog_data->easf_v_bf1_pwl_in_seg2 = 0; // S0.10, BF1 PWL Segment 2 in spl_set_easf_data()
1371 dscl_prog_data->easf_v_bf1_pwl_base_seg2 = 63; // U0.6, BF1 Base PWL Segment 2 in spl_set_easf_data()
1373 dscl_prog_data->easf_v_bf1_pwl_in_seg3 = 16; // S0.10, BF1 PWL Segment 3 in spl_set_easf_data()
1374 dscl_prog_data->easf_v_bf1_pwl_base_seg3 = 63; // U0.6, BF1 Base PWL Segment 3 in spl_set_easf_data()
[all …]
/linux/drivers/net/ethernet/atheros/atlx/
H A Datlx.h24 #define SPEED_10 10
204 #define MAC_CTRL_PRMLEN_SHIFT 10
299 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100,
300 * 00=10
308 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100,
309 * 00=10
329 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
330 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
337 #define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
338 #define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
[all …]
/linux/drivers/phy/mediatek/
H A Dphy-mtk-mipi-dsi-mt8173.c16 #define RG_DSI_DSICLK_FREQ_SEL BIT(10)
39 #define RG_DSI_LNT_AIO_SEL GENMASK(10, 8)
51 #define RG_DSI_V10_SEL GENMASK(10, 8)
71 #define RG_DSI_MPPLL_MONVC_EN BIT(10)
105 #define SW_LNT0_LPTX_N BIT(10)
125 void __iomem *base = mipi_tx->regs; in mtk_mipi_tx_pll_prepare() local
155 mtk_phy_update_bits(base + MIPITX_DSI_BG_CON, in mtk_mipi_tx_pll_prepare()
168 mtk_phy_update_bits(base + MIPITX_DSI_TOP_CON, in mtk_mipi_tx_pll_prepare()
173 mtk_phy_set_bits(base + MIPITX_DSI_CON, in mtk_mipi_tx_pll_prepare()
176 mtk_phy_update_bits(base + MIPITX_DSI_PLL_PWR, in mtk_mipi_tx_pll_prepare()
[all …]
H A Dphy-mtk-mipi-dsi-mt8183.c30 #define RG_DSI_PLL_IBIAS GENMASK(11, 10)
45 #define RG_DSI_PLL_POSDIV GENMASK(10, 8)
50 void __iomem *base = mipi_tx->regs; in mtk_mipi_tx_pll_enable() local
75 mtk_phy_clear_bits(base + MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS); in mtk_mipi_tx_pll_enable()
77 mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); in mtk_mipi_tx_pll_enable()
78 mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN); in mtk_mipi_tx_pll_enable()
80 mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); in mtk_mipi_tx_pll_enable()
82 writel(pcw, base + MIPITX_PLL_CON0); in mtk_mipi_tx_pll_enable()
83 mtk_phy_update_field(base + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, txdiv0); in mtk_mipi_tx_pll_enable()
84 mtk_phy_set_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN); in mtk_mipi_tx_pll_enable()
[all …]
/linux/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2_tai.c59 void __iomem *base; member
90 static void mvpp22_tai_read_ts(struct timespec64 *ts, void __iomem *base) in mvpp22_tai_read_ts() argument
92 ts->tv_sec = (u64)mvpp2_tai_read(base + 0) << 32 | in mvpp22_tai_read_ts()
93 mvpp2_tai_read(base + 4) << 16 | in mvpp22_tai_read_ts()
94 mvpp2_tai_read(base + 8); in mvpp22_tai_read_ts()
96 ts->tv_nsec = mvpp2_tai_read(base + 12) << 16 | in mvpp22_tai_read_ts()
97 mvpp2_tai_read(base + 16); in mvpp22_tai_read_ts()
100 readl_relaxed(base + 20); in mvpp22_tai_read_ts()
101 readl_relaxed(base + 24); in mvpp22_tai_read_ts()
105 void __iomem *base) in mvpp2_tai_write_tlv() argument
[all …]
/linux/arch/x86/include/asm/
H A Dmtrr.h19 #define MTRR_CAP_WC BIT_MASK(10)
22 #define MTRR_DEF_TYPE_FE BIT_MASK(10)
31 #define MTRR_PHYSMASK_RSVD GENMASK(10, 0)
53 extern int mtrr_add(unsigned long base, unsigned long size,
55 extern int mtrr_add_page(unsigned long base, unsigned long size,
57 extern int mtrr_del(int reg, unsigned long base, unsigned long size);
58 extern int mtrr_del_page(int reg, unsigned long base, unsigned long size);
83 static inline int mtrr_add(unsigned long base, unsigned long size, in mtrr_add() argument
88 static inline int mtrr_add_page(unsigned long base, unsigned long size, in mtrr_add_page() argument
93 static inline int mtrr_del(int reg, unsigned long base, unsigned long size) in mtrr_del() argument
[all …]
/linux/drivers/reset/
H A Dreset-eyeq.c20 * 7. SPI1 8. SPI2 9. SPI3 10. UART0
30 * 8. MPC0 9. MPC1 10. MPC2 11. MPC3
36 * 8. PCIE1_LINK_AXI 9. PCIE1_LINK_MGMT 10. PCIE1_LINK_HOT 11. PCIE1_LINK_PIPE
43 * 8. TIMER3 9. WD0 10. WD1 11. EXT0
49 * 8. MPC0 9. MPC1 10. MPC2 11. MPC3
55 * 8. TIMER0 9. TIMER1 10. WD 11. EXT TIMER
61 * 9. PMA0 10. PMA1 11. MPC0 12. MPC1
115 * Registers are: base + 4 * offset.
135 [EQR_EYEQ5_SARCR] = {1, 10},
161 void __iomem *base; member
[all …]
/linux/tools/perf/Documentation/
H A Dperf-daemon.txt32 …916507 916508 ... \_ perf record --control=fifo:control,ack -m 10M -e cycles --overwrite --switc…
58 --base=<PATH>::
59 Base directory path. Each daemon instance is running on top
60 of base directory. Only one instance of server can run on
101 daemon.base:
102 Base path for daemon data. All sessions data are
109 Each perf record session is run in daemon.base/<NAME> directory.
118 base=/opt/perfdata
121 run = -m 10M -e cycles --overwrite --switch-output -a
135 [603349:daemon] base: /opt/perfdata
[all …]
/linux/drivers/phy/marvell/
H A Dphy-berlin-sata.c42 #define DATA_BIT_WIDTH_10 (0x0 << 10)
43 #define DATA_BIT_WIDTH_20 (0x1 << 10)
44 #define DATA_BIT_WIDTH_40 (0x2 << 10)
47 #define PHY_GEN_MAX_1_5 (0x0 << 10)
48 #define PHY_GEN_MAX_3_0 (0x1 << 10)
49 #define PHY_GEN_MAX_6_0 (0x2 << 10)
58 void __iomem *base; member
85 void __iomem *ctrl_reg = priv->base + 0x60 + (desc->index * 0x80); in phy_berlin_sata_power_on()
93 writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR); in phy_berlin_sata_power_on()
94 regval = readl(priv->base + HOST_VSA_DATA); in phy_berlin_sata_power_on()
[all …]

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