| /linux/include/uapi/linux/ |
| H A D | mdio.h | 39 #define MDIO_CTRL2 7 /* 10G control 2 */
40 #define MDIO_STAT2 8 /* 10G status 2 */
41 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
42 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
43 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
46 #define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
47 #define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
60 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
61 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
62 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
[all …]
|
| H A D | mii.h | 23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
37 #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
52 #define BMCR_SPEED10 0x0000 /* Select 10Mbps */
63 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
64 #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
65 #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
66 #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
74 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
75 #define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
[all …]
|
| /linux/tools/perf/tests/shell/ |
| H A D | daemon.sh | 9 local base=$3
30 if [ "${base}" != "${line_base}" ]; then
31 echo "FAILED: wrong base"
56 local base=$4
87 if [ "${base}" != "${line_base}" ]; then
88 echo "FAILED: wrong base"
163 local base
164 base=$(mktemp -d /tmp/perf.daemon.base.XXX)
168 base=BASE
171 run = -e cpu-clock -m 1 sleep 10
[all …]
|
| /linux/arch/arm/mach-rpc/ |
| H A D | irq.c | 18 0, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10,
19 12, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10,
20 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
21 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
22 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10,
23 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10,
24 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
25 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
26 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10,
27 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10,
[all …]
|
| /linux/drivers/rtc/ |
| H A D | rtc-renesas-rtca3.c | 106 * @ten_sec: PPB per cycle in 10 seconds adjutment mode
116 * @base: base address
126 void __iomem *base; member
140 tmp = readb(priv->base + off); in rtca3_byte_update_bits()
143 writeb(tmp, priv->base + off); in rtca3_byte_update_bits()
150 val = readb(priv->base + RTCA3_RSR); in rtca3_alarm_handler_helper()
152 writeb(val & ~pending, priv->base + RTCA3_RSR); in rtca3_alarm_handler_helper()
179 val = readb(priv->base + RTCA3_RSR); in rtca3_periodic_handler()
183 writeb(val & ~pending, priv->base + RTCA3_RSR); in rtca3_periodic_handler()
196 readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, val, in rtca3_periodic_handler()
[all …]
|
| /linux/arch/x86/kernel/cpu/mtrr/ |
| H A D | cleanup.c | 66 unsigned long base, size; in x86_get_mtrr_mem_range() local
74 base = range_state[i].base_pfn; in x86_get_mtrr_mem_range()
77 base, base + size); in x86_get_mtrr_mem_range()
94 base = range_state[i].base_pfn; in x86_get_mtrr_mem_range()
95 if (base < (1<<(20-PAGE_SHIFT)) && mtrr_state.have_fixed && in x86_get_mtrr_mem_range()
100 if (base + size <= (1<<(20-PAGE_SHIFT))) in x86_get_mtrr_mem_range()
102 size -= (1<<(20-PAGE_SHIFT)) - base; in x86_get_mtrr_mem_range()
103 base = 1<<(20-PAGE_SHIFT); in x86_get_mtrr_mem_range()
105 subtract_range(range, RANGE_NUM, base, base + size); in x86_get_mtrr_mem_range()
166 u64 base, mask; in set_var_mtrr() local
[all …]
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| /linux/sound/i2c/other/ |
| H A D | pt2258.c | 24 0x80, 0x90, /* channel 1: -10dB, -1dB */
25 0x40, 0x50, /* channel 2: -10dB, -1dB */
26 0x00, 0x10, /* channel 3: -10dB, -1dB */
27 0x20, 0x30, /* channel 4: -10dB, -1dB */
28 0x60, 0x70, /* channel 5: -10dB, -1dB */
29 0xa0, 0xb0 /* channel 6: -10dB, -1dB */
84 int base = kcontrol->private_value; in pt2258_stereo_volume_get() local
87 ucontrol->value.integer.value[0] = 79 - pt->volume[base]; in pt2258_stereo_volume_get()
88 ucontrol->value.integer.value[1] = 79 - pt->volume[base + 1]; in pt2258_stereo_volume_get()
96 int base = kcontrol->private_value; in pt2258_stereo_volume_put() local
[all …]
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| /linux/drivers/net/phy/ |
| H A D | Kconfig | 104 - ADIN1200 - Robust,Industrial, Low Power 10/100 Ethernet PHY
105 - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
113 - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY
179 Currently supports the BCM8706 and BCM8727 10G Ethernet PHYs.
206 tristate "Cortina EDC CDR 10G Ethernet PHY"
244 tristate "Marvell Alaska 10Gbit PHYs"
252 Support for the Marvell 88Q2XXX 100/1000BASE-T1 Automotive Ethernet
278 tristate "Microchip 10BASE-T1S Ethernet PHYs"
313 tristate "NXP 100BASE-TX PHYs"
315 Support the 100BASE-TX PHY integrated on the SJA1110 automotive
[all …]
|
| /linux/arch/powerpc/boot/ |
| H A D | stdlib.c | 12 /* Not currently supported: leading whitespace, sign, 0x prefix, zero base */
13 unsigned long long int strtoull(const char *ptr, char **end, int base) in strtoull() argument
17 if (base > 36) in strtoull()
23 if (*ptr >= '0' && *ptr <= '9' && *ptr < '0' + base) in strtoull()
25 else if (*ptr >= 'A' && *ptr < 'A' + base - 10) in strtoull()
26 digit = *ptr - 'A' + 10; in strtoull()
27 else if (*ptr >= 'a' && *ptr < 'a' + base - 10) in strtoull()
28 digit = *ptr - 'a' + 10; in strtoull()
32 ret *= base; in strtoull()
|
| /linux/drivers/scsi/ |
| H A D | nsp32_debug.c | 28 /* 23-28 */ unknown, unknown, "Read Capacity", unknown, unknown, "Read (10)",
29 /* 29-2d */ unknown, "Write (10)", "Seek (10)", unknown, unknown,
41 /* 49-4f */ "Play Track Relative(10)(cd)", unknown, "Pause/Resume(cd)", "Log Select", "Log Sense", …
42 /* 50-55 */ unknown, unknown, unknown, unknown, unknown, "Mode Select (10)",
43 /* 56-5b */ unknown, unknown, unknown, unknown, "Mode Sense (10)", unknown,
112 case 10: in print_commandk()
228 static void nsp32_print_register(int base) in nsp32_print_register() argument
233 printk("Phase=0x%x, ", nsp32_read1(base, SCSI_BUS_MONITOR)); in nsp32_print_register()
234 printk("OldPhase=0x%x, ", nsp32_index_read1(base, OLD_SCSI_PHASE)); in nsp32_print_register()
235 printk("syncreg=0x%x, ", nsp32_read1(base, SYNC_REG)); in nsp32_print_register()
[all …]
|
| H A D | nsp32.h | 81 #define IRQ_CONTROL 0x00 /* BASE+00, W, W */
82 #define IRQ_STATUS 0x00 /* BASE+00, W, R */
93 # define IRQSTATUS_BMCNTERR_IRQ BIT(10)
112 #define TRANSFER_CONTROL 0x02 /* BASE+02, W, W */
113 #define TRANSFER_STATUS 0x02 /* BASE+02, W, R */
123 # define ADVANCED_BM_WRITE BIT(10)
130 #define INDEX_REG 0x04 /* BASE+04, Byte(R/W), Word(R) */
132 #define TIMER_SET 0x06 /* BASE+06, W, R/W */
136 #define DATA_REG_LOW 0x08 /* BASE+08, LowW, R/W */
137 #define DATA_REG_HI 0x0a /* BASE+0a, Hi-W, R/W */
[all …]
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| /linux/tools/testing/selftests/net/ |
| H A D | udpgro_fwd.sh | 7 readonly BASE="ns-$(mktemp -u XXXXXX)"
11 readonly NS_SRC=$BASE$SRC
12 readonly NS_DST=$BASE$DST
51 ip link set dev veth$ns netns $BASE$ns
52 ip -n $BASE$ns link set dev veth$ns up
53 ip -n $BASE$ns addr add dev veth$ns $BM_NET_V4$ns/24
54 ip -n $BASE$ns addr add dev veth$ns $BM_NET_V6$ns/64 nodad
80 create_vxlan_endpoint $BASE$ns veth$ns $BM_NET_V4$((3 - $ns)) vxlan$ns 4
81 ip -n $BASE$ns addr add dev vxlan$ns $OL_NET_V4$ns/24
84 create_vxlan_endpoint $BASE$ns veth$ns $BM_NET_V6$((3 - $ns)) vxlan6$ns 6
[all …]
|
| /linux/drivers/clk/imx/ |
| H A D | clk-imx6sll.c | 82 void __iomem *base; in imx6sll_clocks_init() local
102 base = of_iomap(np, 0); in imx6sll_clocks_init()
104 WARN_ON(!base); in imx6sll_clocks_init()
107 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x0)); in imx6sll_clocks_init()
108 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x10)); in imx6sll_clocks_init()
109 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x20)); in imx6sll_clocks_init()
110 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x30)); in imx6sll_clocks_init()
111 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x70)); in imx6sll_clocks_init()
112 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xa0)); in imx6sll_clocks_init()
113 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xe0)); in imx6sll_clocks_init()
[all …]
|
| H A D | clk-imx6ul.c | 77 { .val = 1, .div = 10, },
131 void __iomem *base; in imx6ul_clocks_init() local
151 base = of_iomap(np, 0); in imx6ul_clocks_init()
153 WARN_ON(!base); in imx6ul_clocks_init()
155 …hws[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
156 …hws[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
157 …hws[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
158 …hws[IMX6UL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
159 …hws[IMX6UL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
160 …hws[IMX6UL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
[all …]
|
| /linux/lib/ |
| H A D | test-kstrtox.c | 10 unsigned int base; member
19 unsigned int base; \
36 rv = fn(t->str, t->base, &tmp); \
38 WARN(1, "str '%s', base %u, expected -E, got %d/" fmt "\n", \
39 t->str, t->base, rv, tmp); \
54 rv = fn(t->str, t->base, &res); \
56 WARN(1, "str '%s', base %u, expected 0/" fmt ", got %d\n", \
57 t->str, t->base, t->expected_res, rv); \
61 WARN(1, "str '%s', base %u, expected " fmt ", got " fmt "\n", \
62 t->str, t->base, t->expected_res, res); \
[all …]
|
| /linux/drivers/gpu/drm/atmel-hlcdc/ |
| H A D | atmel_hlcdc_crtc.c | 31 * @base: base CRTC state
36 struct drm_crtc_state base; member
44 return container_of(state, struct atmel_hlcdc_crtc_state, base); in drm_crtc_state_to_atmel_hlcdc_crtc_state()
50 * @base: base DRM CRTC structure
56 struct drm_crtc base; member
65 return container_of(crtc, struct atmel_hlcdc_crtc, base); in drm_crtc_to_atmel_hlcdc_crtc()
138 /* The divider ended up too big, try a lower base rate. */ in atmel_hlcdc_crtc_mode_set_nofb()
148 (10 * (prate / div_low - mode_rate) < in atmel_hlcdc_crtc_mode_set_nofb()
151 * At least 10 times better when using a higher in atmel_hlcdc_crtc_mode_set_nofb()
217 10, 1000)) in atmel_hlcdc_crtc_atomic_disable()
[all …]
|
| /linux/Documentation/ABI/testing/ |
| H A D | debugfs-intel-iommu | 13 IOMMU: dmar0 Register Base Address: 26be37000
24 IOMMU: dmar1 Register Base Address: fed90000
35 IOMMU: dmar2 Register Base Address: fed91000
131 Base: 0x10022e000 Head: 20 Tail: 20
145 Base: 0x10026e000 Head: 32 Tail: 32
191 IOMMU: dmar0 Register Base Address: 26be37000
192 <0.1us 0.1us-1us 1us-10us 10us-100us 100us-1ms
195 1ms-10ms >=10ms min(us) max(us) average(us)
200 IOMMU: dmar2 Register Base Address: fed91000
201 <0.1us 0.1us-1us 1us-10us 10us-100us 100us-1ms
[all …]
|
| /linux/drivers/gpu/drm/sun4i/ |
| H A D | sun8i_mixer.h | 39 #define SUN8I_MIXER_BLEND_PIPE_CTL(base) ((base) + 0) argument
40 #define SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, x) ((base) + 0x4 + 0x10 * (x)) argument
41 #define SUN8I_MIXER_BLEND_ATTR_INSIZE(base, x) ((base) + 0x8 + 0x10 * (x)) argument
42 #define SUN8I_MIXER_BLEND_ATTR_COORD(base, x) ((base) + 0xc + 0x10 * (x)) argument
43 #define SUN8I_MIXER_BLEND_ROUTE(base) ((base) + 0x80) argument
44 #define SUN8I_MIXER_BLEND_PREMULTIPLY(base) ((base) + 0x84) argument
45 #define SUN8I_MIXER_BLEND_BKCOLOR(base) ((base) + 0x88) argument
46 #define SUN8I_MIXER_BLEND_OUTSIZE(base) ((base) + 0x8c) argument
47 #define SUN8I_MIXER_BLEND_MODE(base, x) ((base) + 0x90 + 0x04 * (x)) argument
48 #define SUN8I_MIXER_BLEND_CK_CTL(base) ((base) + 0xb0) argument
[all …]
|
| /linux/arch/mips/include/asm/ |
| H A D | asmmacro.h | 136 bgez \tmp, 10f
138 10:
195 bgez \tmp, 10f # 16 register mode?
198 10:
240 insn32_if_mm 0x0000000E | (\rt << 21) | (\rs << 16) | (\u << 10) | (\sel << 4)
245 insn32_if_mm 0x00000006 | (\rt << 21) | (\rs << 16) | (\u << 10) | (\sel << 4)
267 .macro ld_b wd, off, base
272 ld.b $w\wd, \off(\base)
276 .macro ld_h wd, off, base
281 ld.h $w\wd, \off(\base)
[all …]
|
| /linux/drivers/net/ethernet/atheros/atlx/ |
| H A D | atlx.h | 24 #define SPEED_10 10
204 #define MAC_CTRL_PRMLEN_SHIFT 10
299 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100,
300 * 00=10
308 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100,
309 * 00=10
329 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
330 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
337 #define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
338 #define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
[all …]
|
| /linux/drivers/phy/mediatek/ |
| H A D | phy-mtk-mipi-dsi-mt8173.c | 16 #define RG_DSI_DSICLK_FREQ_SEL BIT(10)
39 #define RG_DSI_LNT_AIO_SEL GENMASK(10, 8)
51 #define RG_DSI_V10_SEL GENMASK(10, 8)
71 #define RG_DSI_MPPLL_MONVC_EN BIT(10)
105 #define SW_LNT0_LPTX_N BIT(10)
125 void __iomem *base = mipi_tx->regs; in mtk_mipi_tx_pll_prepare() local
155 mtk_phy_update_bits(base + MIPITX_DSI_BG_CON, in mtk_mipi_tx_pll_prepare()
168 mtk_phy_update_bits(base + MIPITX_DSI_TOP_CON, in mtk_mipi_tx_pll_prepare()
173 mtk_phy_set_bits(base + MIPITX_DSI_CON, in mtk_mipi_tx_pll_prepare()
176 mtk_phy_update_bits(base + MIPITX_DSI_PLL_PWR, in mtk_mipi_tx_pll_prepare()
[all …]
|
| /linux/crypto/ |
| H A D | blake2b_generic.c | 26 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
27 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
28 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
29 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
30 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
31 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
32 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
33 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
34 { 6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10, 5 },
35 { 10, 2, 8, 4, 7, 6, 1, 5, 15, 11, 9, 14, 3, 12, 13, 0 },
[all …]
|
| /linux/drivers/net/ethernet/marvell/mvpp2/ |
| H A D | mvpp2_tai.c | 59 void __iomem *base; member
90 static void mvpp22_tai_read_ts(struct timespec64 *ts, void __iomem *base) in mvpp22_tai_read_ts() argument
92 ts->tv_sec = (u64)mvpp2_tai_read(base + 0) << 32 | in mvpp22_tai_read_ts()
93 mvpp2_tai_read(base + 4) << 16 | in mvpp22_tai_read_ts()
94 mvpp2_tai_read(base + 8); in mvpp22_tai_read_ts()
96 ts->tv_nsec = mvpp2_tai_read(base + 12) << 16 | in mvpp22_tai_read_ts()
97 mvpp2_tai_read(base + 16); in mvpp22_tai_read_ts()
100 readl_relaxed(base + 20); in mvpp22_tai_read_ts()
101 readl_relaxed(base + 24); in mvpp22_tai_read_ts()
105 void __iomem *base) in mvpp2_tai_write_tlv() argument
[all …]
|
| /linux/drivers/reset/ |
| H A D | reset-eyeq.c | 20 * 7. SPI1 8. SPI2 9. SPI3 10. UART0
30 * 8. MPC0 9. MPC1 10. MPC2 11. MPC3
36 * 8. PCIE1_LINK_AXI 9. PCIE1_LINK_MGMT 10. PCIE1_LINK_HOT 11. PCIE1_LINK_PIPE
43 * 8. TIMER3 9. WD0 10. WD1 11. EXT0
49 * 8. MPC0 9. MPC1 10. MPC2 11. MPC3
55 * 8. TIMER0 9. TIMER1 10. WD 11. EXT TIMER
61 * 9. PMA0 10. PMA1 11. MPC0 12. MPC1
115 * Registers are: base + 4 * offset.
135 [EQR_EYEQ5_SARCR] = {1, 10},
161 void __iomem *base; member
[all …]
|
| /linux/tools/testing/selftests/drivers/net/mlxsw/ |
| H A D | sch_red_core.sh | 25 # | + $h1.10 | | + $h2.10 |
41 # | | + $swp1.10 | | | + $swp2.10 | | |
42 # | | | | .-------------+ $swp5.10 | | |
45 # | | + $swp2.10 | | | | | | |
46 # | +-|-----------------+ | | | + $swp3.10 | | |
67 # | + $h3.10 $h3.11 + |
95 echo 192.0.2.$((16 * (vlan - 10) + host))
109 vlan_create $dev 10
[all...] |