16f52b16cSGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2607ca46eSDavid Howells /* 3607ca46eSDavid Howells * linux/mii.h: definitions for MII-compatible transceivers 4607ca46eSDavid Howells * Originally drivers/net/sunhme.h. 5607ca46eSDavid Howells * 6607ca46eSDavid Howells * Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com) 7607ca46eSDavid Howells */ 8607ca46eSDavid Howells 9607ca46eSDavid Howells #ifndef _UAPI__LINUX_MII_H__ 10607ca46eSDavid Howells #define _UAPI__LINUX_MII_H__ 11607ca46eSDavid Howells 12607ca46eSDavid Howells #include <linux/types.h> 13607ca46eSDavid Howells #include <linux/ethtool.h> 14607ca46eSDavid Howells 15607ca46eSDavid Howells /* Generic MII registers. */ 16607ca46eSDavid Howells #define MII_BMCR 0x00 /* Basic mode control register */ 17607ca46eSDavid Howells #define MII_BMSR 0x01 /* Basic mode status register */ 18607ca46eSDavid Howells #define MII_PHYSID1 0x02 /* PHYS ID 1 */ 19607ca46eSDavid Howells #define MII_PHYSID2 0x03 /* PHYS ID 2 */ 20607ca46eSDavid Howells #define MII_ADVERTISE 0x04 /* Advertisement control reg */ 21607ca46eSDavid Howells #define MII_LPA 0x05 /* Link partner ability reg */ 22607ca46eSDavid Howells #define MII_EXPANSION 0x06 /* Expansion register */ 23607ca46eSDavid Howells #define MII_CTRL1000 0x09 /* 1000BASE-T control */ 24607ca46eSDavid Howells #define MII_STAT1000 0x0a /* 1000BASE-T status */ 25607ca46eSDavid Howells #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ 26607ca46eSDavid Howells #define MII_MMD_DATA 0x0e /* MMD Access Data Register */ 27607ca46eSDavid Howells #define MII_ESTATUS 0x0f /* Extended Status */ 28607ca46eSDavid Howells #define MII_DCOUNTER 0x12 /* Disconnect counter */ 29607ca46eSDavid Howells #define MII_FCSCOUNTER 0x13 /* False carrier counter */ 30607ca46eSDavid Howells #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ 31607ca46eSDavid Howells #define MII_RERRCOUNTER 0x15 /* Receive error counter */ 32607ca46eSDavid Howells #define MII_SREVISION 0x16 /* Silicon revision */ 33607ca46eSDavid Howells #define MII_RESV1 0x17 /* Reserved... */ 34607ca46eSDavid Howells #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ 35607ca46eSDavid Howells #define MII_PHYADDR 0x19 /* PHY address */ 36607ca46eSDavid Howells #define MII_RESV2 0x1a /* Reserved... */ 37607ca46eSDavid Howells #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ 38607ca46eSDavid Howells #define MII_NCONFIG 0x1c /* Network interface config */ 39607ca46eSDavid Howells 40607ca46eSDavid Howells /* Basic mode control register. */ 41607ca46eSDavid Howells #define BMCR_RESV 0x003f /* Unused... */ 42607ca46eSDavid Howells #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ 43607ca46eSDavid Howells #define BMCR_CTST 0x0080 /* Collision test */ 44607ca46eSDavid Howells #define BMCR_FULLDPLX 0x0100 /* Full duplex */ 45607ca46eSDavid Howells #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ 46607ca46eSDavid Howells #define BMCR_ISOLATE 0x0400 /* Isolate data paths from MII */ 47607ca46eSDavid Howells #define BMCR_PDOWN 0x0800 /* Enable low power state */ 48607ca46eSDavid Howells #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ 49607ca46eSDavid Howells #define BMCR_SPEED100 0x2000 /* Select 100Mbps */ 50607ca46eSDavid Howells #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ 51607ca46eSDavid Howells #define BMCR_RESET 0x8000 /* Reset to default state */ 52300d8b93SAppana Durga Kedareswara Rao #define BMCR_SPEED10 0x0000 /* Select 10Mbps */ 53607ca46eSDavid Howells 54607ca46eSDavid Howells /* Basic mode status register. */ 55607ca46eSDavid Howells #define BMSR_ERCAP 0x0001 /* Ext-reg capability */ 56607ca46eSDavid Howells #define BMSR_JCD 0x0002 /* Jabber detected */ 57607ca46eSDavid Howells #define BMSR_LSTATUS 0x0004 /* Link status */ 58607ca46eSDavid Howells #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ 59607ca46eSDavid Howells #define BMSR_RFAULT 0x0010 /* Remote fault detected */ 60607ca46eSDavid Howells #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ 61607ca46eSDavid Howells #define BMSR_RESV 0x00c0 /* Unused... */ 62607ca46eSDavid Howells #define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ 63607ca46eSDavid Howells #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ 64607ca46eSDavid Howells #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ 65607ca46eSDavid Howells #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ 66607ca46eSDavid Howells #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ 67607ca46eSDavid Howells #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ 68607ca46eSDavid Howells #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ 69607ca46eSDavid Howells #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ 70607ca46eSDavid Howells 71607ca46eSDavid Howells /* Advertisement control register. */ 72607ca46eSDavid Howells #define ADVERTISE_SLCT 0x001f /* Selector bits */ 73607ca46eSDavid Howells #define ADVERTISE_CSMA 0x0001 /* Only selector supported */ 74607ca46eSDavid Howells #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ 75607ca46eSDavid Howells #define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */ 76607ca46eSDavid Howells #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 77607ca46eSDavid Howells #define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */ 78607ca46eSDavid Howells #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 79607ca46eSDavid Howells #define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */ 80607ca46eSDavid Howells #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 81607ca46eSDavid Howells #define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */ 82607ca46eSDavid Howells #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ 83607ca46eSDavid Howells #define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ 84607ca46eSDavid Howells #define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ 85607ca46eSDavid Howells #define ADVERTISE_RESV 0x1000 /* Unused... */ 86607ca46eSDavid Howells #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ 87607ca46eSDavid Howells #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ 88607ca46eSDavid Howells #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ 89607ca46eSDavid Howells 90607ca46eSDavid Howells #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ 91607ca46eSDavid Howells ADVERTISE_CSMA) 92607ca46eSDavid Howells #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ 93607ca46eSDavid Howells ADVERTISE_100HALF | ADVERTISE_100FULL) 94607ca46eSDavid Howells 95607ca46eSDavid Howells /* Link partner ability register. */ 96607ca46eSDavid Howells #define LPA_SLCT 0x001f /* Same as advertise selector */ 97607ca46eSDavid Howells #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ 98607ca46eSDavid Howells #define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */ 99607ca46eSDavid Howells #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ 100607ca46eSDavid Howells #define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */ 101607ca46eSDavid Howells #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ 102607ca46eSDavid Howells #define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */ 103607ca46eSDavid Howells #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ 104607ca46eSDavid Howells #define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/ 105607ca46eSDavid Howells #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ 106607ca46eSDavid Howells #define LPA_PAUSE_CAP 0x0400 /* Can pause */ 107607ca46eSDavid Howells #define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */ 108607ca46eSDavid Howells #define LPA_RESV 0x1000 /* Unused... */ 109607ca46eSDavid Howells #define LPA_RFAULT 0x2000 /* Link partner faulted */ 110607ca46eSDavid Howells #define LPA_LPACK 0x4000 /* Link partner acked us */ 111607ca46eSDavid Howells #define LPA_NPAGE 0x8000 /* Next page bit */ 112607ca46eSDavid Howells 113607ca46eSDavid Howells #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) 114607ca46eSDavid Howells #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) 115607ca46eSDavid Howells 116607ca46eSDavid Howells /* Expansion register for auto-negotiation. */ 117607ca46eSDavid Howells #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ 118607ca46eSDavid Howells #define EXPANSION_LCWP 0x0002 /* Got new RX page code word */ 119607ca46eSDavid Howells #define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ 120607ca46eSDavid Howells #define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */ 121607ca46eSDavid Howells #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ 122607ca46eSDavid Howells #define EXPANSION_RESV 0xffe0 /* Unused... */ 123607ca46eSDavid Howells 124ca72efb6SRobert Hancock #define ESTATUS_1000_XFULL 0x8000 /* Can do 1000BaseX Full */ 125ca72efb6SRobert Hancock #define ESTATUS_1000_XHALF 0x4000 /* Can do 1000BaseX Half */ 126607ca46eSDavid Howells #define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ 127607ca46eSDavid Howells #define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ 128607ca46eSDavid Howells 129607ca46eSDavid Howells /* N-way test register. */ 130607ca46eSDavid Howells #define NWAYTEST_RESV1 0x00ff /* Unused... */ 131607ca46eSDavid Howells #define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */ 132607ca46eSDavid Howells #define NWAYTEST_RESV2 0xfe00 /* Unused... */ 133607ca46eSDavid Howells 1346c930994SVladimir Oltean /* MAC and PHY tx_config_Reg[15:0] for SGMII in-band auto-negotiation.*/ 1356c930994SVladimir Oltean #define ADVERTISE_SGMII 0x0001 /* MAC can do SGMII */ 1366c930994SVladimir Oltean #define LPA_SGMII 0x0001 /* PHY can do SGMII */ 13774db1c18SRussell King #define LPA_SGMII_SPD_MASK 0x0c00 /* SGMII speed mask */ 13874db1c18SRussell King #define LPA_SGMII_FULL_DUPLEX 0x1000 /* SGMII full duplex */ 1396c930994SVladimir Oltean #define LPA_SGMII_DPX_SPD_MASK 0x1C00 /* SGMII duplex and speed bits */ 14074db1c18SRussell King #define LPA_SGMII_10 0x0000 /* 10Mbps */ 1416c930994SVladimir Oltean #define LPA_SGMII_10HALF 0x0000 /* Can do 10mbps half-duplex */ 1426c930994SVladimir Oltean #define LPA_SGMII_10FULL 0x1000 /* Can do 10mbps full-duplex */ 14374db1c18SRussell King #define LPA_SGMII_100 0x0400 /* 100Mbps */ 1446c930994SVladimir Oltean #define LPA_SGMII_100HALF 0x0400 /* Can do 100mbps half-duplex */ 1456c930994SVladimir Oltean #define LPA_SGMII_100FULL 0x1400 /* Can do 100mbps full-duplex */ 14674db1c18SRussell King #define LPA_SGMII_1000 0x0800 /* 1000Mbps */ 1476c930994SVladimir Oltean #define LPA_SGMII_1000HALF 0x0800 /* Can do 1000mbps half-duplex */ 1486c930994SVladimir Oltean #define LPA_SGMII_1000FULL 0x1800 /* Can do 1000mbps full-duplex */ 1496c930994SVladimir Oltean #define LPA_SGMII_LINK 0x8000 /* PHY link with copper-side partner */ 1506c930994SVladimir Oltean 151607ca46eSDavid Howells /* 1000BASE-T Control register */ 152607ca46eSDavid Howells #define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ 153607ca46eSDavid Howells #define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ 154*bdbdac76SOleksij Rempel #define CTL1000_PREFER_MASTER 0x0400 /* prefer to operate as master */ 155607ca46eSDavid Howells #define CTL1000_AS_MASTER 0x0800 156607ca46eSDavid Howells #define CTL1000_ENABLE_MASTER 0x1000 157607ca46eSDavid Howells 158607ca46eSDavid Howells /* 1000BASE-T Status register */ 159b8f8c8ebSHeiner Kallweit #define LPA_1000MSFAIL 0x8000 /* Master/Slave resolution failure */ 160*bdbdac76SOleksij Rempel #define LPA_1000MSRES 0x4000 /* Master/Slave resolution status */ 161607ca46eSDavid Howells #define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */ 162607ca46eSDavid Howells #define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */ 163607ca46eSDavid Howells #define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */ 164607ca46eSDavid Howells #define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ 165607ca46eSDavid Howells 166607ca46eSDavid Howells /* Flow control flags */ 167607ca46eSDavid Howells #define FLOW_CTRL_TX 0x01 168607ca46eSDavid Howells #define FLOW_CTRL_RX 0x02 169607ca46eSDavid Howells 170607ca46eSDavid Howells /* MMD Access Control register fields */ 171607ca46eSDavid Howells #define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/ 172607ca46eSDavid Howells #define MII_MMD_CTRL_ADDR 0x0000 /* Address */ 173607ca46eSDavid Howells #define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */ 174607ca46eSDavid Howells #define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */ 175607ca46eSDavid Howells #define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */ 176607ca46eSDavid Howells 177607ca46eSDavid Howells /* This structure is used in all SIOCxMIIxxx ioctl calls */ 178607ca46eSDavid Howells struct mii_ioctl_data { 179607ca46eSDavid Howells __u16 phy_id; 180607ca46eSDavid Howells __u16 reg_num; 181607ca46eSDavid Howells __u16 val_in; 182607ca46eSDavid Howells __u16 val_out; 183607ca46eSDavid Howells }; 184607ca46eSDavid Howells 185607ca46eSDavid Howells #endif /* _UAPI__LINUX_MII_H__ */ 186