16 #define RG_DSI_DSICLK_FREQ_SEL		BIT(10)
39 #define RG_DSI_LNT_AIO_SEL		GENMASK(10, 8)
51 #define RG_DSI_V10_SEL			GENMASK(10, 8)
71 #define RG_DSI_MPPLL_MONVC_EN		BIT(10)
105 #define SW_LNT0_LPTX_N			BIT(10)
125 	void __iomem *base = mipi_tx->regs;  in mtk_mipi_tx_pll_prepare()  local
155 	mtk_phy_update_bits(base + MIPITX_DSI_BG_CON,  in mtk_mipi_tx_pll_prepare()
168 	mtk_phy_update_bits(base + MIPITX_DSI_TOP_CON,  in mtk_mipi_tx_pll_prepare()
173 	mtk_phy_set_bits(base + MIPITX_DSI_CON,  in mtk_mipi_tx_pll_prepare()
176 	mtk_phy_update_bits(base + MIPITX_DSI_PLL_PWR,  in mtk_mipi_tx_pll_prepare()
180 	mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN);  in mtk_mipi_tx_pll_prepare()
182 	mtk_phy_update_bits(base + MIPITX_DSI_PLL_CON0,  in mtk_mipi_tx_pll_prepare()
197 	writel(pcw, base + MIPITX_DSI_PLL_CON2);  in mtk_mipi_tx_pll_prepare()
199 	mtk_phy_set_bits(base + MIPITX_DSI_PLL_CON1, RG_DSI_MPPLL_SDM_FRA_EN);  in mtk_mipi_tx_pll_prepare()
201 	mtk_phy_set_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN);  in mtk_mipi_tx_pll_prepare()
205 	mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON1, RG_DSI_MPPLL_SDM_SSC_EN);  in mtk_mipi_tx_pll_prepare()
207 	mtk_phy_update_field(base + MIPITX_DSI_PLL_TOP,  in mtk_mipi_tx_pll_prepare()
217 	void __iomem *base = mipi_tx->regs;  in mtk_mipi_tx_pll_unprepare()  local
221 	mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN);  in mtk_mipi_tx_pll_unprepare()
223 	mtk_phy_clear_bits(base + MIPITX_DSI_PLL_TOP, RG_DSI_MPPLL_PRESERVE);  in mtk_mipi_tx_pll_unprepare()
225 	mtk_phy_update_bits(base + MIPITX_DSI_PLL_PWR,  in mtk_mipi_tx_pll_unprepare()
229 	mtk_phy_clear_bits(base + MIPITX_DSI_TOP_CON, RG_DSI_LNT_HS_BIAS_EN);  in mtk_mipi_tx_pll_unprepare()
231 	mtk_phy_clear_bits(base + MIPITX_DSI_CON,  in mtk_mipi_tx_pll_unprepare()
234 	mtk_phy_clear_bits(base + MIPITX_DSI_BG_CON,  in mtk_mipi_tx_pll_unprepare()
237 	mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_DIV_MSK);  in mtk_mipi_tx_pll_unprepare()