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/linux/Documentation/devicetree/bindings/net/dsa/
H A Dnxp,sja1105.yaml39 # (one for the internal 100base-T1 PHYs and the other for the single
40 # 100base-TX PHY). The "reg" property does not have physical significance.
41 # The PHY addresses to port correspondence is as follows: for 100base-T1,
42 # port 5 has PHY 1, port 6 has PHY 2 etc, while for 100base-TX, port 1 has
93 rx-internal-delay-ps:
94 $ref: "#/$defs/internal-delay-ps"
95 tx-internal-delay-ps:
96 $ref: "#/$defs/internal-delay-ps"
103 internal-delay-ps:
105 Disable tunable delay lines using 0 ps, or enable them and select
[all …]
/linux/arch/parisc/kernel/
H A Dhardware.c48 {HPHW_NPROC,0x182,0x4,0x91,"TNT 100 (891,T500)"},
78 {HPHW_NPROC,0x317,0x4,0x81,"Scorpio 100 (715/100)"},
81 {HPHW_NPROC,0x320,0x4,0x81,"Spectra (725/100)"},
89 {HPHW_NPROC,0x484,0x4,0x81,"UL Proc L-100 (811/D210,D310)"},
113 {HPHW_NPROC,0x580,0x4,0x81,"KittyHawk DC2-100 (K100)"},
115 {HPHW_NPROC,0x582,0x4,0x91,"KittyHawk DC3 100 (K400)"},
118 {HPHW_NPROC,0x585,0x4,0x91,"SkyHawk 100"},
122 {HPHW_NPROC,0x589,0x4,0x81,"UL Proc 1-way T'100 (821/D250,D350)"},
123 {HPHW_NPROC,0x58A,0x4,0x91,"UL Proc 2-way T'100 (831/D250,D350)"},
124 {HPHW_NPROC,0x58B,0x4,0x91,"KittyHawk DC2 100 (K200)"},
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dmicrel-ksz90x1.txt15 value is 0, the maximum value is 3000, and it can be specified in 200ps
17 skew values actually increase in 120ps steps, starting from -840ps. The
29 0 -840ps 0000
30 200 -720ps 0001
31 400 -600ps 0010
32 600 -480ps 0011
33 800 -360ps 0100
34 1000 -240ps 0101
35 1200 -120ps 0110
36 1400 0ps 0111
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H A Dti,dp83869.yaml18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
67 rx-internal-delay-ps:
73 tx-internal-delay-ps:
97 rx-internal-delay-ps = <2000>;
98 tx-internal-delay-ps = <2000>;
H A Dallwinner,sun8i-a83t-emac.yaml79 allwinner,tx-delay-ps:
83 multipleOf: 100
85 External RGMII PHY TX clock delay chain value in ps.
87 allwinner,rx-delay-ps:
91 multipleOf: 100
93 External RGMII PHY TX clock delay chain value in ps.
104 allwinner,rx-delay-ps:
108 multipleOf: 100
110 External RGMII PHY TX clock delay chain value in ps.
H A Dti,dp83822.yaml14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
49 100base-fx (full and half duplex) modes.
51 rx-internal-delay-ps:
58 tx-internal-delay-ps:
111 rx-internal-delay-ps = <1>;
112 tx-internal-delay-ps = <1>;
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110-starfive-visionfive-2-v1.3b.dts29 motorcomm,tx-clk-100-inverted;
33 rx-internal-delay-ps = <1500>;
34 tx-internal-delay-ps = <1500>;
39 motorcomm,tx-clk-100-inverted;
42 rx-internal-delay-ps = <300>;
43 tx-internal-delay-ps = <0>;
/linux/drivers/gpu/drm/radeon/
H A Dsumo_dpm.c74 struct sumo_ps *ps = rps->ps_priv; in sumo_get_ps() local
76 return ps; in sumo_get_ps()
133 u32 grs = 256 * 25 / 100; in sumo_program_grsd()
318 pi->pasi = 65535 * 100 / high_clk; in sumo_calculate_bsp()
319 pi->asi = 65535 * 100 / high_clk; in sumo_calculate_bsp()
343 struct sumo_ps *ps = sumo_get_ps(rps); in sumo_program_bsp() local
345 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; in sumo_program_bsp()
347 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) in sumo_program_bsp()
352 for (i = 0; i < ps->num_levels - 1; i++) in sumo_program_bsp()
357 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) in sumo_program_bsp()
[all …]
H A Dsi_dpm.c260 100,
294 100,
311 100,
486 100,
494 100
533 100,
550 100,
567 100,
974 100
1488 100
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H A Dtrinity_dpm.c40 #define TRINITY_MGCG_SEQUENCE 100
122 #define TRINITY_SYSLS_SEQUENCE 100
302 struct trinity_ps *ps = rps->ps_priv; in trinity_get_ps() local
304 return ps; in trinity_get_ps()
824 struct trinity_ps *ps = trinity_get_ps(rps); in trinity_setup_uvd_clock_table() local
825 u32 uvdstates = (ps->vclk_low_divider | in trinity_setup_uvd_clock_table()
826 ps->vclk_high_divider << 8 | in trinity_setup_uvd_clock_table()
827 ps->dclk_low_divider << 16 | in trinity_setup_uvd_clock_table()
828 ps->dclk_high_divider << 24); in trinity_setup_uvd_clock_table()
1158 struct trinity_ps *ps = trinity_get_ps(rps); in trinity_dpm_force_performance_level() local
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H A Dni_dpm.c651 #define NISLANDS_SYSLS_SEQUENCE 100
735 struct ni_ps *ps = rps->ps_priv; in ni_get_ps() local
737 return ps; in ni_get_ps()
788 struct ni_ps *ps = ni_get_ps(rps); in ni_apply_state_adjust_rules() local
807 for (i = 0; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()
808 if (ps->performance_levels[i].mclk > max_limits->mclk) in ni_apply_state_adjust_rules()
809 ps->performance_levels[i].mclk = max_limits->mclk; in ni_apply_state_adjust_rules()
810 if (ps->performance_levels[i].sclk > max_limits->sclk) in ni_apply_state_adjust_rules()
811 ps->performance_levels[i].sclk = max_limits->sclk; in ni_apply_state_adjust_rules()
812 if (ps->performance_levels[i].vddc > max_limits->vddc) in ni_apply_state_adjust_rules()
[all …]
H A Drs780_dpm.c37 struct igp_ps *ps = rps->ps_priv; in rs780_get_ps() local
39 return ps; in rs780_get_ps()
420 udelay(100); in rs780_force_fbdiv()
529 udelay(100); in rs780_enable_voltage_scaling()
751 struct igp_ps *ps = rs780_get_ps(rps); in rs780_parse_pplib_clock_info() local
756 ps->sclk_low = sclk; in rs780_parse_pplib_clock_info()
759 ps->sclk_high = sclk; in rs780_parse_pplib_clock_info()
763 ps->min_voltage = RS780_VDDC_LEVEL_UNKNOWN; in rs780_parse_pplib_clock_info()
764 ps->max_voltage = RS780_VDDC_LEVEL_UNKNOWN; in rs780_parse_pplib_clock_info()
767 ps->min_voltage = RS780_VDDC_LEVEL_LOW; in rs780_parse_pplib_clock_info()
[all …]
/linux/tools/testing/selftests/mm/
H A Dthuge-gen.c64 void show(unsigned long ps) in show() argument
66 char buf[100]; in show()
68 if (ps == getpagesize()) in show()
71 ksft_print_msg("%luMB: ", ps >> 20); in show()
76 ps >> 10); in show()
84 char buf[100]; in read_sysfs()
107 unsigned long read_free(unsigned long ps) in read_free() argument
109 return read_sysfs(ps != getpagesize(), in read_free()
111 ps >> 10); in read_free()
225 unsigned long ps = page_sizes[i]; in main() local
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-dhcom-pdk2.dts7 * DHCOM PCB number: 660-100 or newer
174 max-speed = <100>;
179 rxc-skew-ps = <3000>;
180 rxd0-skew-ps = <0>;
181 rxd1-skew-ps = <0>;
182 rxd2-skew-ps = <0>;
183 rxd3-skew-ps = <0>;
184 rxdv-skew-ps = <0>;
185 txc-skew-ps = <3000>;
186 txd0-skew-ps = <0>;
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu10_hwmgr.c45 #define SMU10_DISPCLK_BYPASS_THRESHOLD 10000 /* 100Mhz */
264 if (clock && smu10_data->gfx_max_freq_limit != (clock * 100)) { in smu10_set_soft_max_gfxclk_by_freq()
265 smu10_data->gfx_max_freq_limit = clock * 100; in smu10_set_soft_max_gfxclk_by_freq()
483 ptable->entries[i].clk = pclk_dependency_table->Freq * 100; in smu10_get_clock_voltage_dependency_table()
629 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100; in smu10_dpm_force_dpm_level()
642 min_sclk /= 100; /* transfer 10KHz to MHz */ in smu10_dpm_force_dpm_level()
659 data->gfx_max_freq_limit/100, in smu10_dpm_force_dpm_level()
676 data->gfx_max_freq_limit/100, in smu10_dpm_force_dpm_level()
786 (data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk / 100) : in smu10_dpm_force_dpm_level()
792 data->clock_vol_info.vdd_dep_on_socclk->entries[0].clk / 100, in smu10_dpm_force_dpm_level()
[all …]
H A Dsmu7_hwmgr.c88 {1, 0, 100, 30, 1, 0, 100, 10},
91 {1, 0, 11, 50, 1, 0, 100, 10},
1513 …percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1]… in smu7_populate_umdpstate_clocks()
1518 tmp_sclk = hwmgr->pstate_mclk * percentage / 100; in smu7_populate_umdpstate_clocks()
1558 hwmgr->pstate_sclk /= 100; in smu7_populate_umdpstate_clocks()
1559 hwmgr->pstate_mclk /= 100; in smu7_populate_umdpstate_clocks()
1560 hwmgr->pstate_sclk_peak /= 100; in smu7_populate_umdpstate_clocks()
1561 hwmgr->pstate_mclk_peak /= 100; in smu7_populate_umdpstate_clocks()
1837 data->current_profile_setting.sclk_down_hyst = 100; in smu7_init_dpm_defaults()
1856 data->current_profile_setting.mclk_down_hyst = 100; in smu7_init_dpm_defaults()
[all …]
/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria10_socdk.dtsi74 * These skews assume the user's FPGA design is adding 600ps of delay
81 txd0-skew-ps = <0>; /* -420ps */
82 txd1-skew-ps = <0>; /* -420ps */
83 txd2-skew-ps = <0>; /* -420ps */
84 txd3-skew-ps = <0>; /* -420ps */
85 rxd0-skew-ps = <420>; /* 0ps */
86 rxd1-skew-ps = <420>; /* 0ps */
87 rxd2-skew-ps = <420>; /* 0ps */
88 rxd3-skew-ps = <420>; /* 0ps */
89 txen-skew-ps = <0>; /* -420ps */
[all …]
H A Dsocfpga_arria5_socdk.dts65 rxd0-skew-ps = <0>;
66 rxd1-skew-ps = <0>;
67 rxd2-skew-ps = <0>;
68 rxd3-skew-ps = <0>;
69 txen-skew-ps = <0>;
70 txc-skew-ps = <2600>;
71 rxdv-skew-ps = <0>;
72 rxc-skew-ps = <2000>;
93 * because the LCD module does not work at the standard 100Khz
H A Dsocfpga_cyclone5_socdk.dts69 rxd0-skew-ps = <0>;
70 rxd1-skew-ps = <0>;
71 rxd2-skew-ps = <0>;
72 rxd3-skew-ps = <0>;
73 txen-skew-ps = <0>;
74 txc-skew-ps = <2600>;
75 rxdv-skew-ps = <0>;
76 rxc-skew-ps = <2000>;
97 * because the LCD module does not work at the standard 100Khz
/linux/drivers/net/wireless/ath/
H A Ddfs_pattern_detector.c38 #define PPB_THRESH_RATE(PPB, RATE) ((PPB * RATE + 100 - RATE) / 100)
43 #define WIDTH_LOWER(X) ((X*(100-WIDTH_TOLERANCE)+50)/100)
44 #define WIDTH_UPPER(X) ((X*(100+WIDTH_TOLERANCE)+50)/100)
93 FCC_PATTERN(5, 50, 100, 1000, 2000, 1, 1, true),
118 JP_PATTERN(7, 50, 100, 1000, 2000, 1, 3, 50, true),
293 struct pri_sequence *ps = pd->add_pulse(pd, event); in dpd_add_pulse() local
294 if (ps != NULL) { in dpd_add_pulse()
301 ps->pri, ps->count, ps->count_falses); in dpd_add_pulse()
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-icore-rqs.dtsi174 rxc-skew-ps = <1140>;
175 txc-skew-ps = <1140>;
176 txen-skew-ps = <600>;
177 rxdv-skew-ps = <240>;
178 rxd0-skew-ps = <420>;
179 rxd1-skew-ps = <600>;
180 rxd2-skew-ps = <420>;
181 rxd3-skew-ps = <240>;
182 txd0-skew-ps = <60>;
183 txd1-skew-ps = <60>;
[all …]
/linux/include/linux/phy/
H A Dphy-mipi-dphy.h22 * Maximum value: 60000 ps
34 * Minimum value: 60000 ps + 52 * @hs_clk_rate period in ps
56 * Minimum value: 38000 ps
57 * Maximum value: 95000 ps
68 * Minimum value: 95000 ps
69 * Maximum value: 300000 ps
79 * Maximum value: 38000 ps
90 * Minimum value: 60000 ps
108 * Maximum value: 35000 ps + 4 * @hs_clk_rate period in ps
119 * Maximum value: 105000 ps + 12 * @hs_clk_rate period in ps
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Dps.c8 #include "ps.h"
95 100, 15000, true, rtwdev, in rtw_power_mode_change()
127 * PS bit could be sent due to incorrect REG_TCR setting. in __rtw_fw_leave_lps_check_reg()
129 * In our test, 100ms should be enough for firmware to finish in __rtw_fw_leave_lps_check_reg()
130 * the flow. If REG_TCR Register is still incorrect after 100ms, in __rtw_fw_leave_lps_check_reg()
219 "Should enter LPS before entering deep PS\n"); in __rtw_enter_lps_deep()
265 "Should leave deep PS before leaving LPS\n"); in __rtw_leave_lps()
337 if (data.count == 1 && data.found_vif->cfg.ps) { in rtw_recalc_lps()
/linux/arch/arm/boot/dts/st/
H A Dstm32mp15xx-dhcor-testbench.dtsi59 adc2: adc@100 {
96 rxc-skew-ps = <1500>;
97 rxdv-skew-ps = <540>;
98 rxd0-skew-ps = <420>;
99 rxd1-skew-ps = <420>;
100 rxd2-skew-ps = <420>;
101 rxd3-skew-ps = <420>;
103 txc-skew-ps = <1440>;
104 txen-skew-ps = <540>;
105 txd0-skew-ps = <420>;
[all …]
/linux/arch/microblaze/boot/dts/
H A Dsystem.dts137 xlnx,mch-plb-clk-period-ps = <0x1f40>;
166 xlnx,tavdv-ps-mem-0 = <0x1adb0>;
167 xlnx,tavdv-ps-mem-1 = <0x3a98>;
168 xlnx,tavdv-ps-mem-2 = <0x3a98>;
169 xlnx,tavdv-ps-mem-3 = <0x3a98>;
170 xlnx,tcedv-ps-mem-0 = <0x1adb0>;
171 xlnx,tcedv-ps-mem-1 = <0x3a98>;
172 xlnx,tcedv-ps-mem-2 = <0x3a98>;
173 xlnx,tcedv-ps-mem-3 = <0x3a98>;
174 xlnx,thzce-ps-mem-0 = <0x88b8>;
[all …]

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