| /freebsd/sys/dev/mii/ |
| H A D | miidevs | 3 /*-
35 * For a complete list see http://standards-oui.ieee.org/
39 * IEEE 802.3u-1995, subclause 22.2.4.3.1, figure 22-12, depicts the right
40 * mapping; the bit positions are defined in IEEE 802-1990, figure 5.2.
41 * (There is a formal 802.3 interpretation, number 1-07/98 of July 09 1998,
68 oui PMCSIERRA 0x00e004 PMC-Sierra
109 oui xxPMCSIERRA 0x0009c0 PMC-Sierra
110 oui xxPMCSIERRA2 0x009057 PMC-Sierra
120 model AGERE ET1011 0x0001 ET1011 10/100/1000baseT PHY
121 model AGERE ET1011C 0x0004 ET1011C 10/100/1000baseT PHY
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| H A D | bmtphyreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
48 #define AUX_CTL_FEF_EN 0x0020 /* far-end fault enable */
51 #define AUX_STS_FX_MODE 0x0400 /* 100base-FX mode (strap pin) */
53 #define AUX_STS_100BASE_LINK 0x0100 /* 1 = 100base link */
59 #define AUX_STS_TXERROR 0x0004 /* Tx error detected */
63 #define MII_BMTPHY_RXERROR_CTR 0x12 /* 100base-X Rx error counter */
66 #define MII_BMTPHY_FCS_CTR 0x13 /* 100base-X false carrier counter */
69 #define MII_BMTPHY_DIS_CTR 0x14 /* 100base-X disconnect counter */
81 #define AUX_CSR_ANEG 0x0008 /* auto-negotiation activated */
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| H A D | rgephyreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
60 #define RGEPHY_S100 RGEPHY_BMCR_SPD0 /* 100mpbs */
64 #define RGEPHY_BMSR_100T4 0x8000 /* 100 base T4 capable */
65 #define RGEPHY_BMSR_100TXFDX 0x4000 /* 100 base Tx full duplex capable */
66 #define RGEPHY_BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */
67 #define RGEPHY_BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */
68 #define RGEPHY_BMSR_10THDX 0x0800 /* 10 base T half duplex capable */
69 #define RGEPHY_BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */
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| H A D | mii.h | 3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
63 #define BMCR_S100 BMCR_SPEED0 /* 100 Mb/s */
69 #define BMSR_100T4 0x8000 /* 100 base T4 capable */
70 #define BMSR_100TXFDX 0x4000 /* 100 base Tx full duplex capable */
71 #define BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */
72 #define BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */
73 #define BMSR_10THDX 0x0800 /* 10 base T half duplex capable */
74 #define BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */
75 #define BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */
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| H A D | icsphyreg.h | 3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
44 *--------------------------------------------------------------
49 * 4 Auto-Neg. Advertisement * * *
50 * 5 Auto-Neg. Link Parent Adv * * *
51 * 6 Auto-Neg. Expansion * * *
52 * 7 Auto-Neg. Next Page Tx * *
56 * 12 10Base-T Operation * * *
68 #define QPR_SPEED 0x8000 /* 100Mbps */
99 *-------------------------------------------------------------------
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| H A D | ciphyreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
39 * Register definitions for the Cicada CS8201 10/100/1000 gigE copper
56 #define CIPHY_S100 CIPHY_BMCR_SPD0 /* 100mpbs */
61 #define CIPHY_BMSR_100T4 0x8000 /* 100 base T4 capable */
62 #define CIPHY_BMSR_100TXFDX 0x4000 /* 100 base Tx full duplex capable */
63 #define CIPHY_BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */
64 #define CIPHY_BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */
65 #define CIPHY_BMSR_10THDX 0x0800 /* 10 base T half duplex capable */
[all …]
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| H A D | lxtphyreg.h | 4 /*-
5 * SPDX-License-Identifier: BSD-2-Clause
44 /* All bits user-defined */
57 #define CONFIG_TXMIT_TEST 0x4000 /* 100base-T Transmit Test */
60 #define CONFIG_TPLOOP 0x0800 /* Disable 10base-T Loopback */
70 #define CONFIG_ADVTXCLK 0x0020 /* Advance TX clock */
71 #define CONFIG_5BSYMBOL 0x0010 /* 5-bit Symbol mode */
73 #define CONFIG_100BASEFX 0x0004 /* 100base-FX */
78 #define CSR_DUPLEX 0x1000 /* Full-duplex */
79 #define CSR_SPEED 0x0800 /* 100Mbps */
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | ti,dp83869.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
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| H A D | ti,dp83867.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
21 The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet
34 nvmem-cells:
40 nvmem-cell-names:
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| H A D | ethernet-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
20 local-ma
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| H A D | ti,dp83822.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Davis <afd@ti.com>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
24 - $ref: ethernet-phy.yaml#
30 ti,link-loss-low:
39 ti,fiber-mode:
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| /freebsd/sys/contrib/device-tree/Bindings/net/dsa/ |
| H A D | nxp,sja1105.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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| /freebsd/share/man/man4/ |
| H A D | bce.4 | 1 .\" Copyright (c) 2006-2014 QLogic Corporation
35 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
62 .Bl -item -offset indent -compact
72 10/100/1000Mbps operation in full-duplex mode
74 10/100Mbps operation in half-duplex mode
80 .Bl -tag -width ".Cm 10baseT/UTP"
92 .Cm full-duplex
94 .Cm half-duplex
96 .It Cm 100baseTX
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| H A D | aue.4 | 15 .\" 4. Neither the name of the author nor the names of any co-contributors
41 .Bd -ragged -offset indent
53 .Bd -literal -offset indent
63 will operate at 100Base-TX and full-duplex.
65 The Pegasus contains a 10/100
69 100Mbps peripherals, the existing USB standard specifies a maximum
72 achieve 100Mbps speeds with these devices.
74 The Pegasus supports a 64-bit multicast hash table, single perfect
82 .Bl -tag -width xxxxxxxxxxxxxxxxxxxx
94 .Ar full-duplex
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | microchip,sparx5-serdes.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
21 * Rx built-in fault detector (loss-of-lock/loss-of-signal)
22 * Adjustable tx de-emphasis (FFE)
23 * Tx output amplitude control
31 The SERDES6G is a high-speed SERDES interface, which can operate at
34 * 100 Mbps (100BASE-FX)
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| /freebsd/sys/dev/igc/ |
| H A D | igc_defines.h | 1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
128 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
129 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
215 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
217 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
220 #define IGC_CTRL_SPD_100 0x00000100 /* Force 100Mb */
252 #define IGC_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
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| /freebsd/sys/net/ |
| H A D | sff8472.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2013 George V. Neville-Neil
30 * The following set of constants are from Document SFF-8472
39 * Base Address 0xa0 (Identification Data)
40 * 0-95 Serial ID Defined by SFP MSA
41 * 96-127 Vendor Specific Data
42 * 128-255 Reserved
44 * Base Address 0xa2 (Diagnostic Data)
45 * 0-55 Alarm and Warning Thresholds
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| H A D | sff8436.h | 1 /*-
29 * The following set of constants are from Document SFF-8436
34 * 1) 256-byte addressable block and 128-byte pages
35 * 2) Lower 128-bytes addresses always refer to the same page
44 * 0-127 Monitoring data & page select byte
45 * 128-255:
48 * 128-191 Base ID Fields
49 * 191-223 Extended ID
50 * 223-255 Vendor Specific ID
53 * 128-255 App-specific data
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| /freebsd/sys/dev/e1000/ |
| H A D | e1000_defines.h | 2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
173 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
174 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
262 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
264 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
267 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
332 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
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| H A D | README | 9 - Overview
10 - Identifying Your Adapter
11 - Building and Installation
12 - Additional Features and Configurations
13 - Known Issues/Troubleshooting
14 - Support
15 - License
21 been developed for use with all community-supported versions of FreeBSD.
30 This release includes two gigabit FreeBSD base Drivers for Intel(R) Ethernet.
33 - The igb driver supports all 82575 and 82576-based gigabit network connections.
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| /freebsd/sys/dev/dwc/ |
| H A D | if_dwc_rk.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
121 struct dwc_softc base; member
167 {"rockchip,rk3288-gmac", (uintptr_t)&rk3288_ops},
168 {"rockchip,rk3328-gmac", (uintptr_t)&rk3328_ops},
169 {"rockchip,rk3399-gmac", (uintptr_t)&rk3399_ops},
177 uint32_t tx, rx; in rk3328_set_delays() local
179 if (!mii_contype_is_rgmii(sc->base.phy_mode)) in rk3328_set_delays()
182 reg = SYSCON_READ_4(sc->grf, RK3328_GRF_MAC_CON0); in rk3328_set_delays()
183 tx = ((reg >> MAC_CON0_GMAC2IO_TX_DL_CFG_SHIFT) & MAC_CON0_GMAC2IO_TX_DL_CFG_MASK); in rk3328_set_delays()
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm/nxp/vf/ |
| H A D | vf610-zii-scu4-aib.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 // Copyright (C) 2016-2018 Zodiac Inflight Innovations
5 /dts-v1/;
10 compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610";
13 stdout-path = &uart0;
21 gpio-leds {
22 compatible = "gpio-leds";
23 pinctrl-
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| /freebsd/sys/dev/le/ |
| H A D | lancereg.h | 3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
34 /*-
70 * - Am7990 Local Area Network Controller for Ethernet (LANCE)
71 * (and its descendent Am79c90 C-LANCE).
73 * - Am79c900 Integrated Local Area Communications Controller (ILACC)
75 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
77 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
80 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
83 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
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| /freebsd/sys/dev/msk/ |
| H A D | if_mskreg.h | 17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
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| /freebsd/sys/dev/dc/ |
| H A D | if_dcreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
40 #define DC_TXSTART 0x08 /* tx start demand */
43 #define DC_TXADDR 0x20 /* tx descriptor list start addr */
85 (x->dc_type == DC_TYPE_98713 || \
86 x->dc_type == DC_TYPE_98713A || \
87 x->dc_type == DC_TYPE_987x5)
90 (x->dc_type == DC_TYPE_AL981 || \
91 x->dc_type == DC_TYPE_AN983)
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