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/freebsd/sys/contrib/dev/athk/ath10k/
H A Drx_desc.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
13 RX_ATTENTION_FLAGS_FIRST_MPDU = BIT(0),
14 RX_ATTENTION_FLAGS_LAST_MPDU = BIT(1),
15 RX_ATTENTION_FLAGS_MCAST_BCAST = BIT(2),
16 RX_ATTENTION_FLAGS_PEER_IDX_INVALID = BIT(3),
17 RX_ATTENTION_FLAGS_PEER_IDX_TIMEOUT = BIT(4),
18 RX_ATTENTION_FLAGS_POWER_MGMT = BIT(5),
19 RX_ATTENTION_FLAGS_NON_QOS = BIT(6),
[all …]
/freebsd/sys/contrib/dev/athk/ath12k/
H A Drx_desc.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
27 #define RX_MPDU_START_INFO0_FLOW_ID_TOEPLITZ BIT(7)
28 #define RX_MPDU_START_INFO0_PKT_SEL_FP_UCAST_DATA BIT(8)
29 #define RX_MPDU_START_INFO0_PKT_SEL_FP_MCAST_DATA BIT(9)
30 #define RX_MPDU_START_INFO0_PKT_SEL_FP_CTRL_BAR BIT(10)
33 #define RX_MPDU_START_INFO0_MCAST_ECHO_DROP_EN BIT(17)
34 #define RX_MPDU_START_INFO0_WDS_LEARN_DETECT_EN BIT(18)
35 #define RX_MPDU_START_INFO0_INTRA_BSS_CHECK_EN BIT(19)
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H A Dhal_desc.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
56 * Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
57 * Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
58 * Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
59 * Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
60 * Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
61 * Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
65 * Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
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/freebsd/sys/dev/msk/
H A Dif_mskreg.h17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
57 * 1. Redistributions of source code must retain the above copyright
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
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/freebsd/sys/contrib/dev/athk/ath11k/
H A Drx_desc.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
28 #define RX_DESC_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0)
88 #define RX_ATTENTION_INFO1_FIRST_MPDU BIT(0)
89 #define RX_ATTENTION_INFO1_RSVD_1A BIT(1)
90 #define RX_ATTENTION_INFO1_MCAST_BCAST BIT(2)
91 #define RX_ATTENTION_INFO1_AST_IDX_NOT_FOUND BIT(3)
92 #define RX_ATTENTION_INFO1_AST_IDX_TIMEDOUT BIT(4)
93 #define RX_ATTENTION_INFO1_POWER_MGMT BIT(5)
94 #define RX_ATTENTION_INFO1_NON_QOS BIT(6)
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H A Dhal_desc.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
52 HAL_PHYRX_DATA = 1 /* 0x1 */,
475 #define HAL_TLV_HDR_TAG GENMASK(9, 1)
488 #define RX_MPDU_DESC_INFO0_FRAG_FLAG BIT(20)
489 #define RX_MPDU_DESC_INFO0_MPDU_RETRY BIT(21)
490 #define RX_MPDU_DESC_INFO0_AMPDU_FLAG BIT(22)
491 #define RX_MPDU_DESC_INFO0_BAR_FRAME BIT(23)
492 #define RX_MPDU_DESC_INFO0_VALID_PN BIT(24)
493 #define RX_MPDU_DESC_INFO0_VALID_SA BIT(25)
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/freebsd/sys/contrib/edk2/Include/Library/
H A DBaseLib.h3 functions, file path functions, and CPU architecture-specific functions.
5 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
6 Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
18 // Definitions for architecture-specific types
22 /// The IA-32 architecture context buffer used by SetJump() and LongJump().
54 UINT8 XmmBuffer[160]; ///< XMM6-XMM15.
132 /// The RISC-V architecture context buffer used by SetJump() and LongJump().
161 Returns the length of a Null-terminated Unicode string.
165 If String is not aligned on a 16-bit boundary, then ASSERT().
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/freebsd/sys/contrib/device-tree/Bindings/hwmon/
H A Dmax6697.txt4 - compatible:
16 - reg: I2C address
20 - smbus-timeout-disable
23 - extended-range-enable
24 Only valid for MAX6581. Set to enable extended temperature range.
26 - beta-compensation-enable
27 Only valid for MAX6693 and MX6694. Set to enable beta compensation on
28 remote temperature channel 1.
30 - alert-mask
31 Alert bit mask. Alert disabled for bits set.
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/freebsd/sys/isa/
H A Dpnpreg.h1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
10 * 1. Redistributions of source code must retain the above copyright
18 * 4. Neither the name of the author nor the names of any co-contributors
57 state to compare one bit of the boards ID.
58 This register is read only.
66 Bit[2] Reset CSN to 0
67 Bit[1] Return to the Wait for Key state
68 Bit[0] Reset all logical devices and restore configuration
69 registers to their power-up values.
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/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Drx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2015-2017 Intel Deutschland GmbH
10 /* API for pre-900
[all...]
H A Dtime-event.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2020, 2022-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-201
[all...]
H A Dmac-cfg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2019, 2021-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-201
[all...]
/freebsd/stand/common/
H A Disapnp.h8 * 1. Redistributions of source code must retain the above copyright
16 * 4. Neither the name of the author nor the names of any co-contributors
61 state to compare one bit of the boards ID.
62 This register is read only.
67 Bit[2] Reset CSN to 0
68 Bit[1] Return to the Wait for Key state
69 Bit[0] Reset all logical devices and restore configuration
70 registers to their power-up values.
72 A write to bit[0] of this register performs a reset function on
77 A write to bit[1] of this register causes all cards to enter the
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/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Ddivider.txt3 This binding uses the common clock binding[1]. It assumes a
4 register-mapped adjustable clock rate divider that does not gate and has
5 only one input clock or parent. By default the value programmed into
9 0 1
10 1 2
15 ti,index-starts-at-one - valid divisor values start at 1, not the default
18 1 1
22 ti,index-power-of-two - valid divisor values are powers of two. E.g:
24 0 1
25 1 2
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/freebsd/sys/dev/ice/
H A Dice_adminq_cmd.h1 /* SPDX-License-Identifier: BSD-3-Clause */
8 * 1. Redistributions of source code must retain the above copyright notice,
48 ICE_RES_READ = 1,
87 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
104 #define ICE_AQC_RES_ID_NVM 1
109 #define ICE_AQC_RES_ACCESS_READ 1
123 /* Status is only use
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/freebsd/sys/x86/include/
H A Dsegments.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
14 * 1. Redistributions of source code must retain the above copyright
57 * User segment descriptors (%cs, %ds etc for i386 apps. 64 bit wide)
58 * For long-mode apps, %cs only has the conforming bit in sd_type, the sd_dpl,
59 * sd_p, sd_l and sd_def32 which must be zero). %ds only has sd_p.
66 unsigned sd_p:1; /* segment descriptor present */
69 unsigned sd_def32:1; /* default 32 vs 16 bit size */
70 unsigned sd_gran:1; /* limit granularity (byte/page units)*/
79 unsigned sd_p:1; /* segment descriptor present */
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/freebsd/usr.bin/clang/llvm-nm/
H A Dllvm-nm.14 .nr rst2man-indent-level 0
7 \\$1 \\n[an-margin]
8 level \\n[rst2man-indent-level]
9 level margin: \\n[rst2man-indent\\n[rst2man-indent-level]]
10 -
11 \\n[rst2man-indent0]
12 \\n[rst2man-indent1]
13 \\n[rst2man-indent2]
17 . RS \\$1
18 . nr rst2man-indent\\n[rst2man-indent-level] \\n[an-margin]
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/freebsd/secure/usr.bin/openssl/man/
H A Dopenssl-enc.118 .\" Set up some character translations and predefined strings. \*(-- will
24 .tr \(*W-
27 . ds -- \(*W-
29 . if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
30 . if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch
37 . ds -- \|\(em\|
62 . tm Index:\\$1\t\\n%\t"\\$2"
71 .\" Fear. Run. Save yourself. No user-serviceable parts.
81 . ds #H ((1u-(\\\\n(.fu%2u))*.13m)
97 . ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u"
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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_pcie_w_reg.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
376 * - If MSI-X is enabled and auto_clear control bit =TRUE, automatically
377 * cleared after MSI-X message associated with this specific interrupt
378 * bit is sent (MSI-X acknowledge is received).
379 * - Software can set a bit in this register by writing 1 to the
380 * associated bit in the Interrupt Cause Set register
381 * Write-0 clears a bit. Write-1 has no effect.
382 * - On CPU Read - If clear_on_read control bit =TRUE, automatically
385 * to set a bit in the Interrupt Cause register, the specific bit is set
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/freebsd/sys/contrib/ck/include/
H A Dck_ec.h8 * 1. Redistributions of source code must retain the above copyright
31 * ck_ec implements 32- and 64- bit event counts. Event counts let us
32 * easily integrate OS-level blocking (e.g., futexes) in lock-free
36 * Event counts come in four variants: 32 and 64 bit (with one bit
37 * stolen for internal signaling, so 31 and 63 bit counters), and
39 * consumers. The 32 bit variants are smaller, and more efficient,
40 * especially in single producer mode. The 64 bit variants are larger,
43 * The 32 bit variant is always available. The 64 bit variant is only
44 * available if CK supports 64-bit atomic operations. Currently,
45 * specialization for single producer is only implemented for x86 and
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/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DARMWinEH.h1 //===-- llvm/Support/ARMWinEH.h - Windows on ARM EH Constants ---*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
27 RT_B, /// 16-bit branch
28 RT_BW, /// 32-bit branch
32 /// RuntimeFunction - An entry in the table of procedure data (.pdata)
37 /// 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
38 /// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
39 /// +---------------------------------------------------------------+
41 /// +-------------------+-+-+-+-----+-+---+---------------------+---+
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/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
9 * 1. Redistributions of source code must retain the above copyright
35 …_K2_E5 (0x1<<1) // It indicates ras…
36 …GLCS_REG_INT_STS_RASDP_ERROR_K2_E5_SHIFT 1
38 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
40 … (0x1<<1) // This bit masks, when set, the Interrupt …
41 …GLCS_REG_INT_MASK_RASDP_ERROR_K2_E5_SHIFT 1
45 …ROR_K2_E5 (0x1<<1) // It indicates ras…
46 …GLCS_REG_INT_STS_WR_RASDP_ERROR_K2_E5_SHIFT 1
50 …RROR_K2_E5 (0x1<<1) // It indicates ras…
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/freebsd/contrib/file/magic/Magdir/
H A Delf2 #------------------------------------------------------------------------------
4 # elf: file(1) magic for ELF executables
14 # Modified by (1): Daniel Quinlan <quinlan@yggdrasil.com>
15 # Modified by (2): Peter Tobias <tobias@server.et-inf.fho-emden.de> (core support)
20 0 name elf-mips
21 >0 lelong&0xf0000000 0x00000000 MIPS-I
22 >0 lelong&0xf0000000 0x10000000 MIPS-II
23 >0 lelong&0xf0000000 0x20000000 MIPS-III
24 >0 lelong&0xf0000000 0x30000000 MIPS-IV
25 >0 lelong&0xf0000000 0x40000000 MIPS-V
[all …]
/freebsd/contrib/wpa/src/common/
H A Dqca-vendor.h3 * Copyright (c) 2014-2017, Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2020, The Linux Foundation
5 * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc.
23 #ifndef BIT
24 #define BIT(x) (1U << (x)) macro
28 * enum qca_radiotap_vendor_ids - QCA radiotap vendor namespace IDs
41 * Global NSS configuration - Applies to all bands (2.4 GHz and 5/6 GHz)
52 * @QCA_WLAN_VENDOR_ATTR_CONFIG_NSS: Only symmetric NSS configuration
53 * (such as 2X2 or 1X1) can be done using this attribute.
60 * configuration (such as 2X2 or 1X1) or asymmetric configuration (such as 1X2).
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/freebsd/crypto/openssl/doc/man1/
H A Dopenssl-enc.pod.in2 {- OpenSSL::safe::output_do_not_edit_headers(); -}
6 openssl-enc - symmetric cipher routines
11 [B<-I<cipher>>]
12 [B<-help>]
13 [B<-list>]
14 [B<-ciphers>]
15 [B<-in> I<filename>]
16 [B<-out> I<filename>]
17 [B<-pass> I<arg>]
18 [B<-e>]
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