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2 * Copyright (c) 2017-2018 Cavium, Inc.
9 * 1. Redistributions of source code must retain the above copyright
35 …_K2_E5 (0x1<<1) // It indicates ras…
36 …GLCS_REG_INT_STS_RASDP_ERROR_K2_E5_SHIFT 1
38 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
40 … (0x1<<1) // This bit masks, when set, the Interrupt …
41 …GLCS_REG_INT_MASK_RASDP_ERROR_K2_E5_SHIFT 1
45 …ROR_K2_E5 (0x1<<1) // It indicates ras…
46 …GLCS_REG_INT_STS_WR_RASDP_ERROR_K2_E5_SHIFT 1
50 …RROR_K2_E5 (0x1<<1) // It indicates ras…
51 …GLCS_REG_INT_STS_CLR_RASDP_ERROR_K2_E5_SHIFT 1
54 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
55 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
56 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
57 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
78 …only: Reserved bits for ECO. Bit 0 - For ending "endless completion". 0 - When receiving a complet…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 … // 0 - RX target read and config sync fifo push overflow 1 - RX header sync fifo push overflow…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
83 …he value will not be loaded, EEPROM load will stop, and the FastLinkEnable bit will be set in the …
88 …ndor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of this field are…
90 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
100 … (0x1<<1) // Memory space acc…
101 …CIEIP_REG_PCIEEP_CMD_MSAE_E5_SHIFT 1
102 …aster enable. If the PF or any of its VFs try to master the bus when this bit is not set, the req…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
147 …1) // Enables Memory Access Response. You cannot write to this register if your configuration ha…
148 …CIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_K2_SHIFT 1
185 …2 (0x1<<30) // Fatal or Non-Fatal Error Message s…
189 …20 // This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)
190 … (0x1<<0) // This bit indicates that the …
192 …BB (0x1<<1) // This bit controls the e…
193 …CIEIP_REG_STATUS_COMMAND_MEM_SPACE_BB_SHIFT 1
194 … (0x1<<2) // This bit controls the enabli…
202 …6) // This bit enables the write to the Master data parity error status bit. If this bit is cleare…
206 …bit enables the non fatal and fatal errors detected by the function to be reported to the Root Com…
210 …bit is set, function is not permitted to generate IntX interrupt messages (de-asserted) regardless…
216 …/ This bit indicates the internal interrupt request state (before being masked by INT_DISABLE. A '…
218 … (0x1<<20) // This bit is tied high to ind…
226 …bit is set by a requester if the parity error enable bit is set in its command register and either…
230 …BB (0x1<<27) // This bit is set when a funct…
232 …BB (0x1<<28) // This bit is set when a reque…
234 …_BB (0x1<<29) // This bit is set when a reque…
236 … (0x1<<30) // This bit is set when a function sends an ERR_FATAL or ERR_NONFATAL messag…
238 … (0x1<<31) // When this bit is set, it indicate…
250 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
252 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
254 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
256 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
261 … (0xffffff<<8) // The 24-bit Class Code register…
270 …vice. The multi function device bit is writable through PEM()_CFG_WR. The application must not wr…
281 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
290 …ER_TYPE_BB (0xff<<16) // The 8-bit Header Type registe…
292 … (0xff<<24) // The 8-bit BIST register is used to initiate and report the results o…
295 … (0x1<<0) // Memory space indicator. 0 = BAR 0 is a memory BAR. 1 = BAR 0 is an I/O BA…
297 … (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-b…
298 …CIEIP_REG_PCIEEP_BAR0L_TYP_E5_SHIFT 1
303 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
304 …ccess attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_E…
306 …3<<1) // BAR0 32-bit or 64-bit. Note: The access attributes of this field are as follows: - Dbi…
307 …CIEIP_REG_BAR0_REG_BAR0_TYPE_K2_SHIFT 1
308 …ccess attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_E…
310 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
312 …-bit BAR_1 register programs the base address for the memory space mapped by the card onto the PCI…
313 … (0x1<<0) // This bit indicates that BAR_…
315 … (0x3<<1) // These bits indicate that BAR_1 may be programmed to map this adapt…
316 …CIEIP_REG_BAR_1_SPACE_TYPE_BB_SHIFT 1
317 … (0x1<<3) // This bit indicates that the area mapped by BAR_1 may be pre-fetched or cached by th…
319 …-bit address space that will be card will respond in. These bits may be combined with the bits in …
322 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
323 …ccess attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_E…
325 …3<<1) // BAR1 32-bit or 64-bit. Note: The access attributes of this field are as follows: - Dbi…
326 …CIEIP_REG_BAR1_REG_BAR1_TYPE_K2_SHIFT 1
327 …ccess attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_E…
329 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
331 … 0x000014UL //Access:RW DataWidth:0x20 // The 32-bit BAR_2 register prog…
333 … (0x1<<0) // Memory space indicator. 0 = BAR 1 is a memory BAR. 1 = BAR 1 is an …
335 … (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-b…
336 …CIEIP_REG_PCIEEP_BAR2L_TYP_E5_SHIFT 1
341 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
342 …ccess attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_E…
344 …3<<1) // BAR2 32-bit or 64-bit. Note: The access attributes of this field are as follows: - Dbi…
345 …CIEIP_REG_BAR2_REG_BAR2_TYPE_K2_SHIFT 1
346 …ccess attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_E…
348 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
350 …-bit BAR_3 register programs the 2nd base address for the memory space mapped by the card onto the…
351 … (0x1<<0) // This bit indicates that BAR_…
353 … (0x3<<1) // These bits indicate that BAR_2 may be programmed to map this adapt…
354 …CIEIP_REG_BAR_3_SPACE_TYPE_BB_SHIFT 1
355 … (0x1<<3) // This bit indicates that the area mapped by BAR_2 may b…
357 …-bit address space that will be card will respond in. These bits may be combined with the bits in …
360 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
361 …ccess attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_E…
363 …3<<1) // BAR3 32-bit or 64-bit. Note: The access attributes of this field are as follows: - Dbi…
364 …CIEIP_REG_BAR3_REG_BAR3_TYPE_K2_SHIFT 1
365 …ccess attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_E…
367 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
369 … 0x00001cUL //Access:RW DataWidth:0x20 // The 32-bit BAR_4 register prog…
371 … (0x1<<0) // Memory space indicator. 0 = BAR 2 is a memory BAR. 1 = BAR 2 is an I/O BA…
373 … (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-b…
374 …CIEIP_REG_PCIEEP_BAR4L_TYP_E5_SHIFT 1
379 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
380 …ccess attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_E…
382 …3<<1) // BAR4 32-bit or 64-bit. Note: The access attributes of this field are as follows: - Dbi…
383 …CIEIP_REG_BAR4_REG_BAR4_TYPE_K2_SHIFT 1
384 …ccess attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_E…
386 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
388 …-bit BAR_5 register programs the 3rd base address for the memory space mapped by the card onto the…
389 … (0x1<<0) // This bit indicates that BAR_…
391 … (0x3<<1) // These bits indicate that BAR_3 may be programmed to map this adapt…
392 …CIEIP_REG_BAR_5_SPACE_TYPE_BB_SHIFT 1
393 … (0x1<<3) // This bit indicates that the area mapped by BAR_3 may b…
395 …-bit address space that will be card will respond in. These bits may be combined with the bits in …
398 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
399 …ccess attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_E…
401 …3<<1) // BAR5 32-bit or 64-bit. Note: The access attributes of this field are as follows: - Dbi…
402 …CIEIP_REG_BAR5_REG_BAR5_TYPE_K2_SHIFT 1
403 …ccess attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_E…
405 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
407 … 0x000024UL //Access:RW DataWidth:0x20 // The 32-bit BAR_4 register prog…
412 … (0xffff<<0) // Subsystem vendor ID. Assigned by PCI-SIG, writable through…
414 … (0xffff<<16) // Subsystem ID. Assigned by PCI-SIG, writable through…
417 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
419 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
422 …NDOR_ID_BB (0xffff<<0) // The 16-bit Subsystem Vendor ID…
424 …BB (0xffff<<16) // The 16-bit Subsystem ID regist…
431 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
432 …<<0) // Expansion ROM Enable. Note: The access attributes of this field are as follows: - Dbi: R
434 …Expansion ROM Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W
436 … 0x000030UL //Access:RW DataWidth:0x20 // The 32-bit Expansion ROM BAR r…
437 …bit indicates that the Expansion ROM BAR is valid when set to one. If it is zero, the expansion BA…
439 … (0x3ff<<1) // These bits indic…
440 …CIEIP_REG_EXP_ROM_BAR_LOW_BB_SHIFT 1
449 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
452 …-bit Capabilities Pointer register specifies an offset in the PCI address space of a linked list o…
466 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
469 …NT_LINE_BB (0xff<<0) // The 8-bit Interrupt Line regi…
471 …NT_PIN_BB (0xff<<8) // The 8-bit Interrupt Pin regis…
494 …bit indicates that the device (or function) is not capable of generating PME messages while in tha…
499 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
501 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
505 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
507 …vice Specific Initialization Bit. Note: The access attributes of this field are as follows: - D…
509 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
511 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
513 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
515 …1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1}, where D1_SUPPORT and D2_SUPPORT are fields in this register. …
537 …owever, the read-back value is the actual power state, not the write value. Note: The access attr…
539 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
556 …// The 8-bit Power Management Capability ID is set to 1 to indicate that the next 8 bytes are a Po…
558 …cified an offset in the PCI address space of the next capability. The read-only value of this regi…
560 …ies with revision 1.2 of the PCI Power Management Interface Specification. Bit is programmable thr…
564 …bit indicates that the device relies on the presence of the PCI clock for PME# operation. This chi…
568 …bit indicates that the device requires a specific initialization (DSI) sequence following a transi…
572 …(0x1<<25) // This bit indicates whether the device supports the D1 power management state. This bi…
574 …(0x1<<26) // This bit indicates whether the device supports the D2 power management state. This bi…
576 … // This bit indicates whether the device supports transmiting PME message from the D0 power state…
578 … // This bit indicates whether the device supports transmiting PME message from the D1 power state…
580 … // This bit indicates whether the device supports transmiting PME message from the D2 power state…
582 … This bit indicates whether the device supports transmiting PME message from the D3hot power state…
584 …bit indicates whether the device supports transmiting PME message from the D3cold power state. Thi…
587 …e PCI register space as the PM_STATE bits. When written from the PCI bus, only values of 0 and 3 w…
591 …transitions from D3 to D0, device does not perform an internal reset. This bit can be programmed t…
595 … (0x1<<8) // This bit enables the device to transmit PME messages. On HARD reset, this b…
601 …bit is set when a PME is asserted from the MAC or RX Parser blocks, regardless of the state of the…
610 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
614 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
618 … (0x1<<23) // MSI 64-bit Address Capable. Note: The access attributes of this field are as foll…
623 … (0xff<<0) // The 8-bit VPD Capability ID i…
625 …cified an offset in the PCI address space of the next capability. The read-only value of this regi…
629 …// This value is the 32-bit word address of the VPD value being accessed in the vpd_data register.…
631 …bit is used to control passing of data between the vpd_data register and Non-Volatile memory. To r…
634 …essage Lower Address Field. Note: The access attributes of this field are as follows: - Dbi: R/W
636 … This is the VPD data transfer register. See the instructions for the FLAG bit above for usage of …
637 …58UL //Access:RW DataWidth:0x20 // For a 32 bit MSI Message, this register contains Data. For …
638 …-bit MSI Message, this field contains Data. For 64-bit it contains lower 16 bits of the Upper Addr…
640 …bit MSI Message, this is reserved. For 64-bit it contains upper 16 bits of the Upper Address. Not…
643 … (0xff<<0) // The 8-bit MSI Capability ID i…
645 …cified an offset in the PCI address space of the next capability. The read-only value of this regi…
647 …16) // When this bit is set, the chip will generate MSI cycles to indicate interrupts instead of a…
649 …g. This value comes from the Path = i_cfg_func.i_cfg_private MULTI_MSG_CAP bit in the register spa…
653 … (0x1<<23) // This bit indicates that the chip is capable of generatin…
655 … (0x1<<24) // This bit indicates if the function supports per vector masking. This value come…
657 …5cUL //Access:RW DataWidth:0x20 // For a 64 bit MSI Message, this register contains Data. For …
658 …-bit MSI Message, this field contains Data. For 32-bit, it contains the lower Mask Bits if PVM is …
660 …-bit MSI Message, this field contains Data. For 32-bit, it contains the upper Mask Bits if PVM is …
667 …x20 // Used for MSI when Vector Masking Capable. For 32 bit contains Pending Bits. For 64 bit, c…
669 … 0x000064UL //Access:R DataWidth:0x20 // Used for MSI 64 bit messaging when Vect…
676 … (0xff<<8) // Next capability pointer. Points to the MSI-X Capabilities by def…
682 …This bit is writable through PEM()_CFG_WR. However, it must be 0 for an endpoint device. Therefore…
689 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
695 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
697 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
706 … (0x1<<5) // Extended tag field supported. This bit is writable through…
712 … (0x1<<15) // Role-based error reporting…
714 … (0xff<<18) // Captured slot power limit value. From message from RC, upstream port only.
716 … (0x3<<26) // Captured slot power limit scale. From message from RC, upstream port only.
718 … (0x1<<28) // Function level reset capability. Set to 1 for SR-IOV core.
721 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
723 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
725 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
727 …ies to endpoints only L0s acceptable latency. Note: The access attributes of this field are as f…
729 …lies to endpoints only L1 acceptable latency. Note: The access attributes of this field are as f…
731 …1<<15) // Role-based Error Reporting Implemented. Note: The access attributes of this field are …
737 …Reset Capability (endpoints only). Note: The access attributes of this field are as follows: - …
742 …_EN_E5 (0x1<<1) // Nonfatal error r…
743 …CIEIP_REG_PCIEEP_DEV_CTL_NFE_EN_E5_SHIFT 1
752 … (0x1<<8) // Extended tag field enable. Set this bit to enable extended …
754 … (0x1<<9) // Phantom function enable. This bit should never be set…
762 …_FLR] must not be written to one via the indirect PEM()_CFG_WR. It should only ever be written to …
764 …if we receive any of the errors in PCIEEP_COR_ERR_STAT, for example a replay-timer timeout. Also,…
770 …ests are nonfatal errors, so [UR_D] should cause [NFE_D]. Receiving a vendor-defined message shoul…
774 … (0x1<<21) // Transaction pending. Set to 1 when nonposted reque…
779 …TATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2 (0x1<<1) // Non-fatal Error Repor…
780 …CIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2_SHIFT 1
789 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
791 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
793 …K2 (0x1<<10) // Aux Power PM Enable. This bit is derived by sampl…
795 …(0x1<<11) // Enable No Snoop. Note: The access attributes of this field are as follows: - Dbi: R
803 …_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2 (0x1<<17) // Non-Fatal Error Detected …
809 … (0x1<<20) // Aux Power Detected Status. This bit is derived by sampl…
818 … (0x3<<10) // Active state link PM support. Only L1 is supported (L0…
837 …-PCIe mode, the reset and dynamic values of this field are calculated by the core. Note: The acce…
839 …-PCIe mode, the reset and dynamic values of this field are calculated by the core. Note: The acce…
841 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
843 …bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) deter…
845 …bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) deter…
847 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
855 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
857 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
876 … (0x1<<10) // Link bandwidth management interrupt enable. This bit is not applicable a…
878 … (0x1<<11) // Link autonomous bandwidth interrupt enable. This bit is not applicable a…
882 …bit location in the supported link speeds vector (in the link capabilities 2 register) that corres…
899 …d Completion Boundary (RCB). Note: The access attributes of this field are as follows: - Dbi: R/W
901 …his field are as follows: - Dbi: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_…
903 …e Link Retrain. Note: The access attributes of this field are as follows: - Dbi: see description
909 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
911 …e Autonomous Width Disable. Note: The access attributes of this field are as follows: - Dbi: R/W
913 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
915 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
923 …figuration or Recovery State. Note: The access attributes of this field are as follows: - Dbi: R
925 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
929 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
931 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
942 … (0x1<<7) // 32-bit AtomicOp supported.…
944 … (0x1<<8) // 64-bit AtomicOp supported.…
946 … (0x1<<9) // 128-bit AtomicOp supported.…
948 … (0x1<<10) // No RO-enabled PR-PR passing. (This bit appl…
956 …PP_E5 (0x1<<16) // 10-bit tag completer suppo…
958 …PP_E5 (0x1<<17) // 10-bit tag requestor suppo…
964 … (0x1<<21) // End-end TLP prefix suppor…
966 … (0x3<<22) // Max end-end TLP prefixes. 0x1 = 1. 0x2 =…
977 …E_CAP_32_ATOMIC_CPL_SUPP_K2 (0x1<<7) // 32 Bit AtomicOp Completer …
979 …E_CAP_64_ATOMIC_CPL_SUPP_K2 (0x1<<8) // 64 Bit AtomicOp Completer …
981 …_CAP_128_CAS_CPL_SUPP_K2 (0x1<<9) // 128 Bit CAS Completer Suppo…
983 …R2PR_PAR_K2 (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing.
987 …P_TPH_CMPLT_SUPPORT_0_K2 (0x1<<12) // TPH Completer Supported Bit 0.
989 …P_TPH_CMPLT_SUPPORT_1_K2 (0x1<<13) // TPH Completer Supported Bit 1.
994 …x1 = 50 us to 100 us. 0x2 = 1 ms to 10 ms. 0x3 = 16 ms to 55 ms. 0x6 = 65 ms to 210 ms. 0x9 = …
1008 … (0x1<<10) // Latency tolerance reporting (LTR) mechanism enable. Only R/W for function 0.…
1010 …_E5 (0x1<<12) // 10-bit tag requester enabl…
1014 … (0x1<<15) // End-end TLP prefix blocki…
1017 …/ Completion Timeout Value. Note: The access attributes of this field are as follows: - Dbi: R/W
1036 …1) // Supported link speeds vector. Indicates the supported link speeds of the associated port. F…
1037 …CIEIP_REG_PCIEEP_LINK_CAP2_SLSV_E5_SHIFT 1
1045 …REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_K2 (0x7f<<1) // Supported Link S…
1046 …CIEIP_REG_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_K2_SHIFT 1
1049 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
1052 …e target compliance mode speed when software is using the enter compliance bit to force a link int…
1054 …mode at the speed indicated in the target link speed field by setting this bit to one in both comp…
1056 …he application must disable hardware from changing the link speed for device-specific reasons othe…
1060 …-deemphasized voltage level at the transmitter pins: 0x0 = 800-1200 mV for full swing 400-600 mV …
1062 … (0x1<<10) // Enter modified compliance. When this bit is set to one, the …
1064 …mpliance patterns. When the link is operating at 2.5 GT/s, the setting of this bit has no effect.
1066 …bit sets the deemphasis level in Polling.Compliance state if the entry occurred due to the TX comp…
1068 … operating at 5 GT/s speed, this bit reflects the level of deemphasis. 0 = -6 dB. 1 = -3.5 dB. …
1072 … (0x1<<18) // Equalization phase 1 successful.
1091 …K_SPEED_K2 (0xf<<0) // Target Link Speed. In M-PCIe mode, the conten…
1095 …Speed Disable. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
1097 …EMPHASIS_K2 (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s. …
1101 …ed Compliance. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
1103 … transmission. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1105 … // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. Note: The access attributes of thi…
1107 … (0x1<<16) // Current De-emphasis Level. In M-PCIe mode this register is alwa…
1111 … (0x1<<18) // Equalization 8.0GT/s Phase 1 Successful. Note: …
1126 …cified an offset in the PCI address space of the next capability. The read-only value of this regi…
1128 …<<16) // System sw reads this field to determine the MSI-X table size N, which is encoded as N-1 P…
1132 … (0x1<<30) // If 1, all of the vectors associated with the function are masked regardless…
1134 … (0x1<<31) // If 1, and the MSI enable bit in the M…
1137 … (0x7<<0) // Indicates which one of functions BAR is used to map MSI-X table into memory s…
1142 … (0x7<<0) // Indicates which one of functions BAR is used to map MSI-X PBA into memory spa…
1157 …-X vector is used for the interrupt message generated in association with any of the status bits o…
1160 …MSIXCID_E5 (0xff<<0) // MSI-X capability ID.
1164 … (0x7ff<<16) // MSI-X table size encoded as (table size - 1).…
1166 …ask bit determines whether the vector is masked or not. 1 = All vectors associated with the funct…
1168 … (0x1<<31) // MSI-X enable. If MSI-X is enabled,…
1170 … 0x0000b0UL //Access:RW DataWidth:0x20 // MSI-X Capability ID, Next…
1171 …TRL_REG_PCI_MSIX_CAP_ID_K2 (0xff<<0) // MSI-X Capability ID.
1173 … (0xff<<8) // MSI-X Next Capability Pointer. Note: The access attributes of this field are as f…
1175 …-X Table Size. SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PC…
1177 …(0x1<<30) // Function Mask. Note: The access attributes of this field are as follows: - Dbi: R/W
1179 … (0x1<<31) // MSI-X Enable. Note: The access attributes of this field are…
1186 … (0x1<<5) // Extended Tag Field Support. This bit is programmable thr…
1202 … (0x1<<28) // FLR capability is advertized when flr_supported bit in private device_c…
1205 … (0x7<<0) // MSI-X table BAR indicator register (BIR). Indicates which BAR is u…
1207 … (0x1fffffff<<3) // MSI-X table offset register. Base address of the M…
1209 … 0x0000b4UL //Access:RW DataWidth:0x20 // MSI-X Table Offset and BI…
1210 …7<<0) // MSI-X Table Bar Indicator Register Field. Note: The access attributes of this field are…
1212 … (0x1fffffff<<3) // MSI-X Table Offset. Note: The access attributes of this field are as follows…
1217 …FATAL_ERR_REPORT_EN_BB (0x1<<1) // Non-Fatal Error Repor…
1218 …CIEIP_REG_DEVICE_STATUS_CONTROL_NFATAL_ERR_REPORT_EN_BB_SHIFT 1
1231 …M_ENA_BB (0x1<<10) // This bit when set enables de…
1233 … (0x1<<11) // Enable No Snoop. When this bit is set to 1, PCIE initiates a read request with the …
1237 …bit is writeable only if flr_supported bit in private device_capability register is set. A write o…
1241 …TAL_ERR_DET_BB (0x1<<17) // Non-Fatal Error Detected.…
1247 … (0x1<<20) // This bit is the current state of the VAUX_PRSNT pin of the devic…
1249 … (0x1<<21) // This is bit is read back a 1, whenever a non-pos…
1252 … (0x7<<0) // MSI-X PBA BAR indicator register (BIR). Indicates which BAR is used to …
1254 … (0x1fffffff<<3) // MSI-X table offset register. Base address of the M…
1256 … 0x0000b8UL //Access:RW DataWidth:0x20 // MSI-X PBA Offset and BIR …
1257 … (0x7<<0) // MSI-X PBA BIR. Note: The access attributes of this field are as follows: …
1259 … (0x1fffffff<<3) // MSI-X PBA Offset. Note: The access attributes of this field are as follows:…
1264 … (0x3f<<4) // Maximum Link Width. These are programmable through reg space.Bit 9 is always 0 and i…
1274 … (0x1<<19) // Surprise Down Error Reporting Capable: RC: this bit must be set if the …
1276 …20) // Data Link Layer Link Active Reporting Capable: RC: this bit must be hardwired to 1b if the …
1278 … (0x1<<21) // Link Bandwidth Notification Capability: RC: A value of 1b indicates support f…
1285 …<0) // ASPM Control. Value used by logic is dependent on the value of this bit for each enabled fu…
1291 …4) // Requesting PHY to disable the link. This bit is only applicable to RC. So for EP it is read …
1293 …5) // Requesting PHY to retrain the link. This bit is only applicable to RC. So for EP it is read …
1295 …. Value used by logic is resolved to 1 only if all functions (when enabled) have this bit set. For…
1297 …bit when set forces the transmission of 4096 FTS ordered sets in the L0s state followed by a singl…
1299 …/ Enable Clock Power Management: RC: N/A and hardwired to 0. EP: When this bit is set, the device …
1301 …bit disables hardware from changing the Link width for reasons other than attempting to correct un…
1303 …pt Enable: when Set, this bit enables the generation of an interrupt to indicate that the Link Ban…
1305 …pt Enable: When Set, this bit enables the generation of an interrupt to indicate that the Link Aut…
1315 …B (0x1<<27) // EP: This bit is N/A and is hardw…
1317 … (0x1<<28) // Slot Clock configuration. This bit is read-only by host, but …
1319 … (0x1<<29) // Data Link Layer Link Active: returns a 1b to indicate the DL_…
1355 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
1357 …0x7fff<<16) // VPD Address. Note: The access attributes of this field are as follows: - Dbi: R/W
1359 … (0x1<<31) // VPD Flag. Note: The access attributes of this field are as follows: - Dbi: R/W
1368 …m Supported, Programmable through register space. This field will read 1, when bit 5 of ext_cap_en…
1374 … (0x3<<18) // OBFF Supported using WAKE# signaling only. Value is programma…
1385 … (0x1<<6) // Atomic requester Enable. When this bit is set, function an…
1389 …ble, This field is writeable, when bit ido_supported bit of private device_capability_2 register i…
1391 …ble, This field is writeable, when bit ido_supported bit of private device_capability_2 register i…
1393 …able, This field is writeable, when bit 5 of ext_cap_ena field in private register space is set. T…
1397 …thod. This field is writeable, when bit 5 of ext_cap_ena field in private register space is set. T…
1404 …ill be Read only by default, and will read all 0's to allow compliance with PCIE spec 1.1. To enab…
1411 … bit selects the level of de-emphasis. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap Value used by l…
1425 … (0x1<<17) // Equalization Complete - when set, this indic…
1427 … (0x1<<18) // Equalization Phase 1 Successful - when set, this indicates that Pha…
1429 … (0x1<<19) // Equalization Phase 2 Successful - when set, this indic…
1431 … (0x1<<20) // Equalization Phase 3 Successful - when set, this indic…
1433 …EQ_REQUEST_BB (0x1<<21) // This bit is set by hardware …
1451 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
1453 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
1455 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
1460 … (0xf<<16) // Capability ID Version. These bits are hardwired to 1h indicating the vers…
1518 …al Error Status. The core sets this bit when your application asserts app_err_bus[9]. It does n…
1597 …sk (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1603 …sk (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1605 … Not supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1637 … (0x1<<5) // Surprise down error severity. Set to 1 for endpoint devices.
1686 …ty (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1692 …ty (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1694 … Not supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1701 … (0x1<<5) // Surprise Down Error Severity. Hardwire to 1'b1.
1751 …ATAL_ERR_STATUS_K2 (0x1<<13) // Advisory Non-Fatal Error Status.
1760 …RR_ERR_STATUS_UNUSED0_BB (0x1f<<1) //
1761 …CIEIP_REG_CORR_ERR_STATUS_UNUSED0_BB_SHIFT 1
1772 … (0x1<<13) // Advisory Non fatal Error Status. Only set if role_based_e…
1802 …ERR_MASK_K2 (0x1<<13) // Advisory Non-Fatal Error Mask. N…
1811 …RR_ERR_MASK_UNUSED0_BB (0x1f<<1) //
1812 …CIEIP_REG_CORR_ERR_MASK_UNUSED0_BB_SHIFT 1
1858 … (0x1f<<0) // First Error Pointer - These bits correspond to the bit posi…
1870 … (0xff<<0) // Byte 0 of Header log register of First 32 bit Data Word. Note: …
1872 … (0xff<<8) // Byte 1 of Header log register of First 32 bit D…
1874 … (0xff<<16) // Byte 2 of Header log register of First 32 bit Data Word. Note: …
1876 … (0xff<<24) // Byte 3 of Header log register of First 32 bit Data Word. Note: …
1880 … 0x000120UL //Access:R DataWidth:0x20 // Header Log Register 1.
1881 … (0xff<<0) // Byte 0 of Header log register of Second 32 bit Data Word. Note: …
1883 … (0xff<<8) // Byte 1 of Header log register of Second 32 bit …
1885 … (0xff<<16) // Byte 2 of Header log register of Second 32 bit Data Word. Note: …
1887 … (0xff<<24) // Byte 3 of Header log register of Second 32 bit Data Word. Note: …
1892 … (0xff<<0) // Byte 0 of Header log register of Third 32 bit Data Word. Note: …
1894 … (0xff<<8) // Byte 1 of Header log register of Third 32 bit D…
1896 … (0xff<<16) // Byte 2 of Header log register of Third 32 bit Data Word. Note: …
1898 … (0xff<<24) // Byte 3 of Header log register of Third 32 bit Data Word. Note: …
1903 … (0xff<<0) // Byte 0 of Header log register of Fourth 32 bit Data Word. Note: …
1905 … (0xff<<8) // Byte 1 of Header log register of Fourth 32 bit …
1907 … (0xff<<16) // Byte 2 of Header log register of Fourth 32 bit Data Word. Note: …
1909 … (0xff<<24) // Byte 3 of Header log register of Fourth 32 bit Data Word. Note: …
1916 … 0x000138UL //Access:R DataWidth:0x20 // TLP Prefix Log Register 1.
1917 … (0xff<<0) // Byte 0 of Error TLP Prefix Log 1. Note: This regist…
1919 …ND_BYTE_K2 (0xff<<8) // Byte 1 of Error TLP Prefix Log 1. Note…
1921 … (0xff<<16) // Byte 2 of Error TLP Prefix Log 1. Note: This regist…
1923 … (0xff<<24) // Byte 3 of Error TLP Prefix Log 1. Note: This regist…
1929 …FX_LOG_2_SECOND_BYTE_K2 (0xff<<8) // Byte 1 Error TLP Prefix Log…
1946 …FX_LOG_3_SECOND_BYTE_K2 (0xff<<8) // Byte 1 Error TLP Prefix Log…
1957 …FX_LOG_4_SECOND_BYTE_K2 (0xff<<8) // Byte 1 Error TLP Prefix Log…
1972 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
1974 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
1976 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
1979 … 0x00014cUL //Access:RW DataWidth:0x20 // Port VC Capability Register 1.
1982 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
1990 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
1997 …ility ID Version. These bits are hardwired to 1h indicating the version of the capability ID. Hard…
1999 …cified an offset in the PCI address space of the next capability. The read-only value of this regi…
2004 …REG_VC_ARBI_SELECT_K2 (0x7<<1) // VC Arbitration S…
2005 …CIEIP_REG_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_K2_SHIFT 1
2021 …// Reject Snoop Transactions. Note: The access attributes of this field are as follows: - Dbi: R
2023 … (0x3f<<16) // Maximum Time Slots-1 supported. Note: The access attributes of this field ar…
2044 …C_MAP_VC0_K2 (0x1<<0) // Bit 0 of TC to VC Mappi…
2046 …_MAP_VC0_BIT1_K2 (0x7f<<1) // Bits 7:1 of TC to VC Ma…
2047 …CIEIP_REG_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_K2_SHIFT 1
2057 …bit when set indicates that the power budget for the device is included within the system power bu…
2077 … 0x000160UL //Access:R DataWidth:0x20 // The read-back value of this re…
2080 …ility ID Version. These bits are hardwired to 1h indicating the version of the capability ID. Hard…
2096 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2098 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2100 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2106 …_ACSFGC_E5 (0x1<<1) // ACS function gro…
2107 …CIEIP_REG_PCIEEP_ARI_CAP_CTL_ACSFGC_E5_SHIFT 1
2112 … (0x1<<17) // ACS function groups enable (A). Writable only for Physical Func N…
2116 … 0x00016cUL //Access:RW DataWidth:0x20 // Serial Number 1 Register.
2124 … 0x000174UL //Access:RW DataWidth:0x20 // The read-back value of this re…
2125 … (0x1<<0) // This bit is hardwired to one because DUT is only…
2127 …1) // This field indicates the TCs that are mapped to the VC resource. This field is valid for all…
2128 …CIEIP_REG_VC_RSRC_CONTROL_TC_VC_MAP_BB_SHIFT 1
2131 … (0x1<<31) // Enables virtual channel. This bit is hardwired to 1 for the de…
2141 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2143 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2145 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2155 …QRIE_E5 (0x1<<1) // Link equalizatio…
2156 …CIEIP_REG_PCIEEP_LINK_CTL3_EQRIE_E5_SHIFT 1
2176 …taWidth:0x20 // The read-only value of this register is controlled by setting bit 0 of the EXT_C…
2192 … (0xf<<16) // Lane 1 downstream port tran…
2194 … (0x7<<20) // Lane 1 downstream port rece…
2196 … (0xf<<24) // Lane 1 upstream port transm…
2198 … (0x7<<28) // Lane 1 upstream port receiv…
2201 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2203 …taWidth:0x20 // The read-only value of this register is controlled by setting bit 0 of the EXT_C…
2204 … (0xffff<<0) // VSEC ID. This field is a vendor-defined ID number tha…
2206 … (0xf<<16) // VSEC Rev. This field is a vendor-defined version numbe…
2208 …uding the PCI Express Enhanced Capability header, the Vendor-Specific header, and the Vendor-Speci…
2228 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2230 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2232 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2234 … 0x000188UL //Access:RW DataWidth:0x20 // If bit 0 of the EXT_CAP_ENA for EP or bit 0 …
2235 … alignment of the BAR0 for each VF. This field may only have 1 bit set.This field is ignored when …
2237 … (0x1<<31) // Enable VF Bar0 Stride. When this bit bit is clear, computa…
2259 …N_GRP_CAP_K2 (0x1<<1) // ACS Function Gro…
2260 …CIEIP_REG_CAP_REG_ARI_ACS_FUN_GRP_CAP_K2_SHIFT 1
2288 … alignment of the BAR2 for each VF. This field may only have 1 bit set.This field is ignored when …
2290 … (0x1<<31) // Enable VF Bar2 Stride. When this bit bit is clear, computa…
2328 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2330 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2332 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2335 … alignment of the BAR4 for each VF. This field may only have 1 bit set.This field is ignored when …
2337 … (0x1<<31) // Enable VF Bar4 Stride. When this bit bit is clear, computa…
2357 …0) // Perform Equalization. Note: The access attributes of this field are as follows: - Dbi: R/W
2359 … (0x1<<1) // Link Equalization Request Interrupt Enable. Note: The access attribute…
2360 …CIEIP_REG_LINK_CONTROL3_REG_EQ_REQ_INT_EN_K2_SHIFT 1
2381 … 0x0001a4UL //Access:R DataWidth:0x20 // Lane Equalization Control Register for lanes 1 and 0.
2382 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2384 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2386 …tributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DB…
2388 …tributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DB…
2390 …t 8.0 GT/s Transmitter Preset 1. Note: The access attributes of this field are as follows: - Db…
2392 …8.0 GT/s Receiver Preset Hint 1. Note: The access attributes of this field are as follows: - Db…
2394 …1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.…
2396 …1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.…
2405 …ster is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_…
2406 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2408 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2410 …tributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DB…
2412 …tributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DB…
2414 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2416 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2418 …tributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DB…
2420 …tributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DB…
2423 …ster is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_…
2424 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2426 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2428 …tributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DB…
2430 …tributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DB…
2432 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2434 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2436 …tributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DB…
2438 …tributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DB…
2441 …ster is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_…
2442 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2444 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2446 …tributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DB…
2448 …tributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DB…
2450 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2452 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2454 …tributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DB…
2456 …tributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DB…
2458 …-only value of this register is controlled by setting bit 5 of the EXT_CAP_ENA for EP, By default,…
2468 …S_EQ_CPL_P1_E5 (0x1<<1) // Equalization 16.…
2469 …CIEIP_REG_PCIEEP_PL16G_STATUS_EQ_CPL_P1_E5_SHIFT 1
2476 …DataWidth:0x20 // The RW value of this register is controlled by setting bit 5 of the EXT_CAP_EN…
2477 …g with Max snoop latency scale field, this register specifies the maximum no-snoop latency that a …
2483 …ith Max No snoop latency scale field, this register specifies the maximum no-snoop latency that a …
2490 … 0x0001b8UL //Access:RW DataWidth:0x20 // SR-IOV Capability Header…
2491 …. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2493 …. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2495 …. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2497 …1b8UL //Access:R DataWidth:0x20 // The read-only value of this register is controlled by sett…
2507 … 0x0001bcUL //Access:RW DataWidth:0x20 // SR-IOV Capability Regist…
2510 …1) // ARI Capable Hierarchy Preserved. For a description of this standard PCIe register field, see…
2511 …CIEIP_REG_CAPABILITIES_REG_SRIOV_ARI_CAP_HIER_PRESERVED_K2_SHIFT 1
2514 …DataWidth:0x20 // The RW value of this register is controlled by setting bit 6 of the EXT_CAP_EN…
2517 …ISTER_ACS_FUNC_GROUP_CAP_BB (0x1<<1) // Hardwired to 0
2518 …CIEIP_REG_ARI_CONTROL_REGISTER_ACS_FUNC_GROUP_CAP_BB_SHIFT 1
2528 … 0x0001c0UL //Access:RW DataWidth:0x20 // SR-IOV Control and Statu…
2531 …_SRIOV_VF_MIGRATION_ENABLE_K2 (0x1<<1) // VF Migration Ena…
2532 …CIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MIGRATION_ENABLE_K2_SHIFT 1
2537 …only). For a description of this standard PCIe register field, see the Single Root I/O Virtualizat…
2539 …1c0UL //Access:R DataWidth:0x20 // The read-only value of this register is controlled by sett…
2547 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
2549 …. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2554 …R_PRESERVED_BB (0x1<<1) // This field is only present i…
2555 …CIEIP_REG_SRIOV_CAPABILITIES_ARI_CAP_HIER_PRESERVED_BB_SHIFT 1
2563 … (0xf<<8) // Downstream port 16.0 GT/s transmitter preset 1.
2565 … (0xf<<12) // Upstream port 16.0 GT/s transmitter preset 1.
2575 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
2576 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: STATUS_CONTROL_…
2583 …RIOV_CONTROL_VF_MIG_EN_BB (0x1<<1) //
2584 …CIEIP_REG_SRIOV_CONTROL_VF_MIG_EN_BB_SHIFT 1
2585 …_BB (0x1<<2) // This bit has no effect in IP…
2589 …evice is permitted to locate VF in Func Number 8 to 255. This field is RW only in PF0 and is RO in…
2613 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register" det…
2615 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register". de…
2640 …. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2670 … (0xffff<<16) // This field is hardwired to 1.
2692 …-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derive…
2693 …1) // VF BAR0 32 or 64 bit. For a description of this standard PCIe register field, see the Single…
2694 …CIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_TYPE_K2_SHIFT 1
2695 …e: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) …
2697 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2717 …-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derive…
2718 …1) // VF BAR1 32 or 64 bit. For a description of this standard PCIe register field, see the Single…
2719 …CIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_TYPE_K2_SHIFT 1
2720 …e: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) …
2722 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2742 …-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derive…
2743 …1) // VF BAR2 32 or 64 bit. For a description of this standard PCIe register field, see the Single…
2744 …CIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_TYPE_K2_SHIFT 1
2745 …e: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) …
2747 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2749 …-bit VF_BAR0 register programs the base address for the memory space mapped by the VFs belonging t…
2750 … (0x1<<0) // This bit indicates that VF_B…
2752 … (0x3<<1) // These bits indicate that VF_BAR0 may be programmed to map this adapter to an…
2753 …CIEIP_REG_VF_BAR0_SPACE_TYPE_BB_SHIFT 1
2754 … (0x1<<3) // This bit indicates that the area mapped by VF_BAR0 may be pre-fetched or cached by t…
2758 …-bit address space that device will respond in. These bits may be combined with the bits in VF_BAR…
2777 …-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derive…
2778 …1) // VF BAR3 32 or 64 bit. For a description of this standard PCIe register field, see the Single…
2779 …CIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_TYPE_K2_SHIFT 1
2780 …e: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) …
2782 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2784 … 0x0001e8UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR1 register pr…
2802 …-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derive…
2803 …1) // VF BAR4 32 or 64 bit. For a description of this standard PCIe register field, see the Single…
2804 …CIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_TYPE_K2_SHIFT 1
2805 …e: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) …
2807 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2809 …-bit VF_BAR2 register programs the base address for the memory space mapped by the VFs belonging t…
2810 … (0x1<<0) // This bit indicates that VF_B…
2812 … (0x3<<1) // These bits indicate that VF_BAR2 may be programmed to map this adap…
2813 …CIEIP_REG_VF_BAR2_SPACE_TYPE_BB_SHIFT 1
2814 … (0x1<<3) // This bit indicates that the area mapped by VF_BAR2 may be pre-fetched or cached by t…
2818 …-bit address space that device will respond in. These bits may be combined with the bits in VF_BAR…
2837 …-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derive…
2838 …1) // VF BAR5 32 or 64 bit. For a description of this standard PCIe register field, see the Single…
2839 …CIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_TYPE_K2_SHIFT 1
2840 …e: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) …
2842 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2844 … 0x0001f0UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR3 register pr…
2867 …-bit VF_BAR4 register programs the base address for the memory space mapped by the VFs belonging t…
2868 … (0x1<<0) // This bit indicates that VF_B…
2870 … (0x3<<1) // These bits indicate that VF_BAR4 may be programmed to map this adap…
2871 …CIEIP_REG_VF_BAR4_SPACE_TYPE_BB_SHIFT 1
2872 … (0x1<<3) // This bit indicates that the area mapped by VF_BAR4 may be pre-fetched or cached by t…
2876 …-bit address space that device will respond in. These bits may be combined with the bits in VF_BAR…
2896 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2898 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2900 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2902 … 0x0001f8UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR5 register pr…
2920 …orm a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
2923 … (0x1<<1) // Interrupt Vector Mode Supported. Note: The access attributes of this field are…
2924 …CIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_K2_SHIFT 1
2925 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2927 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2929 …x1<<9) // ST Table Location Bit 0. Note: The access attributes of this field are as follows: - …
2931 …1<<10) // ST Table Location Bit 1. Note: The access attributes of this field are as follows: - …
2933 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
2953 …(0x7<<0) // ST Mode Select. Note: The access attributes of this field are as follows: - Dbi: R/W
2955 …H_REQ_CTRL_REQ_EN_K2 (0x3<<8) // TPH Requester Enable Bit.
2957 …-only value of this register is controlled by setting bit 0 of the EXT3_CAP_ENA for EP, The capabi…
2982 … 0 Lower Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
2984 … 0 Upper Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
2986 …DataWidth:0x20 // The RW value of this register is controlled by setting bit 0 of the EXT3_CAP_E…
3006 …DataWidth:0x20 // The RW value of this register is controlled by setting bit 0 of the EXT3_CAP_E…
3009 …SELECT_BB (0x1<<1) // If Set, device i…
3010 …CIEIP_REG_PTM_CTRL_REG_ROOT_SELECT_BB_SHIFT 1
3049 …210UL //Access:R DataWidth:0x20 // The read-only value of this register is controlled by sett…
3076 …EQ_BB (0x1<<5) // This bit when set indicates …
3080 … in a Translation Completion or Invalidate Requests. A value of 0 indicates 1 block and a value of…
3127 …220UL //Access:R DataWidth:0x20 // The read-only value of this register is controlled by sett…
3137 …RICHP_E5 (0x1<<1) // ARI capable hier…
3138 …CIEIP_REG_PCIEEP_SRIOV_CAP_ARICHP_E5_SHIFT 1
3139 … (0x1<<2) // VF 10-bit tag requester suppo…
3146 … indicates function will operate with Bar sized to 1M. Value reflected here is from corresponding …
3148 …l operate with Bar sized to 2M. Value reflected here is from corresponding bit in private register.
3150 …l operate with Bar sized to 4M. Value reflected here is from corresponding bit in private register.
3152 …l operate with Bar sized to 8M. Value reflected here is from corresponding bit in private register.
3154 … operate with Bar sized to 16M. Value reflected here is from corresponding bit in private register.
3156 … operate with Bar sized to 32M. Value reflected here is from corresponding bit in private register.
3158 … operate with Bar sized to 64M. Value reflected here is from corresponding bit in private register.
3160 …operate with Bar sized to 128M. Value reflected here is from corresponding bit in private register.
3162 …operate with Bar sized to 256M. Value reflected here is from corresponding bit in private register.
3164 …operate with Bar sized to 512M. Value reflected here is from corresponding bit in private register.
3166 … indicates function will operate with Bar sized to 1G. Value reflected here is from corresponding …
3173 …E_E5 (0x1<<1) // VF migration ena…
3174 …CIEIP_REG_PCIEEP_SRIOV_CTL_ME_E5_SHIFT 1
3179 … (0x1<<4) // ARI capable hierarchy. 0 = All PFs have non-ARI capable hierarchy. 1 = All PF…
3181 … (0x1<<5) // VF 10-bit Tag Requester Enabl…
3197 … (0xffff<<16) // Total VFs. Read-only copy of PCIEEP_SRI…
3204 …-only value of this register is controlled by setting bit 0 of the EXT2_CAP_ENA for EP, By default…
3212 …-ARI capable hierarchies. The PCIEEP_SRIOV_CTL[ACH] determines which one is being used for SR-IOV…
3214 …-ARI: 0x1. There are two VF stride registers; one for each ARI capable and non-ARI capable…
3216 …DataWidth:0x20 // The RW value of this register is controlled by setting bit 0 of the EXT2_CAP_E…
3219 …_INT_VECTOR_MODE_SUPPORTED_BB (0x1<<1) // If Set function …
3220 …CIEIP_REG_TPH_REQ_CAPABILITY_INT_VECTOR_MODE_SUPPORTED_BB_SHIFT 1
3231 …are reads this field to determine the STTable Size N, whihc is encoded as N-1. So a returned value…
3236 …DataWidth:0x20 // The RW value of this register is controlled by setting bit 0 of the EXT2_CAP_E…
3245 …-only value of this register is controlled by setting bit 2 of the EXT2_CAP_ENA for EP, By default…
3253 … (0x1<<0) // Memory space indicator: 0 = BAR 0 is a memory BAR. 1 = BAR 0 is an I/O BA…
3255 … (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-b…
3256 …CIEIP_REG_PCIEEP_SRIOV_BAR0L_TYP_E5_SHIFT 1
3264 …M_L1_1_SUPP_BB (0x1<<1) // Advertize L1_1 c…
3265 …CIEIP_REG_PML1_SUB_CAP_REG_PM_L1_1_SUPP_BB_SHIFT 1
3274 … (0xff<<8) // Time in us that device advertizes that it requires to re-establish common mode.
3288 …BLE_BB (0x1<<1) // When set, PM L1.1 is enable…
3289 …CIEIP_REG_PML1_SUB_CONTROL1_PM_L1_1_ENABLE_BB_SHIFT 1
3292 …LE_BB (0x1<<3) // When set, ASPM L1.1 is enabled.
3294 … (0x1<<4) // Value of 0 is hardwired indicating support for only CLKREQ based PM mec…
3298 …DE_RESTORE_TIME_BB (0xff<<8) // For downstream port only.
3307 … (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-b…
3308 …CIEIP_REG_PCIEEP_SRIOV_BAR2L_TYP_E5_SHIFT 1
3324 … (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-b…
3325 …CIEIP_REG_PCIEEP_SRIOV_BAR4L_TYP_E5_SHIFT 1
3346 …_INTV_E5 (0x1<<1) // Interrupt vector…
3347 …CIEIP_REG_PCIEEP_TPH_REQ_CAP_INTV_E5_SHIFT 1
3352 … (0x1<<9) // Steering tag table bit 0.
3354 … (0x1<<10) // Steering tag table bit 1.
3356 … (0x7ff<<16) // ST table size (limited by MSI-X table size).
3369 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
3371 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
3373 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
3375 … 0x000288UL //Access:RW DataWidth:0x20 // LTR Max Snoop and No-Snoop Latency Registe…
3380 …T_K2 (0x3ff<<16) // Max No-Snoop Latency Value.
3382 …LAT_SCALE_K2 (0x7<<26) // Max No-Snoop Latency Scale.
3384 … 0x00028cUL //Access:RW DataWidth:0x20 // Vendor-Specific Extended Cap…
3385 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
3387 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
3389 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
3391 … 0x000290UL //Access:R DataWidth:0x20 // Vendor-Specific Header.
3398 …- Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register det…
3399 …ear' code. The read value is always '0'. - 00: no change - 01: per clear - 10: no change - 11:…
3401 …ays '0'. - 000: no change - 001: per event off - 010: no change - 011: per event on - 100: no…
3403 …alue of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT…
3405 …a returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - ..…
3407 …- 27-24: Group number(4-bit: 0..0x7) - 23-16: Event number(8-bit: 0..0x13) within the Group For e…
3409 …s the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTRO…
3410 …idth:0x20 // Time-based Analysis Control. Used for controlling the measurement of RX/TX data thr…
3411 … (0x1<<0) // Timer Start. - 0: Start/Restart - 1: Stop This bit wi…
3413 …-based Duration Select. Selects the duration of time-based analysis. When "manual control" is sele…
3415 …-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_…
3417 …ataWidth:0x20 // Time-based Analysis Data. Contains the measurement results of RX/TX data throug…
3418 …bit in this register. The specific injection controls for each type of error are defined in the fo…
3421 …ROR_INJECTION1_ENABLE_K2 (0x1<<1) // Error Injection1…
3422 …CIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_K2_SHIFT 1
3431 …set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_R…
3433 …- LCRC. Bad TLP will be detected at the receiver side; receiver responds with NAK DLLP; Data Link …
3434 …- If the counter value is 0x01 and error is inserted, ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG r…
3436 …- 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b:…
3438 …1 (Sequence Number Error). Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. D…
3439 …- If the counter value is 0x01 and error is inserted, ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG r…
3441 …ce number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1…
3443 …-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. …
3445 …- If "ACK/NAK DLLP's transmission block" is selected, replay timeout error will occur at the trans…
3446 …- If the counter value is 0x01 and the error is inserted, ERROR_INJECTION2_ENABLE in EINJ_ENABLE_R…
3448 … inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block …
3450 …- If TS1/TS2/FTS/E-Idle/SKP is selected, it affects whole of the ordered set. It might cause timeo…
3451 …- If the counter value is 0x01 and error is inserted, ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG r…
3453 …- Mask K symbol. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b: COM/PAD(TS2 Order set)…
3455 … - Posted TLP Header credit - Non-Posted TLP Header credit - Completion TLP Header credit - Po…
3456 …- If the counter value is 0x01 and error is inserted, ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG r…
3458 …-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Po…
3462 …-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is repr…
3464 …- For Duplicate TLP, the core initiates Data Link Retry by handling ACK DLLP as NAK DLLP. These TL…
3465 …- If the counter value is 0x01 and error is inserted, ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG r…
3467 …elects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NA…
3469 …on Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP heade…
3470 … DataWidth:0x20 // Error Injection Control 6 (Compare Point Header DWORD #1). Program this regis…
3473 …on Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP heade…
3481 … DataWidth:0x20 // Error Injection Control 6 (Compare Value Header DWORD #1). Program this regis…
3485 …_TB_E5 (0x1<<1) // ACS translation …
3486 …CIEIP_REG_PCIEEP_ACS_CAP_CTL_TB_E5_SHIFT 1
3499 … (0x1<<16) // ACS source validation enable. Writable only when [SV] 1.
3501 … (0x1<<17) // ACS translation blocking enable. Writable only when [TB] 1.
3503 … (0x1<<18) // ACS P2P request redirect enable. Writable only when [CR] is 1.
3505 … (0x1<<19) // ACS P2P completion redirect enable. Writable only when [CR] is 1.
3507 … (0x1<<20) // ACS upstream forwarding enable. Writable only when [UF] is 1.
3509 … (0x1<<21) // ACS P2P egress control enable. Writable only when [EC] is 1.
3511 … (0x1<<22) // ACS direct translated P2P enable. Writable only when [DT] is 1.
3527 …1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you prog…
3533 … (0x3ff<<16) // Max no-snoop latency value.
3535 … (0x7<<26) // Max no-snoop latency scale.
3537 …1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully con…
3545 …he type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_…
3546 …-only value of this register is controlled by setting bit 1 of the EXT2_CAP_ENA for EP, The capabi…
3554 …PCIPM_SUP_E5 (0x1<<0) // PCI-PM L12 supported.
3556 …PCIPM_SUP_E5 (0x1<<1) // PCI-PM L11 supported.
3557 …CIEIP_REG_PCIEEP_L1SUB_CAP_L1_1_PCIPM_SUP_E5_SHIFT 1
3570 …he type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_…
3571 …ataWidth:0x20 // The RW value of this register is controlled by setting bit 1 of the EXT2_CAP_EN…
3574 …K_EQ_REQ_INT_EN_BB (0x1<<1) // N/A to endpoints
3575 …CIEIP_REG_LINK_CONTROL3_LINK_EQ_REQ_INT_EN_BB_SHIFT 1
3577 …1_2_PCIPM_EN_E5 (0x1<<0) // PCI-PM L12 enable.
3579 …1_1_PCIPM_EN_E5 (0x1<<1) // PCI-PM L11 enable.
3580 …CIEIP_REG_PCIEEP_L1SUB_CTL1_L1_1_PCIPM_EN_E5_SHIFT 1
3587 …indicates the LTR threshold use to determine if entry into L1 results in L1.1 (if enabled) or L1.2…
3589 … threshold scale. 0x0 = 1 ns. 0x1 = 32 ns. 0x2 = 1024 ns. 0x3 = 32,768 ns. 0x4 = 1,048,575 n…
3591 …1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you prog…
3593 …_BITS_BB (0xffff<<0) // Each bit indicates if corres…
3600 …1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully con…
3602 …P_PRESETS0_BB (0xff<<0) // Applicable only to Upstream compone…
3610 …_PRESETS1_BB (0xff<<16) // Applicable only to Upstream compone…
3625 …he type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_…
3627 …P_PRESETS2_BB (0xff<<0) // Applicable only to Upstream compone…
3635 …_PRESETS3_BB (0xff<<16) // Applicable only to Upstream compone…
3644 …EG_EPS_E5 (0x1<<1) // Execute permissi…
3645 …CIEIP_REG_PCIEEP_PASID_CTL_REG_EPS_E5_SHIFT 1
3648 …fault value for the width of the PASID field supported by the endpoint. Single PASID support only.
3656 …he type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_…
3658 …P_PRESETS4_BB (0xff<<0) // Applicable only to Upstream compone…
3666 …_PRESETS5_BB (0xff<<16) // Applicable only to Upstream compone…
3681 …Only applies when EINJ6_INVERTED_CONTROL in this register =0. The TLP into that errors are injecte…
3682 …- If the counter value is 0x01 and error is inserted, ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG r…
3684 …- 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2…
3686 …e TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Pref…
3689 …P_PRESETS6_BB (0xff<<0) // Applicable only to Upstream compone…
3697 …_PRESETS7_BB (0xff<<16) // Applicable only to Upstream compone…
3713 …P_PRESETS8_BB (0xff<<0) // Applicable only to Upstream compone…
3721 …_PRESETS9_BB (0xff<<16) // Applicable only to Upstream compone…
3736 …ter data returned in the PCIEEP_RAS_EC_DATA[EV_CNTR_DATA]. 0x0-0x7 = Lane number. 0x8-0xF = Res…
3741 …OMP_PRESETS10_BB (0xff<<0) // Applicable only to Upstream compone…
3749 …MP_PRESETS11_BB (0xff<<16) // Applicable only to Upstream compone…
3759 …OMP_PRESETS12_BB (0xff<<0) // Applicable only to Upstream compone…
3767 …MP_PRESETS13_BB (0xff<<16) // Applicable only to Upstream compone…
3776 … (0x1<<0) // Timer start. 0x0 = Start/restart. 0x1 = Stop. This bit will be cleared aut…
3778 …-based duration select. Selects the duration of time-based analysis. 0x0 = Manual control. Ana…
3780 …-based report select. Selects what type of data is measured for the selected duration [TBASE_DUR_S…
3783 …OMP_PRESETS14_BB (0xff<<0) // Applicable only to Upstream compone…
3791 …MP_PRESETS15_BB (0xff<<16) // Applicable only to Upstream compone…
3800 … 0x00032cUL //Access:RW DataWidth:0x20 // Silicon Debug Control 1. For more details, s…
3801 …uring LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. -…
3803 … (0x1<<16) // Force Detect Lane Enable. When this bit is set, the core ig…
3805 …-reset exit. The core selects the greater value between this register and the value defined by the…
3807 …m receiving EIOS to, RXELECIDLE assertion at the PHY. - 0x0: 40ns - 0x1: 160ns - 0x2: 320ns - …
3810 … (0x1<<0) // Hold and Release LTSSM. For as long as this register is '1', the core stays in …
3812 …1) // Recovery Request. When this bit is set to '1' in L0 or L0s, the LTSSM starts transitioning …
3813 …CIEIP_REG_SD_CONTROL2_REG_RECOVERY_REQUEST_K2_SHIFT 1
3814 … (0x1<<2) // Force LinkDown. When this bit is set and the core…
3816 … (0x1<<8) // Direct Recovery.Idle to Configuration. When this bit is set and the LTSS…
3818 … (0x1<<9) // Direct Polling.Compliance to Detect. When this bit is set and the LTSS…
3820 … (0x1<<10) // Detect Loopback Slave To Exit. When this bit is set and the LTSS…
3822 … (0x1<<16) // Framing Error Recovery Disable. This bit forces a transition…
3824 … // Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the…
3825 …er for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 …
3840 …only valid value when FRAMING_ERR =1. Received Unexpected Framing Token - 01h: When non- STP/SDP…
3846 …Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTS…
3848 …-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negoti…
3851 …- 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDL…
3853 …- 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 08h: L1 - 09h: L1_BLOCK_…
3855 …-send flag. When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit. If host softwar…
3862 …_EINJ1_EN_E5 (0x1<<1) // Sequence number …
3863 …CIEIP_REG_PCIEEP_RAS_EINJ_EN_EINJ1_EN_E5_SHIFT 1
3879 … (0x3<<24) // DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 1…
3888 …-FC DLLP. 0x3 = New TLP's ECRC error injection. 0x4 = TLP's FCRC error injection (128b/130b). 0…
3890 …1] fields in this viewport register return the data for the VC and TLP Type selected by the follow…
3891 …ort-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data …
3893 …IT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CRE…
3895 …iewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 d…
3897 …TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_D…
3899 …TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value …
3901 …YPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value …
3908 …-assigned sequence numbers. This value is represented by two's complement. 0x0FFF = +4095. 0x0…
3911 …- 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: T…
3923 …ng - Mask K symbol. 0x0 = Reserved. 0x1 = COM/PAD(TS1 Order Set). 0x2 = COM/PAD(TS2 Order Set)…
3928 …-FC type. Selects the credit type. 0x0 = Posted TLP header credit value control. 0x1 = Non-Pos…
3932 …-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. The value is rep…
3934 …1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this reg…
3935 …-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] view…
3937 …the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/…
3939 …al Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11:…
3943 …ria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_…
3951 … (0x3f<<0) // Force Local Transmitter Pre-cursor. Indicates th…
3955 … (0x3f<<12) // Force Local Transmitter Post-Cursor. Indicates th…
3961 …fficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CUR…
3969 … (0x3f<<0) // Force Remote Transmitter Pre-Cursor. Indicates th…
3973 … (0x3f<<12) // Force Remote Transmitter Post-Cursor. Indicates th…
3975 …ficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CU…
3979 …1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the…
3982 …1) // EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization i…
3983 …CIEIP_REG_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_K2_SHIFT 1
3984 …ge method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cl…
3986 …ge method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cl…
3988 …ge method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cl…
3990 …receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phas…
3993 …ld is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1). For more details, …
3994 …_K2 (0x3f<<0) // EQ Local Pre-Cursor. Indicates Lo…
3998 …K2 (0x3f<<12) // EQ Local Post-Cursor. Indicates Lo…
4005 …ld is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1). For more details, …
4006 …_K2 (0x3f<<0) // EQ Remote Pre-Cursor. Indicates Re…
4010 …K2 (0x3f<<12) // EQ Remote Post-Cursor. Indicates Re…
4023 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
4025 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
4027 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
4039 …or all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. …
4041 …TRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_K2 (0x1<<1) // Error correction…
4042 …CIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_K2_SHIFT 1
4055 …pletion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. …
4068 … 0x000398UL //Access:RW DataWidth:0x20 // Corrected error (1-bit ECC) counter selec…
4071 …) // Enable correctable errors counters. - 1: counters increment when the core detects a correcta…
4073 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4078 … 0x00039cUL //Access:R DataWidth:0x20 // Corrected error (1-bit ECC) counter data.…
4081 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4086 … 0x0003a0UL //Access:RW DataWidth:0x20 // Uncorrected error (2-bit ECC and parity) cou…
4089 … Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correct…
4091 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4098 …1/2/3] is used to replace bits specified by EINJ6_CHG_PT_H[0/1/2/3]. 0x1 = EINJ6_CHG_VAL_H[0/1/2/…
4100 …rrors into. 0x0 = TLP header. 0x1 = TLP prefix 1st 4-DWORDs. 0x2 = TLP prefix 2nd 4-DWORDs. 0…
4102 … 0x0003a4UL //Access:R DataWidth:0x20 // Uncorrected error (2-bit ECC and parity) cou…
4105 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4109 …he following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection mod…
4112 … (0x3<<4) // Error injection type: - 0: none - 1: 1-bit - 2: 2-bit
4114 … (0xff<<8) // Error injection count. - 0: errors are inserted in every TLP until you clear ERRO…
4119 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4123 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4128 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4132 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4136 …ers RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During…
4137 …ODE_EN_K2 (0x1<<0) // Write '1' to enable the core …
4139 …UTO_LINK_DOWN_EN_K2 (0x1<<1) // Write '1' to enable the…
4140 …CIEIP_REG_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_K2_SHIFT 1
4144 … (0x1<<16) // Force detect lane enable. When this bit is set, the core ig…
4146 …-reset exit. The core selects the greater value between this register and the value defined by the…
4148 …ing EIOS to, RXELECIDLE assertion at the PHY 0x0 = 40ns. 0x1 = 160ns. 0x2 = 320ns. 0x3 - 640ns.
4151 …R_MODE_CLEAR_K2 (0x1<<0) // Write '1' to take the core ou…
4156 …1) // Recovery request. When this bit is set in L0 or L0s, the LTSSM starts transitioning to reco…
4157 …CIEIP_REG_PCIEEP_RAS_SD_CTL2_RCRY_REQ_E5_SHIFT 1
4158 … (0x1<<2) // Force link down. When this bit is set and the core…
4160 … (0x1<<8) // Direct Recovery.Idle to configuration. When this bit is set and the LTSS…
4162 … (0x1<<9) // Direct Polling.Compliance to detect. When this bit is set and the LTSS…
4166 … (0x1<<16) // Framing error recovery disable. This bit disables a transiti…
4168 …UL //Access:R DataWidth:0x20 // RAM Address where a corrected error (1-bit ECC) has been dete…
4169 … (0x7ffffff<<0) // RAM Address where a corrected error (1-bit ECC) has been dete…
4171 … (0xf<<28) // RAM index where a corrected error (1-bit ECC) has been dete…
4173 …/Access:R DataWidth:0x20 // RAM Address where an uncorrected error (2-bit ECC) has been detec…
4174 … (0x7ffffff<<0) // RAM Address where an uncorrected error (2-bit ECC) has been detec…
4176 … (0xf<<28) // RAM index where an uncorrected error (2-bit ECC) has been detec…
4179 …. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
4181 …. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
4183 …. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
4186 … silicon debug status register of Layer1-PerLane. 0x0 = Lane0. 0x1 = Lane1. 0x2 = Lane2. 0x7 …
4201 …. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
4203 …1) // PTM Responder Capable. For a description of this standard PCIe register, see the PCI Express…
4204 …CIEIP_REG_PTM_CAP_OFF_PTM_RES_CAPABLE_K2_SHIFT 1
4205 …. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
4207 …. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
4210 …only valid value when [FRAMING_ERR] = 1. Received unexpected framing token: 0x1 = When non-STP/S…
4218 …ualization_done_8GT_data_rate. 0x7 = equalization_done_16GT_data_rate. 0x8-0xF = idle_to_rlock_t…
4223 …1) // PTM Root Select. When set this Time Source is the PTM Root. For a description of this standa…
4224 …CIEIP_REG_PTM_CONTROL_OFF_ROOT_SELECT_K2_SHIFT 1
4225 …s Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: HWINIT
4228 … 0x17 = L0S_BLOCK_TLP. 0x18 = WAIT_LAST_PMDLLP. 0x19 = WAIT_DSTATE_UPDATE. 0x20-0x1F = Reserved.
4230 …S_L23RDY_WAIT4ALIVE. 0x0F = S_L23RDY_WAIT4IDLE. 0x10 = S_WAIT_LAST_PMDLLP. 0x10-0x1F = Reserved.
4232 … sets PME_Status bit. If host software does not clear PME_Status bit for 100ms (+50%/-5%), the DUT…
4239 …. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
4241 …. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
4243 …. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
4257 …. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
4259 …. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
4261 …. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
4264 …CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields determi…
4266 …ith the [CREDIT_SEL_VC], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields determi…
4268 …] viewport-select fields determines that data that is returned by the [CREDIT_DATA0] and [CREDIT_D…
4270 …CREDIT_SEL_VC], [CREDIT_SEL_CREDIT_TYPE], and [CREDIT_SEL_TLP_TYPE] viewport-select fields determi…
4272 …CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields. RX = …
4274 …t data 1. Current FC credit data selected by the [CREDIT_SEL_VC], [CREDIT_SEL_CREDIT_TYPE], [CRED…
4277 … (0x1<<0) // PTM Requester Auto Update Enabled - When enabled PTM Req…
4279 … (0x1<<1) // PTM Requester Start Update - When set the PTM Requester will attempt a PTM Di…
4280 …CIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_START_UPDATE_K2_SHIFT 1
4281 …- Debug mode for PTM Timers. The 100us timer output will go high at 30us and the 10ms timer output…
4283 …uester Long Timer - Determines the period between each auto update PTM Dialogue in miliseconds. Up…
4286 …bit in message TLP. 0x09 = Unexpected CRS status in completion TLP. 0x0A = Byte enable. 0x0B = …
4291 … (0x1<<0) // PTM Requester Context Valid - Indicate that the Ti…
4293 …E_ALLOWED_K2 (0x1<<1) // PTM Requester Manual Update Allowed -…
4294 …CIEIP_REG_PTM_REQ_STATUS_OFF_PTM_REQ_MANUAL_UPDATE_ALLOWED_K2_SHIFT 1
4298 …-lane silicon debug EQ status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] view…
4300 …[EQ_LANE_SEL] determines the per-lane silicon debug EQ status data returned by the SD_EQ_CONTROL[2…
4304 …time. Indicates interval time of RxEqEval assertion. 0x0 = 500 ns. 0x1 = 1 us. 0x2 = 2 us. 0x…
4308 …ia value of EQ master (DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when PCIEEP_G…
4330 … (0x3f<<0) // Force remote transmitter pre-cursor as selected by…
4343 …1) // EQ convergence info. Indicates equalization convergence information. 0x0 = Equalization is…
4344 …CIEIP_REG_PCIEEP_RAS_SD_EQ_STAT1_EQ_CONV_INFO_E5_SHIFT 1
4345 …for Transmitter Coefficients" in the PCI Express Base Specification. This bit is automatically cl…
4347 …for Transmitter Coefficients" in the PCI Express Base Specification. This bit is automatically cl…
4349 …for Transmitter Coefficients" in the PCI Express Base Specification. This bit is automatically cl…
4351 …receives two consecutive TS1 OS w/Reject=1b during EQ master phase (DSP in EQ Phase3/USP in EQ Pha…
4381 …e bar_1 register of the PCI configuration space. This value is sticky and only reset by HARD Reset…
4383 …bit enables the advertisement of bar_1 as a 32-bit address. The value of this bit maps directly to…
4385 …bit will force the PCI bus to re-try all cycles to the current Expansion ROM BAR area. When this b…
4387 …bit will force the PCI bus to re-try all cycles to the configuration space until it is cleared. Th…
4389 … (0x1<<7) // This bit will be set the fir…
4391 …en this value is non-zero, the Expansion ROM attention must be handled by an internal processor to…
4393 … (0x1<<16) // This bit when set is reflected in bit 3 of bar_1 and indicates tha…
4399 …only reset by HARD Reset such that it can be used to detect initial power up if a non-zero value i…
4401 … (0xff<<8) // This value is reset only by REG_HARD_RST.
4403 …only Setting this bit to '1' forces the VF to drop any mem request that it receives. UR completion…
4407 …bit to '1' forces the PME message to be send This simulates the PME event. The PME control bits in…
4409 … (0x1<<25) // This bit indicates the current state of the PME_STATUS bit in configuration spac…
4411 … // This is the current state of the PME_ENABLE bit in configuration space. This value is sticky a…
4417 … (0x1<<30) // This bit indicates the input…
4419 …OWER This bit indicates the current state of power on the PCI bus. If this bit is '1', it indicate…
4423 …er is 0. This is the power consumed in D0 state. This value is sticky and only reset by HARD Reset.
4425 …ATA_SEL value in the PM_CSR register is 1. This is the power consumed in D1 state. This value is s…
4427 …er is 2. This is the power consumed in D2 state. This value is sticky and only reset by HARD Reset.
4429 …er is 3. This is the power consumed in D3 state. This value is sticky and only reset by HARD Reset.
4433 … is 4. This is the power dissipated in D0 state. This value is sticky and only reset by HARD Reset.
4435 … is 5. This is the power dissipated in D1 state. This value is sticky and only reset by HARD Reset.
4437 … is 6. This is the power dissipated in D2 state. This value is sticky and only reset by HARD Reset.
4439 … is 7. This is the power dissipated in D3 state. This value is sticky and only reset by HARD Reset.
4449 …s register controls the higher bar size advertizements, when a bar size greater than 1G is desired.
4450 …cky and only reset by HARD Reset. These bits are programmed when a BAR size greater than 1GB is de…
4452 …cky and only reset by HARD Reset. These bits are programmed when a BAR size greater than 1GB is de…
4454 …cky and only reset by HARD Reset. These bits are programmed when a BAR size greater than 1GB is de…
4456 …e bar_1 register of the PCI configuration space. This value is sticky and only reset by HARD Reset…
4460 …e bar_3 register of the PCI configuration space. This value is sticky and only reset by HARD Reset…
4462 …e bar_5 register of the PCI configuration space. This value is sticky and only reset by HARD Reset…
4472 … (0xfff<<0) // PTM Requester TX Latency - Requester Transmit path latency (12 bit …
4477 …L_EP_DIS_AXIB_MASC_E5 (0x1<<1) // Error correction…
4478 …CIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_AXIB_MASC_E5_SHIFT 1
4504 … (0xfff<<0) // PTM Requester RX Latency - Requester Receive path latency (12 bit w…
4511 …). 0xB = AXI bridge outbound master completion buffer path (not supported). 0xC - 0xF = Reserved.
4516 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
4518 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
4520 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
4525 …ot supported). 0xB = AXI bridge outbound master completion (not supported). 0xC - 0xF = Reserved.
4530 … (0x1<<4) // Up to 1MB BAR Supported. Note: The access attributes of this field…
4532 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4534 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4536 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4538 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4540 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4542 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4544 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4546 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4548 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4550 … (0x1<<14) // Up to 1GB BAR Supported. Note: The access attributes of this field…
4552 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4554 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4556 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4558 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4560 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4562 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4564 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4566 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4568 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4571 …bit will be set if there is a pending request for action by the firmware to handle a Vital Product…
4578 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4587 …) // BAR Size. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4594 …bit indicates if the host is requesting a read or a write cycle. If this bit is set, then the host…
4599 …). 0xB = AXI bridge outbound master completion buffer path (not supported). 0xC - 0xF = Reserved.
4603 …1' and the WR bit is clear, this word should be written with the NVM data requested in the ADDRESS…
4607 … (0x3<<4) // Error injection type. 0x0 = None. 0x1 = 1-bit. 0x2 = 2-bit. 0x3 = Res…
4609 … 0x0 = errors are injected in every TLP until [ERR_INJ_EN] is cleared. 0x1 - 0xFF = number of err…
4614 …ardware default value is the Broadcom vendor ID. This value is sticky and only reset by HARD Reset…
4616 …ardware default value is the Broadcom vendor ID. This value is sticky and only reset by HARD Reset.
4619 …ot supported). 0xB = AXI bridge outbound master completion (not supported). 0xC - 0xF = Reserved.
4623 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4628 …stem_vendor_id value in the configuration space. This value is sticky and only reset by HARD Reset.
4630 …e subsystem_id value in the configuration space. This value is sticky and only reset by HARD Reset…
4633 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4637 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4642 …-bit Class Code register identifies the generic function of the device. All of the legal values ar…
4647 … (0x1<<0) // Set this bit to enable the core …
4649 …_DN_EN_E5 (0x1<<1) // Set this bit to enable th…
4650 …CIEIP_REG_PCIEEP_RASDP_DE_ME_AUTO_LNK_DN_EN_E5_SHIFT 1
4652 …Bit 0 enables the Power Management capability. Bit 1 enables the VPD capability, and Bit 2 enables…
4656 …register in the PCI Configuration address space. This value is sticky and only reset by HARD Reset.
4660 …lways be equal or less than what was advertised. This value is sticky and only reset by HARD Reset.
4662 …ation space. The default is 0, which is one MSI. This value is sticky and only reset by HARD Reset.
4664 … (0x1<<15) // This bit indicates the programming of the MSI Enable bit in PCI configur…
4669 … (0x1<<0) // Set this bit to take the core ou…
4672 …bit indicates whether the device supports the D1 power management state. It is reflected in the D1…
4674 …1) // This bit indicates whether the device supports the D2 power management state. It is reflecte…
4675 …CIEIP_REG_REG_ID_VAL5_D2_SUPPORT_BB_SHIFT 1
4676 …bit indicates whether the device supports transmiting PME message from the D0 power state. It is r…
4678 …bit indicates whether the device supports transmiting PME message from the D1 power state. It is r…
4680 …bit indicates whether the device supports transmiting PME message from the D2 power state. It is r…
4682 …bit indicates whether the device supports transmiting PME message from the D3hot power state. It i…
4703 …of the bist register in the configuration space. This value is sticky and only reset by HARD Reset.
4718 … (0x3fffff<<1) // Local future dat…
4719 …CIEIP_REG_PCIEEP_DLINK_CAP_FFS_E5_SHIFT 1
4724 … (0x7fffff<<0) // Only bit 0 is currently defined - remo…
4730 … reflects the lower half of the MSI address bit[31:2] value in the configuration space. The lower …
4741 … (0x1<<1) // PTM responder capable. Writable only if [RTC] is 0, o…
4742 …CIEIP_REG_PCIEEP_PTM_CAP_RSC_E5_SHIFT 1
4750 …SEL_E5 (0x1<<1) // PTM root select.…
4751 …CIEIP_REG_PCIEEP_PTM_CTL_RT_SEL_E5_SHIFT 1
4762 … 0x000468UL //Access:RW DataWidth:0x20 // Each pending bit that is set , the f…
4771 … common logic in case of multi function devices. This value is sticky and only reset by HARD Reset.
4778 … (0x1<<1) // PTM requester start update. When set the PTM Requester will attempt a PTM Di…
4779 …CIEIP_REG_PCIEEP_PTM_REQ_CTL_RSD_E5_SHIFT 1
4780 …high at 100us (The Long Timer Value is ignored). There is no change to the 1us timer. The request…
4782 …o update PTM Dialogue in miliseconds. Update period is the register value +1 milisecond. For the …
4787 …T_RMUA_E5 (0x1<<1) // PTM requester ma…
4788 …CIEIP_REG_PCIEEP_PTM_REQ_STAT_RMUA_E5_SHIFT 1
4818 …orted resource sizes. PEM advertises the maximum allowable BAR size (512 GB - 0xF_FFFF) when the f…
4830 …0x3f<<8) // BAR Size. PEM advertises the minimum allowable BAR size of 0x0 (1MB) but will accept v…
4835 …ters located at 10h in configuration space is used to map the function's MSI-X table into memory s…
4837 … one of the functions Base address registers to point to the base of the MSI-X table. Value is con…
4847 …ters located at 10h in configuration space is used to map the function's MSI-X PBA into memory spa…
4849 … one of the functions Base address registers to point to the base of the MSI-X PBA Value is contro…
4859 …-zero values indicate some software-defined post-firmware loaded state information or failure code…
4864 …E_1_1_BB (0x1<<5) // This bit when set, hides any…
4866 … (0x1<<6) // This bit when set, sets the ASPM optionality bit in the Link cap r…
4890 …1 indicating that the Function is in FLR state. Func can be brought out of FLR state either by wri…
4894 …1, indicating that all the VFs that belong to this PF should be flushed. Software should clear thi…
4916 …e bar_3 register of the PCI configuration space. This value is sticky and only reset by HARD Reset…
4918 …bit enables the advertisement of bar_3 as a 32-bit address. The value of this bit maps directly to…
4920 … (0x1<<5) // This bit when set is reflected in bit 3 of bar_3 and indicates tha…
4925 … Timeout Ranges Supported. Controls value in same field in the config space 0xF- Ranges A,B,C and D
4931 … (0x1<<10) // This bit is valid only if IDO_Enabled is defined in version.v.…
4935 …only. It is recommended to set this value to 2 or 3(also supported using Messages) This bit is val…
4944 … (0x1<<0) // RC only. If set, indicates dl_active capability at…
4946 …BILITY_RC_SLOT_CLK_CONFIG_BB (0x1<<1) // If set, indicate…
4947 …CIEIP_REG_REG_PCIE_LINK_CAPABILITY_RC_SLOT_CLK_CONFIG_BB_SHIFT 1
4949 …he PCI configuration space. This value is sticky and only reset by HARD Reset. This register is on…
4951 …bit enables the advertisement of bar_5 as a 32-bit address. The value of this bit maps directly to…
4953 … (0x1<<5) // This bit when set is reflected in bit 3 of bar_5 and indicates that the BAR is pre…
4958 … (0x1<<0) // This register is reserved for RC only. It is not applicab…
4960 … (0x1<<1) // This register is reserved for RC only…
4961 …CIEIP_REG_REG_ROOT_CAP_RC_LTR_SUPPORTED_BB_SHIFT 1
4962 … (0x1<<2) // This register is reserved for RC only. It is not applicab…
4964 …ity will be present only if PMCR_RC_L1_SUBSTATES_ENA is defined in version.v Secondary PCIE extend…
4967 … (0x1<<0) // This register is reserved for RC only. It is not applicab…
4974 …r, dev serial, pwr budget, virtual channel LTR capability will be present only if LTR_ENABLED is d…
4976 …ent only if SRIOV is defined in version.v SRIOV capability should not be enabled without enabling …
4983 … (0x1<<0) // This value controls the corresponding bit in the ADV_ERR_CAP …
4985 … (0x1<<1) // This value controls the corresponding b…
4986 …CIEIP_REG_REG_ADV_ERR_CAP_ECRC_GEN_CAP_BB_SHIFT 1
4988 …e pwr_bdgt_data_sel register (0x154) value is 0. This value is sticky and only reset by HARD Reset.
4993 …0x158) when the pwr_bdgt_data_sel register (0x154) value is 1. This value is sticky and only reset…
4998 …e pwr_bdgt_data_sel register (0x154) value is 2. This value is sticky and only reset by HARD Reset.
5003 …e pwr_bdgt_data_sel register (0x154) value is 3. This value is sticky and only reset by HARD Reset.
5008 …e pwr_bdgt_data_sel register (0x154) value is 4. This value is sticky and only reset by HARD Reset.
5013 …e pwr_bdgt_data_sel register (0x154) value is 5. This value is sticky and only reset by HARD Reset.
5018 …e pwr_bdgt_data_sel register (0x154) value is 6. This value is sticky and only reset by HARD Reset.
5023 …e pwr_bdgt_data_sel register (0x154) value is 7. This value is sticky and only reset by HARD Reset.
5028 …only if TPH_ON is defined in version.v SRIOV capability should not be enabled without enabling ARI…
5035 …e pwr_bdgt_data_sel register (0x154) value is 7. This value is sticky and only reset by HARD Reset.
5042 …1_1_SUPP_BB (0x1<<1) // Advertize L1_1 c…
5043 …CIEIP_REG_REG_L1SUB_CAP_PM_L1_1_SUPP_BB_SHIFT 1
5052 … (0xff<<8) // Time in us that device advertizes that it requires to re-establish common mode.
5068 … (0x1<<0) // This bit controls the system alloc bit in t…
5070 …BDGT_CAPABILITY_RESERVED_BB (0x7fffffff<<1) //
5071 …CIEIP_REG_REG_PWR_BDGT_CAPABILITY_RESERVED_BB_SHIFT 1
5080 …size of the user BAR1 area. This value is sticky and only reset by HARD Reset. This register is on…
5084 … (0x1<<7) // Enable User Defined Mem area in RC mode. If this bit is set, then memory…
5092 …size of the user BAR1 area. This value is sticky and only reset by HARD Reset. This register is on…
5096 … (0x1<<7) // Enable User Defined Mem area in RC mode. If this bit is set, then memory…
5103 … 0x0005ecUL //Access:RW DataWidth:0x20 // This register is visible only if PCIE_EP_MC_SUPP …
5106 … 0x0005f0UL //Access:RW DataWidth:0x20 // This register is visible only if PCIE_PTM_SUPP is…
5109 …P_SUPP_BB (0x1<<1) // This field will …
5110 …CIEIP_REG_REG_PTM_CAP_PTM_CAP_SUPP_BB_SHIFT 1
5114 …V_SPEC_MODE_BB (0x1<<1) // When Set, it ind…
5115 …CIEIP_REG_REG_TPH_CAP_TPH_DEV_SPEC_MODE_BB_SHIFT 1
5116 …e IP supports only a value of 0, which would indicate ST Table is not present, or a value of 2, wh…
5118 …CIE defined TPH capability register. The value programmed here indicates a table size of value + 1.
5123 … (0x1<<4) // when Set, it indicates function will operate with Bar sized to 1M. Value programmed h…
5143 …(0x1<<14) // when Set, it indicates function will operate with Bar sized to 1G. Value programmed h…
5161 …vertized in the VF BAR0 register in the PCIE config space. This register is only applicable for EP.
5163 …bit enables the advertisement of VF BAR0 as a 64-bit address. The value of this bit maps directly …
5165 … (0x1<<5) // This bit when set is reflected in bit 3 of VF BAR0 and indicates that the BAR is pr…
5169 …vertized in the VF BAR2 register in the PCIE config space. This register is only applicable for EP.
5171 …bit enables the advertisement of VF BAR2 as a 64-bit address. The value of this bit maps directly …
5173 … (0x1<<13) // This bit when set is reflected in bit 3 of VF BAR2 and indicates that the BAR is pr…
5183 …o support 4k, 8K, 64K, 256K, 1MB and 4MB page sizes. This PF supports a page size of 2^n+12 if bit…
5185 …lity is always enabled. Bit 0 enables the MSIX capability. This value is sticky and only reset by …
5187 …G_VF_CAP_EN_UNUSED0_BB (0x7f<<1) //
5188 …CIEIP_REG_REG_VF_CAP_EN_UNUSED0_BB_SHIFT 1
5189 …ended capability structures in the VF config space. Value programmed here only affects the VF cfg …
5192 …bility structure of PF configuration space is used to map the function's MSI-X table into memory s…
5194 … one of the functions Base address registers to point to the base of the MSI-X table . All the VF'…
5197 …on space is used to map the VF's's MSI-X PBA into memory space. All the VF's that belong to the PF…
5199 …ress contained by one of the functions Base address registers to point to the base of the MSI-X PBA
5202 … (0x3f<<0) // This field resides in VF only and does not exist …
5207 …vertized in the VF BAR4 register in the PCIE config space. This register is only applicable for EP.
5209 …bit enables the advertisement of VF BAR4 as a 64-bit address. The value of this bit maps directly …
5211 … (0x1<<5) // This bit when set is reflected in bit 3 of VF BAR4 and indicates that the BAR is pr…
5213 …M =0. This register identifies the first VFNUM location for a PF. This register exists only in a PF
5226 …ates the Untranslated Address always aligns to a 4K byte boundary. Setting this bit is recommended.
5233 …H_DEV_SPEC_MODE_BB (0x1<<1) // When Set, it ind…
5234 …CIEIP_REG_REG_VFTPH_CAP_VFTPH_DEV_SPEC_MODE_BB_SHIFT 1
5235 …e IP supports only a value of 0, which would indicate ST Table is not present, or a value of 2, wh…
5237 …d TPH capability register in the VF. The value programmed here indicates a table size of value + 1.
5249 …-7, 3-8, and 3-9 of the PCIe 3.0 specification. The limit must reflect the round trip latency from…
5251 …-4, 3-5, and 3-6 of the PCIe 3.0 specification. If there is a change in the payload size or link s…
5260 …pulse triggers link renegotiation. As the force link is a pulse, writing a 1 to it does trigger t…
5262 …) // Link state. The link state that the PCI Express bus is forced to when bit 15 (force link) is …
5264 …to SKP OS to do deskew for SRIS instead of using received SKP OS if DO_DESKEW_FOR_SRIS is set to 1.
5267 … (0xff<<0) // Link Number. Not used for endpoint. Not used for M-PCIe. Note: This reg…
5269 …The link command that the core is forced to transmit when you set FORCE_EN bit (Force Link). Link …
5271 …bit triggers the following actions: - Forces the LTSSM to the state specified by the Forced LTSSM…
5273 …tate. The LTSSM state that the core is forced to when you set the FORCE_EN bit (Force Link). LTSSM…
5275 …many clock cycles for the associated completion of a CfgWr to D-state register to go low-power. Th…
5284 … (0x7<<24) // L0s entrance latency. Values correspond to: 0x0 = 1 ms. 0x1 = 2 ms. 0x…
5286 … (0x7<<27) // L1 entrance latency. Values correspond to: 0x0 = 1 ms. 0x1 = 2 ms. 0x…
5288 …not go to L0s (receive is not in L0s). When not set, core goes to ASPM L1 only after idle period, …
5290 … 0x00070cUL //Access:RW DataWidth:0x20 // Ack Frequency and L0-L1 ASPM Control Regis…
5291 …- 0: Indicates that this Ack frequency control feature is turned off. The core schedules a low-pri…
5293 …-sets that a component can request is 255. The core does not support a value of zero; a value of z…
5295 …-sets that a component can request is 255. This field is only writable (sticky) when all of the fo…
5297 … - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us…
5299 … Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 …
5301 … // ASPM L1 Entry Control. - 1: Core enters ASPM L1 after a period in which it has been idle. - …
5304 … (0x1<<0) // Other message request. When software writes a one to this bit, the PCI Express bu…
5306 … (0x1<<1) // Scramble disable. Setting this bit t…
5307 …CIEIP_REG_PCIEEP_PORT_CTL_SD_E5_SHIFT 1
5308 …->1 transition, the PCIe core sends TS ordered sets with the loopback bit set to cause the link pa…
5310 …set assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only).
5318 …EPROM load, the first word loaded is 0xFFFFFFFF, the EEPROM load is terminated and this bit is set.
5335 …writes a '1' to this bit, the core transmits the DLLP contained in the VENDOR_SPEC_DLLP field of V…
5337 …_SCRAMBLE_DISABLE_K2 (0x1<<1) // Scramble Disable…
5338 …CIEIP_REG_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_K2_SHIFT 1
5339 …-PCIe, to force the master to enter Digital Loopback mode, you must set this field to "1" during C…
5341 …s a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This regis…
5347 …-outs and to link up faster. The scaling factor is selected in FAST_LINK_SCALING_FACTOR(default : …
5351 …". - 000001: x1 - 000011: x2 - 000111: x4 - 001111: x8 - 011111: x16 - 111111: x32 (not supp…
5370 … (0xf<<27) // Set the implementation-specific number of lanes. Allowed values are: …
5372 … (0x1<<31) // Disable lane-to-lane deskew. Disables the internal lane-t…
5381 … (0x1<<31) // Disable Lane-to-Lane Deskew. Causes the core to disable the intern…
5384 … (0xff<<0) // Max number of functions supported. Used for SR-IOV.
5392 …is 1024 (1 ms is 1 us). 0x1 = Scaling factor is 256 (1 ms is 4 us). 0x2 = Scaling factor is 64 (…
5397 …-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in inc…
5403 …1b. - 0: Scaling Factor is 1024 (1ms is 1us) - 1: Scaling Factor is 256 (1ms is 4us) - 2: Scali…
5418 … (0x1<<19) // Mask type 1 configuration reques…
5440 … (0x1<<30) // Mask filtering of received I/O requests (RC mode only).
5442 … (0x1<<31) // Mask filtering of received configuration requests (RC mode only).
5444 …1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For m…
5445 …at the core actually waits the number of symbol times in this register plus 1 between transmitting…
5451 …1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more detai…
5456 … (0x1<<1) // Mask vendor MSG type 1 dropped…
5457 …CIEIP_REG_PCIEEP_FILT_MSK2_M_VEND1_DRP_E5_SHIFT 1
5466 …SK_TD_E5 (0x1<<6) // Disable unmask TD bit.
5472 …ring" section. In each case, '0' applies the associated filtering rule and '1' masks the associate…
5476 … 0x00072cUL //Access:R DataWidth:0x20 // Debug Register 1
5492 … 0x000734UL //Access:R DataWidth:0x20 // Transmit Non-Posted FC Credit Stat…
5493 … (0xfff<<0) // Transmit Non-Posted Data FC Credits. The non-poste…
5495 … (0xff<<12) // Transmit Non-Posted Header FC Credits. The non-post…
5510 …S_TRBNE_E5 (0x1<<1) // Transmit retry b…
5511 …CIEIP_REG_PCIEEP_QUEUE_STATUS_TRBNE_E5_SHIFT 1
5524 … (0x1<<31) // FC latency timer override enable. When this bit is set, the value i…
5529 …X_RETRY_BUFFER_NE_K2 (0x1<<1) // Transmit Retry B…
5530 …CIEIP_REG_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_K2_SHIFT 1
5535 … (0x1<<31) // FC Latency Timer Override Enable. When this bit is set, the value f…
5546 … 0x000740UL //Access:R DataWidth:0x20 // VC Transmit Arbitration Register 1
5547 …xff<<0) // WRR Weight for VC0. Note: The access attributes of this field are as follows: - Dbi: R
5549 …xff<<8) // WRR Weight for VC1. Note: The access attributes of this field are as follows: - Dbi: R
5551 …ff<<16) // WRR Weight for VC2. Note: The access attributes of this field are as follows: - Dbi: R
5553 …ff<<24) // WRR Weight for VC3. Note: The access attributes of this field are as follows: - Dbi: R
5565 …xff<<0) // WRR Weight for VC4. Note: The access attributes of this field are as follows: - Dbi: R
5567 …xff<<8) // WRR Weight for VC5. Note: The access attributes of this field are as follows: - Dbi: R
5569 …ff<<16) // WRR Weight for VC6. Note: The access attributes of this field are as follows: - Dbi: R
5571 …ff<<24) // WRR Weight for VC7. Note: The access attributes of this field are as follows: - Dbi: R
5580 …only in the segmented-buffer configuration, writable through PEM()_CFG_WR. However, the applicatio…
5588 …only in the segmented-buffer configuration, writable through PEM()_CFG_WR: 0 = Strict ordering for…
5590 …for the receive queues, used only in the segmented-buffer configuration, writable through PEM()_CF…
5592 … 0x000748UL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Posted Rec…
5593 …a credits for VC0, used only in the segmented-buffer configuration. Note: The access attributes o…
5595 …r credits for VC0, used only in the segmented-buffer configuration. Note: The access attributes o…
5603 …s, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: …
5605 …receive queues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher num…
5614 …only in the segmented-buffer configuration, writable through PEM()_CFG_WR. Only one bit can be se…
5616 … (0x3<<24) // VC0 scale non-posted header credits.
5618 … (0x3<<26) // VC0 scale non-posted data credits.
5622 … 0x00074cUL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Non-Posted Receive…
5623 …-Posted Data Credits. The number of initial non-posted data credits for VC0, used only in the segm…
5625 …-Posted Header Credits. The number of initial non-posted header credits for VC0, used only in the …
5640 …only in the segmented-buffer configuration, writable through PEM()_CFG_WR. Only one bit can be se…
5648 … 0x000750UL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Completion…
5649 …a credits for VC0, used only in the segmented-buffer configuration. Note: The access attributes o…
5651 …r credits for VC0, used only in the segmented-buffer configuration. Note: The access attributes o…
5660 …uests it to prepare for leaving L0 before asserting tlp blocked. When this bit is set , if min cre…
5662 … (0x1<<1) // Target mem Rd should not be greater than…
5663 …CIEIP_REG_TL_CONTROL_0_MEMRD_1DW_CHK_BB_SHIFT 1
5666 … (0x1<<3) // Target mem Wr should not be greater than 1 DW if set.
5682 … (0x1<<12) // This bit if set will force D…
5700 … (0x1<<21) // When set, it enables WAKE generation in any L-state, when PME_EN bit is set an…
5706 … (0x1<<24) // When set, it prevents PM from re-entering L1 when programmed to non-D0 p…
5708 …BB (0x1<<25) // This bit is used by PCIE SER…
5714 …, when set, it enables pcie_scnd_rst_b to be asserted when Secondary reset bit in BridgeControl re…
5723 …_CHK_BB (0x1<<1) // Enable checks to…
5724 …CIEIP_REG_TL_CONTROL_1_EN_4K_CHK_BB_SHIFT 1
5741 … (0x1<<10) // Enable Completion Timeout Check( This bit is no longer used, instead bit defi…
5743 … (0x1<<11) // This bit is used to disable function 1. Bit 17 of 800 can also b…
5745 … (0x1<<12) // This bit is used to disable …
5747 … (0x1<<13) // This bit is used to disable …
5749 … (0x1<<14) // This bit is used to disable …
5751 … (0x1<<15) // This bit is used to disable …
5753 … (0x1<<16) // This bit is used to disable …
5755 … (0x1<<17) // This bit is used to disable …
5759 … and not wait for LTR message to be sent first even though device state may have changed to non-D0.
5767 …s bit instructs h/w to send an LTR message with LTR values programmed in 'h848 whenever the h/w as…
5769 …bit enables CRS status to be automatically cleared when internal timer is equal to either 1 second…
5771 …s bit instructs h/w to send an LTR message with LTR values programmed in 'h84c whenever the h/w as…
5773 …LTR message and wait for FC to be returned before entering L1. This bit is used only if LTR_ENABLE…
5775 … bit instructs h/w to send an LTR message with LTR values programmed in 'h844 and 'h848 whenever t…
5777 …bit instructs h/w to immediately send an LTR message with LTR values programmed in 'h840. This sta…
5782 …0_MASK_BB (0x1<<1) // Flow Control Pro…
5783 …CIEIP_REG_TL_CONTROL_2_FCPES0_MASK_BB_SHIFT 1
5845 …e in Polling.Active and L2.Idle. 0x1 = 1 lane. 0x2 = 2 lanes. 0x3 = 3 lanes. _ ... 0x10 = 16…
5847 …1. 0x2 = Connect logical Lane0 to physical lane 3. 0x3 = Connect logical Lane0 to physical l…
5855 …Config TX compliance receive bit. When set to one, signals LTSSM to transmit TS ordered sets with …
5857 … (0x1<<20) // Set the deemphasis level for upstream ports. 0 = -6 dB. 1 = -3.5 dB.
5859 …dition RxValid=0. 0 = Use RxElecIdle signal to infer electrical idle. 1 = Use RxValid signal…
5862 …his field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as…
5864 …1 of the PCI Express Base 3.0 Specification, revision 1.0. Encoding is as follows: - 0x01: 1 lane…
5866 …- 3'b000: Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8…
5868 …his field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as…
5870 …1" to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is …
5872 …bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe. Not…
5874 …Bit. When set to 1, signals LTSSM to transmit TS ordered sets with the compliance receive bit asse…
5876 …-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at…
5878 …1" value on RxElecIdle instead of looking for a "0" on RxValid. If the PHY fails to deassert the R…
5881 …e Completion retry upon completion timeout. (feature is not supported, but bit is defined for post…
5883 … (0x1<<1) // Enable Poisoned completions retry. (feature is not su…
5884 …CIEIP_REG_TL_CONTROL_3_EN_PSND_RETRY_BB_SHIFT 1
5885 …eleasing of Posted header credit. When this bit is set, PH credits are not released by IP if FIFO …
5887 … (0x1<<3) // Indicates no non-posted credit is available to user when bit…
5897 … (0x1<<16) // This bit when set prevents DUT from entering L1 due to bei…
5899 … (0x7fff<<17) // Programmable delay to prevent link from re-entering L1, when lin…
5911 … (0x1<<0) // This bit is set when h/w det…
5913 …_BB (0x1<<1) // This bit is set when h/…
5914 …CIEIP_REG_TL_CTRLSTAT_5_ERR_FC_PRTL_BB_SHIFT 1
5915 …BB (0x1<<2) // This bit is set when h/w det…
5917 …BB (0x1<<3) // This bit is set when h/w det…
5919 … (0x1<<4) // This bit is set when h/w det…
5921 … (0x1<<5) // This bit is set when h/w det…
5923 … (0x1<<6) // This bit is set when h/w det…
5925 … (0x1<<7) // This bit is set when h/w det…
5927 … (0x1<<8) // This bit is set when h/w det…
5931 … (0x1<<10) // This bit is set when h/w detects Poisoned Error Status in …
5933 … (0x1<<11) // This bit is set when h/w detects Flow Control Protocol Error Stat…
5935 … (0x1<<12) // This bit is set when h/w detects Completer Timeout Status in…
5937 …0x1<<13) // This bits is set when h/w detects Receive UR Status in function 1. If set, h/w generat…
5939 … (0x1<<14) // This bit is set when h/w detects Unexpected Completion Status …
5941 … (0x1<<15) // This bit is set when h/w detects Receiver Overflow Status in…
5943 … (0x1<<16) // This bit is set when h/w detects Malformed TLP Status in f…
5945 … (0x1<<17) // This bit is set when h/w detects ECRC Error TLP Status in …
5947 … (0x1<<18) // This bit is set when h/w det…
5982 … (0x1<<0) // This bit is used to disable …
5984 …BB (0x1<<1) // This bit is used to dis…
5985 …CIEIP_REG_TL_CONTROL_6_HIDE_FUNC_9_BB_SHIFT 1
5986 … (0x1<<2) // This bit is used to disable …
5988 … (0x1<<3) // This bit is used to disable …
5990 … (0x1<<4) // This bit is used to disable …
5992 … (0x1<<5) // This bit is used to disable …
5994 … (0x1<<6) // This bit is used to disable …
5996 … (0x1<<7) // This bit is used to disable …
6003 …his scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
6007 … (0x1<<15) // Requirement bit indicates if device…
6011 …his scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
6015 … (0x1<<31) // Requirement bit indicates if device…
6020 …his scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
6024 … (0x1<<15) // Requirement bit indicates if device…
6028 …his scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
6032 … (0x1<<31) // Requirement bit indicates if device…
6037 …his scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
6041 … (0x1<<15) // Requirement bit indicates if device…
6045 …his scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
6049 … (0x1<<31) // Requirement bit indicates if device…
6054 …his scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
6058 … (0x1<<15) // Requirement bit indicates if device…
6062 …his scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
6066 … (0x1<<31) // Requirement bit indicates if device…
6071 …PES2_MASK_BB (0x1<<1) // Flow Control Pro…
6072 …CIEIP_REG_TL_FUNC345_MASK_FCPES2_MASK_BB_SHIFT 1
6132 …BB (0x1<<0) // This bit is set when h/w det…
6134 …TL2_BB (0x1<<1) // This bit is set when h/…
6135 …CIEIP_REG_TL_FUNC345_STAT_ERR_FC_PRTL2_BB_SHIFT 1
6136 …T2_BB (0x1<<2) // This bit is set when h/w det…
6138 …T2_BB (0x1<<3) // This bit is set when h/w det…
6140 …_BB (0x1<<4) // This bit is set when h/w det…
6142 …BB (0x1<<5) // This bit is set when h/w det…
6144 …BB (0x1<<6) // This bit is set when h/w det…
6146 … (0x1<<7) // This bit is set when h/w det…
6148 …BB (0x1<<8) // This bit is set when h/w det…
6152 …B (0x1<<10) // This bit is set when h/w det…
6154 … (0x1<<11) // This bit is set when h/w det…
6156 …3_BB (0x1<<12) // This bit is set when h/w det…
6158 …3_BB (0x1<<13) // This bit is set when h/w det…
6160 …BB (0x1<<14) // This bit is set when h/w det…
6162 …B (0x1<<15) // This bit is set when h/w det…
6164 …3_BB (0x1<<16) // s bit is set when h/w det…
6166 … (0x1<<17) // This bit is set when h/w det…
6168 …B (0x1<<18) // This bit is set when h/w det…
6172 …B (0x1<<20) // This bit is set when h/w det…
6174 … (0x1<<21) // This bit is set when h/w det…
6176 …4_BB (0x1<<22) // This bit is set when h/w det…
6178 …4_BB (0x1<<23) // This bit is set when h/w det…
6180 …BB (0x1<<24) // This bit is set when h/w det…
6182 …B (0x1<<25) // This bit is set when h/w det…
6184 …B (0x1<<26) // This bit is set when h/w det…
6186 … (0x1<<27) // This bit is set when h/w det…
6188 …B (0x1<<28) // This bit is set when h/w det…
6197 …PES5_MASK_BB (0x1<<1) // Flow Control Pro…
6198 …CIEIP_REG_TL_FUNC678_MASK_FCPES5_MASK_BB_SHIFT 1
6260 …R_FC_PRTL5_BB (0x1<<1) // Flow Control Pro…
6261 …CIEIP_REG_TL_FUNC678_STAT_ERR_FC_PRTL5_BB_SHIFT 1
6323 … (0x7<<3) // Route the interrupt pin for Function 1 to any of INTA to IN…
6359 …_BB (0x1<<0) // This bit when cleared will k…
6361 …RST_BB (0x1<<1) // This bit when cleared w…
6362 …CIEIP_REG_TL_RST_CTRL_SEL_DIS_UC_PERST_BB_SHIFT 1
6363 … (0x1<<2) // This bit when set will reset the Serdes register space, pr…
6365 … (0x1<<3) // Tthis bit when set will allow bit 2 value to propogate to Serd…
6367 … (0x1<<4) // This bit when set will reset the micro, provided b…
6369 … (0x1<<5) // For gen3 serdes, this bit when set will allow bit 4 value to propogate to uc re…
6389 …r due to hide_func_1 pad being driven high or due to programming bit in TL reg This bit is tied to…
6391 … (0x1<<1) // Set if func2 is hidden either due to hide_func_2 pad being driven h…
6392 …CIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_2_HIDDEN_BB_SHIFT 1
6393 …func3 is hidden either due to hide_func_3 pad being driven high or due to programming bit in TL reg
6395 …func4 is hidden either due to hide_func_4 pad being driven high or due to programming bit in TL reg
6397 …func5 is hidden either due to hide_func_5 pad being driven high or due to programming bit in TL reg
6399 …func6 is hidden either due to hide_func_6 pad being driven high or due to programming bit in TL reg
6401 …func7 is hidden either due to hide_func_7 pad being driven high or due to programming bit in TL reg
6403 …func8 is hidden either due to hide_func_8 pad being driven high or due to programming bit in TL reg
6405 …func9 is hidden either due to hide_func_9 pad being driven high or due to programming bit in TL reg
6407 …nc10 is hidden either due to hide_func_10 pad being driven high or due to programming bit in TL reg
6409 …nc11 is hidden either due to hide_func_11 pad being driven high or due to programming bit in TL reg
6411 …nc12 is hidden either due to hide_func_12 pad being driven high or due to programming bit in TL reg
6413 …nc13 is hidden either due to hide_func_13 pad being driven high or due to programming bit in TL reg
6415 …nc14 is hidden either due to hide_func_14 pad being driven high or due to programming bit in TL reg
6417 …nc15 is hidden either due to hide_func_15 pad being driven high or due to programming bit in TL reg
6435 … (0x1<<0) // Direct reflection of Config PM PME enable bit for function 0.
6437 … (0x1<<1) // Direct reflection of config PM PME status…
6438 …CIEIP_REG_PM_STATUS_1_CFG_PME_STATUS0_BB_SHIFT 1
6441 … (0x1<<3) // Direct reflection of Config PM PME enable bit for function 1.
6443 … (0x1<<4) // Direct reflection of config PM PME status bit for function 1.
6454 …FCPES8_MASK_BB (0x1<<1) // Flow Control Pro…
6455 …CIEIP_REG_TL_FUNC8TO10_MASK_FCPES8_MASK_BB_SHIFT 1
6517 …ERR_FC_PRTL8_BB (0x1<<1) // Flow Control Pro…
6518 …CIEIP_REG_TL_FUNC8TO10_STAT_ERR_FC_PRTL8_BB_SHIFT 1
6580 …_FCPES11_MASK_BB (0x1<<1) // Flow Control Pro…
6581 …CIEIP_REG_TL_FUNC11TO13_MASK_FCPES11_MASK_BB_SHIFT 1
6641 …gating feature when there is no receive traffic, receive queues and pre/post-queue pipelines are e…
6646 …_ERR_FC_PRTL11_BB (0x1<<1) // Flow Control Pro…
6647 …CIEIP_REG_TL_FUNC11TO13_STAT_ERR_FC_PRTL11_BB_SHIFT 1
6707 … (0x1<<0) // Gen3 receiver impedance ZRX-DC not compliant.
6711 … (0x1<<9) // Equalization phase 2 and phase 3 disable. This applies to downstream ports only.
6717 … (0x1<<12) // Rx equalization phase 0/phase 1 hold enable.
6719 …o instruct the PHY to do Rx adaptation and evaluation. 0x0 = Asserts after 1 us and 2 TS1 receive…
6727 …bit in DSP will not direct the controller to Recovery state to perform Gen4 equalization. Link sta…
6729 …sends 8GT EQ TS2. If this register set to 1, USP does not send 8GT EQ TS2. This applies to upstrea…
6735 …-specific N_FTS field. The N_FTS field in the "Link Width and Speed Change Control Register" is us…
6736 …-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defin…
6740 …only. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If …
6746 …1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds pha…
6748 …1', the core as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evalua…
6761 …_FCPES14_MASK_BB (0x1<<1) // Flow Control Pro…
6762 …CIEIP_REG_TL_FUNC14TO15_MASK_FCPES14_MASK_BB_SHIFT 1
6804 …_ERR_FC_PRTL14_BB (0x1<<1) // Flow Control Pro…
6805 …CIEIP_REG_TL_FUNC14TO15_STAT_ERR_FC_PRTL14_BB_SHIFT 1
6845 … with a data payload of 0xFFFFFFFF. When the MSB of a PF's HIDE_PFn is non-zero, the PF is consi…
6911 … (0xf<<0) // Feedback mode. 0 = Direction of change. 1 = Figure of merit. 2-15 = Reser…
6913 …1 = Recovry.Equalization.Phase3. For a DSP: determine the next LTSSM state from Phase3: 0 = Reco…
6915 …mote transmitter settings. Phase2 will be terminated by the 24 ms timeout. 1 = Ignore the 2 ms ti…
6919 …Bit [15:0] = 0x0: No preset is requested and evaluated in the EQ master phase. Bit [i] = 1: Pres…
6925 … (0x1<<26) // Request core to send back-to-back EIEOS in Recove…
6927 …or Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP). M-PCIe doesn't have Con…
6928 … (0xf<<0) // Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserv…
6930 …- 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found then: …
6932 …val: - 0: abort the current evaluation, stop any attempt to modify the remote transmitter setting…
6934 …Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: "Preset=i"…
6936 …er, when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include …
6940 …-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0:…
6947 … (0xf<<10) // Convergence window aperture for C-1. Precursor coefficie…
6949 … (0xf<<14) // Convergence window aperture for C+1. Postcursor coeffici…
6952 …ore starting to check for convergence of the coefficients. Allowed values 0,1,...,24. Note: When …
6954 … when determining if optimal coefficients have been found. Allowed range: 0,1,2,..16 up to a maxim…
6956 …rgence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence windo…
6958 …gence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence windo…
6961 …-Posted passing posted ordering rule control. Determines if a NP can pass halted P queue. 0x0 = …
6963 …lted P queue. 0x0 = CPL can not pass P (recommended). 0x1 = CPL can pass P. 0x2-0xFF = Reserved.
6966 …0) // Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue.…
6968 …Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1:…
6971 … (0xffff<<0) // Loopback rxvalid (lane enable - 1 bit per lane).
6984 … (0x1<<31) // PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This reg…
6987 … (0x1<<0) // Write to RO registers using DBI. When you set this bit, then some RO bits …
6989 …1) // Default target a received IO or MEM request with UR/CA/CRS is sent to be the controller. 0x…
6990 …CIEIP_REG_PCIEEP_MISC_CTL1_DEF_TARGET_E5_SHIFT 1
6991 …only applies to request TLPs (with UR filtering status) that are chosen to forward to the applicat…
6993 … when extended synch is 0. A value from 80,000 to 100,000 symbol times when extended synch is 1.
6995 … upstream port. 0 = Allow the autonomous generation of LTR clear message. 1 = Disable the autono…
6999 … 0x0008bcUL //Access:RW DataWidth:0x20 // DBI Read-Only Write Enable Regis…
7000 …field to "1", then some RO and HwInit bits are writable from the local application through the DBI…
7005 …bit is set. If PCIEEP_RAS_EINJ_CTL6PE[LTSSM_VAR] is set and PCIEEP_LINK_CTL2[HASD] is zero, the …
7009 … 0x0008c0UL //Access:RW DataWidth:0x20 // UpConfigure Multi-lane Control Register…
7010 …- 6'b000000: Core does not start upconfigure or autonomous width downsizing in the Configuration s…
7012 …bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DI…
7014 …n Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This reg…
7017 …ted condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. …
7019 … = Core waits for the PHY to assert phy_mac_pclkack_n before exiting L1. 1 = Core exits L1 with…
7021 … (0x1<<9) // L1 entry control bit. 0 = Core waits for the PHY to acknowledge transition to P1 …
7023 … (0x1<<10) // L1 clock control bit. 0 = Controller requests aux_clk switch and core_clk g…
7026 …Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. - [0]: Rx EIOS a…
7028 …bit. - 1: Core does not wait for PHY to acknowledge transition to P1 before entering L1. - 0: Co…
7030 …egister you can delete on entry in the target completion LUT. You should only use this register w…
7033 …This is a one-shot bit. Writing a one triggers the deletion of the target completion LUT entry tha…
7035 …ching for received application completions (on XALI0/1/2) corresponding to previously received non…
7038 …hot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is …
7046 … (0xf<<0) // Split table contents for tag0. this corresponds to Device_no[4:1] of PCIE header.
7096 … (0xff<<24) // Non-Posted Data credits available: bit[7:0…
7105 … (0xf<<28) // Non-Posted Data credits available: bit[11:…
7114 … (0xff<<24) // Non-Posted Data credits consumed: bit[7:0].
7123 … (0xf<<28) // Non-Posted Data credits consumed: bit[11:8…
7134 … (0x1<<16) // Available Non-posted credit for tar…
7137 …B (0xff<<0) // Non-Posted header credits…
7139 …B (0xff<<8) // Non-Posted data credits a…
7146 … (0xf<<0) // Target Non-Posted request State …
7175 …bit when set enables the DUT to assume that VFs are residing on a bus number that is different tha…
7177 …1) // This bit when set, prevents DUT from automatically setting VF offset to be greater than 256(…
7178 …CIEIP_REG_TL_IOV_VFCTL_0_VF_OFFSET_VETO_BB_SHIFT 1
7179 …T_BB (0x1<<2) // This bit when set, enables D…
7182 …non-posted data credits since the last request for immediate update that are needed to force an im…
7184 …-posted header credits since the last request for immediate update that are needed to force an imm…
7186 …-posted credits are flagged for immediate update. When clear, the credits may or not be updated un…
7188 …he forced update if there are outstanding non-posted credits to update. The resolution on the time…
7190 …-posted credit updates are forwarded to the DLL as immediate updates after a given number of micro…
7193 …eeded to force an immediate update. The default is (PD_INIT_CREDIT >> 1). A value of 0 means…
7195 …eeded to force an immediate update. The default is (PH_INIT_CREDIT >> 1). A value of 0 means…
7199 … update if there are outstanding posted credits to update. The resolution on the timer is +/- 1 us.
7201 …w) elapses since the last update. This is typically used with non-immediate (threshold-based) upda…
7204 … (0xf<<0) // Each bit, when set, indicates that the corresponding capability available…
7206 … (0x3ff<<4) // Each bit, when set, indicates that the corresponding capability available i…
7208 … (0x3<<14) // Each bit, when set, indicates that the corresponding capability available in …
7210 … (0xf<<16) // Each bit, when set, indicates that the corresponding capability available in…
7212 … (0xf<<20) // Each bit, when set, indicates that the corresponding capability available in…
7216 … (0x1f<<26) // Each bit, when set, indicates that the corresponding capability available in …
7223 … (0x1<<16) // VDM is enabled when this bit is set. PCIe will pass VDM messgaes to user interface…
7226 … (0x1<<0) // This bit when set, forces hardware to generate a PTM Request message. Hardware…
7228 … (0x1<<1) // This field when set will prevent hardware from generating a…
7229 …CIEIP_REG_PTM_CTL0_REG_PTM_ATTN_MASK_BB_SHIFT 1
7232 …is field when set inidcates that the PTM req-response handshake initiated by software has complete…
7234 …ld when set inidcates that the PTM req-response handshake completed successfully. This field is va…
7244 …bit to '1' enables the tx TLP statistics collection. Hardware will count various types of TLPs in …
7246 …IER_TL_STAT_TX_CTL_UNUSED0_BB (0x7f<<1) //
7247 …CIEIP_REG_PCIER_TL_STAT_TX_CTL_UNUSED0_BB_SHIFT 1
7248 …he reg_ttx_tlp_stat_en bit to stop the operation. When it is set to a non-zero value, hardware aut…
7251 …This register contains Enable bit and the TLP type that hardware can detect. Bit[7] is enable bit.…
7253 …This register contains Enable bit and the TLP type that hardware can detect. Bit[15] is enable bit…
7255 …This register contains Enable bit and the TLP type that hardware can detect. Bit[23] is enable bit…
7257 …This register contains Enable bit and the TLP type that hardware can detect. Bit[31] is enable bit…
7260 …value is 0. If a bit is set to 1 then corresponding bit of reg_ttx_det_tlp_type_0 will be masked. …
7264 …value is 0. If a bit is set to 1 then corresponding bit of reg_ttx_det_tlp_type_1 will be masked. …
7268 …value is 0. If a bit is set to 1 then corresponding bit of reg_ttx_det_tlp_type_2 will be masked. …
7272 …value is 0. If a bit is set to 1 then corresponding bit of reg_ttx_det_tlp_type_3 will be masked. …
7274 …ber of TLPs that have been trasmitted. It is cleared when reg_ttx_tlp_stat_en goes from '0' to '1'.
7275 …ber of TLPs that have been trasmitted. It is cleared when reg_ttx_tlp_stat_en goes from '0' to '1'.
7277 …bit to '1' enables the rx TLP statistics collection. Hardware will count various types of TLPs pro…
7279 …IER_TL_STAT_RX_CTL_UNUSED0_BB (0x7f<<1) //
7280 …CIEIP_REG_PCIER_TL_STAT_RX_CTL_UNUSED0_BB_SHIFT 1
7281 …he reg_trx_tlp_stat_en bit to stop the operation. When it is set to a non-zero value, hardware aut…
7284 …This register contains Enable bit and the TLP type that hardware can detect. Bit[7] is enable bit.…
7286 …This register contains Enable bit and the TLP type that hardware can detect. Bit[15] is enable bit…
7288 …This register contains Enable bit and the TLP type that hardware can detect. Bit[23] is enable bit…
7290 …This register contains Enable bit and the TLP type that hardware can detect. Bit[31] is enable bit…
7293 …value is 0. If a bit is set to 1 then corresponding bit of reg_trx_det_tlp_type_0 will be masked. …
7297 …value is 0. If a bit is set to 1 then corresponding bit of reg_trx_det_tlp_type_1 will be masked. …
7301 …value is 0. If a bit is set to 1 then corresponding bit of reg_trx_det_tlp_type_2 will be masked. …
7305 …value is 0. If a bit is set to 1 then corresponding bit of reg_trx_det_tlp_type_3 will be masked. …
7307 …ber of TLPs that have been trasmitted. It is cleared when reg_trx_tlp_stat_en goes from '0' to '1'.
7308 …ber of TLPs that have been trasmitted. It is cleared when reg_trx_tlp_stat_en goes from '0' to '1'.
7323 …<<0) // Snoop Latency Value. Note: The access attributes of this field are as follows: - Dbi: R/W
7325 …<10) // Snoop Latency Scale. Note: The access attributes of this field are as follows: - Dbi: R/W
7327 …/ Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Dbi: R/W
7329 …) // No Snoop Latency Value. Note: The access attributes of this field are as follows: - Dbi: R/W
7331 …) // No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Dbi: R/W
7333 …o Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Dbi: R/W
7336 …clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-…
7339 …1 us reference for counting time during low-power states with aux_clk when the PHY has removed the…
7346 … (0x3<<6) // Max delay (in 1 us units) between a …
7389 …RETRIG_CNT_BB (0xff<<0) // When non-zero, indicates the m…
7391 …FIFO is read by user interface. When set, indicates that the DBG FIFO is read by CS registers only.
7393 …ger location (where data corresponding to the trigger cycle is collected). Bit 17 is a wrap condit…
7397 … (0x1<<26) // Asserted when attn signal is generated and active. Write 1 to clear the attn.
7403 …buffer is filled, the trig_addr field is used to determine the amount of pre-trigger data collected
7422 … (0x1ff<<23) // Current write address to the external FIFO. Bit 31 is a wrap condit…
7424 …- mask bits [319:0] for 0to1 trigger0 Register 10 :: IND_PCIE_DBG_TRIG0_1TO0_MASK - mask bits [319…
7455 …- no FIFO selected to read by user if 001 - PL/DL FIFO is selected to read by user if 010 - TLDA…
7459 … (0x7<<12) // 000 - generic lane is selected 001 - predefined lane 1 010 - predefine…
7490 …only when reading FIFOs from the user interface. When set, all pretrigger data is considered valid…
7496 … (0x1<<14) // When set, indicates that the FIFO is operating in local mode - FIFO will be read fr…
7498 … (0x7f<<15) // The number of pre-trigger samples to keep. pretrig_cnt[6] is on…
7500 … (0x7f<<22) // The FIFO write address at the time of the trigger. Use bit 13 of this register…
7523 …-- First trigger configuration registers Register 0 :: IND_TLDA_TRIG0_0TO1_MASK0 -- Trigger 0 risi…
7525 … 0x000c50UL //Access:R DataWidth:0x20 // Bits [127:96] of the current half-data from the FIFO
7526 … 0x000c54UL //Access:R DataWidth:0x20 // Bits [95:64] of the current half-data from the FIFO
7527 … 0x000c58UL //Access:R DataWidth:0x20 // Bits [63:32] of the current half-data from the FIFO
7528 … 0x000c5cUL //Access:R DataWidth:0x20 // Bits [31:0] of the current half-data from the FIFO
7540 …only when reading FIFOs from the user interface. When set, all pretrigger data is considered valid…
7546 … (0x1<<14) // When set, indicates that the FIFO is operating in local mode - FIFO will be read fr…
7548 … (0x7f<<15) // The number of pre-trigger samples to keep. pretrig_cnt[6] is on…
7550 … (0x7f<<22) // The FIFO write address at the time of the trigger. Use bit 13 of this register…
7573 …-- First trigger configuration registers Register 0 :: IND_TLDA_TRIG0_0TO1_MASK0 -- Trigger 0 risi…
7575 …000c70UL //Access:R DataWidth:0x20 // Bits [127:96] of the current half-data from the second …
7576 …x000c74UL //Access:R DataWidth:0x20 // Bits [95:64] of the current half-data from the second …
7577 …x000c78UL //Access:R DataWidth:0x20 // Bits [63:32] of the current half-data from the second …
7578 …0x000c7cUL //Access:R DataWidth:0x20 // Bits [31:0] of the current half-data from the second …
7582 … (0x1<<1) // PHY: Disable Inverse Polarity. Setting this b…
7583 …CIEIP_REG_PDL_CONTROL_0_DIS_INV_POLARITY_BB_SHIFT 1
7584 … (0x1<<2) // DL: Disable Replay Timer. In effect, REPLAY only occurs when NACK DL…
7596 … (0x1<<10) // PHY: Disable Electrical Idle Retrain. Setting this bit to '1' prevents link f…
7598 … (0x1<<11) // DL: Disable Auto Credit Update. If this bit is set to '1', DL will not…
7602 … (0x1<<13) // DL: Force L0 to L1. When this bit is set to '1', DL will sen…
7606 …HY: Force Receiver Detect All. When this bit is set to '1', internal Receiver Detected signals are…
7610 … (0x1<<27) // DL: Force L0 to L2. When this bit is set to '1', DL will sen…
7616 …(0x1<<31) // PHY: Direct Recovery to Configuration State. When this bit is set to '1', LTSSM is di…
7621 … (0x1<<7) // When this bit is set, the softwar…
7625 … (0x1<<9) // When this bit is set, the software value will be used for UpdateFC L…
7627 …bit is set to '1', Replay Timer will not be reset if a NAK is received during a Replay operation. …
7629 … (0x1<<11) // PHY: Force to TX L0s. Setting this bit to '1' forces LTSSM to…
7633 …x1<<14) // This initiates Link re-training by directing PHY LTSSM to recovery state. It is a pulse…
7641 … (0x1<<30) // Internal ASPM L1 Enable. When this bit is set to '1', hardware au…
7643 … (0x1<<31) // External ASPM L1 Enable. When this bit is set to '1', user can di…
7648 … (0x1<<2) // PHY: Disable SKP OS. When this bit is set to '1', periodic SK…
7650 … will enable ACK Latency Timer. In this case, DL ACK or NACK requests are only sent out when timer…
7652 … HW will select programmable value depending on whether PHY operates in gen 1or gen2. The programm…
7654 … HW will select programmable value depending on whether PHY operates in gen 1or gen2. The programm…
7664 …1<<17) // DL: Enable Non-Posted Latency Timer. If this timer reaches MAX_ACK_LAT_TIMER value, DL w…
7678 … (0xfff<<0) // DL: Non-Posted Data for INITFC
7687 … (0x1<<8) // This bit is set to '1' if IP is con…
7700 … (0xffff<<16) // Reserved - always write 0
7703 …ay timeout in symbol time. It is selected if bit sw_replay_timer_sel is set to '1'; otherwise, the…
7705 …al delay for the replay timeout in symbol time. This delay is only applied to the hardware-calcula…
7707 …_BB (0x7ff<<21) // Reserved - always write 0
7712 …the spec internal delay, this adjustment is subtracted out from the hardware-calculated value so t…
7717 …ay timeout in symbol time. It is selected if bit sw_replay_timer_sel is set to '1'; otherwise, the…
7719 …al delay for the replay timeout in symbol time. This delay is only applied to the hardware-calcula…
7728 … earlier, DL will nullify all subsequence memory write request whose pcie_cksum_err bit is not set.
7730 …WRITE_NULLIFY is set, regardless if they have bad or good checksum If this bit is clear and checks…
7734 …t from sending more Posted FC updates , potentially stall DMA requests, until the flag de-asserted.
7737 …ay timeout in symbol time. It is selected if bit sw_replay_timer_sel is set to '1'; otherwise, the…
7739 …al delay for the replay timeout in symbol time. This delay is only applied to the hardware-calcula…
7744 …the spec internal delay, this adjustment is subtracted out from the hardware-calculated value so t…
7751 …the spec internal delay, this adjustment is subtracted out from the hardware-calculated value so t…
7762 … (0x3<<27) // This selects the source that drives the debug bus 1 when debug access is…
7764 … (0x3<<29) // This selects the source that drives the debug bus 1 when debug access is…
7766 …(0x1<<31) // Enable GRC to control the driving of the debug bus. When this bit is set, it provides…
7769 …a TLP. Generates pcie_err_att status to chip. This status is not cleared till a 1 is written to it.
7771 …UF_OFLOW_ERR_BB (0x1<<1) // Signal DLP2TLP b…
7772 …CIEIP_REG_DLATTN_VEC_DL_D2TBUF_OFLOW_ERR_BB_SHIFT 1
7779 …when Correctable Error counter reach max CORR_ERR_REG_MAX value defined at bit [27:18] of reg 0x10…
7781 … (0x1<<6) // Indicate un-decoded condition in de-framing l…
7791 … (0x1<<11) // Set if DL detects impossible condition to de-allocate entries in R…
7799 … (0x1<<15) // DL TX Underrun. This bit is set to '1' if underrun …
7801 … (0x1<<16) // Detect DLLP with mismatched CRC-16 on receiving side.
7807 … (0x1<<19) // This signal is set to '1' when the TLP length…
7837 …at DL has to send at least one UpdateFC DLLP for each FC credit type when Extended Sync bit is '0'.
7839 …at DL has to send at least one UpdateFC DLLP for each FC credit type when Extended Sync bit is '1'.
7844 …bit is set to '1' to enable the T2D FIFO threshold feature. Depending on TL, DL bus width and cloc…
7846 …_COUNT_THRS_BB (0x7<<1) // T2D FIFO Count T…
7847 …CIEIP_REG_DL_T2D_THRS_DL_T2D_COUNT_THRS_BB_SHIFT 1
7853 …bit replayfifo_testsize_sel is set to '1', this value is used as the Replay FIFO size. This value …
7855 …bit d2tfifo_testsize_sel is set to '1', this value is used as the D2T FIFO size. This value must b…
7859 …lect. When this bit is set to '1', the value in replayfifo_testsize will be used as Replay FIFO si…
7861 … Select. When this bit is set to '1', the value in d2tfifo_testsize will be used as D2T FIFO size.…
7869 …allows the address to be programmed in preparation for a write. A write of '1' on these bits initi…
7874 … bit must be written as a '1' to initiate write cycle based ont the data in bits [15:0] and the md…
7877 …dr register, this area will return the MDIO data. This field is only valid if the CMD field is '1'.
7879 …31) // This bit will read as '0' until a requested read of the PCIE serdes has completed, in which…
7881 …8-bit header information that is sent to TL logic to build a TLP. The header information is passed…
7886 …. Specify the number of TLP's to be transferred. When ate_tlp_go is set to '1', the value in this …
7888 … (0x1<<8) // ATE TLP Nullify. When this bit is set to '1', an internal…
7897 …bit. When this bit is set to '1', the TX User Interface is bypassed and internal logic generates p…
7899 …TE_TLP_CTL_UNUSED0_BB (0x7<<1) //
7900 …CIEIP_REG_ATE_TLP_CTL_UNUSED0_BB_SHIFT 1
7901 …bit. SW needs to read trx_reg_sb_op_done (bit[31]). If trx_reg_sb_op_done register value is 1, it …
7905 …'1' indicates that transmitted TLP header does not match with received TLP header. This bit can be…
7907 …of '1' indicates that transmitted TLP data do not match with received TLP data. This bit can be cl…
7911 … - offset 0x111c). trx_reg_err_tlp_num indicates the number of TLP that has error. This register i…
7915 …1' indicates that number of TLPs received is equal to number of TLPs transmitted (ATE_TLP_CNT (bit…
7928 … (0x1f<<27) // Device ID. Value of 1 for this device.
7935 …This bit must be written as a '1' to initiate read cycle to the pmi_addr value. When the read has …
7937 …bit must be written as a '1' to initiate write cycle based on the data in bits [15:0] and the pmi_…
7940 …dr register, this area will return the MDIO data. This field is only valid if the CMD field is '1'.
7944 …31) // This bit will read as '0' until a requested read of the PCIE serdes has completed, in which…
7967 … (0x1<<0) // Request a width change (ie -make the link wider, …
7969 …_REQ_BB (0x1<<1) // Request a speed change (ie -make …
7970 …CIEIP_REG_REG_PHY_CTL_0_DIRECTED_SPEED_CHANGE_REQ_BB_SHIFT 1
7975 … (0x1<<6) // For multi-lane links on a 2.0 c…
7981 … (0x1<<9) // Consider loss of bit and symbol lock fro…
7997 … Modified Compliance Pattern in Polling.Compliance if the Enter Compliance bit of the Link Control…
8001 …ng.Compliance from Polling.Active. This also causes the Compliance Receive bit in the outgoing TS1…
8003 … (0x1<<21) // The value for the Selectable Deemphasis bit set in TS1s in Poll…
8005 …s to the PCIe Serdes via the TxDeemph signal. 0 == -6 dB, 1 == -3.5 dB (For Gen3, this is the low …
8007 … (0x1<<23) // The value for the Autonomous Change bit set in TS1s in the …
8015 … (0x1<<27) // Disable use of electrical idle in Recovery.Speed - only use inferred elect…
8019 … (0x1<<29) // Disable the ability to compensate for lane reversal in multi-lane links.
8023 … (0x1<<31) // Enable gen2 features when in 1.1 compliance mode (register 0x4d0, bit 5 is set)
8026 … (0x1<<0) // Force the PIPE interface to be 16-bit, even in Gen 1 Software sh…
8028 …DISABLE_COMPLIANCE_BB (0x1<<1) // Disable entry to…
8029 …CIEIP_REG_REG_PHY_CTL_1_REG_DISABLE_COMPLIANCE_BB_SHIFT 1
8030 … (0x1<<2) // Enable the PIPE-style powerdown of unused lanes in a multi-…
8032 … (0x1<<3) // Enable the auxilliary powerdown of unused lanes in a multi-lane link.
8034 … (0x1<<4) // Initiate PL changes required for a far-end loopback
8040 … PIPE interface) so that EIDL OS appears first if present (0 = 24 clocks, 1 = 1 clock, 2 = 2 clock…
8052 …Skip Ordered Set (SOS) is received in any 128 us interval. See comments for bit 19 of this register
8054 …L0 if no UpdateFC is received in any 128 us interval. Can be combined with bit 18 of this register…
8060 … (0x1<<25) // Speed up training by 1000x (1 ms = 1 us)
8062 … (0x1<<26) // Speed up training by 2000x (1 ms = 500 ns). Do not…
8068 … (0x1<<29) // Clear the LTSSM histogram. Not self-clearing
8070 … (0x1<<30) // Clear the Gen2 debug histogram. Not self-clearing
8072 … (0x1<<31) // Clear the recovery histogram. Not self-clearing
8081 …erved - only write 0. Spare flops for the PL - train_ctl_in[1:0]. [29] (PL_FIX_19) Enable Phase 3 …
8083 …es elastic buffers will be prevented from adjusting - generating dynamic clock compensation events…
8085 … (0x1<<31) // Reserved - only write 0. Spare flop for the PL - t…
8092 … (0x1<<14) // Enable the "pins" gloopback - assumes an external …
8121 …_BB (0x1<<0) // For RC only. Select the value t…
8123 …D_MATCH_UP_BB (0x1<<1) // For RC only. Enale autom…
8124 …CIEIP_REG_REG_PHY_CTL_4_REG_ENA_SPEED_MATCH_UP_BB_SHIFT 1
8125 …_DOWN_BB (0x1<<2) // For RC only. Enale automatic sp…
8127 …S_BB (0x1<<3) // For RC only. For testing/simula…
8129 …S_BB (0x1<<4) // For RC only. For testing/simula…
8131 …_DETECT_BB (0x1<<5) // For RC only. When the RC is aut…
8133 …TCH_BB (0x1<<6) // For RC only. Report automatic s…
8135 …itiated speed change (directed_speed_change) even if the link partner has only advertised Gen1 rat…
8137 …low link partner to initiate speed change (directed_speed_change) even if only Gen1 rate has been …
8139 …ES_BB (0x1<<9) // For RC only. Advertise the supp…
8143 …nimum time to wait in Detect.Quiet (in 32 ns increments) if the state is entered at non-Gen1 speeds
8149 … (0x1<<16) // Enable exit from Compliance on 1.1-compliant systems on …
8151 …r of lanes for signal detect to avoid entry to Compliance. 0 means only 1 is needed, 1 means all a…
8155 … (0x1f<<19) // Mask for indicating lanes to upconfigure (1, 2, 4, 8, or 16)
8162 … (0xf<<5) // High 4 bits of the 10 bit-counter of 25 MHz cl…
8168 …erdes device type to minimize the PLL lock time (when set, don't reuse the old value - start over).
8170 … (0x3<<22) // Selects the low-frequency clock used …
8172 … (0x3f<<24) // Low 6 bits of the 10 bit-counter of 25 MHz cl…
8174 … (0x1<<30) // Reserved - only write 0
8176 …<<31) // When set, disables entry to CLKREQ when L2/L23 is requested (ie, only PM L1 and ASPM L1 e…
8181 …B (0x3<<6) // Reserved - only write 0
8185 … (0x3<<14) // Reserved - only write 0
8189 … (0x1<<17) // Use any PhyStatus to indicate the P0->P2 transition. De…
8195 … (0xfff<<20) // Reserved - only write 0
8198 … (0xf<<0) // b0000: select pseudo-random value between 1 to 15 b00…
8202 …ne is chosen b01111 : lane 15 b01110 : lane 14 .... b00010 : lane 2 b00001 : lane 1 b00000 : lane 0
8212 … (0x1fff<<18) // Reserved - always write 0
8219 …ISPARITY_ERR_BB (0x1<<1) // If set, a dispar…
8220 …CIEIP_REG_PHY_ERR_ATTN_VEC_DISPARITY_ERR_BB_SHIFT 1
8233 …1_BB (0xf<<8) // Reserved - only write 0
8240 …MASK_DISPARITY_ERR_BB (0x1<<1) // If set, masks DI…
8241 …CIEIP_REG_PHY_ERR_ATTN_MASK_MASK_DISPARITY_ERR_BB_SHIFT 1
8246 … // If set, masks TRAIN_ERR from generating attention. If clear, TRAIN_ERR generates attention RW 1
8254 …_1_BB (0xf<<8) // Reserved - only write 0
8261 …GEN3_ENA_BLOCK_REALIGN_BB (0x1<<1) // Enable request t…
8262 …CIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_BLOCK_REALIGN_BB_SHIFT 1
8269 … (0x1<<8) // *** Do not modify!! Enable 16-bit data for all rates.
8279 …rity reversal, and lane reversal information is saved, then restored. This bit disables the restor…
8287 … (0x3<<17) // Reserved - only write 0
8289 …) // Enable updated timeouts for Recovery.Equalization phases (now 12 ms for 0 and 1, 32 ms for 3).
8312 … (0x1<<20) // Enable a bad/misplaced End-of-Data-Stream token as a…
8339 …_LOCAL_DEEMPH_HI_BB (0x7<<1) // Upper three bits…
8340 …CIEIP_REG_REG_PHY_CTL_10_REG_LOCAL_DEEMPH_HI_BB_SHIFT 1
8343 … (0x1<<5) // Software sets if it can disable data traffic during re-equalization.
8371 …O_PRESET_BB (0x1<<22) // enable echo preset bit in Phase 3
8375 …1 depending on whether Slave is an RC or EP respectively. When this bit is set to '1', Slave takes…
8383 …B (0x1<<28) // Reserved - only write 0
8387 … (0x1<<30) // Enable exiting Phase 2 only on Tx of EC=2'b11 r…
8398 … (0x1<<7) // For Gen3 TS1s in Equalization, match symbols 1 to 5 as well
8406 … (0x1<<11) // Enable Gen3 redo deskew on framing/post-deskew alignment issu…
8414 … (0x1<<15) // Use the l0s/l1 failure signal only for Gen3
8416 …B (0x1<<16) // Use the phy l1 active signal only for Gen3
8428 … (0x1<<22) // (PL_FIX_05) Enable preset-coefficient lookup fo…
8447 …C_BB (0x1<<6) // SED read address auto-increment
8463 …/ [DEBUG_BIT}: Captures internal defined FS and LF values when receive use preset = 1 in EQ Phase 1
8468 …ET_LUT_ENTRY_5_TO_0_BB (0x3f<<0) // Pre-cursor for the coeffi…
8472 …_LUT_ENTRY_17_TO_12_BB (0x3f<<12) // Post-cursor for the coeffi…
8478 …ET_SEL_BB (0x1<<23) // Conbtrol bit to select the defau…
8480 …y the EP to the Link partner-RC Transmitter in Phase2 EQ programmable preset value advertized by t…
8523 …ister control programming of coefficients for preset-0(-6dB) and preset-1(-3.5dB) in the format {C…
8525 …ogramming index for preset 0 and 1 0: points to the preset 0 coefficients(-6dB) 1: points to the p…
8527 … (0x1<<19) // Gen1/Gen2 deemphasis register control programming write strobe for Preset 0 and 1
8529 …0x1<<20) // Gen2 deemphasis register select control bit to change from Preset-1(-3.5dB) to preset-…
8531 …bit for the read status of the gen1/2 and gen2 lut entry 18-bit value poining to the corresponding…
8544 … (0x1<<0) // AFE TX deemphasis register override enable control bit for prectrl[1:0] LSB two b…
8546 …B (0x3<<1) // AFE TX deemphasis register control two LSB bit value…
8547 …CIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_PRE_CTRL_LSB_VAL_BB_SHIFT 1
8548 … (0x1<<3) // AFE TX deemphasis register override enable control bit for main[1:0] LSB two bits
8550 … (0x3<<4) // AFE TX deemphasis register control two LSB bit value for main[1:0]
8552 … (0x1<<6) // AFE TX deemphasis register override enable control bit for postctrl[1:0] LSB two b…
8554 … (0x3<<7) // AFE TX deemphasis register control two LSB bit value for postctrl[1:0]
8556 … (0x1<<9) // AFE TX deemphasis register override enable control bit for prectrl[4:2] up…
8558 … (0x7<<10) // AFE TX deemphasis register control upper three bit value for prectrl[4…
8560 … (0x1<<13) // AFE TX deemphasis register override enable control bit for main[4:2] upper…
8562 … (0x1f<<14) // AFE TX deemphasis register control upper five bit value for main[6:2]
8564 … (0x1<<19) // AFE TX deemphasis register override enable control bit for postctrl[5:2] u…
8566 … (0xf<<20) // AFE TX deemphasis register control upper four bit value for postctrl[…
8568 … (0x1<<24) // AFE TX deemphasis register override enable control bit for post2[3:0] four…
8570 … (0xf<<25) // AFE TX deemphasis register control for four bit value for post2[3:0]
8576 … (0x1<<31) // RX reset EIEOS control bit for TS1(SYM6-Bit2) in Reco…
8579 … (0x1<<0) // Enable bit to control the registered programmed FULL SWING valu…
8581 … (0x3f<<1) // Registered programmed 6-bit FULL SWING value i…
8582 …CIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EQ_FS_VAL_BB_SHIFT 1
8583 … (0x1<<7) // Enable bit to control the registered programmed LOW FREQUENCY va…
8585 … (0x3f<<8) // Registered programmed 6-bit LOW FREQUENCY value in Phase 1 of …
8589 …BB (0x1<<15) // [DEBUG_BIT]: Disables the 1usec wait time for LP…
8591 …BB (0x1<<16) // Enables EC0 echo use preset bit in EP mode
8593 …ET_BB (0x1<<17) // Enables EC2 echo use preset bit in RC mode
8603 … (0x1<<22) // [DEBUG_BIT]: Ignores the phase 2 received usepreset bit when checking for p…
8611 …<<26) // [DEBUG_BIT]: RC mode : Forces Gen3 equalization for every Speed change over from Gen1-Gen3
8613 … (0x1f<<27) // [DEBUG_BITS]: Equalization static debug 5-bit address control for…
8616 … (0x1<<0) // Enable Illegal Ordered Set After EDS Error. When this bit is set to '1', report Gen3…
8618 … (0x1<<1) // Enable Ordered Set After SDS Error. When this bit …
8619 …CIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_OS_AFTER_SDS_ERR_BB_SHIFT 1
8620 … (0x1<<2) // Enable Ordered Set with No EDS Error. When this bit is set to '1', report Gen3…
8622 … (0x1<<3) // Enable Bad Framing CRC Error. When this bit is set to '1', report Gen3…
8624 … (0x1<<4) // Enable Bad Framing Parity Error. When this bit is set to '1', report Gen3…
8626 … (0x1<<5) // Enable Bad EDB Error. When this bit is set to '1', report Gen3…
8628 … (0x1<<6) // Enable Bad Framing Symbol Error. When this bit is set to '1', report Gen3…
8630 … (0x1<<7) // Enable Data After EDS Error. When this bit is set to '1', report Gen3…
8633 …bit to '1' enables the master loopback operation. Normally, if lpbk_master_len is set to '0', soft…
8635 … (0x1<<1) // Loopback Master Entry State. If this bit is s…
8636 …CIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_ENTRY_BB_SHIFT 1
8637 …back Master Set Compliance Receive. If this bit is set to '1', the Compliance Receive bit in TS1 i…
8639 … Set Compliance Receive. If this bit is set to '1', hardware automatically sets the Compliance Rec…
8641 …ce Setting. When loopback is entered from Recov.Idle state and this bit is set to '1', hardware ap…
8643 …bit is set, SKP OS are periodically inserted to loopback data. If data is generated by PHY, MAC pr…
8645 …r each SKIP OS interval. For testing purpose, when this bit is set to '1', hardware inserts only o…
8653 …e lpbk_master_ena bit to stop the operation. When it is set to a non-zero value, hardware automati…
8656 …Master Entry Timeout. While in Loopback.Entry state, if Compliance Receive bit was not set in tran…
8658 …aWidth:0x20 // The loopback status register is cleared when lpbk_master_ena goes from '0' to '1'.
8659 …ter Status. This is the status of the last loopback operation. 1'b0: completed normally 1'b1: exit…
8661 …1. Entered from Configuration.Linkwidth.Start and changed to a new speed. 2. Entered from Recovery…
8668 …CURSOR_BB (0x3f<<8) // Loopback Master TS1 Pre-Cursor Coefficient. T…
8672 …URSOR_BB (0x3f<<20) // Loopback Master TS1 Post-cursor Coefficient. T…
8674 … (0x1<<26) // Loopback Master TS1 Selectable De-emphasis. This value …
8676 …: 1. Entered from Configuration.Linkwidth.Start and changed to a new speed. 2. Entered from Recove…
8679 … used when loopback is in Gen2 rate. Notes that for Gen1 the TX deemphasis is always set to -3.5db.
8682 … (0x1<<0) // Software LTSSM Enable. Setting this bit to '1' allows software…
8684 … (0x1<<1) // Software LTSSM Delay Start. When this b…
8685 …CIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_DLYSTART_BB_SHIFT 1
8686 …1' to this bit updates the internal software LTSSM state with the state specified by sw_ltssm_tops…
8688 … (0x1<<3) // LTSSM Timeout Disable. When this bit is set to '1', all LTSSM t…
8692 …-level State. This field specifies the state of the sub-level state machine that software wants LT…
8696 … (0x1ff<<20) // Software LTSSM Top-level State. This field specifies the state of th…
8700 …his bit reflects the internal software LTSSM enable that is set to '1' only when S/W is actually i…
8703 …bit to '1' enables the PCIE statistic collection. Hardware will count various things such as the n…
8705 …IE_STATIS_CTL_UNUSED0_BB (0x7f<<1) //
8706 …CIEIP_REG_PCIE_STATIS_CTL_UNUSED0_BB_SHIFT 1
8707 …ar the pcie_statis_ena bit to stop the operation. When it is set to a non-zero value, hardware aut…
8709 …er of TLP bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.
8711 …er of TLP bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.
8713 …r of DLLP bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.
8715 …r of DLLP bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.
8717 …dered set bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.
8719 …dered set bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.
8721 …mber of TLP bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.
8723 …mber of TLP bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.
8725 …ber of DLLP bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.
8727 …ber of DLLP bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.
8729 …ordered set bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.
8731 …ordered set bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.
8733 …rrors detected by Physical Layer Receiver. It is cleared when pcie_statis_ena goes from '0' to '1'.
8734 …LP CRC errors detected by Data Link Layer. It is cleared when pcie_statis_ena goes from '0' to '1'.
8735 …number errors detected by Data Link Layer. It is cleared when pcie_statis_ena goes from '0' to '1'.
8737 …bit to '1' enables the LTSSM statisic collection. When this bit is reset to '0', information is fr…
8739 … (0x1<<1) // LTSSM Statistic Auto Increment. When this bit is set to '1', hardware automatica…
8740 …CIEIP_REG_LTSSM_STATIS_CTL_LTSSM_STATIS_AUTOINC_BB_SHIFT 1
8744 … (0xffff<<0) // Equalization Phase 1 Time. This field contains the time that LTSSM spent in Equ…
8773 …Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this re…
8775 … (0x7f<<8) // For lane 13 in a multi-lane system: The numb…
8777 …<15) // For lane 13 in a multi-lane system: Set by the link partner when it locks to the Modified …
8781 …Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this re…
8783 … (0x7f<<24) // For lane 15 in a multi-lane system: The numb…
8785 …<31) // For lane 15 in a multi-lane system: Set by the link partner when it locks to the Modified …
8790 …Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this re…
8792 … (0x7f<<8) // For lane 9 in a multi-lane system: The numb…
8794 …<<15) // For lane 9 in a multi-lane system: Set by the link partner when it locks to the Modified …
8798 …Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this re…
8800 … (0x7f<<24) // For lane 11 in a multi-lane system: The numb…
8802 …<31) // For lane 11 in a multi-lane system: Set by the link partner when it locks to the Modified …
8807 …Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this re…
8809 … (0x7f<<8) // For lane 5 in a multi-lane system: The numb…
8811 …<<15) // For lane 5 in a multi-lane system: Set by the link partner when it locks to the Modified …
8815 …Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this re…
8817 … (0x7f<<24) // For lane 7 in a multi-lane system: The numb…
8819 …<<31) // For lane 7 in a multi-lane system: Set by the link partner when it locks to the Modified …
8824 …Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this re…
8826 … (0x7f<<8) // For lane 1 in a multi-lane system: Th…
8828 … (0x1<<15) // For lane 1 in a multi-lane system: Set by the link partner when it locks to the Mod…
8832 …Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this re…
8834 … (0x7f<<24) // For lane 3 in a multi-lane system: The numb…
8836 …<<31) // For lane 3 in a multi-lane system: Set by the link partner when it locks to the Modified …
8843 … (0x7f<<8) // For lane 13 in a multi-lane system: The numb…
8845 … (0x1<<15) // For lane 13 in a multi-lane system: Set by t…
8851 … (0x7f<<24) // For lane 15 in a multi-lane system: The numb…
8853 … (0x1<<31) // For lane 15 in a multi-lane system: Set by t…
8860 … (0x7f<<8) // For lane 9 in a multi-lane system: The numb…
8862 … (0x1<<15) // For lane 9 in a multi-lane system: Set by t…
8868 … (0x7f<<24) // For lane 11 in a multi-lane system: The numb…
8870 … (0x1<<31) // For lane 11 in a multi-lane system: Set by t…
8877 … (0x7f<<8) // For lane 5 in a multi-lane system: The numb…
8879 … (0x1<<15) // For lane 5 in a multi-lane system: Set by t…
8885 … (0x7f<<24) // For lane 7 in a multi-lane system: The numb…
8887 … (0x1<<31) // For lane 7 in a multi-lane system: Set by t…
8894 …BB (0x7f<<8) // For lane 1 in a multi-lane system: Th…
8896 …BB (0x1<<15) // For lane 1 in a multi-lane system: Se…
8902 … (0x7f<<24) // For lane 3 in a multi-lane system: The numb…
8904 … (0x1<<31) // For lane 3 in a multi-lane system: Set by t…
8914 … (0xff<<8) // Count of recognized FTSOS 1 Rx_L0s ago
8939 … (0xff<<0) // Gen2 Debug History - current. Changes are…
8941 … (0xff<<8) // Gen2 Debug History 1 transitions ago (see…
8957 … (0xff<<0) // Recovery History - current. Changes are…
8959 … (0xff<<8) // Recovery History 1 transitions ago (see…
9015 …) // The current state of the ATE loopback SM tracker: b00011 : IDLE state - not active b00101 : …
9026 …_SET_GEN3_ERR_BAD_FCRC_BB (0x1<<1) // FCRC error in th…
9027 …CIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_FCRC_BB_SHIFT 1
9062 …L_EDSOS_BB (0x1<<19) // This bit is set to '1' when the ord…
9066 … 0x001d38UL //Access:R DataWidth:0x20 // PHY Debug - Polling Compliance s…
9067 … 0x001d3cUL //Access:R DataWidth:0x20 // PHY Debug - Equalization signals
9154 …FG_1_BB (0xff<<8) // SED Extended Configuration 1.
9177 … (0x7ff<<16) // Debug signals that are muxed to the debug port 1.
9192 … (0xf<<24) // The state of the clock PM state machine and perstb 1 transition in the pa…
9248 … (0x1<<0) // Instantaneous value of the top-level user_allow_gen3…
9250 …_STATUS_UNUSED_BB (0x7fffffff<<1) //
9251 …CIEIP_REG_MISC_DBG_STATUS_UNUSED_BB_SHIFT 1
9253 … (0xffff<<0) // Vendor ID. For SR-IOV VFs always 0xFFFF.
9255 … (0xffff<<16) // Device ID. For SR-IOV VFs always 0xFFFF.
9258 …ENDOR_ID_K2 (0xffff<<0) // Vendor ID. PCI-SIG assigned Manufact…
9263 …E_E5 (0x1<<0) // VF read-only zero.
9265 …E_E5 (0x1<<1) // VF read-only zero.
9266 …CIEIP_VF_REG_PCIEEPVF_CMD_MSAE_E5_SHIFT 1
9267 …bit is not set, the request is discarded. A interrupt will be generated setting the SPEM()_PF()_DB…
9281 … (0x1<<9) // Fast back-to-back transaction ena…
9283 …S_E5 (0x1<<10) // VF read-only zero.
9289 … (0x1<<19) // INTx status. Not applicable for SR-IOV. Hardwired to 0.
9291 … (0x1<<20) // Capabilities list. Indicates presence of an extended capability item. Hardwired to 1.
9295 … (0x1<<23) // Fast back-to-back capable. Not ap…
9312 …. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
9314 …1) // Enables Memory Access Response. You cannot write to this register if your configuration ha…
9315 …CIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_K2_SHIFT 1
9352 …_ERR_K2 (0x1<<30) // Fatal or Non-Fatal Error Message s…
9359 … (0xff<<8) // Read-only copy of the associ…
9361 … (0xff<<16) // Read-only copy of the associ…
9363 … (0xff<<24) // Read-only copy of the associ…
9375 … (0xff<<0) // Read-only copy of the associ…
9381 … (0x1<<23) // Read-only copy of the associ…
9397 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
9400 …E_K2 (0x3<<1) // BAR0 32-bit or 64-bit.
9401 …CIEIP_VF_REG_VF_BAR0_REG_BAR0_TYPE_K2_SHIFT 1
9407 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
9410 …E_K2 (0x3<<1) // BAR1 32-bit or 64-bit.
9411 …CIEIP_VF_REG_VF_BAR1_REG_BAR1_TYPE_K2_SHIFT 1
9417 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
9420 …E_K2 (0x3<<1) // BAR2 32-bit or 64-bit.
9421 …CIEIP_VF_REG_VF_BAR2_REG_BAR2_TYPE_K2_SHIFT 1
9427 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
9430 …E_K2 (0x3<<1) // BAR3 32-bit or 64-bit.
9431 …CIEIP_VF_REG_VF_BAR3_REG_BAR3_TYPE_K2_SHIFT 1
9437 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
9440 …E_K2 (0x3<<1) // BAR4 32-bit or 64-bit.
9441 …CIEIP_VF_REG_VF_BAR4_REG_BAR4_TYPE_K2_SHIFT 1
9447 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
9450 …E_K2 (0x3<<1) // BAR5 32-bit or 64-bit.
9451 …CIEIP_VF_REG_VF_BAR5_REG_BAR5_TYPE_K2_SHIFT 1
9459 … (0xffff<<0) // Read-only copy of the associ…
9461 … (0xffff<<16) // Read-only copy of the associ…
9464 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
9466 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
9469 … (0x1<<0) // Read-only copy of the associ…
9471 … (0x1fff<<19) // Read-only copy of the associ…
9480 … (0xff<<0) // VF's read-only zeros.
9482 … (0xff<<8) // VF's read-only zeros.
9484 … (0xff<<16) // VF's read-only zeros.
9486 … (0xff<<24) // VF's read-only zeros.
9496 … (0xff<<8) // Next capability pointer. Points to the MSI-X capabilities by def…
9498 …5 (0xf<<16) // Read-only copy of the associ…
9500 … (0xf<<20) // Read-only copy of the associ…
9502 … (0x1<<24) // Read-only copy of the associ…
9504 … (0x1f<<25) // Read-only copy of the associ…
9515 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
9522 … (0x7<<0) // Read-only copy of the associ…
9524 … (0x3<<3) // Read-only copy of the associ…
9526 … (0x1<<5) // Read-only copy of the associ…
9528 … (0x7<<6) // Read-only copy of the associ…
9530 … (0x7<<9) // Read-only copy of the associ…
9532 … (0x1<<15) // Read-only copy of the associ…
9538 … (0x1<<28) // Function level reset capability. Set to 1 for SR-IOV core.
9545 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
9547 …CCPT_LATENCY_K2 (0x7<<6) // Applies to endpoints only L0s acceptable late…
9549 …CPT_LATENCY_K2 (0x7<<9) // Applies to endpoints only L1 acceptable laten…
9551 …_PCIE_CAP_ROLE_BASED_ERR_REPORT_K2 (0x1<<15) // Role-based Error Reporting…
9557 … (0x1<<28) // Function Level Reset Capability (endpoints only).
9562 …F_DEV_CTL_NFE_EN_E5 (0x1<<1) // VF RsvdP.
9563 …CIEIP_VF_REG_PCIEEPVF_DEV_CTL_NFE_EN_E5_SHIFT 1
9582 …_FLR] must not be written to one via the indirect PEM()_CFG_WR. It should only ever be written to …
9584 …e receive any of the errors in PCIEEPVF()_COR_ERR_STAT, for example a replay-timer timeout. Also,…
9590 …ests are nonfatal errors, so [UR_D] should cause [NFE_D]. Receiving a vendor-defined message shoul…
9592 …D_E5 (0x1<<20) // VF's read-only zeros.
9594 … (0x1<<21) // Transaction pending. Set to 1 when nonposted reque…
9599 …VICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2 (0x1<<1) // Non-fatal Error Repor…
9600 …CIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2_SHIFT 1
9609 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
9611 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
9613 …PM_EN_K2 (0x1<<10) // Aux Power PM Enable. This bit is derived by sampl…
9615 …(0x1<<11) // Enable No Snoop. Note: The access attributes of this field are as follows: - Dbi: R
9623 …STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2 (0x1<<17) // Non-Fatal Error Detected …
9629 …ED_K2 (0x1<<20) // Aux Power Detected Status. This bit is derived by sampl…
9634 … (0xf<<0) // Read-only copy of the associ…
9636 … (0x3f<<4) // Read-only copy of the associ…
9638 … (0x3<<10) // Read-only copy of the associ…
9640 … (0x7<<12) // Read-only copy of the associ…
9642 … (0x7<<15) // Read-only copy of the associ…
9644 … (0x1<<18) // Read-only copy of the associ…
9646 … (0x1<<19) // Read-only copy of the associ…
9648 … (0x1<<20) // Read-only copy of the associ…
9650 … (0x1<<21) // Read-only copy of the associ…
9652 … (0x1<<22) // Read-only copy of the associ…
9654 … (0xff<<24) // Read-only copy of the associ…
9657 …D_K2 (0xf<<0) // Maximum Link Speed. In M-PCIe mode, the reset …
9659 …_K2 (0x3f<<4) // Maximum Link Width. In M-PCIe mode, the reset …
9663 …bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) deter…
9665 …bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) deter…
9667 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
9675 … ASPM Optionality Compliance. Note: The access attributes of this field are as follows: - Dbi: R
9696 … (0x1<<10) // Link bandwidth management interrupt enable. This bit is not applicable a…
9698 … (0x1<<11) // Link autonomous bandwidth interrupt enable. This bit is not applicable a…
9702 …bit location in the supported link speeds vector (in the link capabilities 2 register) that corres…
9721 …his field are as follows: - Dbi: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_…
9723 …e Link Retrain. Note: The access attributes of this field are as follows: - Dbi: see description
9729 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9733 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9735 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9743 …figuration or Recovery State. Note: The access attributes of this field are as follows: - Dbi: R
9745 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
9749 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9751 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9762 …_E5 (0x1<<7) // 32-bit AtomicOp supported.…
9764 …_E5 (0x1<<8) // 64-bit AtomicOp supported.…
9766 …_E5 (0x1<<9) // 128-bit AtomicOp supported.…
9768 … (0x1<<10) // No RO-enabled PR-PR passing. (This bit appl…
9776 …PL_SUPP_E5 (0x1<<16) // 10-bit tag completer suppo…
9778 …EQ_SUPP_E5 (0x1<<17) // 10-bit tag requestor suppo…
9784 …5 (0x1<<21) // End-end TLP prefix suppor…
9786 … (0x3<<22) // Read-only copy of the associ…
9797 …EG_PCIE_CAP_32_ATOMIC_CPL_SUPP_K2 (0x1<<7) // 32 Bit AtomicOp Completer …
9799 …EG_PCIE_CAP_64_ATOMIC_CPL_SUPP_K2 (0x1<<8) // 64 Bit AtomicOp Completer …
9801 …G_PCIE_CAP_128_CAS_CPL_SUPP_K2 (0x1<<9) // 128 Bit CAS Completer Suppo…
9803 …O_EN_PR2PR_PAR_K2 (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing.
9807 …CIE_CAP_TPH_CMPLT_SUPPORT_0_K2 (0x1<<12) // TPH Completer Supported Bit 0.
9809 …CIE_CAP_TPH_CMPLT_SUPPORT_1_K2 (0x1<<13) // TPH Completer Supported Bit 1.
9828 …EQ_EN_E5 (0x1<<12) // 10-bit tag requestor enabl…
9832 … (0x1<<15) // Unsupported end-end TLP prefix blocki…
9854 …_E5 (0x7f<<1) // Read-only copy of the a…
9855 …CIEIP_VF_REG_PCIEEPVF_LINK_CAP2_SLSV_E5_SHIFT 1
9863 …TIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_K2 (0x7f<<1) // Supported Link S…
9864 …CIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_K2_SHIFT 1
9867 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
9870 …TLS_E5 (0xf<<0) // VF's read-only zeros.
9872 …EC_E5 (0x1<<4) // VF's read-only zeros.
9874 …HASD_E5 (0x1<<5) // VF's read-only zeros.
9876 …SDE_E5 (0x1<<6) // VF's read-only zeros.
9878 …TM_E5 (0x7<<7) // VF's read-only zeros.
9880 …MC_E5 (0x1<<10) // VF's read-only zeros.
9882 …SOS_E5 (0x1<<11) // VF's read-only zeros.
9884 …DE_E5 (0xf<<12) // VF's read-only zeros.
9886 … (0x1<<16) // Read-only copy of the associ…
9909 …ET_LINK_SPEED_K2 (0xf<<0) // Target Link Speed. In M-PCIe mode, the conten…
9913 …Speed Disable. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
9915 …SEL_DEEMPHASIS_K2 (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s. …
9919 …ed Compliance. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
9921 … transmission. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
9923 … // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. Note: The access attributes of thi…
9925 … (0x1<<16) // Current De-emphasis Level. In M-PCIe mode this register is alwa…
9929 …_P1_K2 (0x1<<18) // Equalization 8.0GT/s Phase 1 Successful. Note: …
9942 …NTRL_MSIXCID_E5 (0xff<<0) // MSI-X capability ID.
9946 … (0x7ff<<16) // MSI-X table size encoded as (table size - 1).…
9948 …ask bit determines whether the vector is masked or not. 1 = All vectors associated with the funct…
9950 …X_CAP_CNTRL_MSIXEN_E5 (0x1<<31) // MSI-X enable.
9952 … 0x0000b0UL //Access:RW DataWidth:0x20 // MSI-X Capability ID, Next…
9953 …NEXT_CTRL_REG_PCI_MSIX_CAP_ID_K2 (0xff<<0) // MSI-X Capability ID.
9955 …TRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2 (0xff<<8) // MSI-X Next Capability Poi…
9957 …-X Table Size. SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PC…
9959 …(0x1<<30) // Function Mask. Note: The access attributes of this field are as follows: - Dbi: R/W
9961 … (0x1<<31) // MSI-X Enable. Note: The access attributes of this field are…
9964 …R_E5 (0x7<<0) // Read-only copy of the associ…
9966 … (0x1fffffff<<3) // Read-only copy of the associ…
9968 … 0x0000b4UL //Access:R DataWidth:0x20 // MSI-X Table Offset and BI…
9969 …_PCI_MSIX_BIR_K2 (0x7<<0) // MSI-X Table Bar Indicator…
9971 …_PCI_MSIX_TABLE_OFFSET_K2 (0x1fffffff<<3) // MSI-X Table Offset.
9974 …E5 (0x7<<0) // Read-only copy of the associ…
9976 … (0x1fffffff<<3) // MSI-X table offset register. Base address of the M…
9978 … 0x0000b8UL //Access:R DataWidth:0x20 // MSI-X PBA Offset and BIR …
9979 …OFFSET_REG_PCI_MSIX_PBA_K2 (0x7<<0) // MSI-X PBA BIR.
9981 …_PCI_MSIX_PBA_OFFSET_K2 (0x1fffffff<<3) // MSI-X PBA Offset.
9991 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
9993 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
9995 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
10000 …P_CTL_ACSFGC_E5 (0x1<<1) // ACS function gro…
10001 …CIEIP_VF_REG_PCIEEPVF_ARI_CAP_CTL_ACSFGC_E5_SHIFT 1
10013 …ACS_FUN_GRP_CAP_K2 (0x1<<1) // ACS Function Gro…
10014 …CIEIP_VF_REG_VF_CAP_REG_ARI_ACS_FUN_GRP_CAP_K2_SHIFT 1
10031 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
10033 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
10035 … Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R…
10040 …Q_CAP_INTV_E5 (0x1<<1) // Interrupt Vector…
10041 …CIEIP_VF_REG_PCIEEPVF_TPH_REQ_CAP_INTV_E5_SHIFT 1
10046 … (0x1<<9) // Steering Tag Table Location bit 0
10048 … (0x1<<10) // Steering Tag Table Location bit 1
10052 …orm a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10055 …REG_REG_TPH_REQ_CAP_INT_VEC_K2 (0x1<<1) // Interrupt Vector…
10056 …CIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_K2_SHIFT 1
10061 …BLE_LOC_0_K2 (0x1<<9) // ST Table Location Bit 0. Note: This reg…
10063 …E_LOC_1_K2 (0x1<<10) // ST Table Location Bit 1. Note: This regi…
10070 …EN_E5 (0x3<<8) // TPH Requestor Enable bit.
10073 …(0x7<<0) // ST Mode Select. Note: The access attributes of this field are as follows: - Dbi: R/W
10075 …REG_TPH_REQ_CTRL_REQ_EN_K2 (0x3<<8) // TPH Requester Enable Bit.
10083 … 0 Lower Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
10085 … 0 Upper Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
10097 …P_CTL_TB_E5 (0x1<<1) // ACS translation …
10098 …CIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_TB_E5_SHIFT 1
10126 …ftware and not readable from the application. The BAR 0 mask register is only writable through PE…
10127 …1: BAR 0 is enabled. Bit 0 is interpreted as BAR enable when writing to the BAR mask register rat…
10129 …SKL_LMASK_E5 (0x7fffffff<<1) // BAR mask low.
10130 …CIEIP_SHADOW_REG_PCIEEP_BAR0_MASKL_LMASK_E5_SHIFT 1
10131 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10132 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10134 … (0x7fffffff<<1) // BAR0 Mask. Note: The access attributes of this field are as fol…
10135 …CIEIP_SHADOW_REG_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_K2_SHIFT 1
10136 …ftware and not readable from the application. The BAR 0 mask register is only writable through PE…
10137 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10138 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10140 … (0x7fffffff<<1) // BAR1 Mask. Note: The access attributes of this field are as fol…
10141 …CIEIP_SHADOW_REG_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_K2_SHIFT 1
10142 …0x20 // The BAR 1 mask register is invisible to host software and not readable from the applicat…
10143 …1 is disabled, 1: BAR 1 is enabled. Bit 0 is interpreted as BAR enable when writing to the BAR ma…
10145 …ASKL_LMASK_E5 (0x7fffffff<<1) // BAR mask low
10146 …CIEIP_SHADOW_REG_PCIEEP_BAR1_MASKL_LMASK_E5_SHIFT 1
10147 …0x20 // The BAR 1 mask register is invisible to host software and not readable from the applicat…
10148 …ftware and not readable from the application. The BAR 2 mask register is only writable through PE…
10149 …1: BAR 2 is enabled. Bit 0 is interpreted as BAR enable when writing to the BAR mask register rat…
10151 …SKL_LMASK_E5 (0x7fffffff<<1) // BAR mask low.
10152 …CIEIP_SHADOW_REG_PCIEEP_BAR2_MASKL_LMASK_E5_SHIFT 1
10153 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10154 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10156 … (0x7fffffff<<1) // BAR4 Mask. Note: The access attributes of this field are as fol…
10157 …CIEIP_SHADOW_REG_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_K2_SHIFT 1
10158 …ftware and not readable from the application. The BAR 2 mask register is only writable through PE…
10159 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10160 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10162 … (0x7fffffff<<1) // BAR5 Mask. Note: The access attributes of this field are as fol…
10163 …CIEIP_SHADOW_REG_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_K2_SHIFT 1
10164 … software and not readable from the application. The ROM mask register is only writable through PE…
10165 …1 = BAR ROM is enabled. Bit 0 is interpreted as BAR enable when writing to the BAR mask register r…
10167 …ASK_MASK_E5 (0x7fffffff<<1) // BAR mask low
10168 …CIEIP_SHADOW_REG_PCIEEP_EROM_MASK_MASK_E5_SHIFT 1
10169 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10170 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: if RO…
10172 … (0x7fffffff<<1) // Expansion ROM Mask. Note: The access attributes of this field are a…
10173 …CIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG_ROM_MASK_K2_SHIFT 1
10174 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10175 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10177 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10180 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10182 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10184 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10185 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10187 … (0x7fffffff<<1) // BAR0 Mask. Note: The access attributes of this field are as fol…
10188 …CIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG_PCI_SRIOV_BAR0_MASK_K2_SHIFT 1
10189 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10190 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10192 … (0x7fffffff<<1) // BAR1 Mask. Note: The access attributes of this field are as fol…
10193 …CIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG_PCI_SRIOV_BAR1_MASK_K2_SHIFT 1
10194 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10195 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10197 … (0x7fffffff<<1) // BAR2 Mask. Note: The access attributes of this field are as fol…
10198 …CIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG_PCI_SRIOV_BAR2_MASK_K2_SHIFT 1
10199 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10200 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10202 … (0x7fffffff<<1) // BAR3 Mask. Note: The access attributes of this field are as fol…
10203 …CIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG_PCI_SRIOV_BAR3_MASK_K2_SHIFT 1
10204 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10205 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10207 … (0x7fffffff<<1) // BAR4 Mask. Note: The access attributes of this field are as fol…
10208 …CIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG_PCI_SRIOV_BAR4_MASK_K2_SHIFT 1
10209 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10210 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10212 … (0x7fffffff<<1) // BAR5 Mask. Note: The access attributes of this field are as fol…
10213 …CIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG_PCI_SRIOV_BAR5_MASK_K2_SHIFT 1
10219 … (0x1<<0) // This bit masks, when set, the Interrupt bit: S…
10230 … (0x1<<0) // This bit masks, when set, the Parity bit: SE…
10232 … (0x1<<1) // This bit masks, when set, the Parity bi…
10233 …EM_FAST_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5_SHIFT 1
10234 … (0x1<<2) // This bit masks, when set, the Parity bit: SE…
10236 … (0x1<<3) // This bit masks, when set, the Parity bit: SE…
10238 … (0x1<<4) // This bit masks, when set, the Parity bit: SE…
10240 … (0x1<<5) // This bit masks, when set, the Parity bit: SE…
10242 … (0x1<<6) // This bit masks, when set, the Parity bit: SE…
10244 … (0x1<<7) // This bit masks, when set, the Parity bit: SE…
10246 … (0x1<<0) // This bit masks, when set, the Parity bit: SE…
10248 … (0x1<<1) // This bit masks, when set, the Parity bi…
10249 …EM_FAST_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_SHIFT 1
10250 … (0x1<<2) // This bit masks, when set, the Parity bit: SE…
10252 … (0x1<<3) // This bit masks, when set, the Parity bit: SE…
10254 … (0x1<<4) // This bit masks, when set, the Parity bit: SE…
10256 … (0x1<<5) // This bit masks, when set, the Parity bit: SE…
10258 … (0x1<<6) // This bit masks, when set, the Parity bit: SE…
10290 …-only access of the GPRE registers. Register can be accessed only when storm is stalled. Address b…
10292 … 0x000480UL //Access:R DataWidth:0x20 // 15-0 STORM0 GPRE0 bits 15:0. 31-16 STOR…
10293 …- misc_local_mux_other_stall, 20 - ram_mux_bkpt_stall, 19 - mux_lock_stall, 18 - pram_mux_pipe_st…
10298 …ether or not the Storm is currently stalled. bit0- STORM A. bit1- STORM B. bit2- Pram Breakpoint. …
10303 …R DataWidth:0xf // This register delivers the PRAM address for the low-word instruction that…
10304 … DataWidth:0xf // This register delivers the PRAM address for the high-word instruction that…
10307 … Storm. A value of 1 means that the PortID will be taken as a single bit , a value of 2 means that…
10308 …efines the offset (in bits) from the lsb of the CID in which to assign to bit-0 of the port ID. I.…
10309 …dth:0x1 // Defines the Storm register file set that is currently active. 0 - STORM A 1 - STORM B
10310 …- DRA WR STM Core_A, 3:5 - DRA WR STM Core_B, 6:8 - DRA RD STM Core_A, 9:11 - DRA RD STM Core_B, …
10311 … DataWidth:0x20 // Last read address from STORM to pram {add_p_out_high; 1'b0; add_p_out_low}.
10312 … DataWidth:0x20 // Last read address from STORM to pram {add_p_out_high; 1'b0; add_p_out_low}.
10313 …bit in the data field will result in a corresponding bit inversion in the written data while ECC i…
10315 …th:0x20 // This register delivers the Storm PC for read-only debug access. 15-0 - STORM A. 31-16…
10316 …e access type defined in data_breakpoint_access_set), the STORMs bits 15:0 - IRAM stall start add…
10317 …efined in data_breakpoint_access_set), the STORMs will be stalled. bit15:0 - IRAM stall end addre…
10318 …- stall on read access. bit1 - stall on write access. bit3:2 - stall on write BE (bit2 -to IRAM'…
10319 …er defines the IRAM address for which the data breakpoint stall was set. bits 0:15 - IRAM address.
10320 … DataWidth:0x20 // Last read address from STORM to pram {add_p_out_high; 1'b0; add_p_out_low}.
10323 … indirect registers defines the modulus (roll-over) values for the corresponding real time clocks.…
10326 …-time clock with regard to the associated RTClkTickValue. The Storm decode assignments used for th…
10329 …-time clocks. This value is assigned to the corresponding real-time clock only when the Storm corr…
10332 …-time clock with the value provided by the associated RTClkInitValue register. The Storm decode as…
10335 …direct registers provides read access to the real time clock values. The sub-address for this indi…
10337 … vector containing a bit per RTC used to enable each of the ten real-time clocks. The bit index co…
10347 …is register delivers the valid bit from CAM for the most recent RBC read request issued. The valid…
10350 … (0x1<<0) // Writing a one to this register bit (transition from 0 to 1) causes…
10352 … (0x1<<1) // When set, this bit enables h…
10353 …EM_FAST_REG_CAM_CONTROL_CAM_SCRUB_HIT_EN_SHIFT 1
10354 … (0x1<<2) // When set, this bit enables miss parity…
10357 …-bit CAM match vector returned in the most recent RBC-initiaged search request. For this, cam_matc…
10359 …ate the SEMI fast debug, based on the mode defined by the DebugMode register; 0=inactive, 1=active.
10360 …-PRINTF; 0x1-PRAM address; 0x2-Reserved; 0x3-DRA read + DRA write; 0x4-load/store address; 0x5-fas…
10361 …ources for modes 2 and 3 on the fast debug channel: b0-DRA write disable; b1-DRA read disable; b2-…
10362 …able any of the following debug sources for mode-4 on the fast debug channel: b0-store data disabl…
10363 …ces for mode-6 on the fast debug channel: b0-dra_in disable; b1-fin disable; b2-load disable; b3-t…
10364 … id that should compared with cid field of the data (in Dra-In message); Note: applicable only whe…
10365 …aWidth:0x8 // Event id that should compared with event id field of the data (in Dra-In message).
10366 …//Access:RW DataWidth:0x8 // Mask for event id. 1- specified bit is ignored; 0 - specified bi…
10367 …e event ID range filter. A range of event IDs to capture for fast debug mode-6 and for active stat…
10368 …e event ID range filter. A range of event IDs to capture for fast debug mode-6 and for active stat…
10370 …- Filter off; in that case all data should be transmitted to the DBG block without any filtering i…
10372 …1 - use the recorded connection id field which arrives from the DBG block (dbg_sem_cid interface) …
10378 … // Used to define the DRA-In source that should be compared for recording handlers. A value of 0 …
10386 …nsmit store transactions. For all the bits of the mask that are set, then only if the correspondin…
10387 … transactions. For all the bits of dbg_store_addr_mask that are set, then only if the correspondin…
10388 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
10400 …ABLE_ACT_FILTER_EVNT_ID_EN (0x1<<1) // Used to enable E…
10401 …EM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_EVNT_ID_EN_SHIFT 1
10402 … Used to define the DRA-In source that should be compared for active statistics counter. A value o…
10408 … 0x000a44UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10409 … 0x000a44UL //Access:RC DataWidth:0x20 // Statistics - The accumulated numb…
10411 … 0x000a4cUL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10412 … 0x000a4cUL //Access:RC DataWidth:0x20 // Statistics - The accumulated numb…
10413 … 0x000a50UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10414 …- The accumulated number of Storm cycles in which the Storm has been idle due to having no threads…
10415 … 0x000a54UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10416 … 0x000a54UL //Access:RC DataWidth:0x20 // Statistics - The accumulated numb…
10417 … 0x000a58UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10418 … 0x000a5cUL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10419 … 0x000a60UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10420 … 0x000a64UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10425 …- response is ready. It is set when response cycle of 32 bit is ready from VFC block. It is reset …
10429 … 0x000c4cUL //Access:R DataWidth:0x20 // Provides read-only access to the BIST…
10434 …m bits 31:0; otherway from bits 63:32. Upper bit 9 selects the RF. Upper bit 10 selects the STORM.…
10437 …-address. Bits [3:0] of the data bus provide the OpCode for the request where the following numera…
10439 … 0x00a000UL //Access:RW DataWidth:0x20 // Provides a memory-mapped region for VFC…
10441 …uished). If lsb bit of addr = 0 => write to lock ID of addr[3:1] LOCK_VAL[31:0] if lsb bit of add…
10447 … 0x020000UL //Access:RW DataWidth:0x20 // Internal RAM (if bit lsb of addr =0 => w…
10450 …vector CAM mask that are used for search and add commands. 1 means the corresponding data bit shou…
10451 …vector CAM mask that are used for search and add commands. 1 means the corresponding data bit shou…
10452 …vector CAM mask that are used for search and add commands. 1 means the corresponding data bit shou…
10453 …vector CAM mask that are used for search and add commands. 1 means the corresponding data bit shou…
10454 … vector CAM mask that are used for search and add commands.1 means the corresponding data bit shou…
10455 …vector CAM mask that are used for search and add commands. 1 means the corresponding data bit shou…
10456 … vector CAM mask that are used for search and add commands.1 means the corresponding data bit shou…
10457 …vector CAM mask that are used for search and add commands. 1 means the corresponding data bit shou…
10458 …ister includes bit per ALU vector: 0-4 long vectors; 5-11 short vectors. When it is set then appro…
10459 …e that will be written to DSt vector for analyze operation. If it is set to 1, then row from targe…
10461 …be asserted when there is attempt to write to read only register. It will be de-asserted aftre wri…
10463 …O_ITERRUPT (0x1<<1) // This is error in…
10464 …FC_REG_INTERRUPT_IND_INP_FIFO_ITERRUPT_SHIFT 1
10471 …ess not equal to 12 bit or data cycle not equal 64 bit or number of data cycles bigger than 6. It…
10473 …d when waitp is asserted and output FIFO is also full. It will be de-asserted aftre write 1 to it.
10475 …d when it was address overflow of INFO part of RSS RAM. It will be de-asserted aftre write 1 to it.
10477 …n it was address overflow of KEY LSB part of RSS RAM. It will be de-asserted aftre write 1 to it.
10479 …hen it was address overflow of KEY MSB part of RSS RAM. It will be de-asserted aftre write 1 to it.
10482 … (0x1<<1) // This is parity interrupt. It may be asserted when it was CAM parity error.…
10483 …FC_REG_PARITY_IND_CAM_PARITY_SHIFT 1
10484 …may be asserted when it was parity error inside TT RAM. It will be de-asserted aftre write 1 to it.
10486 …. It may be asserted when it was RSS RAM parity error. It will be de-asserted aftre write 1 to it.
10491 …_EMPTY (0x1<<1) // Empty indication…
10492 …FC_REG_INDICATIONS1_LEN_FIFO_EMPTY_SHIFT 1
10532 … 0x000038UL //Access:W DataWidth:0x1 // Write to this bit will cause to block…
10534 …1 to this bit will cause reset of all CAM rows including valid bit and all bits in a row. Write 0 …
10536 …1 to this bit will cause reset of all Target tables rows. Write 0 to it will have no effect. Read …
10538 …1) // Write 1 to this bit will cause reset of all RSS RAM rows. Write 0 to it will have no effect.…
10539 …FC_REG_MEMORIES_RST_RAM_RST_BB_K2_SHIFT 1
10540 …-If this bit is set then background mechanism for parity check will be enabled; 0 - disabled. This…
10541 … 0x000044UL //Access:RW DataWidth:0x4 // Cam clock divider : may be equal to 2 only.
10542 … 0x000048UL //Access:RW DataWidth:0x3 // REQUIRED - 0 - parity is enabled;1 parity c…
10543 … 0x00004cUL //Access:RW DataWidth:0xa // REQUIRED - 0 - interrupt is enabled;1- interr…
10545 … 0x000054UL //Access:RW DataWidth:0x5 // TM indication for RSS RAM instance 1.
10548 … 0x000060UL //Access:RW DataWidth:0x1 // Bist enable bit for Cam.
10553 …allow for RBC to configurate block. STORM command may be executed when this bit will be deasserted.
10556 …ccess:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset;…
10557 …ccess:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset;…
10595 … 0x0000fcUL //Access:R DataWidth:0x9 // Last analyze offset for ALU vector 1.
10602 …UL //Access:RW DataWidth:0x1 // If this bit set to 0 then allows to work with 160 clients. If…
10607 … (0x1<<0) // This bit masks, when set, the Parity bit: VF…
10609 … (0x1<<1) // This bit masks, when set, the Parity bi…
10610 …FC_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_E5_SHIFT 1
10611 … (0x1<<2) // This bit masks, when set, the Parity bit: VF…
10613 … (0x1<<5) // This bit masks, when set, the Parity bit: VF…
10615 … (0x1<<3) // This bit masks, when set, the Parity bit: VF…
10617 … (0x1<<4) // This bit masks, when set, the Parity bit: VF…
10619 … (0x1<<0) // This bit masks, when set, the Parity bit: VF…
10621 … (0x1<<1) // This bit masks, when set, the Parity bi…
10622 …FC_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_BB_K2_SHIFT 1
10623 … (0x1<<2) // This bit masks, when set, the Parity bit: VF…
10625 … (0x1<<3) // This bit masks, when set, the Parity bit: VF…
10627 … (0x1<<4) // This bit masks, when set, the Parity bit: VF…
10629 … (0x1<<2) // This bit masks, when set, the Parity bit: VF…
10634 …01_I_ECC_EN_E5 (0x1<<1) // Enable ECC for m…
10635 …FC_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_E5_SHIFT 1
10638 …02_I_ECC_EN_BB_K2 (0x1<<1) // Enable ECC for m…
10639 …FC_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_BB_K2_SHIFT 1
10641 …E5 (0x1<<0) // Set parity only for memory ecc inst…
10643 …ECC_PRTY_E5 (0x1<<1) // Set parity only for memory…
10644 …FC_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_E5_SHIFT 1
10645 …BB_K2 (0x1<<0) // Set parity only for memory ecc inst…
10647 …ECC_PRTY_BB_K2 (0x1<<1) // Set parity only for memory…
10648 …FC_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_BB_K2_SHIFT 1
10652 …ED_0_MEM001_I_ECC_CORRECT_E5 (0x1<<1) // Record if a corr…
10653 …FC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_E5_SHIFT 1
10656 …ED_0_MEM002_I_ECC_CORRECT_BB_K2 (0x1<<1) // Record if a corr…
10657 …FC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_BB_K2_SHIFT 1
10662 … (0x1<<1) // EOP check error.
10663 …B_REG_INT_STS_EOP_ERROR_SHIFT 1
10679 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
10681 … (0x1<<1) // This bit masks, when set, the Interrupt …
10682 …B_REG_INT_MASK_EOP_ERROR_SHIFT 1
10683 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
10685 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
10687 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
10689 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
10691 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
10693 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
10695 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
10700 … (0x1<<1) // EOP check error.
10701 …B_REG_INT_STS_WR_EOP_ERROR_SHIFT 1
10719 … (0x1<<1) // EOP check error.
10720 …B_REG_INT_STS_CLR_EOP_ERROR_SHIFT 1
10736 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
10739 … (0x1<<0) // Indicates if to switch the CRC result byte ordering. 0=don't switch;1=switch.
10741 …R (0x1<<1) // Indicates if to …
10742 …B_REG_CONTROL_DB_IGNORE_ERROR_SHIFT 1
10751 … (0x1<<6) // Debug only: Disable PB.
10755 … (0x1<<11) // Dbug only.
10757 …ived on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
10759 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
10760 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
10761 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
10762 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
10763 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
10764 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
10765 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
10766 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
10767 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
10768 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
10769 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
10770 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
10781 …bit of this register. Bits 31:29 provide additional information about the instruction. Bit 31 in…
10783 …er being executed at the time EOP error is detected. The task passthrough bit is not kept and is …
10791 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
10792 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
10793 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
10794 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
10795 … 0x002000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the data…
10800 …5 (0xff<<0) // 8-bit value from package …
10802 … (0xff<<8) // 8-bit value from package …
10808 … (0x1<<0) // MAC Transmit Path Enable. Should be set to '1' to enable the MAC t…
10810 … (0x1<<1) // MAC Receive Path Enable. Should be set to…
10811 …TH_MAC_REG_COMMAND_CONFIG_RX_ENA_K2_E5_SHIFT 1
10816 … (0x1<<4) // Enable MAC Promiscuous Operation. If set to '1', all frames are rec…
10820 …1', the CRC field of received frames is forwarded with the frame to the user application. If set t…
10822 … (0x1<<7) // Terminate / Forward Pause Frames. If set to '1', pause frames are f…
10824 … (0x1<<8) // Ignore received Pause frame quanta. If set to '1', received pause fra…
10826 … (0x1<<9) // Set Source MAC Address on Transmit. If set to '1', the MAC overwrites…
10828 … (0x1<<10) // Enable PHY Interface loopback. If set to '1', the signal loop_ena is set to '1'. I…
10832 … (0x1<<12) // Self-Clearing Software Reset. When written with '…
10834 …ble Reception of all Control Frames. If set to '1', all control frames are accepted. If set to '0'…
10836 … (0x1<<14) // Enable Receive Errored Frame Discard. Use only with RX FIFO Store …
10840 … (0x1<<16) // Force Idle Generation. If set to '1', the MAC permanentl…
10846 … (0x1<<19) // Priority Flow Control Mode enable. If set to 1, the Core generates …
10848 … (0x1<<20) // Link Pause compatible with PFC mode. Pause is only indicated but does …
10860 …_K2_E5 (0x1<<26) // Self-Clearing TX FIFO rese…
10862 … faults and remote faults, respectively, on ingress direction. When set to '1', this feature is di…
10904 …FRAME_K2_E5 (0x1<<8) // enables (1) or disables (0) mul…
10909 …DIO_READ_ERROR_K2_E5 (0x1<<1) // MDIO read error.…
10910 …TH_MAC_REG_MDIO_CFG_STATUS_MDIO_READ_ERROR_K2_E5_SHIFT 1
10913 … (0x1<<5) // MDIO transaction preamble disable. Shortens transaction but is non-standard.
10915 … (0x1<<6) // MDIO transaction use Clause 45 format (1) or Clause 22 format…
10917 …DIO clock divisor; A value of 5 to 511. The frequency is reg_clk/(2*divisor+1). The reset default …
10924 … (0x1<<14) // If written with 1, a read with address post-increment will be perform…
10926 …E5 (0x1<<15) // If written with 1, a normal read trans…
10929 …-bit data word. When written- Initiates a write transaction to the PHY. The MDIO_COMMAND register …
10931 …PHY device to read from or write to. After writing this register, an address-write transaction wil…
10935 … (0x1<<0) // Local Fault Status. Set to '1' when the MAC detect…
10937 … (0x1<<1) // Remote Fault Status. Set to '1' wh…
10938 …TH_MAC_REG_STATUS_RX_REM_FAULT_K2_E5_SHIFT 1
10939 … (0x1<<2) // PHY indicates loss-of-signal. Represents v…
10941 … is available in the register TS_TIMESTAMP. To clear TS_AVAIL, the bit must be written with a '1'.
10959 … (0x1<<0) // Credit-based FIFO only: When written with a 1, …
10962 … (0xff<<0) // Credit-based FIFO only: Specifies th…
10965 … (0xff<<0) // Current credit register value (for debug purpose only).
10967 … 0x000054UL //Access:RW DataWidth:0x20 // Class 0 and 1 pause quanta. When l…
10970 …C quanta value for that class when a class XOFF is triggered. Each Quanta specifies a 512 bit-time.
10987 … 0x000064UL //Access:RW DataWidth:0x20 // Class 0 and 1 refresh threshold. W…
11008 … (0xff<<0) // Status bit for software to read the current received pause sta…
11012 … (0x1<<0) // Enable XGMII-64 (4byte alignment)
11016 … (0x1<<5) // Enable 1-step capable datapath…
11019 … (0x1<<0) // Configure saturation behavior. When set to 1, the counters saturate at all-1. Oth…
11021 … (0x1<<1) // Configure clear-on-read behavior. When set…
11022 …TH_MAC_REG_STATN_CONFIG_CLEAR_ON_READ_K2_E5_SHIFT 1
11023 … (0x1<<2) // Clear all counters command (self-clearing). When written with 1 all c…
11025 …W DataWidth:0x20 // Lower 32bit of 64bit value written into statistics memory when a counter i…
11026 …W DataWidth:0x20 // Upper 32bit of 64bit value written into statistics memory when a counter i…
11124 … 0x000384UL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11126 … 0x00038cUL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11128 … 0x000394UL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11130 … 0x00039cUL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11132 … 0x0003a4UL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11134 … 0x0003acUL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11136 … 0x0003b4UL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11138 … 0x0003bcUL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11140 … 0x0003c4UL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11142 … 0x0003ccUL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11144 … 0x0003d4UL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11146 … 0x0003dcUL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11148 … 0x0003e4UL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11150 … 0x0003ecUL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11152 … 0x0003f4UL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11154 … 0x0003fcUL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11156 …ECTION_K2_E5 (0x1<<0) // When 1, bypass the decoder'…
11158 …_ERROR_INDICATION_K2_E5 (0x1<<1) // When 1, configure the …
11159 …TH_RSFEC_REG_RS_FEC_CONTROL_BYPASS_ERROR_INDICATION_K2_E5_SHIFT 1
11163 …YPASS_INDICATION_K2_E5 (0x1<<1) // Indicates the ab…
11164 …TH_RSFEC_REG_RS_FEC_STATUS_BYPASS_INDICATION_K2_E5_SHIFT 1
11167 … (0xf<<8) // RS-FEC receive lane locked and aligned; One bit per lane: Bit 8 = lane 0, Bit…
11169 … (0x1<<14) // Indicates, when 1 that the RS-FEC receiver ha…
11171 …TATUS_PCS_ALIGN_STATUS_K2_E5 (0x1<<15) // Always 1.
11173 …x20 // Counts number of corrected FEC codewords lower 16-bits; None roll-over when upper 16-bits…
11174 …umber of corrected FEC codewords lower 16-bits; Must be read before upper 16-bits; None roll-over …
11176 …h:0x20 // Counts number of corrected FEC codewords upper 16-bits; Clears on read; None roll-over.
11177 … (0xffff<<0) // Counts number of corrected FEC codewords upper 16-bits; None roll-over; Clears …
11179 …0 // Counts number of uncorrected FEC codewords lower 16-bits; None roll-over when upper 16-bits…
11180 …ber of uncorrected FEC codewords lower 16-bits; Must be read before upper 16-bits; None roll-over …
11182 …0x20 // Counts number of uncorrected FEC codewords upper 16-bits; Clears on read; None roll-over.
11183 … (0xffff<<0) // Counts number of uncorrected FEC codewords upper 16-bits; None roll-over; Clears …
11188 …_E5 (0x3<<2) // FEC lane mapped to PMA lane 1.
11194 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 0; None roll-over whe…
11195 … (corrected) 10-bit symbol errors found in lane 0 for correctable codewords only; Lower 16-bit of …
11197 …L //Access:R DataWidth:0x20 // Upper 16-bit of counter (with above register); Clears on read;…
11198 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 0; Clears o…
11200 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 1; None roll-over whe…
11201 … (corrected) 10-bit symbol errors found in lane 1 for correctable codewords only; Lower 16-bit of …
11203 …L //Access:R DataWidth:0x20 // Upper 16-bit of counter (with above register); Clears on read;…
11204 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 1; Clears o…
11206 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 2; None roll-over whe…
11207 … (corrected) 10-bit symbol errors found in lane 2 for correctable codewords only; Lower 16-bit of …
11209 …L //Access:R DataWidth:0x20 // Upper 16-bit of counter (with above register); Clears on read;…
11210 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 2; Clears o…
11212 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 3; None roll-over whe…
11213 … (corrected) 10-bit symbol errors found in lane 3 for correctable codewords only; Lower 16-bit of …
11215 … //Access:R DataWidth:0x20 // Upper 16 bit of counter (with above register); Clears on read; …
11216 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 3; Clears o…
11218 … 0x000200UL //Access:RW DataWidth:0x20 // Additional control to enable RS-FEC operation.
11219 …EC_ENABLE_K2_E5 (0x1<<2) // When 1, enable RSFEC datapa…
11221 …1<<15) // Indicates the operatyional outcome of the (above) enable bit control; When 1 = FEC enabl…
11224 … (0xf<<0) // Per PMA lane FEC synchronization status; Bit 0=lane 0 up to Bit 3 = lane 3…
11240 … (0xf<<12) // Real-time indication from FEC deskew FIFO per lane; bit 12 = l…
11243 … // Per PMA lane FEC synchronization status; Realtime updates; Bit 0 = lane 0 upto bit 3 = lane …
11248 …W DataWidth:0x20 // Bits 7:0; Must be written with the 8-bit value of 0x57 to enable RS-FEC tr…
11249 … (0xff<<0) // Bits 7:0; Must be written with 8-bit value 0x57 to enable RS-FEC tra…
11251 … 0x000214UL //Access:RW DataWidth:0x20 // Bits 15:0. One bit per 10-bit Symbol; Each bit is ap…
11252 … (0xffff<<0) // Bits 15:0. One bit per 10-bit Symbol; When a bit is 1 th…
11254 … 0x000218UL //Access:RW DataWidth:0x20 // Bits 9:0; A 10-bit value which XORed w…
11255 …TEST_PATTERN_K2_E5 (0x3ff<<0) // A 10-bit value which will be…
11257 …VERWRITE_K2_E5 (0x1<<10) // If the bit is set the 10B symb…
11259 …x20 // Enable register to control the triggers with the error insertion; Bit 0 clears on operati…
11260 … (0x1<<0) // For bit 0 only, when written with 1 triggers the error insertion (on one wo…
11263 … (0x1<<6) // Speed Selection Indication; always 1
11265 … (0x1<<8) // Indicate full-duplex operation; always 1
11269 … (0x1<<10) // Set PCS isolate mode; Controls toplevel pin only, no internal functi…
11279 … (0x1<<15) // PCS soft-reset command; self-clearing
11282 … (0x1<<0) // Indicate extended register support; always 1
11284 … (0x1<<2) // Indicate link status; latch-low
11286 … (0x1<<3) // Autonegotiation ability; always 1
11296 …x20 // Local Device Abilities for Autonegotiation. Contents differs for 1000Base-X or SGMII mode.
11297 … (0x1f<<0) // reserved; SGMII:=set to 1 to indicate SGMII to…
11299 … (0x1<<5) // Indicate full-duplex support; SGMII…
11301 … (0x1<<6) // Indicate half-duplex support; SGMII…
11303 … (0x1<<7) // Pause Support 1; SGMII:=reserved
11309 … (0x1<<12) // Remote fault 1; SGMII:=reserved
11317 …/ Received Abilities during Autonegotiation. Contents differ depending on 1000Base-X or SGMII mode.
11318 …ABILITY_RSV05_K2_E5 (0x1f<<0) // reserved; SGMII:=1
11320 … (0x1<<5) // Indicate full-duplex support; SGMII…
11322 … (0x1<<6) // Indicate half-duplex support; SGMII…
11324 … (0x1<<7) // Pause Support 1; SGMII:=reserved
11332 … (0x1<<12) // Remote fault 1; SGMII:=Copper Duple…
11341 … (0x1<<1) // Autoneg page received indication; latch…
11342 …TH_PCS1G_REG_AN_EXPANSION_PAGERECEIVED_K2_E5_SHIFT 1
11348 … (0x1<<11) // Next Page toggle handshaking bit
11361 … (0x1<<11) // Next Page toggle handshaking bit
11378 …_E5 (0x1<<0) // Bit 0 of link timer val…
11380 …_E5 (0x7fff<<1) // Bits 15:1 of link timer…
11381 …TH_PCS1G_REG_LINK_TIMER_0_TIMER15_1_K2_E5_SHIFT 1
11383 … (0x1f<<0) // Link timer uppest 5 bits of 21bit timer
11388 …II_AN_K2_E5 (0x1<<1) // Use the SGMII au…
11389 …TH_PCS1G_REG_IF_MODE_USE_SGMII_AN_K2_E5_SHIFT 1
11392 … (0x1<<4) // Set SGMII half-duplex mode when not …
11397 …er is not accurate and intended only to be of help during test/debug; Clears when writing CONTROL.…
11402 …TROL1_SPEED_ALWAYS1_K2_E5 (0x1<<6) // Always 1.
11406 …ROL1_SPEED_SELECT_ALWAYS1_K2_E5 (0x1<<13) // Always 1.
11408 …K2_E5 (0x1<<14) // 1=Enable loopback, 0=d…
11410 …E5 (0x1<<15) // 1=PCS reset, 0=normal;…
11413 …ABILITY_K2_E5 (0x1<<1) // Set to 1 to indicate th…
11414 …TH_PCS10_50G_REG_STATUS1_LOW_POWER_ABILITY_K2_E5_SHIFT 1
11415 …NK_K2_E5 (0x1<<2) // When 1, indicates PCS recei…
11417 … (0x1<<7) // When 1, indicates a fault c…
11419 …TIVE_K2_E5 (0x1<<8) // 1: receive is currentl…
11421 …TIVE_K2_E5 (0x1<<9) // 1: transmit is current…
11423 …E5 (0x1<<10) // 1: receive is or was i…
11425 …E5 (0x1<<11) // 1: transmit is or was …
11433 … DataWidth:0x20 // PCS supported speeds (values as defined by standard only, no proprietary spe…
11434 …K2_E5 (0x1<<0) // When 1, this PCS is 10Geth …
11436 … (0x1<<1) // When 1, this PCS is 10PASS-TS/2Base-T…
11437 …TH_PCS10_50G_REG_SPEED_ABILITY_C10PASS_TS_K2_E5_SHIFT 1
11438 …E5 (0x1<<2) // When 1, this PCS is 40G cap…
11440 …_E5 (0x1<<3) // When 1, this PCS is 100G ca…
11443 …5 (0x1<<0) // Clause 22 registers present when 1.
11445 …MD_PMA_K2_E5 (0x1<<1) // PMD/PMA present when 1.
11446 …TH_PCS10_50G_REG_DEVICES_IN_PKG1_PMD_PMA_K2_E5_SHIFT 1
11447 …G1_WIS_PRES_K2_E5 (0x1<<2) // WIS present when 1.
11449 …G1_PCS_PRES_K2_E5 (0x1<<3) // PCS present when 1.
11451 …PHY_XS_K2_E5 (0x1<<4) // PHY XS present when 1.
11453 …DTE_XS_K2_E5 (0x1<<5) // DTE XS present when 1.
11455 …KG1_TC_PRES_K2_E5 (0x1<<6) // TC present when 1.
11460 …E5 (0x1<<14) // Vendor specific device 1 present
11468 … (0x1<<0) // When 1, this PCS is 10GBase-R capable.
11470 … (0x1<<1) // When 1, this PCS is 10GBase-X cap…
11471 …TH_PCS10_50G_REG_STATUS2_C10GBASE_X_K2_E5_SHIFT 1
11472 … (0x1<<2) // When 1, this PCS is 10GBase-W capable.
11474 … (0x1<<3) // When 1, this PCS is 10GBase-T capable.
11476 … (0x1<<4) // When 1, this PCS is 40GBase-R capable.
11478 … (0x1<<5) // When 1, this PCS is 100GBase-R capable.
11480 … (0x1<<10) // Receive fault. 1=Fault condition on r…
11482 … (0x1<<11) // Transmit fault. 1=Fault condition on t…
11492 …UL //Access:RW DataWidth:0x20 // EEE Control and Capabilities (exists only if EEE is available…
11493 … (0x1<<0) // Mode for selecting select 40G EEE mode; 1 = Fast wake mode; 0 …
11495 …_K2_E5 (0x1<<6) // When 1, EEE is supported for 10GBASE-KR.
11497 …5 (0x1<<8) // When 1, EEE fast wake is supported for 40GBASE-R.
11499 …5 (0x1<<9) // When 1, EEE deep sleep is supported for 40GBASE-…
11501 …000058UL //Access:R DataWidth:0x20 // EEE Wake error counter (exists only if EEE is available…
11502 … Increments each time the LPI enters the RX_WTF state indicating a wake time fault; None roll-over.
11505 …CK_LOCK_K2_E5 (0x1<<0) // 1=PCS locked to receiv…
11507 …HIGH_BER_K2_E5 (0x1<<1) // 1=PCS reporting a h…
11508 …TH_PCS10_50G_REG_BASER_STATUS1_HIGH_BER_K2_E5_SHIFT 1
11509 … (0x1<<12) // Receive link status. 1=Link up; 0=link down.
11512 … (0xff<<0) // Errored blocks counter; None roll-over.
11514 …ER_K2_E5 (0x3f<<8) // BER counter; None roll-over.
11520 … 0x000088UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11521 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11523 … 0x00008cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11524 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11526 … 0x000090UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11527 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11529 … 0x000094UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11530 … (0x3ff<<0) // 10GBase-R Test Pattern Seed A…
11532 … 0x000098UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11533 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11535 … 0x00009cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11536 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11538 … 0x0000a0UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11539 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11541 … 0x0000a4UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11542 … (0x3ff<<0) // 10GBase-R Test Pattern Seed B…
11545 … (0x1<<0) // Data Pattern Select: 1=all Zero, 0=2x Local Fault; 10G only.
11547 … (0x1<<1) // Select Square Wave (1) or Pseudo Random (0) test pat…
11548 …TH_PCS10_50G_REG_BASER_TEST_CONTROL_SELECT_SQUARE_K2_E5_SHIFT 1
11549 …TESTPATTERN_K2_E5 (0x1<<2) // Receive test-pattern enable.
11551 …ESTPATTERN_K2_E5 (0x1<<3) // Transmit test-pattern enable.
11553 … (0x1<<7) // Select Random Idle test pattern (40G); Overrides bits 1:0 when set.
11555 …0acUL //Access:R DataWidth:0x20 // Test Pattern Error Counter; Clears on read; None roll-over.
11556 … (0xffff<<0) // Test pattern error counter; Clears on read; None roll-over.
11558 …0000b0UL //Access:R DataWidth:0x20 // BER High Order Counter of BER bits 21:6; None roll-over.
11559 … (0xffff<<0) // Bits 21:6 of BER counter; None roll-over.
11561 …00b4UL //Access:R DataWidth:0x20 // Error Blocks High Order Counter bits 21:8; None roll-over.
11562 …2_E5 (0x3fff<<0) // Bits 21:8 of Error Blocks counter; None roll-over.
11564 …R_PRESENT_K2_E5 (0x1<<15) // High order counter present; Always 1.
11569 …IGN_STAT1_LANE1_BLOCK_LOCK_K2_E5 (0x1<<1) // Lane 1 block lock.
11570 …TH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE1_BLOCK_LOCK_K2_E5_SHIFT 1
11575 …2_E5 (0x1<<12) // Lane alignment status; 1=All Receive lanes lo…
11580 …TAT3_LANE1_MARKER_LOCK_K2_E5 (0x1<<1) // Lane 1 alignment marke…
11581 …TH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE1_MARKER_LOCK_K2_E5_SHIFT 1
11586 …00320UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 0; Clears on read; None roll-over.
11587 …_E5 (0xffff<<0) // BIP error counter lane 0; None roll-over.
11589 …00324UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 1; Clears on read; None roll-over.
11590 …_E5 (0xffff<<0) // BIP error counter lane 1; None roll-over.
11592 …00328UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 2; Clears on read; None roll-over.
11593 …_E5 (0xffff<<0) // BIP error counter lane 2; None roll-over.
11595 …0032cUL //Access:R DataWidth:0x20 // BIP Error Counter Lane 3; Clears on read; None roll-over.
11596 …_E5 (0xffff<<0) // BIP error counter lane 3; None roll-over.
11598 … 0x000640UL //Access:R DataWidth:0x20 // Lane Channel 0 mapping bits 1:0.
11599 …_MAPPING_K2_E5 (0x3<<0) // Lane 0 mapping bits 1:0.
11601 … 0x000644UL //Access:R DataWidth:0x20 // Lane Channel 1 mapping bits 1:0.
11602 …_MAPPING_K2_E5 (0x3<<0) // Lane 1 mapping bits 1:0.
11604 … 0x000648UL //Access:R DataWidth:0x20 // Lane Channel 2 mapping bits 1:0.
11605 …_MAPPING_K2_E5 (0x3<<0) // Lane 2 mapping bits 1:0.
11607 … 0x00064cUL //Access:R DataWidth:0x20 // Lane Channel 3 mapping bits 1:0.
11608 …_MAPPING_K2_E5 (0x3<<0) // Lane 3 mapping bits 1:0.
11616 …x20 // Vendor Specific Reg; Set the amount of data between markers. (I.e. distance of markers-1).
11617 … (0xffff<<0) // A 16-bit value defining the amount of data between markers; (dist…
11620 …HRESHOLD_K2_E5 (0xf<<0) // A 4-bit value to define the…
11622 …0010UL //Access:RW DataWidth:0x20 // Vendor Specific Reg; Define Reduced-XLAUI PMA mode using …
11623 …_K2_E5 (0x1<<0) // Enable Reduced-XLAUI PMA mode using …
11625 …UI_CONFIG_RESERVED_WRITEABLE_BITS_K2_E5 (0x7<<1) // These bits are w…
11626 …TH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_RESERVED_WRITEABLE_BITS_K2_E5_SHIFT 1
11629 …E5 (0xf<<8) // Set VL (0..3) to transmit to RXLAUI lane 1.
11641 …028UL //Access:RW DataWidth:0x20 // Vendor Specific Reg; Marker pattern for PCS Virtual Lane 1.
11642 … (0xff<<0) // Lane 1 Marker pattern for m…
11644 … (0xff<<8) // Lane 1 Marker pattern for m…
11646 …ccess:RW DataWidth:0x20 // Vendor Specific Reg; Last byte of PCS Virtual Lane 1 marker pattern.
11647 … (0xff<<0) // Lane 1 last btye of Marker …
11666 … (0x1<<0) // When 0 PCS uses Clause 82 encoder/decoder functions; When 1 PCS uses Clause 49 e…
11668 … (0x1<<1) // When 0 PCS 4-lane MLD function is active; W…
11669 …TH_PCS10_50G_REG_VENDOR_PCS_MODE_DISABLE_MLD_K2_E5_SHIFT 1
11677 …TROL1_SPEED_ALWAYS1_K2_E5 (0x1<<6) // Always 1.
11681 …ROL1_SPEED_SELECT_ALWAYS1_K2_E5 (0x1<<13) // Always 1.
11683 …K2_E5 (0x1<<14) // 1=Enable loopback, 0=d…
11685 …E5 (0x1<<15) // 1=PCS reset, 0=normal;…
11688 …ABILITY_K2_E5 (0x1<<1) // Set to 1 to indicate th…
11689 …TH_PCS10_25G_REG_STATUS1_LOW_POWER_ABILITY_K2_E5_SHIFT 1
11690 …NK_K2_E5 (0x1<<2) // When 1, indicates PCS recei…
11692 … (0x1<<7) // When 1, indicates a fault c…
11694 …TIVE_K2_E5 (0x1<<8) // 1: receive is currentl…
11696 …TIVE_K2_E5 (0x1<<9) // 1: transmit is current…
11698 …E5 (0x1<<10) // 1: receive is or was i…
11700 …E5 (0x1<<11) // 1: transmit is or was …
11708 … DataWidth:0x20 // PCS supported speeds (values as defined by standard only, no proprietary spe…
11709 …K2_E5 (0x1<<0) // When 1, this PCS is 10Geth …
11711 … (0x1<<1) // When 1, this PCS is 10PASS-TS/2Base-T…
11712 …TH_PCS10_25G_REG_SPEED_ABILITY_C10PASS_TS_K2_E5_SHIFT 1
11713 …E5 (0x1<<2) // When 1, this PCS is 40G cap…
11715 …_E5 (0x1<<3) // When 1, this PCS is 100G ca…
11718 …5 (0x1<<0) // Clause 22 registers present when 1.
11720 …MD_PMA_K2_E5 (0x1<<1) // PMD/PMA present when 1.
11721 …TH_PCS10_25G_REG_DEVICES_IN_PKG1_PMD_PMA_K2_E5_SHIFT 1
11722 …G1_WIS_PRES_K2_E5 (0x1<<2) // WIS present when 1.
11724 …G1_PCS_PRES_K2_E5 (0x1<<3) // PCS present when 1.
11726 …PHY_XS_K2_E5 (0x1<<4) // PHY XS present when 1.
11728 …DTE_XS_K2_E5 (0x1<<5) // DTE XS present when 1.
11730 …KG1_TC_PRES_K2_E5 (0x1<<6) // TC present when 1.
11735 …E5 (0x1<<14) // Vendor specific device 1 present
11743 … (0x1<<0) // When 1, this PCS is 10GBase-R capable.
11745 … (0x1<<1) // When 1, this PCS is 10GBase-X cap…
11746 …TH_PCS10_25G_REG_STATUS2_C10GBASE_X_K2_E5_SHIFT 1
11747 … (0x1<<2) // When 1, this PCS is 10GBase-W capable.
11749 … (0x1<<3) // When 1, this PCS is 10GBase-T capable.
11751 … (0x1<<4) // When 1, this PCS is 40GBase-R capable.
11753 … (0x1<<5) // When 1, this PCS is 100GBase-R capable.
11755 … (0x1<<10) // Receive fault. 1=Fault condition on r…
11757 … (0x1<<11) // Transmit fault. 1=Fault condition on t…
11767 …UL //Access:RW DataWidth:0x20 // EEE Control and Capabilities (exists only if EEE is available…
11768 … (0x1<<0) // Mode for selecting select 40G EEE mode; 1 = Fast wake mode; 0 …
11770 …_K2_E5 (0x1<<6) // When 1, EEE is supported for 10GBASE-KR.
11772 …5 (0x1<<8) // When 1, EEE fast wake is supported for 40GBASE-R.
11774 …5 (0x1<<9) // When 1, EEE deep sleep is supported for 40GBASE-…
11776 …000058UL //Access:R DataWidth:0x20 // EEE Wake error counter (exists only if EEE is available…
11777 … Increments each time the LPI enters the RX_WTF state indicating a wake time fault; None roll-over.
11780 …CK_LOCK_K2_E5 (0x1<<0) // 1=PCS locked to receiv…
11782 …HIGH_BER_K2_E5 (0x1<<1) // 1=PCS reporting a h…
11783 …TH_PCS10_25G_REG_BASER_STATUS1_HIGH_BER_K2_E5_SHIFT 1
11784 … (0x1<<12) // Receive link status. 1=Link up; 0=link down.
11787 … (0xff<<0) // Errored blocks counter; None roll-over.
11789 …ER_K2_E5 (0x3f<<8) // BER counter; None roll-over.
11795 … 0x000088UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11796 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11798 … 0x00008cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11799 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11801 … 0x000090UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11802 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11804 … 0x000094UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11805 … (0x3ff<<0) // 10GBase-R Test Pattern Seed A…
11807 … 0x000098UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11808 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11810 … 0x00009cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11811 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11813 … 0x0000a0UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11814 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11816 … 0x0000a4UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11817 … (0x3ff<<0) // 10GBase-R Test Pattern Seed B…
11820 … (0x1<<0) // Data Pattern Select: 1=all Zero, 0=2x Local Fault; 10G only.
11822 … (0x1<<1) // Select Square Wave (1) or Pseudo Random (0) test pat…
11823 …TH_PCS10_25G_REG_BASER_TEST_CONTROL_SELECT_SQUARE_K2_E5_SHIFT 1
11824 …TESTPATTERN_K2_E5 (0x1<<2) // Receive test-pattern enable.
11826 …ESTPATTERN_K2_E5 (0x1<<3) // Transmit test-pattern enable.
11828 … (0x1<<7) // Select Random Idle test pattern (40G); Overrides bits 1:0 when set.
11830 …0acUL //Access:R DataWidth:0x20 // Test Pattern Error Counter; Clears on read; None roll-over.
11831 … (0xffff<<0) // Test pattern error counter; Clears on read; None roll-over.
11833 …0000b0UL //Access:R DataWidth:0x20 // BER High Order Counter of BER bits 21:6; None roll-over.
11834 … (0xffff<<0) // Bits 21:6 of BER counter; None roll-over.
11836 …00b4UL //Access:R DataWidth:0x20 // Error Blocks High Order Counter bits 21:8; None roll-over.
11837 …2_E5 (0x3fff<<0) // Bits 21:8 of Error Blocks counter; None roll-over.
11839 …R_PRESENT_K2_E5 (0x1<<15) // High order counter present; Always 1.
11842 …2_E5 (0x1<<12) // Lane alignment status; 1=All Receive lanes lo…
11847 …TAT3_LANE1_MARKER_LOCK_K2_E5 (0x1<<1) // Lane 1 alignment marke…
11848 …TH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE1_MARKER_LOCK_K2_E5_SHIFT 1
11853 …00320UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 0; Clears on read; None roll-over.
11854 …_E5 (0xffff<<0) // BIP error counter lane 0; None roll-over.
11856 …00324UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 1; Clears on read; None roll-over.
11857 …_E5 (0xffff<<0) // BIP error counter lane 1; None roll-over.
11859 …00328UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 2; Clears on read; None roll-over.
11860 …_E5 (0xffff<<0) // BIP error counter lane 2; None roll-over.
11862 …0032cUL //Access:R DataWidth:0x20 // BIP Error Counter Lane 3; Clears on read; None roll-over.
11863 …_E5 (0xffff<<0) // BIP error counter lane 3; None roll-over.
11871 …x20 // Vendor Specific Reg; Set the amount of data between markers. (I.e. distance of markers-1).
11872 … (0xffff<<0) // A 16-bit value defining the amount of data between markers; (dist…
11875 …HRESHOLD_K2_E5 (0xf<<0) // A 4-bit value to define the…
11885 …028UL //Access:RW DataWidth:0x20 // Vendor Specific Reg; Marker pattern for PCS Virtual Lane 1.
11886 … (0xff<<0) // Lane 1 Marker pattern for m…
11888 … (0xff<<8) // Lane 1 Marker pattern for m…
11890 …ccess:RW DataWidth:0x20 // Vendor Specific Reg; Last byte of PCS Virtual Lane 1 marker pattern.
11891 … (0xff<<0) // Lane 1 last btye of Marker …
11910 … (0x1<<0) // When 0 PCS uses Clause 82 encoder/decoder functions; When 1 PCS uses Clause 49 e…
11912 … (0x1<<1) // When 0 PCS 4-lane MLD function is active; W…
11913 …TH_PCS10_25G_REG_VENDOR_PCS_MODE_DISABLE_MLD_K2_E5_SHIFT 1
11952 …OP_RESERVEDREGISTER9_RESERVEDFIELD13_K2_E5 (0x1<<1) // Reserved
11953 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER9_RESERVEDFIELD13_K2_E5_SHIFT 1
11962 …- off high-impedance 0x1 - CMU 0 0x3 - Lane 0 0x4 - Lane 1 0x5 - Lane 2 0x6 - Lane 3 0x15 - SoC ci…
11970 …OP_RESERVEDREGISTER11_RESERVEDFIELD18_K2_E5 (0x1<<1) // Reserved
11971 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER11_RESERVEDFIELD18_K2_E5_SHIFT 1
11979 …OP_RESERVEDREGISTER12_RESERVEDFIELD22_K2_E5 (0x1<<1) // Reserved
11980 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER12_RESERVEDFIELD22_K2_E5_SHIFT 1
11988 …OP_RESERVEDREGISTER13_RESERVEDFIELD26_K2_E5 (0x1<<1) // Reserved
11989 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD26_K2_E5_SHIFT 1
12003 …OP_RESERVEDREGISTER14_RESERVEDFIELD33_K2_E5 (0x1<<1) // Reserved
12004 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD33_K2_E5_SHIFT 1
12018 …OP_RESERVEDREGISTER15_RESERVEDFIELD40_K2_E5 (0x1<<1) // Reserved
12019 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD40_K2_E5_SHIFT 1
12033 …OP_RESERVEDREGISTER16_RESERVEDFIELD47_K2_E5 (0x1<<1) // Reserved
12034 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD47_K2_E5_SHIFT 1
12048 …OP_RESERVEDREGISTER17_RESERVEDFIELD54_K2_E5 (0x1<<1) // Reserved
12049 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER17_RESERVEDFIELD54_K2_E5_SHIFT 1
12077 …OP_RESERVEDREGISTER22_RESERVEDFIELD66_K2_E5 (0x1<<1) // Reserved
12078 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER22_RESERVEDFIELD66_K2_E5_SHIFT 1
12084 …OP_RESERVEDREGISTER23_RESERVEDFIELD69_K2_E5 (0x3<<1) // Reserved
12085 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER23_RESERVEDFIELD69_K2_E5_SHIFT 1
12093 …OP_RESERVEDREGISTER24_RESERVEDFIELD73_K2_E5 (0x1<<1) // Reserved
12094 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER24_RESERVEDFIELD73_K2_E5_SHIFT 1
12105 …OP_RESERVEDREGISTER25_RESERVEDFIELD77_K2_E5 (0x1<<1) // Reserved
12106 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER25_RESERVEDFIELD77_K2_E5_SHIFT 1
12117 …OP_RESERVEDREGISTER26_RESERVEDFIELD81_K2_E5 (0x1<<1) // Reserved
12118 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER26_RESERVEDFIELD81_K2_E5_SHIFT 1
12124 …OP_RESERVEDREGISTER27_RESERVEDFIELD84_K2_E5 (0x3<<1) // Reserved
12125 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER27_RESERVEDFIELD84_K2_E5_SHIFT 1
12133 …OP_RESERVEDREGISTER28_RESERVEDFIELD88_K2_E5 (0x1<<1) // Reserved
12134 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER28_RESERVEDFIELD88_K2_E5_SHIFT 1
12145 …OP_RESERVEDREGISTER29_RESERVEDFIELD92_K2_E5 (0x1<<1) // Reserved
12146 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER29_RESERVEDFIELD92_K2_E5_SHIFT 1
12157 …OP_RESERVEDREGISTER30_RESERVEDFIELD96_K2_E5 (0x1<<1) // Reserved
12158 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER30_RESERVEDFIELD96_K2_E5_SHIFT 1
12169 …OP_RESERVEDREGISTER31_RESERVEDFIELD100_K2_E5 (0x1<<1) // Reserved
12170 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER31_RESERVEDFIELD100_K2_E5_SHIFT 1
12190 …OP_RESERVEDREGISTER32_RESERVEDFIELD106_K2_E5 (0x1<<1) // Reserved
12191 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER32_RESERVEDFIELD106_K2_E5_SHIFT 1
12208 …OP_RESERVEDREGISTER33_RESERVEDFIELD112_K2_E5 (0x1<<1) // Reserved
12209 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER33_RESERVEDFIELD112_K2_E5_SHIFT 1
12232 …OP_RESERVEDREGISTER36_RESERVEDFIELD120_K2_E5 (0x1<<1) // Reserved
12233 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER36_RESERVEDFIELD120_K2_E5_SHIFT 1
12250 …OP_RESERVEDREGISTER37_RESERVEDFIELD126_K2_E5 (0x1<<1) // Reserved
12251 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER37_RESERVEDFIELD126_K2_E5_SHIFT 1
12274 …OP_RESERVEDREGISTER40_RESERVEDFIELD134_K2_E5 (0x1<<1) // Reserved
12275 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER40_RESERVEDFIELD134_K2_E5_SHIFT 1
12292 …OP_RESERVEDREGISTER41_RESERVEDFIELD140_K2_E5 (0x1<<1) // Reserved
12293 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER41_RESERVEDFIELD140_K2_E5_SHIFT 1
12316 …OP_RESERVEDREGISTER44_RESERVEDFIELD148_K2_E5 (0x1<<1) // Reserved
12317 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER44_RESERVEDFIELD148_K2_E5_SHIFT 1
12334 …OP_RESERVEDREGISTER45_RESERVEDFIELD154_K2_E5 (0x1<<1) // Reserved
12335 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER45_RESERVEDFIELD154_K2_E5_SHIFT 1
12349 …OP_RESERVEDREGISTER48_RESERVEDFIELD160_K2_E5 (0x1<<1) // Reserved
12350 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER48_RESERVEDFIELD160_K2_E5_SHIFT 1
12358 …OP_RESERVEDREGISTER49_RESERVEDFIELD164_K2_E5 (0x1<<1) // Reserved
12359 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER49_RESERVEDFIELD164_K2_E5_SHIFT 1
12362 … (0x1<<0) // PHY error status. 0x0 - no error 0x1 - PHY has an in…
12364 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit PHY error code. 0x0 - indicates that there i…
12365 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit PHY error code. 0x0 - indicates that there i…
12367 …5 (0x1<<0) // Rebug error status. Write 1 to clear.
12373 …_TYPE_K2_E5 (0x3<<0) // Type of error: 1 = err ack 2 = timeout
12375 … (0x1<<2) // Errored register transfer type: 0 = read transfer 1 = write transfer
12382 … 0x000630UL //Access:R DataWidth:0x8 // Errored register transfer write data bit enable
12383 … 0x000680UL //Access:RW DataWidth:0x8 // lower 8-bits of the 16-bit digital tes…
12384 … 0x000684UL //Access:RW DataWidth:0x8 // higher 8-bits of the 16-bit digital tes…
12393 … (0x1<<0) // Set if running a 1b simulation. Firmwa…
12398 …L_CRC_DISABLE_K2_E5 (0x1<<1) // Prevents firmwar…
12399 …HY_NW_IP_REG_PHY0_TOP_FW_CTRL_CRC_DISABLE_K2_E5_SHIFT 1
12400 …RW DataWidth:0x8 // Command to the PHY firmware. It is expected that only the APB master writ…
12402 …matically when CMD is written. It is expected to be cleared by the PHY firmware by writing 1 to it.
12405 … 0x000810UL //Access:RW DataWidth:0x8 // Command auxiliary data or argument 1
12412 …W DataWidth:0x8 // Response to the PHY firmware. It is expected that only the APB master writ…
12414 …matically when RSP is written. It is expected to be cleared by the PHY firmware by writing 1 to it.
12417 … 0x000850UL //Access:RW DataWidth:0x8 // Response auxiliary data or argument 1
14319 …0_TOP_RESERVEDREGISTER686_RESERVEDFIELD171_K2_E5 (0x1<<1) // Reserved
14320 …HY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD171_K2_E5_SHIFT 1
14334 …0_TOP_RESERVEDREGISTER687_RESERVEDFIELD178_K2_E5 (0x1<<1) // Reserved
14335 …HY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER687_RESERVEDFIELD178_K2_E5_SHIFT 1
14341 …0_TOP_RESERVEDREGISTER688_RESERVEDFIELD181_K2_E5 (0x1<<1) // Reserved
14342 …HY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER688_RESERVEDFIELD181_K2_E5_SHIFT 1
14356 …0_TOP_RESERVEDREGISTER691_RESERVEDFIELD187_K2_E5 (0x1<<1) // Reserved
14357 …HY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER691_RESERVEDFIELD187_K2_E5_SHIFT 1
14374 …0_TOP_RESERVEDREGISTER695_RESERVEDFIELD194_K2_E5 (0x7<<1) // Reserved
14375 …HY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER695_RESERVEDFIELD194_K2_E5_SHIFT 1
14394 …0_TOP_AFE_CMCP_CTRL0_RESERVEDFIELD202_K2_E5 (0x1<<1) // Reserved
14395 …HY_NW_IP_REG_CMU_LC0_TOP_AFE_CMCP_CTRL0_RESERVEDFIELD202_K2_E5_SHIFT 1
14398 …used in gearbox applications. 0x0 - DIV4 0x1 - DIV8 0x2 - DIV16 0x3 - DIV20 0x4 - DIV32 0x5 - DIV…
14426 …0_TOP_RESERVEDREGISTER704_RESERVEDFIELD215_K2_E5 (0x1<<1) // Reserved
14427 …HY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER704_RESERVEDFIELD215_K2_E5_SHIFT 1
14429 …to the half-rate TX clock path to provide visibility at the TX driver output. 0x0 - mission mode …
14431 …CMU macro to all lanes macros. 0x0 - DIV1 0x1 - DIV2 0x2 - DIV4 0x3 - DIV5 0x4 - DIV8 0x5 - DIV10…
14473 … (0x1<<0) // CMU OK status. 0x0 - CMU PLL is not locked 0x1 - indica…
14477 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14478 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14480 … (0x1<<0) // CMU macro error status. 0x0 - no error 0x1 - PHY CMU macro…
14485 …0_TOP_RESERVEDREGISTER714_RESERVEDFIELD233_K2_E5 (0x1<<1) // Reserved
14486 …HY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER714_RESERVEDFIELD233_K2_E5_SHIFT 1
14493 …0_TOP_RESERVEDREGISTER716_RESERVEDFIELD236_K2_E5 (0x3<<1) // Reserved
14494 …HY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER716_RESERVEDFIELD236_K2_E5_SHIFT 1
14500 …0_PLL_RESERVEDREGISTER717_RESERVEDFIELD239_K2_E5 (0x1<<1) // Reserved
14501 …HY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER717_RESERVEDFIELD239_K2_E5_SHIFT 1
14505 …0_PLL_RESERVEDREGISTER718_RESERVEDFIELD241_K2_E5 (0x1<<1) // Reserved
14506 …HY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER718_RESERVEDFIELD241_K2_E5_SHIFT 1
14510 …0_PLL_RESERVEDREGISTER719_RESERVEDFIELD243_K2_E5 (0x7<<1) // Reserved
14511 …HY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER719_RESERVEDFIELD243_K2_E5_SHIFT 1
14515 … (0x1<<0) // CMU PLL regulator vddha setting. 0x0 - vddha is 1.5V nominal 0x1 - vddha …
14520 …0_PLL_RESERVEDREGISTER720_RESERVEDFIELD246_K2_E5 (0x3<<1) // Reserved
14521 …HY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER720_RESERVEDFIELD246_K2_E5_SHIFT 1
14527 …0_PLL_RESERVEDREGISTER721_RESERVEDFIELD249_K2_E5 (0x1<<1) // Reserved
14528 …HY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER721_RESERVEDFIELD249_K2_E5_SHIFT 1
14532 …0_PLL_RESERVEDREGISTER722_RESERVEDFIELD251_K2_E5 (0x1<<1) // Reserved
14533 …HY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER722_RESERVEDFIELD251_K2_E5_SHIFT 1
14554 …0_PLL_RESERVEDREGISTER726_RESERVEDFIELD260_K2_E5 (0x1<<1) // Reserved
14555 …HY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER726_RESERVEDFIELD260_K2_E5_SHIFT 1
14575 …0_PLL_RESERVEDREGISTER731_RESERVEDFIELD268_K2_E5 (0x1<<1) // Reserved
14576 …HY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER731_RESERVEDFIELD268_K2_E5_SHIFT 1
14670 … (0x1<<0) // CMU PLL lock detector status. 0x0 - CMU PLL is not locked 0x1 - CMU PL…
14682 …0_PLL_RESERVEDREGISTER771_RESERVEDFIELD297_K2_E5 (0x1<<1) // Reserved
14683 …HY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER771_RESERVEDFIELD297_K2_E5_SHIFT 1
14694 …0_PLL_RESERVEDREGISTER775_RESERVEDFIELD303_K2_E5 (0x3<<1) // Reserved
14695 …HY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER775_RESERVEDFIELD303_K2_E5_SHIFT 1
14715 …0_GCFSM2_RESERVEDREGISTER782_RESERVEDFIELD311_K2_E5 (0xf<<1) // Reserved
14716 …HY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER782_RESERVEDFIELD311_K2_E5_SHIFT 1
14769 …0_GCFSM2_RESERVEDREGISTER806_RESERVEDFIELD338_K2_E5 (0xf<<1) // Reserved
14770 …HY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER806_RESERVEDFIELD338_K2_E5_SHIFT 1
14775 …0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD341_K2_E5 (0x1<<1) // Reserved
14776 …HY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD341_K2_E5_SHIFT 1
14790 …0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD348_K2_E5 (0x1<<1) // Reserved
14791 …HY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD348_K2_E5_SHIFT 1
14815 …_FEATURE_RESERVEDREGISTER812_RESERVEDFIELD359_K2_E5 (0x7f<<1) // Reserved
14816 …HY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER812_RESERVEDFIELD359_K2_E5_SHIFT 1
14837 …_TOP_RESERVEDREGISTER824_RESERVEDFIELD364_K2_E5 (0x1<<1) // Reserved
14838 …HY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER824_RESERVEDFIELD364_K2_E5_SHIFT 1
14848 …_TOP_RESERVEDREGISTER825_RESERVEDFIELD369_K2_E5 (0x1<<1) // Reserved
14849 …HY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER825_RESERVEDFIELD369_K2_E5_SHIFT 1
14864 …_TOP_RESERVEDREGISTER827_RESERVEDFIELD376_K2_E5 (0x1<<1) // Reserved
14865 …HY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER827_RESERVEDFIELD376_K2_E5_SHIFT 1
14884 …_TOP_RESERVEDREGISTER831_RESERVEDFIELD385_K2_E5 (0x1<<1) // Reserved
14885 …HY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER831_RESERVEDFIELD385_K2_E5_SHIFT 1
14910 … (0x1<<0) // CMU OK status. 0x0 - CMU PLL is not locked 0x1 - indica…
14914 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14915 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14917 … (0x1<<0) // CMU macro error status. 0x0 - no error 0x1 - PHY CMU macro…
14922 …_TOP_RESERVEDREGISTER839_RESERVEDFIELD397_K2_E5 (0x1<<1) // Reserved
14923 …HY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER839_RESERVEDFIELD397_K2_E5_SHIFT 1
14930 …_TOP_RESERVEDREGISTER841_RESERVEDFIELD400_K2_E5 (0x3<<1) // Reserved
14931 …HY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER841_RESERVEDFIELD400_K2_E5_SHIFT 1
14937 …_RPLL_AFE_PD_CTRL0_RESERVEDFIELD402_K2_E5 (0x1<<1) // Reserved
14938 …HY_NW_IP_REG_CMU_R0_RPLL_AFE_PD_CTRL0_RESERVEDFIELD402_K2_E5_SHIFT 1
14942 …MU_R0_RPLL_AFE_RST_CTRL0_RST_CMPLL2_DIV4P125_N_K2_E5 (0x1<<1) // TBD
14943 …HY_NW_IP_REG_CMU_R0_RPLL_AFE_RST_CTRL0_RST_CMPLL2_DIV4P125_N_K2_E5_SHIFT 1
14950 … (0x1<<0) // Select the reference clock. 0 - clk_ref 1- clk_pllref
14955 …U_R0_RPLL_AFE_VCO_CTRL0_CMPLL2_BIAS_TRIM_K2_E5 (0x1f<<1) // TBD
14956 …HY_NW_IP_REG_CMU_R0_RPLL_AFE_VCO_CTRL0_CMPLL2_BIAS_TRIM_K2_E5_SHIFT 1
14969 …MU_R0_RPLL_AFE_PFD_CTRL1_CMPLL2_PFD_FORCE_UP_K2_E5 (0x1<<1) // TBD
14970 …HY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL1_CMPLL2_PFD_FORCE_UP_K2_E5_SHIFT 1
14984 …MU_R0_RPLL_AFE_INT_CTRL0_CMPLL2_IHIZ_K2_E5 (0x1<<1) // TBD
14985 …HY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL0_CMPLL2_IHIZ_K2_E5_SHIFT 1
14993 …MU_R0_RPLL_AFE_INT_CTRL1_CMPLL2_IFORCE_K2_E5 (0x3<<1) // TBD
14994 …HY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL1_CMPLL2_IFORCE_K2_E5_SHIFT 1
15005 …MU_R0_RPLL_AFE_INT_CTRL3_CMPLL2_CPCHOP_DIV_K2_E5 (0x7<<1) // TBD
15006 …HY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL3_CMPLL2_CPCHOP_DIV_K2_E5_SHIFT 1
15008 … (0x1<<0) // Selects between FracN and integer divide modes 0 � integer mode 1 � FracN/SSC mode
15086 …W DataWidth:0x8 // Increment value in SSC mode;Enabled when ssc_gen_en=1.Note: this is an uns…
15087 …W DataWidth:0x8 // Increment value in SSC mode;Enabled when ssc_gen_en=1.Note: this is an uns…
15091 …_GEN_CTRL5_FRACSYN_EN_K2_E5 (0x1<<1) // Enable for loadi…
15092 …HY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL5_FRACSYN_EN_K2_E5_SHIFT 1
15095 …ss:RW DataWidth:0x8 // Used as frequency offset in SSC when ssc_gen_en=1 or when fracsyn_en=1
15096 …ss:RW DataWidth:0x8 // Used as frequency offset in SSC when ssc_gen_en=1 or when fracsyn_en=1
15098 … (0xf<<0) // Used as frequency offset in SSC when ssc_gen_en=1 or when fracsyn_en=1
15103 …_RPLL_FRACN_CTRL3_RESERVEDFIELD415_K2_E5 (0x3<<1) // Reserved
15104 …HY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL3_RESERVEDFIELD415_K2_E5_SHIFT 1
15124 …_GCFSM2_RESERVEDREGISTER877_RESERVEDFIELD422_K2_E5 (0xf<<1) // Reserved
15125 …HY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER877_RESERVEDFIELD422_K2_E5_SHIFT 1
15178 …_GCFSM2_RESERVEDREGISTER901_RESERVEDFIELD449_K2_E5 (0xf<<1) // Reserved
15179 …HY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER901_RESERVEDFIELD449_K2_E5_SHIFT 1
15187 …FEATURE_RESERVEDREGISTER904_RESERVEDFIELD453_K2_E5 (0x7f<<1) // Reserved
15188 …HY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER904_RESERVEDFIELD453_K2_E5_SHIFT 1
15204 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
15206 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0…
15207 …HY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_K2_E5_SHIFT 1
15208 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
15210 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission …
15232 …P_RESERVEDREGISTER918_RESERVEDFIELD464_K2_E5 (0x1<<1) // Reserved
15233 …HY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER918_RESERVEDFIELD464_K2_E5_SHIFT 1
15286 …1) // Select value for TX data path mux in DPL. The corresponding mux select override enable must…
15287 …HY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_VAL_K2_E5_SHIFT 1
15290 …rols tx_en for Far-End-Digital FED loopback mode. In FED loopback mode, tx_en will be set when th…
15293 …<<0) // A mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NE…
15295 … (0x1<<1) // A bit stripping selection for RX data path in …
15296 …HY_NW_IP_REG_LN0_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN_K2_E5_SHIFT 1
15328 …P_RESERVEDREGISTER934_RESERVEDFIELD494_K2_E5 (0x1<<1) // Reserved
15329 …HY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER934_RESERVEDFIELD494_K2_E5_SHIFT 1
15336 … (0x7<<1) // lnX_data_width_i override value for TX. It takes effect when ovr_en is 1. 0x5-…
15337 …HY_NW_IP_REG_LN0_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_K2_E5_SHIFT 1
15338 … (0x7<<4) // lnX_data_width_i override value for RX. It takes effect when ovr_en is 1.
15364 …P_RESERVEDREGISTER939_RESERVEDFIELD506_K2_E5 (0x3<<1) // Reserved
15365 …HY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER939_RESERVEDFIELD506_K2_E5_SHIFT 1
15371 …P_RESERVEDREGISTER940_RESERVEDFIELD509_K2_E5 (0x1<<1) // Reserved
15372 …HY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER940_RESERVEDFIELD509_K2_E5_SHIFT 1
15378 …P_RESERVEDREGISTER941_RESERVEDFIELD512_K2_E5 (0x3<<1) // Reserved
15379 …HY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER941_RESERVEDFIELD512_K2_E5_SHIFT 1
15383 …P_RESERVEDREGISTER942_RESERVEDFIELD514_K2_E5 (0x3<<1) // Reserved
15384 …HY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER942_RESERVEDFIELD514_K2_E5_SHIFT 1
15397 …P_RESERVEDREGISTER944_RESERVEDFIELD520_K2_E5 (0x1<<1) // Reserved
15398 …HY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER944_RESERVEDFIELD520_K2_E5_SHIFT 1
15416 …P_RESERVEDREGISTER947_RESERVEDFIELD528_K2_E5 (0x1<<1) // Reserved
15417 …HY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER947_RESERVEDFIELD528_K2_E5_SHIFT 1
15418 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
15419 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
15421 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
15472 …R_RXCLK_RESERVEDREGISTER966_RESERVEDFIELD549_K2_E5 (0x1<<1) // Reserved
15473 …HY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER966_RESERVEDFIELD549_K2_E5_SHIFT 1
15488 … 0x0062fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
15490 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
15495 …LPF_STATUS4_DLPF_TOO_LOW_K2_E5 (0x1<<1) // Indicates that D…
15496 …HY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_K2_E5_SHIFT 1
15497 …s of lock indicator. 1 means lock has been lost. Once lock is lost, this status is sticky until c…
15500 … (0x1<<0) // CDR lock indicator. 1 means lock is achiev…
15536 …R_RXCLK_RESERVEDREGISTER983_RESERVEDFIELD572_K2_E5 (0x1<<1) // Reserved
15537 …HY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER983_RESERVEDFIELD572_K2_E5_SHIFT 1
15573 …R_REFCLK_RESERVEDREGISTER996_RESERVEDFIELD589_K2_E5 (0x1<<1) // Reserved
15574 …HY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER996_RESERVEDFIELD589_K2_E5_SHIFT 1
15613 …R_REFCLK_RESERVEDREGISTER1004_RESERVEDFIELD605_K2_E5 (0x1<<1) // Reserved
15614 …HY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1004_RESERVEDFIELD605_K2_E5_SHIFT 1
15630 …EG_RESERVEDREGISTER1011_RESERVEDFIELD613_K2_E5 (0x1<<1) // Reserved
15631 …HY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1011_RESERVEDFIELD613_K2_E5_SHIFT 1
15655 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
15660 …G_CTRL0_RESERVEDFIELD624_K2_E5 (0x7f<<1) // Reserved
15661 …HY_NW_IP_REG_LN0_ANEG_CTRL0_RESERVEDFIELD624_K2_E5_SHIFT 1
15673 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
15677 …he ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks …
15684 … (0x1<<0) // Page Received. To clear it, write 1 to it.
15686 …1_AN_LINK_GOOD_K2_E5 (0x1<<1) // Autoneg has comp…
15687 …HY_NW_IP_REG_LN0_ANEG_STATUS1_AN_LINK_GOOD_K2_E5_SHIFT 1
15688 … (0x1<<2) // Autoneg Parallel Detection Fault. Write 1 to clear it.
15696 … 0x006650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
15697 … 0x006654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
15701 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
15704 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
15720 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
15722 …H0_ABILITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology …
15723 …HY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT 1
15724 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
15726 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
15728 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
15730 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
15732 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
15734 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
15737 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
15739 …1_ABILITY_25G_GR_S_K2_E5 (0x1<<1) // 25GBase-GR-S KR or CR te…
15740 …HY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT 1
15741 …LITY_25G_GR_K2_E5 (0x1<<2) // 25GBase-GR KR or CR technolog…
15743 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
15746 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
15749 …TY_K2_E5 (0x1<<0) // base page bit F0. It advertises …
15751 …EC_REQ_K2_E5 (0x1<<1) // base page bit F1. It req…
15752 …HY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_FEC_REQ_K2_E5_SHIFT 1
15753 … (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR…
15755 … (0x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-…
15758 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
15760 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consort…
15761 …HY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_25G_CR_K2_E5_SHIFT 1
15762 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
15764 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
15766 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
15768 …// Extended advertised FEC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consorti…
15770 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
15772 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
15793 …EG_RESERVEDREGISTER1029_RESERVEDFIELD637_K2_E5 (0x1<<1) // Reserved
15794 …HY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD637_K2_E5_SHIFT 1
15810 …EG_RESERVEDREGISTER1030_RESERVEDFIELD645_K2_E5 (0x1<<1) // Reserved
15811 …HY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD645_K2_E5_SHIFT 1
15825 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
15828 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
15846 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
15848 …ABILITY_10G_KX4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 tech…
15849 …HY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT 1
15850 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
15852 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
15854 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
15856 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
15858 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
15860 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
15863 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
15865 …ILITY_25G_GR_S_K2_E5 (0x1<<1) // Link partner 25GBase-GR-S KR or…
15866 …HY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT 1
15867 …R_K2_E5 (0x1<<2) // Link partner 25GBase-GR KR or CR technolog…
15869 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
15872 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
15875 … (0x1<<0) // Link partner base page bit F0. It advertises …
15877 …EQ_K2_E5 (0x1<<1) // Link partner base page bit F1. …
15878 …HY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_FEC_REQ_K2_E5_SHIFT 1
15879 … (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR…
15881 …1<<3) // Link partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-…
15884 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
15886 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G …
15887 …HY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_25G_CR_K2_E5_SHIFT 1
15888 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
15890 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
15892 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
15894 …er extended advertised FEC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consorti…
15896 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
15898 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
15919 …EG_RESERVEDREGISTER1037_RESERVEDFIELD657_K2_E5 (0x1<<1) // Reserved
15920 …HY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD657_K2_E5_SHIFT 1
15936 …EG_RESERVEDREGISTER1038_RESERVEDFIELD665_K2_E5 (0x1<<1) // Reserved
15937 …HY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD665_K2_E5_SHIFT 1
15949 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when status0.an_link_good is…
15951 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid when statu…
15952 …HY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT 1
15953 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when status0.an_link_good is…
15955 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid when status0.an_link_good i…
15957 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid when status0.an_link_good i…
15959 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid when status0.an_link_good i…
15961 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid when status0.an_link_good i…
15963 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid when status0.an_link_good i…
15966 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid when status0.an_link_good i…
15968 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is valid when …
15969 …HY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT 1
15970 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is valid when status0.an_link_go…
15972 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when status0.an_link_good is…
15974 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid when status0.an_link_good i…
15976 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid when status0.an_link_good i…
15978 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid when status0.an_link_good i…
15981 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is valid when status0.an_link_go…
15983 … (0x1<<1) // Resolution result for Firecode base page FEC. It is valid when…
15984 …HY_NW_IP_REG_LN0_ANEG_RESOLUTION_FEC_FC_K2_E5_SHIFT 1
15986 … (0x1<<0) // Resolution result for RX PAUSE enable. It is valid when status0.an_link_good is 1.
15988 … (0x1<<1) // Resolution result for TX PAUSE enable. It is valid when st…
15989 …HY_NW_IP_REG_LN0_ANEG_RESOLUTION_PAUSE_TX_K2_E5_SHIFT 1
15991 …1 if both the local device and the link partner advertise the EEE capability for the resolved PHY …
15994 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
15996 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
15997 …HY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_10G_KX4_K2_E5_SHIFT 1
15998 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
16000 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
16002 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
16004 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
16006 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
16008 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
16011 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
16013 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-…
16014 …HY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_25G_GR_K2_E5_SHIFT 1
16015 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
16017 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
16019 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
16021 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
16037 …E_RESERVEDREGISTER1042_RESERVEDFIELD676_K2_E5 (0x3<<1) // Reserved
16038 …HY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1042_RESERVEDFIELD676_K2_E5_SHIFT 1
16062 …Q_REFCLK_RESERVEDREGISTER1049_RESERVEDFIELD688_K2_E5 (0x3<<1) // Reserved
16063 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1049_RESERVEDFIELD688_K2_E5_SHIFT 1
16147 …Q_REFCLK_RESERVEDREGISTER1070_RESERVEDFIELD726_K2_E5 (0x1<<1) // Reserved
16148 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1070_RESERVEDFIELD726_K2_E5_SHIFT 1
16170 …Q_REFCLK_RESERVEDREGISTER1076_RESERVEDFIELD735_K2_E5 (0x1<<1) // Reserved
16171 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1076_RESERVEDFIELD735_K2_E5_SHIFT 1
16215 …Q_REFCLK_RESERVEDREGISTER1087_RESERVEDFIELD752_K2_E5 (0x1<<1) // Reserved
16216 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1087_RESERVEDFIELD752_K2_E5_SHIFT 1
16232 …Q_REFCLK_RESERVEDREGISTER1090_RESERVEDFIELD759_K2_E5 (0x1<<1) // Reserved
16233 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1090_RESERVEDFIELD759_K2_E5_SHIFT 1
16374 …Q_REFCLK_RESERVEDREGISTER1117_RESERVEDFIELD815_K2_E5 (0x1<<1) // Reserved
16375 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1117_RESERVEDFIELD815_K2_E5_SHIFT 1
16410 …Q_REFCLK_RESERVEDREGISTER1122_RESERVEDFIELD826_K2_E5 (0x1<<1) // Reserved
16411 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1122_RESERVEDFIELD826_K2_E5_SHIFT 1
16447 …Q_REFCLK_RESERVEDREGISTER1131_RESERVEDFIELD840_K2_E5 (0x1<<1) // Reserved
16448 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1131_RESERVEDFIELD840_K2_E5_SHIFT 1
16476 …Q_REFCLK_RESERVEDREGISTER1137_RESERVEDFIELD851_K2_E5 (0x1<<1) // Reserved
16477 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1137_RESERVEDFIELD851_K2_E5_SHIFT 1
16492 …Q_REFCLK_RESERVEDREGISTER1141_RESERVEDFIELD859_K2_E5 (0x1<<1) // Reserved
16493 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1141_RESERVEDFIELD859_K2_E5_SHIFT 1
16511 …Q_REFCLK_RESERVEDREGISTER1148_RESERVEDFIELD870_K2_E5 (0x1<<1) // Reserved
16512 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1148_RESERVEDFIELD870_K2_E5_SHIFT 1
16516 …Q_REFCLK_RESERVEDREGISTER1149_RESERVEDFIELD872_K2_E5 (0x1<<1) // Reserved
16517 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1149_RESERVEDFIELD872_K2_E5_SHIFT 1
16570 …_REFCLK_RESERVEDREGISTER1173_RESERVEDFIELD893_K2_E5 (0x1f<<1) // Reserved
16571 …HY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1173_RESERVEDFIELD893_K2_E5_SHIFT 1
16578 …V_REFCLK_RESERVEDREGISTER1175_RESERVEDFIELD896_K2_E5 (0x1<<1) // Reserved
16579 …HY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1175_RESERVEDFIELD896_K2_E5_SHIFT 1
16589 …V_REFCLK_RESERVEDREGISTER1176_RESERVEDFIELD901_K2_E5 (0x1<<1) // Reserved
16590 …HY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1176_RESERVEDFIELD901_K2_E5_SHIFT 1
16621 … (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until ack is 1. S…
16624 …ACK_K2_E5 (0x1<<0) // Set to 1 by firmware when upd…
16627 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
16633 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
16638 …V_REFCLK_RESERVEDREGISTER1183_RESERVEDFIELD916_K2_E5 (0x1<<1) // Reserved
16639 …HY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1183_RESERVEDFIELD916_K2_E5_SHIFT 1
16646 …V_REFCLK_RESERVEDREGISTER1184_RESERVEDFIELD918_K2_E5 (0x1<<1) // Reserved
16647 …HY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1184_RESERVEDFIELD918_K2_E5_SHIFT 1
16657 …V_REFCLK_RESERVEDREGISTER1185_RESERVEDFIELD923_K2_E5 (0x1<<1) // Reserved
16658 …HY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1185_RESERVEDFIELD923_K2_E5_SHIFT 1
16698 …E_REFCLK_RESERVEDREGISTER1194_RESERVEDFIELD939_K2_E5 (0x1<<1) // Reserved
16699 …HY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1194_RESERVEDFIELD939_K2_E5_SHIFT 1
16724 …E_REFCLK_RESERVEDREGISTER1198_RESERVEDFIELD950_K2_E5 (0x3<<1) // Reserved
16725 …HY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1198_RESERVEDFIELD950_K2_E5_SHIFT 1
16730 …E_REFCLK_RESERVEDREGISTER1200_RESERVEDFIELD953_K2_E5 (0xf<<1) // Reserved
16731 …HY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1200_RESERVEDFIELD953_K2_E5_SHIFT 1
16742 … (0x1<<0) // Write 1 to request a command CMD execution. It should be held at 1 unti…
16744 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Other…
16745 …HY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_CMD_K2_E5_SHIFT 1
16748 …BEFORE_EVAL_K2_E5 (0x1<<7) // Set it to 1 when changing DFE ta…
16768 … (0x1<<0) // Acknowledge from DFE after command execution. Will be set to 1 after a command is c…
16770 …E_REFCLK_FSM_STATUS0_RESERVEDFIELD967_K2_E5 (0x1<<1) // Reserved
16771 …HY_NW_IP_REG_LN0_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD967_K2_E5_SHIFT 1
16777 … (0x1<<0) // Enables updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - D…
16779 … (0x1<<1) // Enables updating Tap 1 Even 1 Path when FSM LOAD_ONLY command …
16780 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_K2_E5_SHIFT 1
16781 … (0x1<<2) // Enables updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - D…
16783 … (0x1<<3) // Enables updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - D…
16785 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16787 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16789 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16791 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16794 …// Starting value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields …
16796 …0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
16799 …// Starting value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields …
16801 …1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
16804 … // Starting value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields …
16806 …_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
16809 … // Starting value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields …
16811 …_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
16816 …4_TAP2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
16821 …5_TAP3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
16826 …6_TAP4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
16831 …7_TAP5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
16834 … // Loading value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields …
16836 …_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
16839 … // Loading value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields …
16841 …_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
16844 …) // Loading value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields …
16846 …POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
16849 …) // Loading value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields …
16851 …POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
16856 …_TAP2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
16861 …_TAP3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
16866 …_TAP4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
16871 …_TAP5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
16874 …2_E5 (0x1f<<0) // binary value for Tap 1 Even 0 Path for Tap …
16876 …P1_EVEN0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
16879 … (0x1f<<0) // binary value for Tap 1 Even 1 Path for Tap Adap…
16881 …P1_EVEN1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
16884 …E5 (0x1f<<0) // binary value for Tap 1 Odd 0 Path for Tap A…
16886 …P1_ODD0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
16889 … (0x1f<<0) // binary value for Tap 1 Odd 1 Path for Tap Adap…
16891 …P1_ODD1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
16896 …P2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
16901 …P3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
16906 …P4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
16911 …P5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
16916 …E_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD971_K2_E5 (0x1<<1) // Reserved
16917 …HY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD971_K2_E5_SHIFT 1
16987 …E_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD997_K2_E5 (0x1<<1) // Reserved
16988 …HY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD997_K2_E5_SHIFT 1
17004 …E_REFCLK_RESERVEDREGISTER1231_RESERVEDFIELD1005_K2_E5 (0x1<<1) // Reserved
17005 …HY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1231_RESERVEDFIELD1005_K2_E5_SHIFT 1
17011 …E_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1008_K2_E5 (0x1<<1) // Reserved
17012 …HY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1008_K2_E5_SHIFT 1
17039 …E_RXCLK_RESERVEDREGISTER1236_RESERVEDFIELD1021_K2_E5 (0x1<<1) // Reserved
17040 …HY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1236_RESERVEDFIELD1021_K2_E5_SHIFT 1
17048 …E_RXCLK_RESERVEDREGISTER1239_RESERVEDFIELD1025_K2_E5 (0x1<<1) // Reserved
17049 …HY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1239_RESERVEDFIELD1025_K2_E5_SHIFT 1
17061 …E_RXCLK_RESERVEDREGISTER1244_RESERVEDFIELD1031_K2_E5 (0x1<<1) // Reserved
17062 …HY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1244_RESERVEDFIELD1031_K2_E5_SHIFT 1
17173 …E_RXCLK_RESERVEDREGISTER1296_RESERVEDFIELD1089_K2_E5 (0x1<<1) // Reserved
17174 …HY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1296_RESERVEDFIELD1089_K2_E5_SHIFT 1
17203 …2_E5 (0x1<<0) // Enables the run-length detection digi…
17205 … 0x007410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
17207 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
17209 … (0x1<<1) // Indicates that the run-length filter has, at some time, exce…
17210 …HY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_K2_E5_SHIFT 1
17211 …of consecutive clk_i clock cycles that the analog LOS must remain a logic �1� before the output o…
17212 …of consecutive clk_i clock cycles that the analog LOS must remain a logic �1� before the output o…
17213 …onsecutive clk_i clock cycles that the raw analog LOS must remain a logic �1� before the output o…
17254 …S_REFCLK_RESERVEDREGISTER1321_RESERVEDFIELD1118_K2_E5 (0x7<<1) // Reserved
17255 …HY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1321_RESERVEDFIELD1118_K2_E5_SHIFT 1
17261 …S_REFCLK_RESERVEDREGISTER1322_RESERVEDFIELD1121_K2_E5 (0x1<<1) // Reserved
17262 …HY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1322_RESERVEDFIELD1121_K2_E5_SHIFT 1
17275 …S_REFCLK_RESERVEDREGISTER1326_RESERVEDFIELD1128_K2_E5 (0x1<<1) // Reserved
17276 …HY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1326_RESERVEDFIELD1128_K2_E5_SHIFT 1
17286 …S_REFCLK_RESERVEDREGISTER1329_RESERVEDFIELD1132_K2_E5 (0x1<<1) // Reserved
17287 …HY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1329_RESERVEDFIELD1132_K2_E5_SHIFT 1
17291 …S_REFCLK_STATUS0_RESERVEDFIELD1133_K2_E5 (0x1<<1) // Reserved
17292 …HY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_RESERVEDFIELD1133_K2_E5_SHIFT 1
17311 …FSM2_RESERVEDREGISTER1333_RESERVEDFIELD1139_K2_E5 (0xf<<1) // Reserved
17312 …HY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1333_RESERVEDFIELD1139_K2_E5_SHIFT 1
17365 …FSM2_RESERVEDREGISTER1357_RESERVEDFIELD1166_K2_E5 (0xf<<1) // Reserved
17366 …HY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1357_RESERVEDFIELD1166_K2_E5_SHIFT 1
17371 …L_PATTERN_SEL_K2_E5 (0xf<<1) // Selects the patt…
17372 …HY_NW_IP_REG_LN0_BIST_TX_CTRL_PATTERN_SEL_K2_E5_SHIFT 1
17380 … 0x00781cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
17381 … 0x007820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
17416 …1) // Selects the pattern to search for: 0x1 � PRBS 0xC1 0x2 � PRBS 0x221 0x3 � PRBS 0xA01 0x4 � P…
17417 …HY_NW_IP_REG_LN0_BIST_RX_CTRL_PATTERN_SEL_K2_E5_SHIFT 1
17418 …K2_E5 (0x1<<5) // Clears the bit error counter.
17422 …ces the PRBS LFSR to reseed with Rx data every cycle. This will cause the bit error counter to be…
17429 … 0x007a20UL //Access:R DataWidth:0x8 // Number of bit errors.
17430 … 0x007a24UL //Access:R DataWidth:0x8 // Number of bit errors.
17431 … 0x007a28UL //Access:R DataWidth:0x8 // Number of bit errors.
17439 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
17440 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
17441 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
17442 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
17444 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
17473 … (0x1<<0) // Configures AC/DC coupling of the lane 0: DC coupled 1: AC coupled
17481 …ATURE_RESERVEDREGISTER1363_RESERVEDFIELD1173_K2_E5 (0x1<<1) // Reserved
17482 …HY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1363_RESERVEDFIELD1173_K2_E5_SHIFT 1
17486 …ATURE_RESERVEDREGISTER1364_RESERVEDFIELD1175_K2_E5 (0x1<<1) // Reserved
17487 …HY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1364_RESERVEDFIELD1175_K2_E5_SHIFT 1
17499 …ATURE_RESERVEDREGISTER1365_RESERVEDFIELD1181_K2_E5 (0x1<<1) // Reserved
17500 …HY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1365_RESERVEDFIELD1181_K2_E5_SHIFT 1
17508 …ATURE_RESERVEDREGISTER1366_RESERVEDFIELD1185_K2_E5 (0x1<<1) // Reserved
17509 …HY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1185_K2_E5_SHIFT 1
17525 …ATURE_RESERVEDREGISTER1367_RESERVEDFIELD1193_K2_E5 (0x1<<1) // Reserved
17526 …HY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1367_RESERVEDFIELD1193_K2_E5_SHIFT 1
17536 …ATURE_RESERVEDREGISTER1368_RESERVEDFIELD1198_K2_E5 (0x1<<1) // Reserved
17537 …HY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1368_RESERVEDFIELD1198_K2_E5_SHIFT 1
17549 …TURE_RESERVEDREGISTER1371_RESERVEDFIELD1203_K2_E5 (0x7f<<1) // Reserved
17550 …HY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1371_RESERVEDFIELD1203_K2_E5_SHIFT 1
17555 …ATURE_RESERVEDREGISTER1373_RESERVEDFIELD1206_K2_E5 (0x1<<1) // Reserved
17556 …HY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1373_RESERVEDFIELD1206_K2_E5_SHIFT 1
17560 …ATURE_RESERVEDREGISTER1374_RESERVEDFIELD1208_K2_E5 (0x1<<1) // Reserved
17561 …HY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1374_RESERVEDFIELD1208_K2_E5_SHIFT 1
17565 …ATURE_RESERVEDREGISTER1375_RESERVEDFIELD1210_K2_E5 (0x1<<1) // Reserved
17566 …HY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1375_RESERVEDFIELD1210_K2_E5_SHIFT 1
17573 … (0x3<<2) // How many times to repeat CTLE adaptation sequence for initial adaptation set 1
17590 …1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed…
17592 …1 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone c…
17601 …E_ADAPT_HFG_CFG0_INIT0_DATA_EN_K2_E5 (0x1<<1) // Enables CTLE EQ …
17602 …HY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_K2_E5_SHIFT 1
17603 … (0x1<<2) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 1
17605 … (0x1<<3) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 1
17618 … (0x3<<2) // Selects which HFG result to use for the initial adaptation set 1 0x0: Edge Based 0x1:…
17630 … (0x1<<1) // Enables CTLE midband shaping adaptation for initial a…
17631 …HY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_K2_E5_SHIFT 1
17639 …ATURE_RESERVEDREGISTER1378_RESERVEDFIELD1228_K2_E5 (0x1<<1) // Reserved
17640 …HY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1228_K2_E5_SHIFT 1
17654 … (0x1<<0) // Enables DFE Tap 1. Tap1 will not be po…
17656 …_CFG_TAP2_EN_K2_E5 (0x1<<1) // Enables DFE Tap …
17657 …HY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP2_EN_K2_E5_SHIFT 1
17665 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
17668 …_INIT_EN_K2_E5 (0x1<<0) // Enables initial adaptations for Tap 1
17670 …ATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD1235_K2_E5 (0x1<<1) // Reserved
17671 …HY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD1235_K2_E5_SHIFT 1
17679 …ATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD1238_K2_E5 (0x1<<1) // Reserved
17680 …HY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD1238_K2_E5_SHIFT 1
17688 …ATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD1241_K2_E5 (0x1<<1) // Reserved
17689 …HY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD1241_K2_E5_SHIFT 1
17697 …ATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD1244_K2_E5 (0x1<<1) // Reserved
17698 …HY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD1244_K2_E5_SHIFT 1
17706 …ATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD1247_K2_E5 (0x1<<1) // Reserved
17707 …HY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD1247_K2_E5_SHIFT 1
17715 …ATURE_ADAPT_CONT_CFG0_RESERVEDFIELD1250_K2_E5 (0x1<<1) // Reserved
17716 …HY_NW_IP_REG_LN0_FEATURE_ADAPT_CONT_CFG0_RESERVEDFIELD1250_K2_E5_SHIFT 1
17717 …UL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~279 mins
17718 …UL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~279 mins
17719 …UL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~279 mins
17753 …T_CFG0_RX_CTRL_DIS_K2_E5 (0x1<<1) // Disables the fir…
17754 …HY_NW_IP_REG_LN0_FEATURE_TEST_CFG0_RX_CTRL_DIS_K2_E5_SHIFT 1
17770 …TRL0_MR_TRAINING_ENABLE_K2_E5 (0x1<<1) // Indicates to LTS…
17771 …HY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE_K2_E5_SHIFT 1
17785 …TRL5_RX_TRAINED_K2_E5 (0x1<<1) // Input to LTSM in…
17786 …HY_NW_IP_REG_LN0_LT_TX_FSM_CTRL5_RX_TRAINED_K2_E5_SHIFT 1
17792 …TATUS_TRAINING_K2_E5 (0x1<<1) // Output from LTSM…
17793 …HY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_TRAINING_K2_E5_SHIFT 1
17794 …802.3 defined variable. This value is only visible internally, and is not the signal_det value dr…
17799 … 0 � CL72 1 + x^9 +x^11 1 � CL93 1 + x^5 + x^6 + x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3…
17806 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
17810 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
17817 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
17821 …E5 (0x3<<4) // Status report field for pre-cursor tap.
17838 …_TRAINING_K2_E5 (0x1<<1) // This is the 802.…
17839 …HY_NW_IP_REG_LN0_LT_RX_CTRL0_TRAINING_K2_E5_SHIFT 1
17841 …0 � CL72 1 + x^9 + x^11 1 � CL93 1 + x^5 + x^6 + x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3…
17843 … 0x007f0cUL //Access:RW DataWidth:0x8 // Maximum number of PRBS bit errors allowed in s…
17847 …STATUS0_LOCK_K2_E5 (0x1<<1) // Indicates that a…
17848 …HY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS0_LOCK_K2_E5_SHIFT 1
17849 … 0x007f18UL //Access:R DataWidth:0x8 // Number of bit errors in PRBS patt…
17864 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
17868 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
17875 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
17879 … (0x3<<4) // Received status report field for pre-cursor tap.
17886 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
17888 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0…
17889 …HY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_K2_E5_SHIFT 1
17890 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
17892 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission …
17914 …P_RESERVEDREGISTER1402_RESERVEDFIELD1278_K2_E5 (0x1<<1) // Reserved
17915 …HY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1402_RESERVEDFIELD1278_K2_E5_SHIFT 1
17968 …1) // Select value for TX data path mux in DPL. The corresponding mux select override enable must…
17969 …HY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_VAL_K2_E5_SHIFT 1
17972 …rols tx_en for Far-End-Digital FED loopback mode. In FED loopback mode, tx_en will be set when th…
17975 …<<0) // A mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NE…
17977 … (0x1<<1) // A bit stripping selection for RX data path in …
17978 …HY_NW_IP_REG_LN1_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN_K2_E5_SHIFT 1
18010 …P_RESERVEDREGISTER1418_RESERVEDFIELD1308_K2_E5 (0x1<<1) // Reserved
18011 …HY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1418_RESERVEDFIELD1308_K2_E5_SHIFT 1
18018 … (0x7<<1) // lnX_data_width_i override value for TX. It takes effect when ovr_en is 1. 0x5-…
18019 …HY_NW_IP_REG_LN1_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_K2_E5_SHIFT 1
18020 … (0x7<<4) // lnX_data_width_i override value for RX. It takes effect when ovr_en is 1.
18046 …P_RESERVEDREGISTER1423_RESERVEDFIELD1320_K2_E5 (0x3<<1) // Reserved
18047 …HY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1423_RESERVEDFIELD1320_K2_E5_SHIFT 1
18053 …P_RESERVEDREGISTER1424_RESERVEDFIELD1323_K2_E5 (0x1<<1) // Reserved
18054 …HY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1424_RESERVEDFIELD1323_K2_E5_SHIFT 1
18060 …P_RESERVEDREGISTER1425_RESERVEDFIELD1326_K2_E5 (0x3<<1) // Reserved
18061 …HY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1425_RESERVEDFIELD1326_K2_E5_SHIFT 1
18065 …P_RESERVEDREGISTER1426_RESERVEDFIELD1328_K2_E5 (0x3<<1) // Reserved
18066 …HY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1426_RESERVEDFIELD1328_K2_E5_SHIFT 1
18079 …P_RESERVEDREGISTER1428_RESERVEDFIELD1334_K2_E5 (0x1<<1) // Reserved
18080 …HY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1428_RESERVEDFIELD1334_K2_E5_SHIFT 1
18098 …P_RESERVEDREGISTER1431_RESERVEDFIELD1342_K2_E5 (0x1<<1) // Reserved
18099 …HY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1431_RESERVEDFIELD1342_K2_E5_SHIFT 1
18100 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
18101 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
18103 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
18154 …R_RXCLK_RESERVEDREGISTER1450_RESERVEDFIELD1363_K2_E5 (0x1<<1) // Reserved
18155 …HY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1450_RESERVEDFIELD1363_K2_E5_SHIFT 1
18170 … 0x0082fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
18172 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
18177 …LPF_STATUS4_DLPF_TOO_LOW_K2_E5 (0x1<<1) // Indicates that D…
18178 …HY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_K2_E5_SHIFT 1
18179 …s of lock indicator. 1 means lock has been lost. Once lock is lost, this status is sticky until c…
18182 … (0x1<<0) // CDR lock indicator. 1 means lock is achiev…
18218 …R_RXCLK_RESERVEDREGISTER1467_RESERVEDFIELD1386_K2_E5 (0x1<<1) // Reserved
18219 …HY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1467_RESERVEDFIELD1386_K2_E5_SHIFT 1
18255 …R_REFCLK_RESERVEDREGISTER1480_RESERVEDFIELD1403_K2_E5 (0x1<<1) // Reserved
18256 …HY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1480_RESERVEDFIELD1403_K2_E5_SHIFT 1
18295 …R_REFCLK_RESERVEDREGISTER1488_RESERVEDFIELD1419_K2_E5 (0x1<<1) // Reserved
18296 …HY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1488_RESERVEDFIELD1419_K2_E5_SHIFT 1
18312 …EG_RESERVEDREGISTER1495_RESERVEDFIELD1427_K2_E5 (0x1<<1) // Reserved
18313 …HY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1495_RESERVEDFIELD1427_K2_E5_SHIFT 1
18337 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
18342 …G_CTRL0_RESERVEDFIELD1438_K2_E5 (0x7f<<1) // Reserved
18343 …HY_NW_IP_REG_LN1_ANEG_CTRL0_RESERVEDFIELD1438_K2_E5_SHIFT 1
18355 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
18359 …he ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks …
18366 … (0x1<<0) // Page Received. To clear it, write 1 to it.
18368 …1_AN_LINK_GOOD_K2_E5 (0x1<<1) // Autoneg has comp…
18369 …HY_NW_IP_REG_LN1_ANEG_STATUS1_AN_LINK_GOOD_K2_E5_SHIFT 1
18370 … (0x1<<2) // Autoneg Parallel Detection Fault. Write 1 to clear it.
18378 … 0x008650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
18379 … 0x008654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
18383 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
18386 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
18402 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
18404 …H0_ABILITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology …
18405 …HY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT 1
18406 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
18408 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
18410 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
18412 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
18414 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
18416 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
18419 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
18421 …1_ABILITY_25G_GR_S_K2_E5 (0x1<<1) // 25GBase-GR-S KR or CR te…
18422 …HY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT 1
18423 …LITY_25G_GR_K2_E5 (0x1<<2) // 25GBase-GR KR or CR technolog…
18425 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
18428 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
18431 …TY_K2_E5 (0x1<<0) // base page bit F0. It advertises …
18433 …EC_REQ_K2_E5 (0x1<<1) // base page bit F1. It req…
18434 …HY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_FEC_REQ_K2_E5_SHIFT 1
18435 … (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR…
18437 … (0x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-…
18440 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
18442 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consort…
18443 …HY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_25G_CR_K2_E5_SHIFT 1
18444 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
18446 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
18448 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
18450 …// Extended advertised FEC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consorti…
18452 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
18454 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
18475 …EG_RESERVEDREGISTER1513_RESERVEDFIELD1451_K2_E5 (0x1<<1) // Reserved
18476 …HY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1451_K2_E5_SHIFT 1
18492 …EG_RESERVEDREGISTER1514_RESERVEDFIELD1459_K2_E5 (0x1<<1) // Reserved
18493 …HY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1459_K2_E5_SHIFT 1
18507 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
18510 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
18528 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
18530 …ABILITY_10G_KX4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 tech…
18531 …HY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT 1
18532 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
18534 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
18536 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
18538 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
18540 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
18542 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
18545 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
18547 …ILITY_25G_GR_S_K2_E5 (0x1<<1) // Link partner 25GBase-GR-S KR or…
18548 …HY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT 1
18549 …R_K2_E5 (0x1<<2) // Link partner 25GBase-GR KR or CR technolog…
18551 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
18554 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
18557 … (0x1<<0) // Link partner base page bit F0. It advertises …
18559 …EQ_K2_E5 (0x1<<1) // Link partner base page bit F1. …
18560 …HY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_FEC_REQ_K2_E5_SHIFT 1
18561 … (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR…
18563 …1<<3) // Link partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-…
18566 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
18568 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G …
18569 …HY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_25G_CR_K2_E5_SHIFT 1
18570 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
18572 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
18574 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
18576 …er extended advertised FEC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consorti…
18578 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
18580 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
18601 …EG_RESERVEDREGISTER1521_RESERVEDFIELD1471_K2_E5 (0x1<<1) // Reserved
18602 …HY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1471_K2_E5_SHIFT 1
18618 …EG_RESERVEDREGISTER1522_RESERVEDFIELD1479_K2_E5 (0x1<<1) // Reserved
18619 …HY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1479_K2_E5_SHIFT 1
18631 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when status0.an_link_good is…
18633 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid when statu…
18634 …HY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT 1
18635 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when status0.an_link_good is…
18637 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid when status0.an_link_good i…
18639 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid when status0.an_link_good i…
18641 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid when status0.an_link_good i…
18643 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid when status0.an_link_good i…
18645 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid when status0.an_link_good i…
18648 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid when status0.an_link_good i…
18650 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is valid when …
18651 …HY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT 1
18652 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is valid when status0.an_link_go…
18654 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when status0.an_link_good is…
18656 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid when status0.an_link_good i…
18658 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid when status0.an_link_good i…
18660 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid when status0.an_link_good i…
18663 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is valid when status0.an_link_go…
18665 … (0x1<<1) // Resolution result for Firecode base page FEC. It is valid when…
18666 …HY_NW_IP_REG_LN1_ANEG_RESOLUTION_FEC_FC_K2_E5_SHIFT 1
18668 … (0x1<<0) // Resolution result for RX PAUSE enable. It is valid when status0.an_link_good is 1.
18670 … (0x1<<1) // Resolution result for TX PAUSE enable. It is valid when st…
18671 …HY_NW_IP_REG_LN1_ANEG_RESOLUTION_PAUSE_TX_K2_E5_SHIFT 1
18673 …1 if both the local device and the link partner advertise the EEE capability for the resolved PHY …
18676 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
18678 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
18679 …HY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_10G_KX4_K2_E5_SHIFT 1
18680 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
18682 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
18684 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
18686 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
18688 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
18690 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
18693 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
18695 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-…
18696 …HY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_25G_GR_K2_E5_SHIFT 1
18697 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
18699 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
18701 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
18703 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
18719 …E_RESERVEDREGISTER1526_RESERVEDFIELD1490_K2_E5 (0x3<<1) // Reserved
18720 …HY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1526_RESERVEDFIELD1490_K2_E5_SHIFT 1
18744 …Q_REFCLK_RESERVEDREGISTER1533_RESERVEDFIELD1502_K2_E5 (0x3<<1) // Reserved
18745 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1533_RESERVEDFIELD1502_K2_E5_SHIFT 1
18829 …Q_REFCLK_RESERVEDREGISTER1554_RESERVEDFIELD1540_K2_E5 (0x1<<1) // Reserved
18830 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1554_RESERVEDFIELD1540_K2_E5_SHIFT 1
18852 …Q_REFCLK_RESERVEDREGISTER1560_RESERVEDFIELD1549_K2_E5 (0x1<<1) // Reserved
18853 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1560_RESERVEDFIELD1549_K2_E5_SHIFT 1
18897 …Q_REFCLK_RESERVEDREGISTER1571_RESERVEDFIELD1566_K2_E5 (0x1<<1) // Reserved
18898 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1571_RESERVEDFIELD1566_K2_E5_SHIFT 1
18914 …Q_REFCLK_RESERVEDREGISTER1574_RESERVEDFIELD1573_K2_E5 (0x1<<1) // Reserved
18915 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1574_RESERVEDFIELD1573_K2_E5_SHIFT 1
19056 …Q_REFCLK_RESERVEDREGISTER1601_RESERVEDFIELD1629_K2_E5 (0x1<<1) // Reserved
19057 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1601_RESERVEDFIELD1629_K2_E5_SHIFT 1
19092 …Q_REFCLK_RESERVEDREGISTER1606_RESERVEDFIELD1640_K2_E5 (0x1<<1) // Reserved
19093 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1606_RESERVEDFIELD1640_K2_E5_SHIFT 1
19129 …Q_REFCLK_RESERVEDREGISTER1615_RESERVEDFIELD1654_K2_E5 (0x1<<1) // Reserved
19130 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1615_RESERVEDFIELD1654_K2_E5_SHIFT 1
19158 …Q_REFCLK_RESERVEDREGISTER1621_RESERVEDFIELD1665_K2_E5 (0x1<<1) // Reserved
19159 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1621_RESERVEDFIELD1665_K2_E5_SHIFT 1
19174 …Q_REFCLK_RESERVEDREGISTER1625_RESERVEDFIELD1673_K2_E5 (0x1<<1) // Reserved
19175 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1625_RESERVEDFIELD1673_K2_E5_SHIFT 1
19193 …Q_REFCLK_RESERVEDREGISTER1632_RESERVEDFIELD1684_K2_E5 (0x1<<1) // Reserved
19194 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1632_RESERVEDFIELD1684_K2_E5_SHIFT 1
19198 …Q_REFCLK_RESERVEDREGISTER1633_RESERVEDFIELD1686_K2_E5 (0x1<<1) // Reserved
19199 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1633_RESERVEDFIELD1686_K2_E5_SHIFT 1
19252 …_REFCLK_RESERVEDREGISTER1657_RESERVEDFIELD1707_K2_E5 (0x1f<<1) // Reserved
19253 …HY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1657_RESERVEDFIELD1707_K2_E5_SHIFT 1
19260 …V_REFCLK_RESERVEDREGISTER1659_RESERVEDFIELD1710_K2_E5 (0x1<<1) // Reserved
19261 …HY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1659_RESERVEDFIELD1710_K2_E5_SHIFT 1
19271 …V_REFCLK_RESERVEDREGISTER1660_RESERVEDFIELD1715_K2_E5 (0x1<<1) // Reserved
19272 …HY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1660_RESERVEDFIELD1715_K2_E5_SHIFT 1
19303 … (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until ack is 1. S…
19306 …ACK_K2_E5 (0x1<<0) // Set to 1 by firmware when upd…
19309 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
19315 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
19320 …V_REFCLK_RESERVEDREGISTER1667_RESERVEDFIELD1730_K2_E5 (0x1<<1) // Reserved
19321 …HY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1667_RESERVEDFIELD1730_K2_E5_SHIFT 1
19328 …V_REFCLK_RESERVEDREGISTER1668_RESERVEDFIELD1732_K2_E5 (0x1<<1) // Reserved
19329 …HY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1668_RESERVEDFIELD1732_K2_E5_SHIFT 1
19339 …V_REFCLK_RESERVEDREGISTER1669_RESERVEDFIELD1737_K2_E5 (0x1<<1) // Reserved
19340 …HY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1669_RESERVEDFIELD1737_K2_E5_SHIFT 1
19380 …E_REFCLK_RESERVEDREGISTER1678_RESERVEDFIELD1753_K2_E5 (0x1<<1) // Reserved
19381 …HY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1678_RESERVEDFIELD1753_K2_E5_SHIFT 1
19406 …E_REFCLK_RESERVEDREGISTER1682_RESERVEDFIELD1764_K2_E5 (0x3<<1) // Reserved
19407 …HY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1682_RESERVEDFIELD1764_K2_E5_SHIFT 1
19412 …E_REFCLK_RESERVEDREGISTER1684_RESERVEDFIELD1767_K2_E5 (0xf<<1) // Reserved
19413 …HY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1684_RESERVEDFIELD1767_K2_E5_SHIFT 1
19424 … (0x1<<0) // Write 1 to request a command CMD execution. It should be held at 1 unti…
19426 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Other…
19427 …HY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_CMD_K2_E5_SHIFT 1
19430 …BEFORE_EVAL_K2_E5 (0x1<<7) // Set it to 1 when changing DFE ta…
19450 … (0x1<<0) // Acknowledge from DFE after command execution. Will be set to 1 after a command is c…
19452 …E_REFCLK_FSM_STATUS0_RESERVEDFIELD1781_K2_E5 (0x1<<1) // Reserved
19453 …HY_NW_IP_REG_LN1_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD1781_K2_E5_SHIFT 1
19459 … (0x1<<0) // Enables updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - D…
19461 … (0x1<<1) // Enables updating Tap 1 Even 1 Path when FSM LOAD_ONLY command …
19462 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_K2_E5_SHIFT 1
19463 … (0x1<<2) // Enables updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - D…
19465 … (0x1<<3) // Enables updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - D…
19467 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19469 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19471 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19473 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19476 …// Starting value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields …
19478 …0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
19481 …// Starting value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields …
19483 …1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
19486 … // Starting value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields …
19488 …_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
19491 … // Starting value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields …
19493 …_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
19498 …4_TAP2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
19503 …5_TAP3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
19508 …6_TAP4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
19513 …7_TAP5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
19516 … // Loading value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields …
19518 …_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
19521 … // Loading value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields …
19523 …_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
19526 …) // Loading value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields …
19528 …POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
19531 …) // Loading value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields …
19533 …POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
19538 …_TAP2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
19543 …_TAP3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
19548 …_TAP4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
19553 …_TAP5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
19556 …2_E5 (0x1f<<0) // binary value for Tap 1 Even 0 Path for Tap …
19558 …P1_EVEN0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
19561 … (0x1f<<0) // binary value for Tap 1 Even 1 Path for Tap Adap…
19563 …P1_EVEN1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
19566 …E5 (0x1f<<0) // binary value for Tap 1 Odd 0 Path for Tap A…
19568 …P1_ODD0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
19571 … (0x1f<<0) // binary value for Tap 1 Odd 1 Path for Tap Adap…
19573 …P1_ODD1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
19578 …P2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
19583 …P3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
19588 …P4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
19593 …P5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
19598 …E_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1785_K2_E5 (0x1<<1) // Reserved
19599 …HY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1785_K2_E5_SHIFT 1
19669 …E_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1811_K2_E5 (0x1<<1) // Reserved
19670 …HY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1811_K2_E5_SHIFT 1
19686 …E_REFCLK_RESERVEDREGISTER1715_RESERVEDFIELD1819_K2_E5 (0x1<<1) // Reserved
19687 …HY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1715_RESERVEDFIELD1819_K2_E5_SHIFT 1
19693 …E_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1822_K2_E5 (0x1<<1) // Reserved
19694 …HY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1822_K2_E5_SHIFT 1
19721 …E_RXCLK_RESERVEDREGISTER1720_RESERVEDFIELD1835_K2_E5 (0x1<<1) // Reserved
19722 …HY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1720_RESERVEDFIELD1835_K2_E5_SHIFT 1
19730 …E_RXCLK_RESERVEDREGISTER1723_RESERVEDFIELD1839_K2_E5 (0x1<<1) // Reserved
19731 …HY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1723_RESERVEDFIELD1839_K2_E5_SHIFT 1
19743 …E_RXCLK_RESERVEDREGISTER1728_RESERVEDFIELD1845_K2_E5 (0x1<<1) // Reserved
19744 …HY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1728_RESERVEDFIELD1845_K2_E5_SHIFT 1
19855 …E_RXCLK_RESERVEDREGISTER1780_RESERVEDFIELD1903_K2_E5 (0x1<<1) // Reserved
19856 …HY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1780_RESERVEDFIELD1903_K2_E5_SHIFT 1
19885 …2_E5 (0x1<<0) // Enables the run-length detection digi…
19887 … 0x009410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
19889 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
19891 … (0x1<<1) // Indicates that the run-length filter has, at some time, exce…
19892 …HY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_K2_E5_SHIFT 1
19893 …of consecutive clk_i clock cycles that the analog LOS must remain a logic �1� before the output o…
19894 …of consecutive clk_i clock cycles that the analog LOS must remain a logic �1� before the output o…
19895 …onsecutive clk_i clock cycles that the raw analog LOS must remain a logic �1� before the output o…
19936 …S_REFCLK_RESERVEDREGISTER1805_RESERVEDFIELD1932_K2_E5 (0x7<<1) // Reserved
19937 …HY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1805_RESERVEDFIELD1932_K2_E5_SHIFT 1
19943 …S_REFCLK_RESERVEDREGISTER1806_RESERVEDFIELD1935_K2_E5 (0x1<<1) // Reserved
19944 …HY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1806_RESERVEDFIELD1935_K2_E5_SHIFT 1
19957 …S_REFCLK_RESERVEDREGISTER1810_RESERVEDFIELD1942_K2_E5 (0x1<<1) // Reserved
19958 …HY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1810_RESERVEDFIELD1942_K2_E5_SHIFT 1
19968 …S_REFCLK_RESERVEDREGISTER1813_RESERVEDFIELD1946_K2_E5 (0x1<<1) // Reserved
19969 …HY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1813_RESERVEDFIELD1946_K2_E5_SHIFT 1
19973 …S_REFCLK_STATUS0_RESERVEDFIELD1947_K2_E5 (0x1<<1) // Reserved
19974 …HY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_RESERVEDFIELD1947_K2_E5_SHIFT 1
19993 …FSM2_RESERVEDREGISTER1817_RESERVEDFIELD1953_K2_E5 (0xf<<1) // Reserved
19994 …HY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1817_RESERVEDFIELD1953_K2_E5_SHIFT 1
20047 …FSM2_RESERVEDREGISTER1841_RESERVEDFIELD1980_K2_E5 (0xf<<1) // Reserved
20048 …HY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1841_RESERVEDFIELD1980_K2_E5_SHIFT 1
20053 …L_PATTERN_SEL_K2_E5 (0xf<<1) // Selects the patt…
20054 …HY_NW_IP_REG_LN1_BIST_TX_CTRL_PATTERN_SEL_K2_E5_SHIFT 1
20062 … 0x00981cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
20063 … 0x009820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
20098 …1) // Selects the pattern to search for: 0x1 � PRBS 0xC1 0x2 � PRBS 0x221 0x3 � PRBS 0xA01 0x4 � P…
20099 …HY_NW_IP_REG_LN1_BIST_RX_CTRL_PATTERN_SEL_K2_E5_SHIFT 1
20100 …K2_E5 (0x1<<5) // Clears the bit error counter.
20104 …ces the PRBS LFSR to reseed with Rx data every cycle. This will cause the bit error counter to be…
20111 … 0x009a20UL //Access:R DataWidth:0x8 // Number of bit errors.
20112 … 0x009a24UL //Access:R DataWidth:0x8 // Number of bit errors.
20113 … 0x009a28UL //Access:R DataWidth:0x8 // Number of bit errors.
20121 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
20122 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
20123 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
20124 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
20126 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
20155 … (0x1<<0) // Configures AC/DC coupling of the lane 0: DC coupled 1: AC coupled
20163 …ATURE_RESERVEDREGISTER1847_RESERVEDFIELD1987_K2_E5 (0x1<<1) // Reserved
20164 …HY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1847_RESERVEDFIELD1987_K2_E5_SHIFT 1
20168 …ATURE_RESERVEDREGISTER1848_RESERVEDFIELD1989_K2_E5 (0x1<<1) // Reserved
20169 …HY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1848_RESERVEDFIELD1989_K2_E5_SHIFT 1
20181 …ATURE_RESERVEDREGISTER1849_RESERVEDFIELD1995_K2_E5 (0x1<<1) // Reserved
20182 …HY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1849_RESERVEDFIELD1995_K2_E5_SHIFT 1
20190 …ATURE_RESERVEDREGISTER1850_RESERVEDFIELD1999_K2_E5 (0x1<<1) // Reserved
20191 …HY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD1999_K2_E5_SHIFT 1
20207 …ATURE_RESERVEDREGISTER1851_RESERVEDFIELD2007_K2_E5 (0x1<<1) // Reserved
20208 …HY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1851_RESERVEDFIELD2007_K2_E5_SHIFT 1
20218 …ATURE_RESERVEDREGISTER1852_RESERVEDFIELD2012_K2_E5 (0x1<<1) // Reserved
20219 …HY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1852_RESERVEDFIELD2012_K2_E5_SHIFT 1
20231 …TURE_RESERVEDREGISTER1855_RESERVEDFIELD2017_K2_E5 (0x7f<<1) // Reserved
20232 …HY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1855_RESERVEDFIELD2017_K2_E5_SHIFT 1
20237 …ATURE_RESERVEDREGISTER1857_RESERVEDFIELD2020_K2_E5 (0x1<<1) // Reserved
20238 …HY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1857_RESERVEDFIELD2020_K2_E5_SHIFT 1
20242 …ATURE_RESERVEDREGISTER1858_RESERVEDFIELD2022_K2_E5 (0x1<<1) // Reserved
20243 …HY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1858_RESERVEDFIELD2022_K2_E5_SHIFT 1
20247 …ATURE_RESERVEDREGISTER1859_RESERVEDFIELD2024_K2_E5 (0x1<<1) // Reserved
20248 …HY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1859_RESERVEDFIELD2024_K2_E5_SHIFT 1
20255 … (0x3<<2) // How many times to repeat CTLE adaptation sequence for initial adaptation set 1
20272 …1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed…
20274 …1 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone c…
20283 …E_ADAPT_HFG_CFG0_INIT0_DATA_EN_K2_E5 (0x1<<1) // Enables CTLE EQ …
20284 …HY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_K2_E5_SHIFT 1
20285 … (0x1<<2) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 1
20287 … (0x1<<3) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 1
20300 … (0x3<<2) // Selects which HFG result to use for the initial adaptation set 1 0x0: Edge Based 0x1:…
20312 … (0x1<<1) // Enables CTLE midband shaping adaptation for initial a…
20313 …HY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_K2_E5_SHIFT 1
20321 …ATURE_RESERVEDREGISTER1862_RESERVEDFIELD2042_K2_E5 (0x1<<1) // Reserved
20322 …HY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2042_K2_E5_SHIFT 1
20336 … (0x1<<0) // Enables DFE Tap 1. Tap1 will not be po…
20338 …_CFG_TAP2_EN_K2_E5 (0x1<<1) // Enables DFE Tap …
20339 …HY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP2_EN_K2_E5_SHIFT 1
20347 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
20350 …_INIT_EN_K2_E5 (0x1<<0) // Enables initial adaptations for Tap 1
20352 …ATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2049_K2_E5 (0x1<<1) // Reserved
20353 …HY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2049_K2_E5_SHIFT 1
20361 …ATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2052_K2_E5 (0x1<<1) // Reserved
20362 …HY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2052_K2_E5_SHIFT 1
20370 …ATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2055_K2_E5 (0x1<<1) // Reserved
20371 …HY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2055_K2_E5_SHIFT 1
20379 …ATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2058_K2_E5 (0x1<<1) // Reserved
20380 …HY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2058_K2_E5_SHIFT 1
20388 …ATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2061_K2_E5 (0x1<<1) // Reserved
20389 …HY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2061_K2_E5_SHIFT 1
20397 …ATURE_ADAPT_CONT_CFG0_RESERVEDFIELD2064_K2_E5 (0x1<<1) // Reserved
20398 …HY_NW_IP_REG_LN1_FEATURE_ADAPT_CONT_CFG0_RESERVEDFIELD2064_K2_E5_SHIFT 1
20399 …UL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~279 mins
20400 …UL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~279 mins
20401 …UL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~279 mins
20435 …T_CFG0_RX_CTRL_DIS_K2_E5 (0x1<<1) // Disables the fir…
20436 …HY_NW_IP_REG_LN1_FEATURE_TEST_CFG0_RX_CTRL_DIS_K2_E5_SHIFT 1
20452 …TRL0_MR_TRAINING_ENABLE_K2_E5 (0x1<<1) // Indicates to LTS…
20453 …HY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE_K2_E5_SHIFT 1
20467 …TRL5_RX_TRAINED_K2_E5 (0x1<<1) // Input to LTSM in…
20468 …HY_NW_IP_REG_LN1_LT_TX_FSM_CTRL5_RX_TRAINED_K2_E5_SHIFT 1
20474 …TATUS_TRAINING_K2_E5 (0x1<<1) // Output from LTSM…
20475 …HY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_TRAINING_K2_E5_SHIFT 1
20476 …802.3 defined variable. This value is only visible internally, and is not the signal_det value dr…
20481 … 0 � CL72 1 + x^9 +x^11 1 � CL93 1 + x^5 + x^6 + x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3…
20488 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
20492 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
20499 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
20503 …E5 (0x3<<4) // Status report field for pre-cursor tap.
20520 …_TRAINING_K2_E5 (0x1<<1) // This is the 802.…
20521 …HY_NW_IP_REG_LN1_LT_RX_CTRL0_TRAINING_K2_E5_SHIFT 1
20523 …0 � CL72 1 + x^9 + x^11 1 � CL93 1 + x^5 + x^6 + x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3…
20525 … 0x009f0cUL //Access:RW DataWidth:0x8 // Maximum number of PRBS bit errors allowed in s…
20529 …STATUS0_LOCK_K2_E5 (0x1<<1) // Indicates that a…
20530 …HY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS0_LOCK_K2_E5_SHIFT 1
20531 … 0x009f18UL //Access:R DataWidth:0x8 // Number of bit errors in PRBS patt…
20546 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
20550 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
20557 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
20561 … (0x3<<4) // Received status report field for pre-cursor tap.
20568 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
20570 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0…
20571 …HY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_K2_E5_SHIFT 1
20572 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
20574 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission …
20596 …P_RESERVEDREGISTER1886_RESERVEDFIELD2092_K2_E5 (0x1<<1) // Reserved
20597 …HY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1886_RESERVEDFIELD2092_K2_E5_SHIFT 1
20650 …1) // Select value for TX data path mux in DPL. The corresponding mux select override enable must…
20651 …HY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_VAL_K2_E5_SHIFT 1
20654 …rols tx_en for Far-End-Digital FED loopback mode. In FED loopback mode, tx_en will be set when th…
20657 …<<0) // A mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NE…
20659 … (0x1<<1) // A bit stripping selection for RX data path in …
20660 …HY_NW_IP_REG_LN2_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN_K2_E5_SHIFT 1
20692 …P_RESERVEDREGISTER1902_RESERVEDFIELD2122_K2_E5 (0x1<<1) // Reserved
20693 …HY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1902_RESERVEDFIELD2122_K2_E5_SHIFT 1
20700 … (0x7<<1) // lnX_data_width_i override value for TX. It takes effect when ovr_en is 1. 0x5-…
20701 …HY_NW_IP_REG_LN2_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_K2_E5_SHIFT 1
20702 … (0x7<<4) // lnX_data_width_i override value for RX. It takes effect when ovr_en is 1.
20728 …P_RESERVEDREGISTER1907_RESERVEDFIELD2134_K2_E5 (0x3<<1) // Reserved
20729 …HY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1907_RESERVEDFIELD2134_K2_E5_SHIFT 1
20735 …P_RESERVEDREGISTER1908_RESERVEDFIELD2137_K2_E5 (0x1<<1) // Reserved
20736 …HY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1908_RESERVEDFIELD2137_K2_E5_SHIFT 1
20742 …P_RESERVEDREGISTER1909_RESERVEDFIELD2140_K2_E5 (0x3<<1) // Reserved
20743 …HY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1909_RESERVEDFIELD2140_K2_E5_SHIFT 1
20747 …P_RESERVEDREGISTER1910_RESERVEDFIELD2142_K2_E5 (0x3<<1) // Reserved
20748 …HY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1910_RESERVEDFIELD2142_K2_E5_SHIFT 1
20761 …P_RESERVEDREGISTER1912_RESERVEDFIELD2148_K2_E5 (0x1<<1) // Reserved
20762 …HY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1912_RESERVEDFIELD2148_K2_E5_SHIFT 1
20780 …P_RESERVEDREGISTER1915_RESERVEDFIELD2156_K2_E5 (0x1<<1) // Reserved
20781 …HY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1915_RESERVEDFIELD2156_K2_E5_SHIFT 1
20782 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
20783 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
20785 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
20836 …R_RXCLK_RESERVEDREGISTER1934_RESERVEDFIELD2177_K2_E5 (0x1<<1) // Reserved
20837 …HY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1934_RESERVEDFIELD2177_K2_E5_SHIFT 1
20852 … 0x00a2fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
20854 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
20859 …LPF_STATUS4_DLPF_TOO_LOW_K2_E5 (0x1<<1) // Indicates that D…
20860 …HY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_K2_E5_SHIFT 1
20861 …s of lock indicator. 1 means lock has been lost. Once lock is lost, this status is sticky until c…
20864 … (0x1<<0) // CDR lock indicator. 1 means lock is achiev…
20900 …R_RXCLK_RESERVEDREGISTER1951_RESERVEDFIELD2200_K2_E5 (0x1<<1) // Reserved
20901 …HY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1951_RESERVEDFIELD2200_K2_E5_SHIFT 1
20937 …R_REFCLK_RESERVEDREGISTER1964_RESERVEDFIELD2217_K2_E5 (0x1<<1) // Reserved
20938 …HY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1964_RESERVEDFIELD2217_K2_E5_SHIFT 1
20977 …R_REFCLK_RESERVEDREGISTER1972_RESERVEDFIELD2233_K2_E5 (0x1<<1) // Reserved
20978 …HY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1972_RESERVEDFIELD2233_K2_E5_SHIFT 1
20994 …EG_RESERVEDREGISTER1979_RESERVEDFIELD2241_K2_E5 (0x1<<1) // Reserved
20995 …HY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1979_RESERVEDFIELD2241_K2_E5_SHIFT 1
21019 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
21024 …G_CTRL0_RESERVEDFIELD2252_K2_E5 (0x7f<<1) // Reserved
21025 …HY_NW_IP_REG_LN2_ANEG_CTRL0_RESERVEDFIELD2252_K2_E5_SHIFT 1
21037 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
21041 …he ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks …
21048 … (0x1<<0) // Page Received. To clear it, write 1 to it.
21050 …1_AN_LINK_GOOD_K2_E5 (0x1<<1) // Autoneg has comp…
21051 …HY_NW_IP_REG_LN2_ANEG_STATUS1_AN_LINK_GOOD_K2_E5_SHIFT 1
21052 … (0x1<<2) // Autoneg Parallel Detection Fault. Write 1 to clear it.
21060 … 0x00a650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
21061 … 0x00a654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
21065 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
21068 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
21084 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
21086 …H0_ABILITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology …
21087 …HY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT 1
21088 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
21090 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
21092 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
21094 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
21096 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
21098 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
21101 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
21103 …1_ABILITY_25G_GR_S_K2_E5 (0x1<<1) // 25GBase-GR-S KR or CR te…
21104 …HY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT 1
21105 …LITY_25G_GR_K2_E5 (0x1<<2) // 25GBase-GR KR or CR technolog…
21107 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
21110 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
21113 …TY_K2_E5 (0x1<<0) // base page bit F0. It advertises …
21115 …EC_REQ_K2_E5 (0x1<<1) // base page bit F1. It req…
21116 …HY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_FEC_REQ_K2_E5_SHIFT 1
21117 … (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR…
21119 … (0x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-…
21122 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
21124 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consort…
21125 …HY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_25G_CR_K2_E5_SHIFT 1
21126 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
21128 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
21130 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
21132 …// Extended advertised FEC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consorti…
21134 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
21136 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
21157 …EG_RESERVEDREGISTER1997_RESERVEDFIELD2265_K2_E5 (0x1<<1) // Reserved
21158 …HY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2265_K2_E5_SHIFT 1
21174 …EG_RESERVEDREGISTER1998_RESERVEDFIELD2273_K2_E5 (0x1<<1) // Reserved
21175 …HY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2273_K2_E5_SHIFT 1
21189 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
21192 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
21210 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
21212 …ABILITY_10G_KX4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 tech…
21213 …HY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT 1
21214 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
21216 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
21218 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
21220 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
21222 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
21224 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
21227 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
21229 …ILITY_25G_GR_S_K2_E5 (0x1<<1) // Link partner 25GBase-GR-S KR or…
21230 …HY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT 1
21231 …R_K2_E5 (0x1<<2) // Link partner 25GBase-GR KR or CR technolog…
21233 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
21236 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
21239 … (0x1<<0) // Link partner base page bit F0. It advertises …
21241 …EQ_K2_E5 (0x1<<1) // Link partner base page bit F1. …
21242 …HY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_FEC_REQ_K2_E5_SHIFT 1
21243 … (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR…
21245 …1<<3) // Link partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-…
21248 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
21250 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G …
21251 …HY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_25G_CR_K2_E5_SHIFT 1
21252 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
21254 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
21256 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
21258 …er extended advertised FEC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consorti…
21260 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
21262 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
21283 …EG_RESERVEDREGISTER2005_RESERVEDFIELD2285_K2_E5 (0x1<<1) // Reserved
21284 …HY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2285_K2_E5_SHIFT 1
21300 …EG_RESERVEDREGISTER2006_RESERVEDFIELD2293_K2_E5 (0x1<<1) // Reserved
21301 …HY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2293_K2_E5_SHIFT 1
21313 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when status0.an_link_good is…
21315 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid when statu…
21316 …HY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT 1
21317 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when status0.an_link_good is…
21319 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid when status0.an_link_good i…
21321 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid when status0.an_link_good i…
21323 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid when status0.an_link_good i…
21325 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid when status0.an_link_good i…
21327 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid when status0.an_link_good i…
21330 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid when status0.an_link_good i…
21332 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is valid when …
21333 …HY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT 1
21334 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is valid when status0.an_link_go…
21336 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when status0.an_link_good is…
21338 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid when status0.an_link_good i…
21340 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid when status0.an_link_good i…
21342 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid when status0.an_link_good i…
21345 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is valid when status0.an_link_go…
21347 … (0x1<<1) // Resolution result for Firecode base page FEC. It is valid when…
21348 …HY_NW_IP_REG_LN2_ANEG_RESOLUTION_FEC_FC_K2_E5_SHIFT 1
21350 … (0x1<<0) // Resolution result for RX PAUSE enable. It is valid when status0.an_link_good is 1.
21352 … (0x1<<1) // Resolution result for TX PAUSE enable. It is valid when st…
21353 …HY_NW_IP_REG_LN2_ANEG_RESOLUTION_PAUSE_TX_K2_E5_SHIFT 1
21355 …1 if both the local device and the link partner advertise the EEE capability for the resolved PHY …
21358 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
21360 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
21361 …HY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_10G_KX4_K2_E5_SHIFT 1
21362 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
21364 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
21366 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
21368 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
21370 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
21372 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
21375 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
21377 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-…
21378 …HY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_25G_GR_K2_E5_SHIFT 1
21379 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
21381 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
21383 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
21385 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
21401 …E_RESERVEDREGISTER2010_RESERVEDFIELD2304_K2_E5 (0x3<<1) // Reserved
21402 …HY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2010_RESERVEDFIELD2304_K2_E5_SHIFT 1
21426 …Q_REFCLK_RESERVEDREGISTER2017_RESERVEDFIELD2316_K2_E5 (0x3<<1) // Reserved
21427 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2017_RESERVEDFIELD2316_K2_E5_SHIFT 1
21511 …Q_REFCLK_RESERVEDREGISTER2038_RESERVEDFIELD2354_K2_E5 (0x1<<1) // Reserved
21512 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2038_RESERVEDFIELD2354_K2_E5_SHIFT 1
21534 …Q_REFCLK_RESERVEDREGISTER2044_RESERVEDFIELD2363_K2_E5 (0x1<<1) // Reserved
21535 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2044_RESERVEDFIELD2363_K2_E5_SHIFT 1
21579 …Q_REFCLK_RESERVEDREGISTER2055_RESERVEDFIELD2380_K2_E5 (0x1<<1) // Reserved
21580 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2055_RESERVEDFIELD2380_K2_E5_SHIFT 1
21596 …Q_REFCLK_RESERVEDREGISTER2058_RESERVEDFIELD2387_K2_E5 (0x1<<1) // Reserved
21597 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2058_RESERVEDFIELD2387_K2_E5_SHIFT 1
21738 …Q_REFCLK_RESERVEDREGISTER2085_RESERVEDFIELD2443_K2_E5 (0x1<<1) // Reserved
21739 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2085_RESERVEDFIELD2443_K2_E5_SHIFT 1
21774 …Q_REFCLK_RESERVEDREGISTER2090_RESERVEDFIELD2454_K2_E5 (0x1<<1) // Reserved
21775 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2090_RESERVEDFIELD2454_K2_E5_SHIFT 1
21811 …Q_REFCLK_RESERVEDREGISTER2099_RESERVEDFIELD2468_K2_E5 (0x1<<1) // Reserved
21812 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2099_RESERVEDFIELD2468_K2_E5_SHIFT 1
21840 …Q_REFCLK_RESERVEDREGISTER2105_RESERVEDFIELD2479_K2_E5 (0x1<<1) // Reserved
21841 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2105_RESERVEDFIELD2479_K2_E5_SHIFT 1
21856 …Q_REFCLK_RESERVEDREGISTER2109_RESERVEDFIELD2487_K2_E5 (0x1<<1) // Reserved
21857 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2109_RESERVEDFIELD2487_K2_E5_SHIFT 1
21875 …Q_REFCLK_RESERVEDREGISTER2116_RESERVEDFIELD2498_K2_E5 (0x1<<1) // Reserved
21876 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2116_RESERVEDFIELD2498_K2_E5_SHIFT 1
21880 …Q_REFCLK_RESERVEDREGISTER2117_RESERVEDFIELD2500_K2_E5 (0x1<<1) // Reserved
21881 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2117_RESERVEDFIELD2500_K2_E5_SHIFT 1
21934 …_REFCLK_RESERVEDREGISTER2141_RESERVEDFIELD2521_K2_E5 (0x1f<<1) // Reserved
21935 …HY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2141_RESERVEDFIELD2521_K2_E5_SHIFT 1
21942 …V_REFCLK_RESERVEDREGISTER2143_RESERVEDFIELD2524_K2_E5 (0x1<<1) // Reserved
21943 …HY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2143_RESERVEDFIELD2524_K2_E5_SHIFT 1
21953 …V_REFCLK_RESERVEDREGISTER2144_RESERVEDFIELD2529_K2_E5 (0x1<<1) // Reserved
21954 …HY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2144_RESERVEDFIELD2529_K2_E5_SHIFT 1
21985 … (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until ack is 1. S…
21988 …ACK_K2_E5 (0x1<<0) // Set to 1 by firmware when upd…
21991 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
21997 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
22002 …V_REFCLK_RESERVEDREGISTER2151_RESERVEDFIELD2544_K2_E5 (0x1<<1) // Reserved
22003 …HY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2151_RESERVEDFIELD2544_K2_E5_SHIFT 1
22010 …V_REFCLK_RESERVEDREGISTER2152_RESERVEDFIELD2546_K2_E5 (0x1<<1) // Reserved
22011 …HY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2152_RESERVEDFIELD2546_K2_E5_SHIFT 1
22021 …V_REFCLK_RESERVEDREGISTER2153_RESERVEDFIELD2551_K2_E5 (0x1<<1) // Reserved
22022 …HY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2153_RESERVEDFIELD2551_K2_E5_SHIFT 1
22062 …E_REFCLK_RESERVEDREGISTER2162_RESERVEDFIELD2567_K2_E5 (0x1<<1) // Reserved
22063 …HY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2162_RESERVEDFIELD2567_K2_E5_SHIFT 1
22088 …E_REFCLK_RESERVEDREGISTER2166_RESERVEDFIELD2578_K2_E5 (0x3<<1) // Reserved
22089 …HY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2166_RESERVEDFIELD2578_K2_E5_SHIFT 1
22094 …E_REFCLK_RESERVEDREGISTER2168_RESERVEDFIELD2581_K2_E5 (0xf<<1) // Reserved
22095 …HY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2168_RESERVEDFIELD2581_K2_E5_SHIFT 1
22106 … (0x1<<0) // Write 1 to request a command CMD execution. It should be held at 1 unti…
22108 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Other…
22109 …HY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_CMD_K2_E5_SHIFT 1
22112 …BEFORE_EVAL_K2_E5 (0x1<<7) // Set it to 1 when changing DFE ta…
22132 … (0x1<<0) // Acknowledge from DFE after command execution. Will be set to 1 after a command is c…
22134 …E_REFCLK_FSM_STATUS0_RESERVEDFIELD2595_K2_E5 (0x1<<1) // Reserved
22135 …HY_NW_IP_REG_LN2_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD2595_K2_E5_SHIFT 1
22141 … (0x1<<0) // Enables updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - D…
22143 … (0x1<<1) // Enables updating Tap 1 Even 1 Path when FSM LOAD_ONLY command …
22144 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_K2_E5_SHIFT 1
22145 … (0x1<<2) // Enables updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - D…
22147 … (0x1<<3) // Enables updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - D…
22149 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22151 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22153 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22155 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22158 …// Starting value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields …
22160 …0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
22163 …// Starting value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields …
22165 …1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
22168 … // Starting value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields …
22170 …_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
22173 … // Starting value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields …
22175 …_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
22180 …4_TAP2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
22185 …5_TAP3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
22190 …6_TAP4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
22195 …7_TAP5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
22198 … // Loading value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields …
22200 …_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
22203 … // Loading value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields …
22205 …_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
22208 …) // Loading value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields …
22210 …POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
22213 …) // Loading value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields …
22215 …POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
22220 …_TAP2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
22225 …_TAP3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
22230 …_TAP4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
22235 …_TAP5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
22238 …2_E5 (0x1f<<0) // binary value for Tap 1 Even 0 Path for Tap …
22240 …P1_EVEN0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
22243 … (0x1f<<0) // binary value for Tap 1 Even 1 Path for Tap Adap…
22245 …P1_EVEN1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
22248 …E5 (0x1f<<0) // binary value for Tap 1 Odd 0 Path for Tap A…
22250 …P1_ODD0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
22253 … (0x1f<<0) // binary value for Tap 1 Odd 1 Path for Tap Adap…
22255 …P1_ODD1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
22260 …P2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
22265 …P3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
22270 …P4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
22275 …P5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
22280 …E_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2599_K2_E5 (0x1<<1) // Reserved
22281 …HY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2599_K2_E5_SHIFT 1
22351 …E_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2625_K2_E5 (0x1<<1) // Reserved
22352 …HY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2625_K2_E5_SHIFT 1
22368 …E_REFCLK_RESERVEDREGISTER2199_RESERVEDFIELD2633_K2_E5 (0x1<<1) // Reserved
22369 …HY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2199_RESERVEDFIELD2633_K2_E5_SHIFT 1
22375 …E_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2636_K2_E5 (0x1<<1) // Reserved
22376 …HY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2636_K2_E5_SHIFT 1
22403 …E_RXCLK_RESERVEDREGISTER2204_RESERVEDFIELD2649_K2_E5 (0x1<<1) // Reserved
22404 …HY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2204_RESERVEDFIELD2649_K2_E5_SHIFT 1
22412 …E_RXCLK_RESERVEDREGISTER2207_RESERVEDFIELD2653_K2_E5 (0x1<<1) // Reserved
22413 …HY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2207_RESERVEDFIELD2653_K2_E5_SHIFT 1
22425 …E_RXCLK_RESERVEDREGISTER2212_RESERVEDFIELD2659_K2_E5 (0x1<<1) // Reserved
22426 …HY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2212_RESERVEDFIELD2659_K2_E5_SHIFT 1
22537 …E_RXCLK_RESERVEDREGISTER2264_RESERVEDFIELD2717_K2_E5 (0x1<<1) // Reserved
22538 …HY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2264_RESERVEDFIELD2717_K2_E5_SHIFT 1
22567 …2_E5 (0x1<<0) // Enables the run-length detection digi…
22569 … 0x00b410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
22571 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
22573 … (0x1<<1) // Indicates that the run-length filter has, at some time, exce…
22574 …HY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_K2_E5_SHIFT 1
22575 …of consecutive clk_i clock cycles that the analog LOS must remain a logic �1� before the output o…
22576 …of consecutive clk_i clock cycles that the analog LOS must remain a logic �1� before the output o…
22577 …onsecutive clk_i clock cycles that the raw analog LOS must remain a logic �1� before the output o…
22618 …S_REFCLK_RESERVEDREGISTER2289_RESERVEDFIELD2746_K2_E5 (0x7<<1) // Reserved
22619 …HY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2289_RESERVEDFIELD2746_K2_E5_SHIFT 1
22625 …S_REFCLK_RESERVEDREGISTER2290_RESERVEDFIELD2749_K2_E5 (0x1<<1) // Reserved
22626 …HY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2290_RESERVEDFIELD2749_K2_E5_SHIFT 1
22639 …S_REFCLK_RESERVEDREGISTER2294_RESERVEDFIELD2756_K2_E5 (0x1<<1) // Reserved
22640 …HY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2294_RESERVEDFIELD2756_K2_E5_SHIFT 1
22650 …S_REFCLK_RESERVEDREGISTER2297_RESERVEDFIELD2760_K2_E5 (0x1<<1) // Reserved
22651 …HY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2297_RESERVEDFIELD2760_K2_E5_SHIFT 1
22655 …S_REFCLK_STATUS0_RESERVEDFIELD2761_K2_E5 (0x1<<1) // Reserved
22656 …HY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_RESERVEDFIELD2761_K2_E5_SHIFT 1
22675 …FSM2_RESERVEDREGISTER2301_RESERVEDFIELD2767_K2_E5 (0xf<<1) // Reserved
22676 …HY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2301_RESERVEDFIELD2767_K2_E5_SHIFT 1
22729 …FSM2_RESERVEDREGISTER2325_RESERVEDFIELD2794_K2_E5 (0xf<<1) // Reserved
22730 …HY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2325_RESERVEDFIELD2794_K2_E5_SHIFT 1
22735 …L_PATTERN_SEL_K2_E5 (0xf<<1) // Selects the patt…
22736 …HY_NW_IP_REG_LN2_BIST_TX_CTRL_PATTERN_SEL_K2_E5_SHIFT 1
22744 … 0x00b81cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
22745 … 0x00b820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
22780 …1) // Selects the pattern to search for: 0x1 � PRBS 0xC1 0x2 � PRBS 0x221 0x3 � PRBS 0xA01 0x4 � P…
22781 …HY_NW_IP_REG_LN2_BIST_RX_CTRL_PATTERN_SEL_K2_E5_SHIFT 1
22782 …K2_E5 (0x1<<5) // Clears the bit error counter.
22786 …ces the PRBS LFSR to reseed with Rx data every cycle. This will cause the bit error counter to be…
22793 … 0x00ba20UL //Access:R DataWidth:0x8 // Number of bit errors.
22794 … 0x00ba24UL //Access:R DataWidth:0x8 // Number of bit errors.
22795 … 0x00ba28UL //Access:R DataWidth:0x8 // Number of bit errors.
22803 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
22804 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
22805 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
22806 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
22808 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
22837 … (0x1<<0) // Configures AC/DC coupling of the lane 0: DC coupled 1: AC coupled
22845 …ATURE_RESERVEDREGISTER2331_RESERVEDFIELD2801_K2_E5 (0x1<<1) // Reserved
22846 …HY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2331_RESERVEDFIELD2801_K2_E5_SHIFT 1
22850 …ATURE_RESERVEDREGISTER2332_RESERVEDFIELD2803_K2_E5 (0x1<<1) // Reserved
22851 …HY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2332_RESERVEDFIELD2803_K2_E5_SHIFT 1
22863 …ATURE_RESERVEDREGISTER2333_RESERVEDFIELD2809_K2_E5 (0x1<<1) // Reserved
22864 …HY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2333_RESERVEDFIELD2809_K2_E5_SHIFT 1
22872 …ATURE_RESERVEDREGISTER2334_RESERVEDFIELD2813_K2_E5 (0x1<<1) // Reserved
22873 …HY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2813_K2_E5_SHIFT 1
22889 …ATURE_RESERVEDREGISTER2335_RESERVEDFIELD2821_K2_E5 (0x1<<1) // Reserved
22890 …HY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2335_RESERVEDFIELD2821_K2_E5_SHIFT 1
22900 …ATURE_RESERVEDREGISTER2336_RESERVEDFIELD2826_K2_E5 (0x1<<1) // Reserved
22901 …HY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2336_RESERVEDFIELD2826_K2_E5_SHIFT 1
22913 …TURE_RESERVEDREGISTER2339_RESERVEDFIELD2831_K2_E5 (0x7f<<1) // Reserved
22914 …HY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2339_RESERVEDFIELD2831_K2_E5_SHIFT 1
22919 …ATURE_RESERVEDREGISTER2341_RESERVEDFIELD2834_K2_E5 (0x1<<1) // Reserved
22920 …HY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2341_RESERVEDFIELD2834_K2_E5_SHIFT 1
22924 …ATURE_RESERVEDREGISTER2342_RESERVEDFIELD2836_K2_E5 (0x1<<1) // Reserved
22925 …HY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2342_RESERVEDFIELD2836_K2_E5_SHIFT 1
22929 …ATURE_RESERVEDREGISTER2343_RESERVEDFIELD2838_K2_E5 (0x1<<1) // Reserved
22930 …HY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2343_RESERVEDFIELD2838_K2_E5_SHIFT 1
22937 … (0x3<<2) // How many times to repeat CTLE adaptation sequence for initial adaptation set 1
22954 …1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed…
22956 …1 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone c…
22965 …E_ADAPT_HFG_CFG0_INIT0_DATA_EN_K2_E5 (0x1<<1) // Enables CTLE EQ …
22966 …HY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_K2_E5_SHIFT 1
22967 … (0x1<<2) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 1
22969 … (0x1<<3) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 1
22982 … (0x3<<2) // Selects which HFG result to use for the initial adaptation set 1 0x0: Edge Based 0x1:…
22994 … (0x1<<1) // Enables CTLE midband shaping adaptation for initial a…
22995 …HY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_K2_E5_SHIFT 1
23003 …ATURE_RESERVEDREGISTER2346_RESERVEDFIELD2856_K2_E5 (0x1<<1) // Reserved
23004 …HY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2856_K2_E5_SHIFT 1
23018 … (0x1<<0) // Enables DFE Tap 1. Tap1 will not be po…
23020 …_CFG_TAP2_EN_K2_E5 (0x1<<1) // Enables DFE Tap …
23021 …HY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP2_EN_K2_E5_SHIFT 1
23029 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
23032 …_INIT_EN_K2_E5 (0x1<<0) // Enables initial adaptations for Tap 1
23034 …ATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2863_K2_E5 (0x1<<1) // Reserved
23035 …HY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2863_K2_E5_SHIFT 1
23043 …ATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2866_K2_E5 (0x1<<1) // Reserved
23044 …HY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2866_K2_E5_SHIFT 1
23052 …ATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2869_K2_E5 (0x1<<1) // Reserved
23053 …HY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2869_K2_E5_SHIFT 1
23061 …ATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2872_K2_E5 (0x1<<1) // Reserved
23062 …HY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2872_K2_E5_SHIFT 1
23070 …ATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2875_K2_E5 (0x1<<1) // Reserved
23071 …HY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2875_K2_E5_SHIFT 1
23079 …ATURE_ADAPT_CONT_CFG0_RESERVEDFIELD2878_K2_E5 (0x1<<1) // Reserved
23080 …HY_NW_IP_REG_LN2_FEATURE_ADAPT_CONT_CFG0_RESERVEDFIELD2878_K2_E5_SHIFT 1
23081 …UL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~279 mins
23082 …UL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~279 mins
23083 …UL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~279 mins
23117 …T_CFG0_RX_CTRL_DIS_K2_E5 (0x1<<1) // Disables the fir…
23118 …HY_NW_IP_REG_LN2_FEATURE_TEST_CFG0_RX_CTRL_DIS_K2_E5_SHIFT 1
23134 …TRL0_MR_TRAINING_ENABLE_K2_E5 (0x1<<1) // Indicates to LTS…
23135 …HY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE_K2_E5_SHIFT 1
23149 …TRL5_RX_TRAINED_K2_E5 (0x1<<1) // Input to LTSM in…
23150 …HY_NW_IP_REG_LN2_LT_TX_FSM_CTRL5_RX_TRAINED_K2_E5_SHIFT 1
23156 …TATUS_TRAINING_K2_E5 (0x1<<1) // Output from LTSM…
23157 …HY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_TRAINING_K2_E5_SHIFT 1
23158 …802.3 defined variable. This value is only visible internally, and is not the signal_det value dr…
23163 … 0 � CL72 1 + x^9 +x^11 1 � CL93 1 + x^5 + x^6 + x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3…
23170 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
23174 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
23181 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
23185 …E5 (0x3<<4) // Status report field for pre-cursor tap.
23202 …_TRAINING_K2_E5 (0x1<<1) // This is the 802.…
23203 …HY_NW_IP_REG_LN2_LT_RX_CTRL0_TRAINING_K2_E5_SHIFT 1
23205 …0 � CL72 1 + x^9 + x^11 1 � CL93 1 + x^5 + x^6 + x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3…
23207 … 0x00bf0cUL //Access:RW DataWidth:0x8 // Maximum number of PRBS bit errors allowed in s…
23211 …STATUS0_LOCK_K2_E5 (0x1<<1) // Indicates that a…
23212 …HY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS0_LOCK_K2_E5_SHIFT 1
23213 … 0x00bf18UL //Access:R DataWidth:0x8 // Number of bit errors in PRBS patt…
23228 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
23232 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
23239 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
23243 … (0x3<<4) // Received status report field for pre-cursor tap.
23250 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
23252 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0…
23253 …HY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_K2_E5_SHIFT 1
23254 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
23256 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission …
23278 …P_RESERVEDREGISTER2370_RESERVEDFIELD2906_K2_E5 (0x1<<1) // Reserved
23279 …HY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2370_RESERVEDFIELD2906_K2_E5_SHIFT 1
23332 …1) // Select value for TX data path mux in DPL. The corresponding mux select override enable must…
23333 …HY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_VAL_K2_E5_SHIFT 1
23336 …rols tx_en for Far-End-Digital FED loopback mode. In FED loopback mode, tx_en will be set when th…
23339 …<<0) // A mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NE…
23341 … (0x1<<1) // A bit stripping selection for RX data path in …
23342 …HY_NW_IP_REG_LN3_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN_K2_E5_SHIFT 1
23374 …P_RESERVEDREGISTER2386_RESERVEDFIELD2936_K2_E5 (0x1<<1) // Reserved
23375 …HY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2386_RESERVEDFIELD2936_K2_E5_SHIFT 1
23382 … (0x7<<1) // lnX_data_width_i override value for TX. It takes effect when ovr_en is 1. 0x5-…
23383 …HY_NW_IP_REG_LN3_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_K2_E5_SHIFT 1
23384 … (0x7<<4) // lnX_data_width_i override value for RX. It takes effect when ovr_en is 1.
23410 …P_RESERVEDREGISTER2391_RESERVEDFIELD2948_K2_E5 (0x3<<1) // Reserved
23411 …HY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2391_RESERVEDFIELD2948_K2_E5_SHIFT 1
23417 …P_RESERVEDREGISTER2392_RESERVEDFIELD2951_K2_E5 (0x1<<1) // Reserved
23418 …HY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2392_RESERVEDFIELD2951_K2_E5_SHIFT 1
23424 …P_RESERVEDREGISTER2393_RESERVEDFIELD2954_K2_E5 (0x3<<1) // Reserved
23425 …HY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2393_RESERVEDFIELD2954_K2_E5_SHIFT 1
23429 …P_RESERVEDREGISTER2394_RESERVEDFIELD2956_K2_E5 (0x3<<1) // Reserved
23430 …HY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2394_RESERVEDFIELD2956_K2_E5_SHIFT 1
23443 …P_RESERVEDREGISTER2396_RESERVEDFIELD2962_K2_E5 (0x1<<1) // Reserved
23444 …HY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2396_RESERVEDFIELD2962_K2_E5_SHIFT 1
23462 …P_RESERVEDREGISTER2399_RESERVEDFIELD2970_K2_E5 (0x1<<1) // Reserved
23463 …HY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2399_RESERVEDFIELD2970_K2_E5_SHIFT 1
23464 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
23465 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
23467 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
23518 …R_RXCLK_RESERVEDREGISTER2418_RESERVEDFIELD2991_K2_E5 (0x1<<1) // Reserved
23519 …HY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2418_RESERVEDFIELD2991_K2_E5_SHIFT 1
23534 … 0x00c2fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
23536 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
23541 …LPF_STATUS4_DLPF_TOO_LOW_K2_E5 (0x1<<1) // Indicates that D…
23542 …HY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_K2_E5_SHIFT 1
23543 …s of lock indicator. 1 means lock has been lost. Once lock is lost, this status is sticky until c…
23546 … (0x1<<0) // CDR lock indicator. 1 means lock is achiev…
23582 …R_RXCLK_RESERVEDREGISTER2435_RESERVEDFIELD3014_K2_E5 (0x1<<1) // Reserved
23583 …HY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2435_RESERVEDFIELD3014_K2_E5_SHIFT 1
23619 …R_REFCLK_RESERVEDREGISTER2448_RESERVEDFIELD3031_K2_E5 (0x1<<1) // Reserved
23620 …HY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2448_RESERVEDFIELD3031_K2_E5_SHIFT 1
23659 …R_REFCLK_RESERVEDREGISTER2456_RESERVEDFIELD3047_K2_E5 (0x1<<1) // Reserved
23660 …HY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2456_RESERVEDFIELD3047_K2_E5_SHIFT 1
23676 …EG_RESERVEDREGISTER2463_RESERVEDFIELD3055_K2_E5 (0x1<<1) // Reserved
23677 …HY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2463_RESERVEDFIELD3055_K2_E5_SHIFT 1
23701 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
23706 …G_CTRL0_RESERVEDFIELD3066_K2_E5 (0x7f<<1) // Reserved
23707 …HY_NW_IP_REG_LN3_ANEG_CTRL0_RESERVEDFIELD3066_K2_E5_SHIFT 1
23719 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
23723 …he ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks …
23730 … (0x1<<0) // Page Received. To clear it, write 1 to it.
23732 …1_AN_LINK_GOOD_K2_E5 (0x1<<1) // Autoneg has comp…
23733 …HY_NW_IP_REG_LN3_ANEG_STATUS1_AN_LINK_GOOD_K2_E5_SHIFT 1
23734 … (0x1<<2) // Autoneg Parallel Detection Fault. Write 1 to clear it.
23742 … 0x00c650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
23743 … 0x00c654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
23747 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
23750 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
23766 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
23768 …H0_ABILITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology …
23769 …HY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT 1
23770 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
23772 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
23774 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
23776 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
23778 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
23780 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
23783 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
23785 …1_ABILITY_25G_GR_S_K2_E5 (0x1<<1) // 25GBase-GR-S KR or CR te…
23786 …HY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT 1
23787 …LITY_25G_GR_K2_E5 (0x1<<2) // 25GBase-GR KR or CR technolog…
23789 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
23792 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
23795 …TY_K2_E5 (0x1<<0) // base page bit F0. It advertises …
23797 …EC_REQ_K2_E5 (0x1<<1) // base page bit F1. It req…
23798 …HY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_FEC_REQ_K2_E5_SHIFT 1
23799 … (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR…
23801 … (0x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-…
23804 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
23806 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consort…
23807 …HY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_25G_CR_K2_E5_SHIFT 1
23808 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
23810 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
23812 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
23814 …// Extended advertised FEC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consorti…
23816 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
23818 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
23839 …EG_RESERVEDREGISTER2481_RESERVEDFIELD3079_K2_E5 (0x1<<1) // Reserved
23840 …HY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3079_K2_E5_SHIFT 1
23856 …EG_RESERVEDREGISTER2482_RESERVEDFIELD3087_K2_E5 (0x1<<1) // Reserved
23857 …HY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3087_K2_E5_SHIFT 1
23871 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
23874 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
23892 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
23894 …ABILITY_10G_KX4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 tech…
23895 …HY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT 1
23896 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
23898 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
23900 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
23902 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
23904 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
23906 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
23909 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
23911 …ILITY_25G_GR_S_K2_E5 (0x1<<1) // Link partner 25GBase-GR-S KR or…
23912 …HY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT 1
23913 …R_K2_E5 (0x1<<2) // Link partner 25GBase-GR KR or CR technolog…
23915 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
23918 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
23921 … (0x1<<0) // Link partner base page bit F0. It advertises …
23923 …EQ_K2_E5 (0x1<<1) // Link partner base page bit F1. …
23924 …HY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_FEC_REQ_K2_E5_SHIFT 1
23925 … (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR…
23927 …1<<3) // Link partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-…
23930 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
23932 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G …
23933 …HY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_25G_CR_K2_E5_SHIFT 1
23934 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
23936 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
23938 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
23940 …er extended advertised FEC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consorti…
23942 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
23944 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
23965 …EG_RESERVEDREGISTER2489_RESERVEDFIELD3099_K2_E5 (0x1<<1) // Reserved
23966 …HY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3099_K2_E5_SHIFT 1
23982 …EG_RESERVEDREGISTER2490_RESERVEDFIELD3107_K2_E5 (0x1<<1) // Reserved
23983 …HY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3107_K2_E5_SHIFT 1
23995 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when status0.an_link_good is…
23997 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid when statu…
23998 …HY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4_K2_E5_SHIFT 1
23999 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when status0.an_link_good is…
24001 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid when status0.an_link_good i…
24003 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid when status0.an_link_good i…
24005 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid when status0.an_link_good i…
24007 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid when status0.an_link_good i…
24009 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid when status0.an_link_good i…
24012 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid when status0.an_link_good i…
24014 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is valid when …
24015 …HY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S_K2_E5_SHIFT 1
24016 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is valid when status0.an_link_go…
24018 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when status0.an_link_good is…
24020 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid when status0.an_link_good i…
24022 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid when status0.an_link_good i…
24024 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid when status0.an_link_good i…
24027 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is valid when status0.an_link_go…
24029 … (0x1<<1) // Resolution result for Firecode base page FEC. It is valid when…
24030 …HY_NW_IP_REG_LN3_ANEG_RESOLUTION_FEC_FC_K2_E5_SHIFT 1
24032 … (0x1<<0) // Resolution result for RX PAUSE enable. It is valid when status0.an_link_good is 1.
24034 … (0x1<<1) // Resolution result for TX PAUSE enable. It is valid when st…
24035 …HY_NW_IP_REG_LN3_ANEG_RESOLUTION_PAUSE_TX_K2_E5_SHIFT 1
24037 …1 if both the local device and the link partner advertise the EEE capability for the resolved PHY …
24040 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
24042 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
24043 …HY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_10G_KX4_K2_E5_SHIFT 1
24044 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
24046 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
24048 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
24050 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
24052 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
24054 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
24057 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
24059 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-…
24060 …HY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_25G_GR_K2_E5_SHIFT 1
24061 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
24063 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
24065 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
24067 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
24083 …E_RESERVEDREGISTER2494_RESERVEDFIELD3118_K2_E5 (0x3<<1) // Reserved
24084 …HY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2494_RESERVEDFIELD3118_K2_E5_SHIFT 1
24108 …Q_REFCLK_RESERVEDREGISTER2501_RESERVEDFIELD3130_K2_E5 (0x3<<1) // Reserved
24109 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2501_RESERVEDFIELD3130_K2_E5_SHIFT 1
24193 …Q_REFCLK_RESERVEDREGISTER2522_RESERVEDFIELD3168_K2_E5 (0x1<<1) // Reserved
24194 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2522_RESERVEDFIELD3168_K2_E5_SHIFT 1
24216 …Q_REFCLK_RESERVEDREGISTER2528_RESERVEDFIELD3177_K2_E5 (0x1<<1) // Reserved
24217 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2528_RESERVEDFIELD3177_K2_E5_SHIFT 1
24261 …Q_REFCLK_RESERVEDREGISTER2539_RESERVEDFIELD3194_K2_E5 (0x1<<1) // Reserved
24262 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2539_RESERVEDFIELD3194_K2_E5_SHIFT 1
24278 …Q_REFCLK_RESERVEDREGISTER2542_RESERVEDFIELD3201_K2_E5 (0x1<<1) // Reserved
24279 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2542_RESERVEDFIELD3201_K2_E5_SHIFT 1
24420 …Q_REFCLK_RESERVEDREGISTER2569_RESERVEDFIELD3257_K2_E5 (0x1<<1) // Reserved
24421 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2569_RESERVEDFIELD3257_K2_E5_SHIFT 1
24456 …Q_REFCLK_RESERVEDREGISTER2574_RESERVEDFIELD3268_K2_E5 (0x1<<1) // Reserved
24457 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2574_RESERVEDFIELD3268_K2_E5_SHIFT 1
24493 …Q_REFCLK_RESERVEDREGISTER2583_RESERVEDFIELD3282_K2_E5 (0x1<<1) // Reserved
24494 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2583_RESERVEDFIELD3282_K2_E5_SHIFT 1
24522 …Q_REFCLK_RESERVEDREGISTER2589_RESERVEDFIELD3293_K2_E5 (0x1<<1) // Reserved
24523 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2589_RESERVEDFIELD3293_K2_E5_SHIFT 1
24538 …Q_REFCLK_RESERVEDREGISTER2593_RESERVEDFIELD3301_K2_E5 (0x1<<1) // Reserved
24539 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2593_RESERVEDFIELD3301_K2_E5_SHIFT 1
24557 …Q_REFCLK_RESERVEDREGISTER2600_RESERVEDFIELD3312_K2_E5 (0x1<<1) // Reserved
24558 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2600_RESERVEDFIELD3312_K2_E5_SHIFT 1
24562 …Q_REFCLK_RESERVEDREGISTER2601_RESERVEDFIELD3314_K2_E5 (0x1<<1) // Reserved
24563 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2601_RESERVEDFIELD3314_K2_E5_SHIFT 1
24616 …_REFCLK_RESERVEDREGISTER2625_RESERVEDFIELD3335_K2_E5 (0x1f<<1) // Reserved
24617 …HY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2625_RESERVEDFIELD3335_K2_E5_SHIFT 1
24624 …V_REFCLK_RESERVEDREGISTER2627_RESERVEDFIELD3338_K2_E5 (0x1<<1) // Reserved
24625 …HY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2627_RESERVEDFIELD3338_K2_E5_SHIFT 1
24635 …V_REFCLK_RESERVEDREGISTER2628_RESERVEDFIELD3343_K2_E5 (0x1<<1) // Reserved
24636 …HY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2628_RESERVEDFIELD3343_K2_E5_SHIFT 1
24667 … (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until ack is 1. S…
24670 …ACK_K2_E5 (0x1<<0) // Set to 1 by firmware when upd…
24673 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
24679 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
24684 …V_REFCLK_RESERVEDREGISTER2635_RESERVEDFIELD3358_K2_E5 (0x1<<1) // Reserved
24685 …HY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2635_RESERVEDFIELD3358_K2_E5_SHIFT 1
24692 …V_REFCLK_RESERVEDREGISTER2636_RESERVEDFIELD3360_K2_E5 (0x1<<1) // Reserved
24693 …HY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2636_RESERVEDFIELD3360_K2_E5_SHIFT 1
24703 …V_REFCLK_RESERVEDREGISTER2637_RESERVEDFIELD3365_K2_E5 (0x1<<1) // Reserved
24704 …HY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2637_RESERVEDFIELD3365_K2_E5_SHIFT 1
24744 …E_REFCLK_RESERVEDREGISTER2646_RESERVEDFIELD3381_K2_E5 (0x1<<1) // Reserved
24745 …HY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2646_RESERVEDFIELD3381_K2_E5_SHIFT 1
24770 …E_REFCLK_RESERVEDREGISTER2650_RESERVEDFIELD3392_K2_E5 (0x3<<1) // Reserved
24771 …HY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2650_RESERVEDFIELD3392_K2_E5_SHIFT 1
24776 …E_REFCLK_RESERVEDREGISTER2652_RESERVEDFIELD3395_K2_E5 (0xf<<1) // Reserved
24777 …HY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2652_RESERVEDFIELD3395_K2_E5_SHIFT 1
24788 … (0x1<<0) // Write 1 to request a command CMD execution. It should be held at 1 unti…
24790 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Other…
24791 …HY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_CMD_K2_E5_SHIFT 1
24794 …BEFORE_EVAL_K2_E5 (0x1<<7) // Set it to 1 when changing DFE ta…
24814 … (0x1<<0) // Acknowledge from DFE after command execution. Will be set to 1 after a command is c…
24816 …E_REFCLK_FSM_STATUS0_RESERVEDFIELD3409_K2_E5 (0x1<<1) // Reserved
24817 …HY_NW_IP_REG_LN3_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD3409_K2_E5_SHIFT 1
24823 … (0x1<<0) // Enables updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - D…
24825 … (0x1<<1) // Enables updating Tap 1 Even 1 Path when FSM LOAD_ONLY command …
24826 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_K2_E5_SHIFT 1
24827 … (0x1<<2) // Enables updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - D…
24829 … (0x1<<3) // Enables updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - D…
24831 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24833 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24835 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24837 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24840 …// Starting value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields …
24842 …0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
24845 …// Starting value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields …
24847 …1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
24850 … // Starting value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields …
24852 …_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
24855 … // Starting value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields …
24857 …_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
24862 …4_TAP2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
24867 …5_TAP3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
24872 …6_TAP4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
24877 …7_TAP5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
24880 … // Loading value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields …
24882 …_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
24885 … // Loading value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields …
24887 …_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
24890 …) // Loading value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields …
24892 …POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
24895 …) // Loading value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields …
24897 …POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive Note that…
24902 …_TAP2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
24907 …_TAP3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
24912 …_TAP4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
24917 …_TAP5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
24920 …2_E5 (0x1f<<0) // binary value for Tap 1 Even 0 Path for Tap …
24922 …P1_EVEN0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
24925 … (0x1f<<0) // binary value for Tap 1 Even 1 Path for Tap Adap…
24927 …P1_EVEN1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
24930 …E5 (0x1f<<0) // binary value for Tap 1 Odd 0 Path for Tap A…
24932 …P1_ODD0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
24935 … (0x1f<<0) // binary value for Tap 1 Odd 1 Path for Tap Adap…
24937 …P1_ODD1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
24942 …P2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
24947 …P3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
24952 …P4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
24957 …P5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = negative, 1 = positive
24962 …E_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3413_K2_E5 (0x1<<1) // Reserved
24963 …HY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3413_K2_E5_SHIFT 1
25033 …E_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3439_K2_E5 (0x1<<1) // Reserved
25034 …HY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3439_K2_E5_SHIFT 1
25050 …E_REFCLK_RESERVEDREGISTER2683_RESERVEDFIELD3447_K2_E5 (0x1<<1) // Reserved
25051 …HY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2683_RESERVEDFIELD3447_K2_E5_SHIFT 1
25057 …E_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3450_K2_E5 (0x1<<1) // Reserved
25058 …HY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3450_K2_E5_SHIFT 1
25085 …E_RXCLK_RESERVEDREGISTER2688_RESERVEDFIELD3463_K2_E5 (0x1<<1) // Reserved
25086 …HY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2688_RESERVEDFIELD3463_K2_E5_SHIFT 1
25094 …E_RXCLK_RESERVEDREGISTER2691_RESERVEDFIELD3467_K2_E5 (0x1<<1) // Reserved
25095 …HY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2691_RESERVEDFIELD3467_K2_E5_SHIFT 1
25107 …E_RXCLK_RESERVEDREGISTER2696_RESERVEDFIELD3473_K2_E5 (0x1<<1) // Reserved
25108 …HY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2696_RESERVEDFIELD3473_K2_E5_SHIFT 1
25219 …E_RXCLK_RESERVEDREGISTER2748_RESERVEDFIELD3531_K2_E5 (0x1<<1) // Reserved
25220 …HY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2748_RESERVEDFIELD3531_K2_E5_SHIFT 1
25249 …2_E5 (0x1<<0) // Enables the run-length detection digi…
25251 … 0x00d410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
25253 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
25255 … (0x1<<1) // Indicates that the run-length filter has, at some time, exce…
25256 …HY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_K2_E5_SHIFT 1
25257 …of consecutive clk_i clock cycles that the analog LOS must remain a logic �1� before the output o…
25258 …of consecutive clk_i clock cycles that the analog LOS must remain a logic �1� before the output o…
25259 …onsecutive clk_i clock cycles that the raw analog LOS must remain a logic �1� before the output o…
25300 …S_REFCLK_RESERVEDREGISTER2773_RESERVEDFIELD3560_K2_E5 (0x7<<1) // Reserved
25301 …HY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2773_RESERVEDFIELD3560_K2_E5_SHIFT 1
25307 …S_REFCLK_RESERVEDREGISTER2774_RESERVEDFIELD3563_K2_E5 (0x1<<1) // Reserved
25308 …HY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2774_RESERVEDFIELD3563_K2_E5_SHIFT 1
25321 …S_REFCLK_RESERVEDREGISTER2778_RESERVEDFIELD3570_K2_E5 (0x1<<1) // Reserved
25322 …HY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2778_RESERVEDFIELD3570_K2_E5_SHIFT 1
25332 …S_REFCLK_RESERVEDREGISTER2781_RESERVEDFIELD3574_K2_E5 (0x1<<1) // Reserved
25333 …HY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2781_RESERVEDFIELD3574_K2_E5_SHIFT 1
25337 …S_REFCLK_STATUS0_RESERVEDFIELD3575_K2_E5 (0x1<<1) // Reserved
25338 …HY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_RESERVEDFIELD3575_K2_E5_SHIFT 1
25357 …FSM2_RESERVEDREGISTER2785_RESERVEDFIELD3581_K2_E5 (0xf<<1) // Reserved
25358 …HY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2785_RESERVEDFIELD3581_K2_E5_SHIFT 1
25411 …FSM2_RESERVEDREGISTER2809_RESERVEDFIELD3608_K2_E5 (0xf<<1) // Reserved
25412 …HY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2809_RESERVEDFIELD3608_K2_E5_SHIFT 1
25417 …L_PATTERN_SEL_K2_E5 (0xf<<1) // Selects the patt…
25418 …HY_NW_IP_REG_LN3_BIST_TX_CTRL_PATTERN_SEL_K2_E5_SHIFT 1
25426 … 0x00d81cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
25427 … 0x00d820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
25462 …1) // Selects the pattern to search for: 0x1 � PRBS 0xC1 0x2 � PRBS 0x221 0x3 � PRBS 0xA01 0x4 � P…
25463 …HY_NW_IP_REG_LN3_BIST_RX_CTRL_PATTERN_SEL_K2_E5_SHIFT 1
25464 …K2_E5 (0x1<<5) // Clears the bit error counter.
25468 …ces the PRBS LFSR to reseed with Rx data every cycle. This will cause the bit error counter to be…
25475 … 0x00da20UL //Access:R DataWidth:0x8 // Number of bit errors.
25476 … 0x00da24UL //Access:R DataWidth:0x8 // Number of bit errors.
25477 … 0x00da28UL //Access:R DataWidth:0x8 // Number of bit errors.
25485 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
25486 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
25487 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
25488 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
25490 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
25519 … (0x1<<0) // Configures AC/DC coupling of the lane 0: DC coupled 1: AC coupled
25527 …ATURE_RESERVEDREGISTER2815_RESERVEDFIELD3615_K2_E5 (0x1<<1) // Reserved
25528 …HY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2815_RESERVEDFIELD3615_K2_E5_SHIFT 1
25532 …ATURE_RESERVEDREGISTER2816_RESERVEDFIELD3617_K2_E5 (0x1<<1) // Reserved
25533 …HY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2816_RESERVEDFIELD3617_K2_E5_SHIFT 1
25545 …ATURE_RESERVEDREGISTER2817_RESERVEDFIELD3623_K2_E5 (0x1<<1) // Reserved
25546 …HY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2817_RESERVEDFIELD3623_K2_E5_SHIFT 1
25554 …ATURE_RESERVEDREGISTER2818_RESERVEDFIELD3627_K2_E5 (0x1<<1) // Reserved
25555 …HY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3627_K2_E5_SHIFT 1
25571 …ATURE_RESERVEDREGISTER2819_RESERVEDFIELD3635_K2_E5 (0x1<<1) // Reserved
25572 …HY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2819_RESERVEDFIELD3635_K2_E5_SHIFT 1
25582 …ATURE_RESERVEDREGISTER2820_RESERVEDFIELD3640_K2_E5 (0x1<<1) // Reserved
25583 …HY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2820_RESERVEDFIELD3640_K2_E5_SHIFT 1
25595 …TURE_RESERVEDREGISTER2823_RESERVEDFIELD3645_K2_E5 (0x7f<<1) // Reserved
25596 …HY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2823_RESERVEDFIELD3645_K2_E5_SHIFT 1
25601 …ATURE_RESERVEDREGISTER2825_RESERVEDFIELD3648_K2_E5 (0x1<<1) // Reserved
25602 …HY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2825_RESERVEDFIELD3648_K2_E5_SHIFT 1
25606 …ATURE_RESERVEDREGISTER2826_RESERVEDFIELD3650_K2_E5 (0x1<<1) // Reserved
25607 …HY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2826_RESERVEDFIELD3650_K2_E5_SHIFT 1
25611 …ATURE_RESERVEDREGISTER2827_RESERVEDFIELD3652_K2_E5 (0x1<<1) // Reserved
25612 …HY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2827_RESERVEDFIELD3652_K2_E5_SHIFT 1
25619 … (0x3<<2) // How many times to repeat CTLE adaptation sequence for initial adaptation set 1
25636 …1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed…
25638 …1 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone c…
25647 …E_ADAPT_HFG_CFG0_INIT0_DATA_EN_K2_E5 (0x1<<1) // Enables CTLE EQ …
25648 …HY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_K2_E5_SHIFT 1
25649 … (0x1<<2) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 1
25651 … (0x1<<3) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 1
25664 … (0x3<<2) // Selects which HFG result to use for the initial adaptation set 1 0x0: Edge Based 0x1:…
25676 … (0x1<<1) // Enables CTLE midband shaping adaptation for initial a…
25677 …HY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_K2_E5_SHIFT 1
25685 …ATURE_RESERVEDREGISTER2830_RESERVEDFIELD3670_K2_E5 (0x1<<1) // Reserved
25686 …HY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3670_K2_E5_SHIFT 1
25700 … (0x1<<0) // Enables DFE Tap 1. Tap1 will not be po…
25702 …_CFG_TAP2_EN_K2_E5 (0x1<<1) // Enables DFE Tap …
25703 …HY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP2_EN_K2_E5_SHIFT 1
25711 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
25714 …_INIT_EN_K2_E5 (0x1<<0) // Enables initial adaptations for Tap 1
25716 …ATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD3677_K2_E5 (0x1<<1) // Reserved
25717 …HY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD3677_K2_E5_SHIFT 1
25725 …ATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD3680_K2_E5 (0x1<<1) // Reserved
25726 …HY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD3680_K2_E5_SHIFT 1
25734 …ATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD3683_K2_E5 (0x1<<1) // Reserved
25735 …HY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD3683_K2_E5_SHIFT 1
25743 …ATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD3686_K2_E5 (0x1<<1) // Reserved
25744 …HY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD3686_K2_E5_SHIFT 1
25752 …ATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD3689_K2_E5 (0x1<<1) // Reserved
25753 …HY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD3689_K2_E5_SHIFT 1
25761 …ATURE_ADAPT_CONT_CFG0_RESERVEDFIELD3692_K2_E5 (0x1<<1) // Reserved
25762 …HY_NW_IP_REG_LN3_FEATURE_ADAPT_CONT_CFG0_RESERVEDFIELD3692_K2_E5_SHIFT 1
25763 …UL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~279 mins
25764 …UL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~279 mins
25765 …UL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~279 mins
25799 …T_CFG0_RX_CTRL_DIS_K2_E5 (0x1<<1) // Disables the fir…
25800 …HY_NW_IP_REG_LN3_FEATURE_TEST_CFG0_RX_CTRL_DIS_K2_E5_SHIFT 1
25816 …TRL0_MR_TRAINING_ENABLE_K2_E5 (0x1<<1) // Indicates to LTS…
25817 …HY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE_K2_E5_SHIFT 1
25831 …TRL5_RX_TRAINED_K2_E5 (0x1<<1) // Input to LTSM in…
25832 …HY_NW_IP_REG_LN3_LT_TX_FSM_CTRL5_RX_TRAINED_K2_E5_SHIFT 1
25838 …TATUS_TRAINING_K2_E5 (0x1<<1) // Output from LTSM…
25839 …HY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_TRAINING_K2_E5_SHIFT 1
25840 …802.3 defined variable. This value is only visible internally, and is not the signal_det value dr…
25845 … 0 � CL72 1 + x^9 +x^11 1 � CL93 1 + x^5 + x^6 + x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3…
25852 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
25856 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
25863 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
25867 …E5 (0x3<<4) // Status report field for pre-cursor tap.
25884 …_TRAINING_K2_E5 (0x1<<1) // This is the 802.…
25885 …HY_NW_IP_REG_LN3_LT_RX_CTRL0_TRAINING_K2_E5_SHIFT 1
25887 …0 � CL72 1 + x^9 + x^11 1 � CL93 1 + x^5 + x^6 + x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3…
25889 … 0x00df0cUL //Access:RW DataWidth:0x8 // Maximum number of PRBS bit errors allowed in s…
25893 …STATUS0_LOCK_K2_E5 (0x1<<1) // Indicates that a…
25894 …HY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS0_LOCK_K2_E5_SHIFT 1
25895 … 0x00df18UL //Access:R DataWidth:0x8 // Number of bit errors in PRBS patt…
25910 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
25914 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
25921 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
25925 … (0x3<<4) // Received status report field for pre-cursor tap.
25932 … (0xf<<0) // Static divider control for SOC0 The only access to this divi…
25934 … (0xf<<4) // Static divider control for SOC1 The only access to this divi…
25937 …rride for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Override for p…
25941 … (0x3<<5) // Static divider control for CMU GCFSM clock The only access to this divi…
25946 … (0x7<<0) // Static divider control for the SSC block The only access to this divi…
25950 … (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by…
25953 …AHB_PMA_CM_DIVNSEL_O_6_0_K2_E5 (0x7f<<0) // CMU N-divider setting
25965 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25966 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25967 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25969 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25971 … 0x000028UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
25972 … 0x00002cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
25973 … 0x000030UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
25974 … 0x000034UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
25975 … 0x000038UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
25976 … 0x00003cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
25977 … 0x000040UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
25978 … 0x000044UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
25979 … 0x000048UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
25980 … 0x00004cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
25981 … 0x000050UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
25982 … 0x000054UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
25983 … 0x000058UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
25984 … 0x00005cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
25985 … 0x000060UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
25986 … 0x000064UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
25990 …_X26_GCFSM_CMU_PMA_DATA_OVR_O_6_0_K2_E5 (0x7f<<1) // GCFSM pma_data_o…
25991 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X26_GCFSM_CMU_PMA_DATA_OVR_O_6_0_K2_E5_SHIFT 1
26004 …errides for the following functions: [0] - active high, Override Enable [1] - SOC…
26006 …errides for the following functions: [0] - active high, Override Enable [1] - REF…
26008 …errides for the following functions: [0] - active high, Override Enable [1] - LOC…
26010 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26013 …he following functions: [0] - active high, Override Enable [1] - SOC clock output…
26015 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26017 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26019 …errides for the following functions: [0] - active high, Override Enable [1] - IDD…
26022 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26024 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26026 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26028 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26031 …errides for the following functions: [0] - active high, Override Enable [1] - PCS…
26033 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26035 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26037 …errides for the following functions: [0] - active high, Override Enable [1] - LF …
26040 …errides for the following functions: [0] - active high, Override Enable [1] - LFI…
26042 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26044 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26096 …0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag ov…
26104 …PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycl…
26136 …0_X98_AHB_PMA_CM_PFD_FORCE_UP_O_K2_E5 (0x1<<1) // Force PFD to out…
26137 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_UP_O_K2_E5_SHIFT 1
26138 …2_E5 (0x1<<2) // Override enable for overriding N-div value
26157 …1_AHB_PMA_CM_DIVPSEL_O_K2_E5 (0x7f<<0) // CMU P-divider setting
26177 …0_X109_PMA_REFCLK_OE_R_O_K2_E5 (0x1<<1) // "Override for pr…
26178 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_R_O_K2_E5_SHIFT 1
26207 … // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down…
26214 … (0x3<<4) // Test i/p control source : 0-modulator 1-bypass modulator 2-modulator …
26216 … (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
26225 …TEMP_CAL_POLARITY_O_K2_E5 (0x1<<6) // chicken bit for counter polarity
26229 … 0x0001e0UL //Access:RW DataWidth:0x8 // Divider input for Div-by-N counter
26231 …P_CAL_CLK_DIV_O_14_8_K2_E5 (0x7f<<0) // Divider input for Div-by-N counter
26247 …0_X125_AHB_RX_TC_WAIT_NEXT_SAMPLE_K2_E5 (0x7<<1) // in txterm calibr…
26248 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_WAIT_NEXT_SAMPLE_K2_E5_SHIFT 1
26254 …_AHB_RX_TC_BIAS_OVR_K2_E5 (0x7<<1) // Bit 3:1 RX termination…
26255 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X126_AHB_RX_TC_BIAS_OVR_K2_E5_SHIFT 1
26259 …1) // Determines rate for PLL clock pcs_rate_o[0] : 0: VCO clock untouched 1: VCO clock …
26260 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X127_PCS_RATE_O_K2_E5_SHIFT 1
26261 … 0x000200UL //Access:RW DataWidth:0x8 // Bit 7:5 amux_ena[2:0] Bit 4:0 amux…
26263 …erride for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pi…
26271 … 0x000210UL //Access:RW DataWidth:0x8 // CMU Test Bus address 7-0
26273 …BUS_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
26285 … 0x000264UL //Access:RW DataWidth:0x8 // Inverts up_i when set to 1
26286 … 0x000268UL //Access:RW DataWidth:0x8 // Inverts up_i when set to 1
26287 … function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - …
26320 …0_X191_PD_BIAS_IDDQ_SETVAL_O_K2_E5 (0x1<<1) // MSM Function IDD…
26321 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_BIAS_IDDQ_SETVAL_O_K2_E5_SHIFT 1
26337 …0_X192_RESET_CMU_GCRX_IDDQ_SETVAL_O_K2_E5 (0x1<<1) // MSM Function IDD…
26338 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_GCRX_IDDQ_SETVAL_O_K2_E5_SHIFT 1
26354 …0_X193_REFCLK_EN_IDDQ_SETVAL_O_K2_E5 (0x1<<1) // MSM Function IDD…
26355 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_REFCLK_EN_IDDQ_SETVAL_O_K2_E5_SHIFT 1
26371 …0_X194_PD_BIAS_RST_SETVAL_O_K2_E5 (0x1<<1) // MSM Function RST…
26372 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_BIAS_RST_SETVAL_O_K2_E5_SHIFT 1
26388 …0_X195_RESET_CMU_GCRX_RST_SETVAL_O_K2_E5 (0x1<<1) // MSM Function RST…
26389 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_GCRX_RST_SETVAL_O_K2_E5_SHIFT 1
26405 …0_X196_REFCLK_EN_RST_SETVAL_O_K2_E5 (0x1<<1) // MSM Function RST…
26406 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_REFCLK_EN_RST_SETVAL_O_K2_E5_SHIFT 1
26422 …0_X197_PD_BIAS_NORM_SETVAL_O_K2_E5 (0x1<<1) // MSM Function NOR…
26423 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_BIAS_NORM_SETVAL_O_K2_E5_SHIFT 1
26439 …0_X198_RESET_CMU_GCRX_NORM_SETVAL_O_K2_E5 (0x1<<1) // MSM Function NOR…
26440 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_GCRX_NORM_SETVAL_O_K2_E5_SHIFT 1
26456 …0_X199_REFCLK_EN_NORM_SETVAL_O_K2_E5 (0x1<<1) // MSM Function NOR…
26457 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_REFCLK_EN_NORM_SETVAL_O_K2_E5_SHIFT 1
26473 …0_X200_PD_BIAS_PD_SETVAL_O_K2_E5 (0x1<<1) // MSM Function POW…
26474 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_BIAS_PD_SETVAL_O_K2_E5_SHIFT 1
26490 …0_X201_RESET_CMU_GCRX_PD_SETVAL_O_K2_E5 (0x1<<1) // MSM Function POW…
26491 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_GCRX_PD_SETVAL_O_K2_E5_SHIFT 1
26507 …0_X202_REFCLK_EN_PD_SETVAL_O_K2_E5 (0x1<<1) // MSM Function POW…
26508 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_REFCLK_EN_PD_SETVAL_O_K2_E5_SHIFT 1
26523 …1 clock : 3'b000 - lnX_clk_i 3'b001- qd_ck_i 3'b010 - pma_lX_rxb_iRecovered byte clock 3'b011 - c…
26525 … (0x1<<3) // Clock divider for TX path branch 1 : 0-No division, 1- Divide by 2
26527 …h branch 2 clock : 3'b000 - lnX_clk_i 3'b001- qd_ck_i 3'b011 - ck_soc1_int_root 3'b010,3'b100,3'b1…
26529 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
26532 …ch 1 clock : 3'b000 - pma_lX_rxb_iRecovered byte clock 3'b001- pma_lX_txb_iTransmit byte clock 3'b…
26534 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
26536 …ck : 3'b000 - pma_lX_rxb_iRecovered byte clock 3'b001- pma_lX_txb_iTransmit byte clock 3'b010,3'b0…
26538 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
26541 …- qd_ck_i 3'b001- pma_lX_rxb_iRecovered byte clock 3'b010 - lnX_clk_i 3'b011 - pma_lX_txb_iTransmi…
26543 … (0x1<<3) // Clock divider for RX path branch 3 : 0-No division, 1- Divide by 2
26545 …- qd_ck_i 3'b001- pma_lX_rxb_iRecovered byte clock 3'b010 - lnX_clk_i 3'b011 - pma_lX_txb_iTransmi…
26547 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
26550 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
26552 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 C…
26553 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X3_PMA_TXCLK_SEL_O_1_K2_E5_SHIFT 1
26555 …0_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
26557 … (0x3<<2) // Static divider control for Lane GCFSM clock The only access to this divi…
26560 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
26562 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
26567 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
26569 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
26575 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
26577 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
26582 …3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends norm…
26584 …/ Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ev…
26586 … 0x001024UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
26587 … 0x001028UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
26588 … 0x00102cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
26589 … 0x001030UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
26590 …// Bist generator - Number of words between insert word insertions. Insertions are done in both pr…
26592 …// Bist generator - Number of words between insert word insertions. Insertions are done in both pr…
26599 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
26607 …checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be…
26609 …checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be…
26613 …_ON_ZEROS_K2_E5 (0x1<<5) // Setting this bit allows BIST to sync…
26619 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
26620 … 0x001054UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26621 … 0x001058UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26622 … 0x00105cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26623 … 0x001060UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26631 … 0x001080UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
26632 … 0x001084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
26633 … 0x001088UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
26634 … 0x00108cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
26635 … 0x001090UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
26636 … 0x001094UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
26637 … 0x001098UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
26638 … 0x00109cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
26639 … 0x0010a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
26640 … 0x0010a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
26641 … 0x0010a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
26642 … 0x0010acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
26643 … 0x0010b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
26644 … 0x0010b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
26645 … 0x0010b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
26646 … 0x0010bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
26647 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA me…
26648 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
26649 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA me…
26650 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
26653 … (0x1f<<0) // The start length of DFE offset calibration, except for the 1st cycle.
26655 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
26657 …E5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
26659 …_K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
26661 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
26662 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
26663 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
26665 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
26667 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
26679 …lect, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion…
26680 …lect, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion…
26682 …2_E5 (0x3<<0) // Bit 0: Override enable for msm_ln_req Bit 1…
26684 …N_MSM_FUNC_IN_OVR_O_K2_E5 (0x3f<<2) // Bit 2: Override enable…
26712 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
26714 …1) // ATT wait control. Upon detection of signal, DFE ATT calibration is enabled, without CISEL be…
26715 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_CDR_CONTROL_ATT_CTRL_O_K2_E5_SHIFT 1
26716 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
26720 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
26721 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
26722 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
26724 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
26726 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
26756 …5 (0x3<<2) // EI Exit time cycles = timer_len_sel[1:0]+1*exit_timer_len_i[9…
26763 …_1_X86_NES_LB_ENA_O_K2_E5 (0x1<<1) // NES loopback ena…
26764 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X86_NES_LB_ENA_O_K2_E5_SHIFT 1
26770 …1_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_K2_E5 (0x7f<<1) // RX boost overrid…
26771 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_K2_E5_SHIFT 1
26776 …_O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
26778 … (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye …
26783 …_O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
26810 …e_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
26826 …x3<<6) // CDR phase detector proportional path enable bit 0: enables D4/D3 data/edge samplers bit …
26828 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
26830 …-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2…
26834 … (0x1<<3) // RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth
26836 …rides the ck_270 DFE clock "right" eye edge clock with the shifted clock. Only assert one of pma_l…
26838 …errides the ck_90 DFE clock "left" eye edge clock with the shifted clock. Only assert one of pma_l…
26846 …(0xf<<4) // TX coefficient polarity enable. Set to "1" for negative polarity. bit 0: Cm bit 1: C0 …
26875 …4) // when 1, the final tx term value is calibrated txterm value + tx_cxp_margin; when 0, the fina…
26877 …5) // when 1, the final tx term value is calibrated txterm value + tx_cxn_margin; when 0, the fina…
26889 … (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not c…
26891 … (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_slew_sld[1:0]
26894 …11f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx_slew_sld3f[2…
26898 …_1_X126_RXEQ_LN_RATE_OW_O_2_0_K2_E5 (0x7<<1) // These bits have …
26899 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE_OW_O_2_0_K2_E5_SHIFT 1
26900 … (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is l…
26902 … (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is l…
26904 … (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is l…
26906 … (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is l…
26909 …1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: en…
26912 …1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: en…
26962 …LIMIT_O_K2_E5 (0xf<<1) // Max limit value for BOOST auto-cal…
26963 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X143_BOOST_MAX_LIMIT_O_K2_E5_SHIFT 1
26964 …K2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
26975 …2_E5 (0xf<<4) // boost_adj_val This register Is not bit reversed
27003 … for comparator calibration select. Enabled by rxeq_ovr_en_o: 1: Calibrate DFE comparator 1 2: Cal…
27005 … (0x3<<3) // Override the value of rx_att_gain output to PMA when rx_att_gain_autocal_dis=1
27007 … (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_autocal_dis=1
27023 …DFE_TAP1_OVR_VAL_O_6_0_K2_E5 (0x7f<<0) // DFE Tap 1 Override Value
27041 … (0x1<<0) // This bit has similar function as txeq_rxrecal_init in COMLANE CSR. It is l…
27044 …2_E5 (0x1<<0) // cdfe enable bit. 1: enable cdfe when…
27046 …1) // The cdfe input word_i overwrite. …
27047 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X201_CDFE_WORD_OV_O_1_0_K2_E5_SHIFT 1
27048 … 0 10-bit or 20-bit mode. 2'b11: the mode_8b_…
27050 …1:0] overwrite. …
27056 …e calibration enable. 1: enable force cdfe calibration. 0: disable force cdfe calibration. Note…
27058 …e calibration enable. 1: enable force cdfe calibration. 0: disable force cdfe calibration. Note…
27060 …1: the cdfe calibration is enabled when EI exits and when rate is 2'b01 or 2'b10. …
27063 …1: the continuous cdfe calibration is enabled when the rate is 2'b01 or 2'b10. …
27065 …1) // Enables cdfe calibration during Txeq adaptation phase. …
27066 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL_K2_E5_SHIFT 1
27067 … 1: the cdfe calibratio…
27069 … (0x1<<3) // Enables the cdfe calibration in rate3. 1: enables cdfe calibr…
27071 … (0x1<<4) // Enables the cdfe calibration in rate2. 1: enables cdfe calibr…
27073 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
27074 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
27075 …-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
27077 … (0x1<<7) // cdfe coarse dll overwrite enable. 1: enable coarse dll o…
27083 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
27084 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
27085 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
27086 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
27087 …-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
27092 …bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enabl…
27095 …bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enabl…
27098 …) // Override for CMP1 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[1]
27113 …) // Override for CMP2 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[1]
27128 …) // Override for CMP3 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[1]
27143 …) // Override for CMP4 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[1]
27170 … (0x1<<4) // cdfe fine dll overwrite enable. 1: enable fine dll ove…
27175 …_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_K2_E5 (0x1<<1) //
27176 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_K2_E5_SHIFT 1
27188 …_1_X255_CDFE_DIR_OV_VAL_K2_E5 (0x1<<1) // Override value f…
27189 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_VAL_K2_E5_SHIFT 1
27190 … (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed…
27192 … (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed…
27194 … (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed…
27196 … (0x1<<5) // cdfe eye delay overwrite enable. 1: enable eye delay ov…
27198 … (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed…
27204 …1_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_K2_E5 (0x7f<<1) // This register re…
27205 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_K2_E5_SHIFT 1
27210 …LEV_OV_EN_K2_E5 (0x1<<1) // cdfe dlev overwrite enable. 1: en…
27211 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_DLEV_OV_EN_K2_E5_SHIFT 1
27212 …ister override for overriding adaptation comparator select bit [0] : override enable bit [4:1] : o…
27214 …override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : o…
27216 …override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : o…
27219 …Bit[0]: enable tap1 overwrite for cdfe. Bit[1]: enable tap2 overwrite for cdfe Bit[2]: enable tap3…
27241 …_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_K2_E5 (0x1<<1) //
27242 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_K2_E5_SHIFT 1
27250 …_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_STROBE_EN_O_K2_E5 (0x1<<1) //
27251 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_STROBE_EN_O_K2_E5_SHIFT 1
27288 …_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_ra Bit …
27290 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_p2s Bit…
27292 …_O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_reset_lnregh Bi…
27294 …_O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_reset_lnreg Bi…
27297 …O_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_cdr Bit…
27299 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_dfe Bit…
27301 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_pd_lnregh Bit…
27303 …O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_pd_vco_buf Bit…
27306 …R_O_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_cdr_gcrx B…
27308 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_rxgate_en Bit…
27310 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_reset_vco Bit…
27312 …_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_iddq_sd Bit …
27315 …K2_E5 (0x3<<0) // Bit 0: Override enable for msm_pd_dfe Bit 1…
27317 …_O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_pd_dfe_bias Bi…
27319 …R_O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_txdrv_lp_idle B…
27321 …VR_O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_txreg_bleed_ena …
27324 …_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_pd_txreg Bit …
27326 …_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_pd_lnreg Bit …
27328 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for pd_p2s Bit 1: …
27330 …O_K2_E5 (0x3<<6) // Bit 0: Override enable for pd_ra Bit 1: …
27333 …VR_O_K2_E5 (0x3<<2) // Bit 0: Override enable for pd_slv_bias Bit …
27335 …_O_K2_E5 (0x3<<4) // Bit 0: Override enable for pd_txdrv Bit 1:…
27337 …K2_E5 (0x3<<6) // Bit 0: Override enable for msm_pd_vco Bit 1…
27340 …K2_E5 (0x3<<0) // Bit 0: Override enable for msm_cdr_en Bit 1…
27342 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_s2p Bit…
27344 …_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_rxclk_en Bit …
27346 …2_E5 (0x3<<6) // Bit 0: Override enable for msm_word Bit 1:…
27349 …_E5 (0x7<<0) // Bit 0: Override enable for msm_rate Bit [2:…
27351 …K2_E5 (0x7<<3) // Bit 0: Override enable for msm_rxvcodiv Bit […
27356 …K2_E5 (0x7<<0) // Bit 0: Override enable for msm_txvcodiv Bit […
27359 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
27361 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmo…
27362 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_TREG0_POL_O_K2_E5_SHIFT 1
27363 …0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
27365 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27369 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
27372 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
27374 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmod…
27375 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_TREG1_BIT_O_K2_E5_SHIFT 1
27376 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27378 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
27380 …(0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
27382 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27387 …(0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
27389 … (0x1<<1) // Reg0 data bank word order select. 0 - Normal word order used - words are not …
27390 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_REG0_WORD_O_K2_E5_SHIFT 1
27393 …03_TX_CTRL_O_24_K2_E5 (0x1<<5) // Bit 24: txdrv_c2_in[3]
27395 …CHNG_EN_O_K2_E5 (0x1<<6) // Enable bit for width_chng modu…
27402 … (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2�b00: no bit stripping 2�b01: 2x bit st…
27407 … communication between the external 64-bit data and the internal 20-bit data. The reading operatio…
27409 …Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2�b00: no bit stuf…
27411 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
27431 … (0x1<<0) // Mux select for data input to polbit_reg0 0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i
27433 … (0x1<<1) // To skip cdr calibration routines for PCIe gen3. Can be used when P…
27434 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN3_O_K2_E5_SHIFT 1
27446 …SR_1_X317_AHB_BEACON_ENA_OVR_O_K2_E5 (0x1<<1) // Beacon Override
27447 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_O_K2_E5_SHIFT 1
27452 …f<<4) // Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty…
27455 …_1_0_K2_E5 (0x3<<0) // Bit[0]: Overide value. Bit[1] :Overr…
27457 …x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the override, while bit 0 …
27459 … (0x3<<4) // Override enable for DFE signal detect indicator input. Bit 1 is overide enable …
27462 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override enable, bit 0 is …
27464 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override enable, bit 0 is …
27466 …x3<<4) // Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 …
27472 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
27473 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
27474 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
27475 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
27476 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
27477 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
27479 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
27481 … (0x1<<1) // Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is …
27482 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_AHB_LN_IN_OVR_CHG_FLAG_O_K2_E5_SHIFT 1
27488 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
27498 … (0x1<<0) // Lane Reference Clock Enable. 0 - gcfsm_refmux_clk = pma_cm_ref_clk_i 1 - …
27501 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
27503 …1) // Enable/Disable the internal PRBS data pattern inverter. 0x0 � Invert the PRBS data pattern f…
27504 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_GEN_INV_PRBS_O_K2_E5_SHIFT 1
27509 …818UL //Access:RW DataWidth:0x8 // Symbol aligner alignment word. Expects bit 0 received first
27511 … (0x3<<0) // Symbol aligner alignment word. Expects bit 0 received first
27521 …CSR_5_X43_CDR_CTRL_DLPF_RAIL_RST_EN_O_K2_E5 (0x1<<1) // Enable resetting…
27522 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X43_CDR_CTRL_DLPF_RAIL_RST_EN_O_K2_E5_SHIFT 1
27526 …SR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_VAL_O_K2_E5 (0x1f<<1) // Default DOSC adj…
27527 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_VAL_O_K2_E5_SHIFT 1
27533 …CSR_5_X49_EYE_SCAN_RUN_O_K2_E5 (0x1<<1) // Run eye scan cou…
27534 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_RUN_O_K2_E5_SHIFT 1
27551 … (0x3<<0) // Static divider control for Lane GCFSM clock The only access to this divi…
27553 … 0x0028e0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
27554 … 0x0028e4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
27555 … 0x0028e8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
27556 … 0x0028ecUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
27557 … 0x0028f0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
27558 … 0x0028f4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
27559 … 0x0028f8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
27560 … 0x0028fcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
27561 … 0x002900UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
27562 … 0x002904UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
27563 … 0x002908UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
27564 … 0x00290cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
27565 … 0x002910UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
27566 … 0x002914UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
27567 … 0x002918UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
27568 … 0x00291cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
27571 …nction. Varies depending on function number. Bits 15-7: Address of first command to run Bits: 6-…
27640 …M state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to rec…
27641 …M state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to rec…
27645 …CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_O_K2_E5 (0x1<<1) // MSM Function IDD…
27646 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_O_K2_E5_SHIFT 1
27662 …CSR_5_X144_MSM_SAPI_IDDQ_PD_TXDRV_O_K2_E5 (0x1<<1) // MSM Function IDD…
27663 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXDRV_O_K2_E5_SHIFT 1
27679 …CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREGH_O_K2_E5 (0x1<<1) // MSM Function IDD…
27680 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREGH_O_K2_E5_SHIFT 1
27696 …CSR_5_X146_MSM_SAPI_IDDQ_RXBCLK_EN_O_K2_E5 (0x1<<1) // MSM Function IDD…
27697 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RXBCLK_EN_O_K2_E5_SHIFT 1
27705 …CSR_5_X147_MSM_SAPI_RST_PD_DFE_O_K2_E5 (0x1<<1) // MSM Function RES…
27706 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_O_K2_E5_SHIFT 1
27722 …CSR_5_X148_MSM_SAPI_RST_PD_TXDRV_O_K2_E5 (0x1<<1) // MSM Function RES…
27723 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXDRV_O_K2_E5_SHIFT 1
27739 …CSR_5_X149_MSM_SAPI_RST_RESET_LNREGH_O_K2_E5 (0x1<<1) // MSM Function RES…
27740 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREGH_O_K2_E5_SHIFT 1
27756 …CSR_5_X150_MSM_SAPI_RST_RXBCLK_EN_O_K2_E5 (0x1<<1) // MSM Function RES…
27757 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RXBCLK_EN_O_K2_E5_SHIFT 1
27765 …CSR_5_X151_MSM_SAPI_NORM_PD_DFE_O_K2_E5 (0x1<<1) // MSM Function NOR…
27766 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_O_K2_E5_SHIFT 1
27782 …CSR_5_X152_MSM_SAPI_NORM_PD_TXDRV_O_K2_E5 (0x1<<1) // MSM Function NOR…
27783 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXDRV_O_K2_E5_SHIFT 1
27799 …CSR_5_X153_MSM_SAPI_NORM_RESET_LNREGH_O_K2_E5 (0x1<<1) // MSM Function NOR…
27800 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREGH_O_K2_E5_SHIFT 1
27816 …CSR_5_X154_MSM_SAPI_NORM_RXBCLK_EN_O_K2_E5 (0x1<<1) // MSM Function NOR…
27817 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RXBCLK_EN_O_K2_E5_SHIFT 1
27825 …CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_O_K2_E5 (0x1<<1) // MSM Function PAR…
27826 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_O_K2_E5_SHIFT 1
27842 …CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXDRV_O_K2_E5 (0x1<<1) // MSM Function PAR…
27843 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXDRV_O_K2_E5_SHIFT 1
27859 …CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREGH_O_K2_E5 (0x1<<1) // MSM Function PAR…
27860 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREGH_O_K2_E5_SHIFT 1
27876 …CSR_5_X158_MSM_SAPI_PARTIAL_RXBCLK_EN_O_K2_E5 (0x1<<1) // MSM Function PAR…
27877 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RXBCLK_EN_O_K2_E5_SHIFT 1
27885 …CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_O_K2_E5 (0x1<<1) // MSM Function SLU…
27886 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_O_K2_E5_SHIFT 1
27902 …CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXDRV_O_K2_E5 (0x1<<1) // MSM Function SLU…
27903 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXDRV_O_K2_E5_SHIFT 1
27919 …CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREGH_O_K2_E5 (0x1<<1) // MSM Function SLU…
27920 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREGH_O_K2_E5_SHIFT 1
27936 …CSR_5_X162_MSM_SAPI_SLUMBER_RXBCLK_EN_O_K2_E5 (0x1<<1) // MSM Function SLU…
27937 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RXBCLK_EN_O_K2_E5_SHIFT 1
27978 …_LOW_EN_O_K2_E5 (0x1<<6) // Brings the TxEq pre-cursor down to a prog…
27980 …LOW_EN_O_K2_E5 (0x1<<7) // Brings the TxEq pre-cursor down to a prog…
27998 … (0x1<<6) // Set all DFE calibration values to mid-scale instead of usin…
28000 … 0x002b5cUL //Access:RW DataWidth:0x8 // DFE block -continuous calibratio…
28002 …ONT_LENGTH_O_14_8_K2_E5 (0x7f<<0) // DFE block -continuous calibratio…
28004 … 0x002b64UL //Access:RW DataWidth:0x8 // DFE block - ATT calibration cycl…
28005 … 0x002b68UL //Access:RW DataWidth:0x8 // DFE block - Boost calibration cy…
28006 … 0x002b6cUL //Access:RW DataWidth:0x8 // DFE block - TAP1 calibration cyc…
28007 … 0x002b70UL //Access:RW DataWidth:0x8 // DFE block - TAP2 calibration cyc…
28008 … 0x002b74UL //Access:RW DataWidth:0x8 // DFE block - TAP3 calibration cyc…
28009 … 0x002b78UL //Access:RW DataWidth:0x8 // DFE block - TAP4 calibration cyc…
28010 … 0x002b7cUL //Access:RW DataWidth:0x8 // DFE block - TAP5 calibration cyc…
28014 …4_RXEQ_RECAL_O_6_0_K2_E5 (0x7f<<1) // Enables re-calibration f…
28015 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X224_RXEQ_RECAL_O_6_0_K2_E5_SHIFT 1
28017 …bit [0]: Enables ATT calibration when asserted bit [1]: Enables Boost calibration when asserted bi…
28020 …bit [0]: Enables ATT calibration when asserted bit [1]: Enables Boost calibration when asserted bi…
28023 …ATE2_RECAL_O_6_0_K2_E5 (0x7f<<0) // Enables re-calibration for { Tap…
28049 …SR_5_X233_RXEQ_FIN_HIGH_O_6_0_K2_E5 (0x7f<<1) // Enable final cal…
28050 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X233_RXEQ_FIN_HIGH_O_6_0_K2_E5_SHIFT 1
28054 … (0x1<<7) // Testbus select for comp_offset and tap_offset 1: Raw output from i_d…
28057 …bit [0]: Reverses polarity of ATT calibration when asserted bit [1]: Reverses polarity of Boost ca…
28164 …CSR_5_X273_TXEQ_ADAPT_RUN_1_0_K2_E5 (0x3<<1) // TxEQ Adapt 2 TAPs
28165 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X273_TXEQ_ADAPT_RUN_1_0_K2_E5_SHIFT 1
28170 …CSR_5_X275_TXEQ_ADAPT_INIT_O_1_K2_E5 (0x1<<1) // Initiate TXEQ ad…
28171 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X275_TXEQ_ADAPT_INIT_O_1_K2_E5_SHIFT 1
28173 …NE_I_3_0_K2_E5 (0xf<<0) // RXEQ calibration done status - per lane
28175 …ADAPT_DONE_I_3_0_K2_E5 (0xf<<4) // TXEQ Adapt Done status - per lane
28199 …g bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern b…
28202 …g bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern b…
28205 …g bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern b…
28208 …g bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern b…
28211 …g bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern b…
28214 …g bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern b…
28235 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
28238 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
28241 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
28244 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
28247 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
28250 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
28253 …bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enabl…
28256 …bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enabl…
28259 …bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enabl…
28262 …bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enabl…
28283 …/ Level of averaging used during cdfe dll coarse calibration 0: last data, 1: avg of last two dat…
28285 … // Level of averaging used during cdfe dll fine calibration 0: last data, 1: avg of last two dat…
28287 …<<4) // Level of averaging used during cdfe dlev calibration 0: last data, 1: avg of last two dat…
28293 …_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_COARSE_OV_FINE_EN_K2_E5 (0x1<<1) //
28294 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_COARSE_OV_FINE_EN_K2_E5_SHIFT 1
28354 …SR_5_X369_QAHB_TAP1_CM1_DONT_CARE_O_K2_E5 (0x3f<<1) // Mask bits for CM…
28355 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_TAP1_CM1_DONT_CARE_O_K2_E5_SHIFT 1
28377 …CSR_5_X376_MSM_PIPE_RST_PD_DFE_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28378 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_O_K2_E5_SHIFT 1
28394 …CSR_5_X377_MSM_PIPE_RST_PD_TXDRV_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28395 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXDRV_O_K2_E5_SHIFT 1
28411 …CSR_5_X378_MSM_PIPE_RST_RESET_LNREGH_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28412 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREGH_O_K2_E5_SHIFT 1
28428 …CSR_5_X379_MSM_PIPE_RST_RXBCLK_EN_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28429 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RXBCLK_EN_O_K2_E5_SHIFT 1
28437 …CSR_5_X380_MSM_PIPE_P0_PD_DFE_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28438 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_O_K2_E5_SHIFT 1
28454 …CSR_5_X381_MSM_PIPE_P0_PD_TXDRV_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28455 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXDRV_O_K2_E5_SHIFT 1
28471 …CSR_5_X382_MSM_PIPE_P0_RESET_LNREGH_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28472 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREGH_O_K2_E5_SHIFT 1
28488 …CSR_5_X383_MSM_PIPE_P0_RXBCLK_EN_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28489 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RXBCLK_EN_O_K2_E5_SHIFT 1
28497 …CSR_5_X384_MSM_PIPE_P1_PD_DFE_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28498 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_O_K2_E5_SHIFT 1
28514 …CSR_5_X385_MSM_PIPE_P1_PD_TXDRV_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28515 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXDRV_O_K2_E5_SHIFT 1
28531 …CSR_5_X386_MSM_PIPE_P1_RESET_LNREGH_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28532 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREGH_O_K2_E5_SHIFT 1
28548 …CSR_5_X387_MSM_PIPE_P1_RXBCLK_EN_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28549 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RXBCLK_EN_O_K2_E5_SHIFT 1
28557 …CSR_5_X388_MSM_PIPE_P2_PD_DFE_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28558 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_O_K2_E5_SHIFT 1
28574 …CSR_5_X389_MSM_PIPE_P2_PD_TXDRV_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28575 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXDRV_O_K2_E5_SHIFT 1
28591 …CSR_5_X390_MSM_PIPE_P2_RESET_LNREGH_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28592 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREGH_O_K2_E5_SHIFT 1
28608 …CSR_5_X391_MSM_PIPE_P2_RXBCLK_EN_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28609 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RXBCLK_EN_O_K2_E5_SHIFT 1
28624 …CSR_5_X401_L1_MASTER_CDN_O_K2_E5 (0x1<<1) // Lane1 master res…
28625 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L1_MASTER_CDN_O_K2_E5_SHIFT 1
28637 …E_I_2_0_K2_E5 (0x7<<0) // 1000Base-KX Mode status for CPU
28646 …X407_LN1_SIG_LEVEL_VALID_I_1_K2_E5 (0x1<<1) // Lane 1 Signal Detect V…
28647 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_SIG_LEVEL_VALID_I_1_K2_E5_SHIFT 1
28654 …_CSR_5_X407_LN1_OK_I_5_K2_E5 (0x1<<5) // Lane 1 OK Status
28663 …X408_LN1_RX_LOCKED_I_3_2_K2_E5 (0x3<<2) // Lane 1 RX Locked Status
28711 …CSR_5_X483_MSM_PIPE_P1_0_PD_VCO_BUF_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28712 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_VCO_BUF_O_K2_E5_SHIFT 1
28728 …CSR_5_X484_MSM_PIPE_P1_0_RESET_VCO_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28729 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_VCO_O_K2_E5_SHIFT 1
28745 …CSR_5_X485_MSM_PIPE_P1_0_PD_SLV_BIAS_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28746 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_SLV_BIAS_O_K2_E5_SHIFT 1
28762 …CSR_5_X486_MSM_PIPE_P1_0_TXREG_BLEED_ENA_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28763 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TXREG_BLEED_ENA_O_K2_E5_SHIFT 1
28771 …CSR_5_X487_MSM_PIPE_P1_1_PD_VCO_BUF_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28772 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_VCO_BUF_O_K2_E5_SHIFT 1
28788 …CSR_5_X488_MSM_PIPE_P1_1_RESET_VCO_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28789 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_VCO_O_K2_E5_SHIFT 1
28805 …CSR_5_X489_MSM_PIPE_P1_1_PD_SLV_BIAS_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28806 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_SLV_BIAS_O_K2_E5_SHIFT 1
28822 …CSR_5_X490_MSM_PIPE_P1_1_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28823 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 1
28831 …CSR_5_X491_MSM_PIPE_P1_2_PD_VCO_BUF_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28832 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_VCO_BUF_O_K2_E5_SHIFT 1
28848 …CSR_5_X492_MSM_PIPE_P1_2_RESET_DFE_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28849 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_DFE_O_K2_E5_SHIFT 1
28865 …CSR_5_X493_MSM_PIPE_P1_2_PD_S2P_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28866 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_S2P_O_K2_E5_SHIFT 1
28882 …CSR_5_X494_MSM_PIPE_P1_2_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
28883 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 1
28896 … (0xf<<0) // Static divider control for SOC0 The only access to this divi…
28898 … (0xf<<4) // Static divider control for SOC1 The only access to this divi…
28901 …rride for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Override for p…
28905 … (0x3<<5) // Static divider control for CMU GCFSM clock The only access to this divi…
28910 … (0x7<<0) // Static divider control for the SSC block The only access to this divi…
28914 … (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by…
28917 …_AHB_PMA_CM_DIVNSEL_O_6_0_K2_E5 (0x7f<<0) // CMU N-divider setting
28929 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28930 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28931 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28933 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28935 … 0x003028UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
28936 … 0x00302cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
28937 … 0x003030UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
28938 … 0x003034UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
28939 … 0x003038UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
28940 … 0x00303cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
28941 … 0x003040UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
28942 … 0x003044UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
28943 … 0x003048UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
28944 … 0x00304cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
28945 … 0x003050UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
28946 … 0x003054UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
28947 … 0x003058UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
28948 … 0x00305cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
28949 … 0x003060UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
28950 … 0x003064UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
28954 …6_X26_GCFSM_CMU_PMA_DATA_OVR_O_6_0_K2_E5 (0x7f<<1) // GCFSM pma_data_o…
28955 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X26_GCFSM_CMU_PMA_DATA_OVR_O_6_0_K2_E5_SHIFT 1
28968 …errides for the following functions: [0] - active high, Override Enable [1] - SOC…
28970 …errides for the following functions: [0] - active high, Override Enable [1] - REF…
28972 …errides for the following functions: [0] - active high, Override Enable [1] - LOC…
28974 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28977 …he following functions: [0] - active high, Override Enable [1] - SOC clock output…
28979 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28981 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28983 …errides for the following functions: [0] - active high, Override Enable [1] - IDD…
28986 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28988 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28990 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28992 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28995 …errides for the following functions: [0] - active high, Override Enable [1] - PCS…
28997 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28999 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29001 …errides for the following functions: [0] - active high, Override Enable [1] - LF …
29004 …errides for the following functions: [0] - active high, Override Enable [1] - LFI…
29006 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29008 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29060 …0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag ov…
29068 …PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycl…
29100 …_6_X98_AHB_PMA_CM_PFD_FORCE_UP_O_K2_E5 (0x1<<1) // Force PFD to out…
29101 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_PFD_FORCE_UP_O_K2_E5_SHIFT 1
29102 …K2_E5 (0x1<<2) // Override enable for overriding N-div value
29121 …01_AHB_PMA_CM_DIVPSEL_O_K2_E5 (0x7f<<0) // CMU P-divider setting
29141 …_6_X109_PMA_REFCLK_OE_R_O_K2_E5 (0x1<<1) // "Override for pr…
29142 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_OE_R_O_K2_E5_SHIFT 1
29171 … // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down…
29178 … (0x3<<4) // Test i/p control source : 0-modulator 1-bypass modulator 2-modulator …
29180 … (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
29189 …_TEMP_CAL_POLARITY_O_K2_E5 (0x1<<6) // chicken bit for counter polarity
29193 … 0x0031e0UL //Access:RW DataWidth:0x8 // Divider input for Div-by-N counter
29195 …MP_CAL_CLK_DIV_O_14_8_K2_E5 (0x7f<<0) // Divider input for Div-by-N counter
29211 …_6_X125_AHB_RX_TC_WAIT_NEXT_SAMPLE_K2_E5 (0x7<<1) // in txterm calibr…
29212 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X125_AHB_RX_TC_WAIT_NEXT_SAMPLE_K2_E5_SHIFT 1
29218 …6_AHB_RX_TC_BIAS_OVR_K2_E5 (0x7<<1) // Bit 3:1 RX termination…
29219 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X126_AHB_RX_TC_BIAS_OVR_K2_E5_SHIFT 1
29223 …1) // Determines rate for PLL clock pcs_rate_o[0] : 0: VCO clock untouched 1: VCO clock …
29224 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X127_PCS_RATE_O_K2_E5_SHIFT 1
29227 …erride for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pi…
29235 … 0x003210UL //Access:RW DataWidth:0x8 // CMU Test Bus address 7-0
29237 …TBUS_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
29249 … 0x003264UL //Access:RW DataWidth:0x8 // Inverts up_i when set to 1
29250 … 0x003268UL //Access:RW DataWidth:0x8 // Inverts up_i when set to 1
29251 … function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - …
29284 …_6_X191_PD_BIAS_IDDQ_SETVAL_O_K2_E5 (0x1<<1) // MSM Function IDD…
29285 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_BIAS_IDDQ_SETVAL_O_K2_E5_SHIFT 1
29301 …_6_X192_RESET_CMU_GCRX_IDDQ_SETVAL_O_K2_E5 (0x1<<1) // MSM Function IDD…
29302 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMU_GCRX_IDDQ_SETVAL_O_K2_E5_SHIFT 1
29318 …_6_X193_REFCLK_EN_IDDQ_SETVAL_O_K2_E5 (0x1<<1) // MSM Function IDD…
29319 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_REFCLK_EN_IDDQ_SETVAL_O_K2_E5_SHIFT 1
29335 …_6_X194_PD_BIAS_RST_SETVAL_O_K2_E5 (0x1<<1) // MSM Function RST…
29336 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_BIAS_RST_SETVAL_O_K2_E5_SHIFT 1
29352 …_6_X195_RESET_CMU_GCRX_RST_SETVAL_O_K2_E5 (0x1<<1) // MSM Function RST…
29353 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMU_GCRX_RST_SETVAL_O_K2_E5_SHIFT 1
29369 …_6_X196_REFCLK_EN_RST_SETVAL_O_K2_E5 (0x1<<1) // MSM Function RST…
29370 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_REFCLK_EN_RST_SETVAL_O_K2_E5_SHIFT 1
29386 …_6_X197_PD_BIAS_NORM_SETVAL_O_K2_E5 (0x1<<1) // MSM Function NOR…
29387 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_BIAS_NORM_SETVAL_O_K2_E5_SHIFT 1
29403 …_6_X198_RESET_CMU_GCRX_NORM_SETVAL_O_K2_E5 (0x1<<1) // MSM Function NOR…
29404 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMU_GCRX_NORM_SETVAL_O_K2_E5_SHIFT 1
29420 …_6_X199_REFCLK_EN_NORM_SETVAL_O_K2_E5 (0x1<<1) // MSM Function NOR…
29421 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_REFCLK_EN_NORM_SETVAL_O_K2_E5_SHIFT 1
29437 …_6_X200_PD_BIAS_PD_SETVAL_O_K2_E5 (0x1<<1) // MSM Function POW…
29438 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_BIAS_PD_SETVAL_O_K2_E5_SHIFT 1
29454 …_6_X201_RESET_CMU_GCRX_PD_SETVAL_O_K2_E5 (0x1<<1) // MSM Function POW…
29455 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMU_GCRX_PD_SETVAL_O_K2_E5_SHIFT 1
29471 …_6_X202_REFCLK_EN_PD_SETVAL_O_K2_E5 (0x1<<1) // MSM Function POW…
29472 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_REFCLK_EN_PD_SETVAL_O_K2_E5_SHIFT 1
29487 … (0xf<<0) // Static divider control for SOC0 The only access to this divi…
29489 … (0xf<<4) // Static divider control for SOC1 The only access to this divi…
29492 …rride for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Override for p…
29496 … (0x3<<5) // Static divider control for CMU GCFSM clock The only access to this divi…
29501 … (0x7<<0) // Static divider control for the SSC block The only access to this divi…
29505 … (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by…
29508 …HB_PMA_CM_DIVNSEL_6_0_O_K2_E5 (0x7f<<0) // CMU N-divider setting
29520 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29521 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29522 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29524 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29526 … 0x000028UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
29527 … 0x00002cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
29528 … 0x000030UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
29529 … 0x000034UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
29530 … 0x000038UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
29531 … 0x00003cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
29532 … 0x000040UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
29533 … 0x000044UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
29534 … 0x000048UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
29535 … 0x00004cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
29536 … 0x000050UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
29537 … 0x000054UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
29538 … 0x000058UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
29539 … 0x00005cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
29540 … 0x000060UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
29541 … 0x000064UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
29545 …X26_GCFSM_CMU_PMA_DATA_OVR_O_6_0_K2_E5 (0x7f<<1) // GCFSM pma_data_o…
29546 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X26_GCFSM_CMU_PMA_DATA_OVR_O_6_0_K2_E5_SHIFT 1
29559 …errides for the following functions: [0] - active high, Override Enable [1] - SOC…
29561 …errides for the following functions: [0] - active high, Override Enable [1] - REF…
29563 …errides for the following functions: [0] - active high, Override Enable [1] - LOC…
29565 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29568 …he following functions: [0] - active high, Override Enable [1] - SOC clock output…
29570 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29572 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29574 …errides for the following functions: [0] - active high, Override Enable [1] - IDD…
29577 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29579 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29581 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29583 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29586 …errides for the following functions: [0] - active high, Override Enable [1] - PCS…
29588 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29590 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29592 …errides for the following functions: [0] - active high, Override Enable [1] - LF …
29595 …errides for the following functions: [0] - active high, Override Enable [1] - LFI…
29597 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29599 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29640 …0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag ov…
29648 …PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycl…
29680 …_X98_AHB_PMA_CM_PFD_FORCE_UP_O_K2_E5 (0x1<<1) // Force PFD to out…
29681 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_UP_O_K2_E5_SHIFT 1
29682 …_E5 (0x1<<2) // Override enable for overriding N-div value
29701 …_AHB_PMA_CM_DIVPSEL_O_K2_E5 (0x7f<<0) // CMU P-divider setting
29716 …_X109_PMA_REFCLK_OE_R_O_K2_E5 (0x1<<1) // "Override for pr…
29717 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_R_O_K2_E5_SHIFT 1
29746 … // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down…
29753 … (0x3<<4) // Test i/p control source : 0-modulator 1-bypass modulator 2-modulator …
29755 … (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
29764 …EMP_CAL_POLARITY_O_K2_E5 (0x1<<6) // chicken bit for counter polarity
29768 … 0x0001e0UL //Access:RW DataWidth:0x8 // Divider input for Div-by-N counter
29770 …_CAL_CLK_DIV_O_14_8_K2_E5 (0x7f<<0) // Divider input for Div-by-N counter
29786 …_X125_AHB_RX_TC_WAIT_NEXT_SAMPLE_K2_E5 (0x7<<1) // in txterm calibr…
29787 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_WAIT_NEXT_SAMPLE_K2_E5_SHIFT 1
29793 …AHB_RX_TC_BIAS_OVR_K2_E5 (0x7<<1) // Bit 3:1 RX termination…
29794 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X126_AHB_RX_TC_BIAS_OVR_K2_E5_SHIFT 1
29798 …1) // Determines rate for PLL clock pcs_rate_o[0] : 0: VCO clock untouched 1: VCO clock …
29799 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X127_PCS_RATE_O_K2_E5_SHIFT 1
29802 …erride for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pi…
29810 … 0x000210UL //Access:RW DataWidth:0x8 // CMU Test Bus address 7-0
29812 …US_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
29816 … (0x3<<0) // "Divider for pma_cm_ref_clk in gen3 rate. Used only in PCIe3 1CMU config"
29818 … in gen3 rate The only access to this divider. Not an override 4�d0: No division 4�d1: /2 4�d2:…
29820 … in gen3 rate. The only access to this divider. Not an override 4�d0: No division 4�d1: /2 4�d2…
29823 …1: VCO clock divided by 2 pcs_rate_o[1] : 0: …
29832 … (0x3<<2) // CMU LF Force value in gen3 rate Used only in PCIe3 1CMU config
29836 … (0x1<<6) // CMU PLL HIZ setting in gen3 rate Used only in PCIe3 1CMU config
29843 … (0x1<<3) // Charge pump chop enable in gen3 rate Used only in PCIe3 1CMU config
29852 … (0x3<<4) // CMU VREG setting in gen3 rate Used only in PCIe3 1CMU config
29854 … (0x3<<6) // CMU VREGH setting in gen3 rate Used only in PCIe3 1CMU config
29857 … (0x1<<0) // Force PFD to output down in gen3 rate Used only in PCIe3 1CMU config
29859 …EN3_O_K2_E5 (0x1<<1) // Force PFD to output up in gen3 rate Used only i…
29860 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PFD_FORCE_UP_GEN3_O_K2_E5_SHIFT 1
29861 … (0x1<<2) // CMU V2I filter enable in gen3 rate Used only in PCIe3 1CMU config
29869 …0234UL //Access:RW DataWidth:0x8 // CMU AFE spares in gen3 rate Used only in PCIe3 1CMU config
29871 … (0x3<<0) // PFD pulse width setting in gen3 rate Used only in PCIe3 1CMU config
29875 … (0x1f<<3) // CMU PLL KVCO setting in gen3 rate Used only in PCIe3 1CMU config
29878 … (0x7f<<0) // CMU P-divider setting in gen3 rate Used only in PCIe…
29881 … (0x7<<0) // Override enable for overriding VCOFR value in gen3 rate Used only in PCIe3 1CMU config
29899 …l word for SSC in synth mode or SSC_GEN fracsyn_en mode in gen3 rate Used only in PCIe3 1CMU config
29900 …l word for SSC in synth mode or SSC_GEN fracsyn_en mode in gen3 rate Used only in PCIe3 1CMU config
29902 …l word for SSC in synth mode or SSC_GEN fracsyn_en mode in gen3 rate Used only in PCIe3 1CMU config
29904 … 0x000264UL //Access:RW DataWidth:0x8 // Inverts up_i when set to 1
29905 … 0x000268UL //Access:RW DataWidth:0x8 // Inverts up_i when set to 1
29906 … function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - …
29937 …_X191_PD_BIAS_IDDQ_SETVAL_O_K2_E5 (0x1<<1) // MSM Function IDD…
29938 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_BIAS_IDDQ_SETVAL_O_K2_E5_SHIFT 1
29954 …_X192_RESET_CMU_GCRX_IDDQ_SETVAL_O_K2_E5 (0x1<<1) // MSM Function IDD…
29955 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_GCRX_IDDQ_SETVAL_O_K2_E5_SHIFT 1
29971 …_X193_REFCLK_EN_IDDQ_SETVAL_O_K2_E5 (0x1<<1) // MSM Function IDD…
29972 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_REFCLK_EN_IDDQ_SETVAL_O_K2_E5_SHIFT 1
29988 …_X194_PD_BIAS_RST_SETVAL_O_K2_E5 (0x1<<1) // MSM Function RST…
29989 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_BIAS_RST_SETVAL_O_K2_E5_SHIFT 1
30005 …_X195_RESET_CMU_GCRX_RST_SETVAL_O_K2_E5 (0x1<<1) // MSM Function RST…
30006 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_GCRX_RST_SETVAL_O_K2_E5_SHIFT 1
30022 …_X196_REFCLK_EN_RST_SETVAL_O_K2_E5 (0x1<<1) // MSM Function RST…
30023 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_REFCLK_EN_RST_SETVAL_O_K2_E5_SHIFT 1
30039 …_X197_PD_BIAS_NORM_SETVAL_O_K2_E5 (0x1<<1) // MSM Function NOR…
30040 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_BIAS_NORM_SETVAL_O_K2_E5_SHIFT 1
30056 …_X198_RESET_CMU_GCRX_NORM_SETVAL_O_K2_E5 (0x1<<1) // MSM Function NOR…
30057 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_GCRX_NORM_SETVAL_O_K2_E5_SHIFT 1
30073 …_X199_REFCLK_EN_NORM_SETVAL_O_K2_E5 (0x1<<1) // MSM Function NOR…
30074 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_REFCLK_EN_NORM_SETVAL_O_K2_E5_SHIFT 1
30090 …_X200_PD_BIAS_PD_SETVAL_O_K2_E5 (0x1<<1) // MSM Function POW…
30091 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_BIAS_PD_SETVAL_O_K2_E5_SHIFT 1
30107 …_X201_RESET_CMU_GCRX_PD_SETVAL_O_K2_E5 (0x1<<1) // MSM Function POW…
30108 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_GCRX_PD_SETVAL_O_K2_E5_SHIFT 1
30124 …_X202_REFCLK_EN_PD_SETVAL_O_K2_E5 (0x1<<1) // MSM Function POW…
30125 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_REFCLK_EN_PD_SETVAL_O_K2_E5_SHIFT 1
30141 …_X203_PD_BIAS_NORM_REFCLK_SETVAL_O_K2_E5 (0x1<<1) // MSM Function NOR…
30142 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_BIAS_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT 1
30158 …_X204_RESET_CMU_GCRX_NORM_REFCLK_SETVAL_O_K2_E5 (0x1<<1) // MSM Function NOR…
30159 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMU_GCRX_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT 1
30175 …_X205_REFCLK_EN_NORM_REFCLK_SETVAL_O_K2_E5 (0x1<<1) // MSM Function NOR…
30176 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_REFCLK_EN_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT 1
30192 …_X206_PD_BIAS_P1_2_SETVAL_O_K2_E5 (0x1<<1) // MSM Function P1_…
30193 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_BIAS_P1_2_SETVAL_O_K2_E5_SHIFT 1
30209 …_X207_RESET_CMU_GCRX_P1_2_SETVAL_O_K2_E5 (0x1<<1) // MSM Function P1_…
30210 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMU_GCRX_P1_2_SETVAL_O_K2_E5_SHIFT 1
30226 …_X208_REFCLK_EN_P1_2_SETVAL_O_K2_E5 (0x1<<1) // MSM Function P1_…
30227 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_REFCLK_EN_P1_2_SETVAL_O_K2_E5_SHIFT 1
30245 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
30248 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
30250 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
30253 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
30256 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
30258 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 C…
30259 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X3_PMA_TXCLK_SEL_O_1_K2_E5_SHIFT 1
30261 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
30263 … (0x3<<2) // Static divider control for Lane GCFSM clock The only access to this divi…
30265 … 2'b00: lnX_ck_txb_o is divided by 1 version of the tx by…
30270 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
30272 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
30277 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
30279 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
30285 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
30287 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
30292 …3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends norm…
30294 …/ Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ev…
30296 … 0x000824UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
30297 … 0x000828UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
30298 … 0x00082cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
30299 … 0x000830UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
30300 …// Bist generator - Number of words between insert word insertions. Insertions are done in both pr…
30302 …// Bist generator - Number of words between insert word insertions. Insertions are done in both pr…
30309 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
30317 …checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be…
30319 …checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be…
30323 …ON_ZEROS_K2_E5 (0x1<<5) // Setting this bit allows BIST to sync…
30329 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
30330 … 0x000854UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30331 … 0x000858UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30332 … 0x00085cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30333 … 0x000860UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30341 … 0x000880UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
30342 … 0x000884UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
30343 … 0x000888UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
30344 … 0x00088cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
30345 … 0x000890UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
30346 … 0x000894UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
30347 … 0x000898UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
30348 … 0x00089cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
30349 … 0x0008a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
30350 … 0x0008a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
30351 … 0x0008a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
30352 … 0x0008acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
30353 … 0x0008b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
30354 … 0x0008b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
30355 … 0x0008b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
30356 … 0x0008bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
30357 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA me…
30358 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
30359 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA me…
30360 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
30363 … (0x1f<<0) // The start length of DFE offset calibration, except for the 1st cycle.
30365 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
30367 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
30369 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
30371 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
30372 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
30373 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
30375 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
30377 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
30389 …lect, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion…
30390 …lect, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion…
30392 …_E5 (0x3<<0) // Bit 0: Override enable for msm_ln_req Bit 1…
30394 …_MSM_FUNC_IN_OVR_O_K2_E5 (0x3f<<2) // Bit 2: Override enable…
30421 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
30423 …1) // ATT wait control. Upon detection of signal, DFE ATT calibration is enabled, without CISEL be…
30424 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_CDR_CONTROL_ATT_CTRL_O_K2_E5_SHIFT 1
30425 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
30429 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
30430 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
30431 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
30433 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
30435 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
30465 … (0x3<<2) // EI Exit time cycles = timer_len_sel[1:0]+1*exit_timer_len_i[9…
30472 …1_X86_NES_LB_ENA_O_K2_E5 (0x1<<1) // NES loopback ena…
30473 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X86_NES_LB_ENA_O_K2_E5_SHIFT 1
30479 …_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O_K2_E5 (0x7f<<1) // RX boost overrid…
30480 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O_K2_E5_SHIFT 1
30485 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
30487 … (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye …
30492 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
30519 …e_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
30534 …x3<<6) // CDR phase detector proportional path enable bit 0: enables D4/D3 data/edge samplers bit …
30536 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
30538 …-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2…
30542 … (0x1<<3) // RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth
30544 …rides the ck_270 DFE clock "right" eye edge clock with the shifted clock. Only assert one of pma_l…
30546 …errides the ck_90 DFE clock "left" eye edge clock with the shifted clock. Only assert one of pma_l…
30554 …(0xf<<4) // TX coefficient polarity enable. Set to "1" for negative polarity. bit 0: Cm bit 1: C0 …
30569 …_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O_K2_E5 (0x7f<<1) // RX boost overrid…
30570 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O_K2_E5_SHIFT 1
30577 … (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye …
30602 …e_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
30627 …4) // when 1, the final tx term value is calibrated txterm value + tx_cxp_margin; when 0, the fina…
30629 …5) // when 1, the final tx term value is calibrated txterm value + tx_cxn_margin; when 0, the fina…
30641 … (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not c…
30643 … (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_slew_sld[1:0]
30646 …09f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx_slew_sld3f[2…
30650 …1_X126_RXEQ_LN_RATE_OW_O_2_0_K2_E5 (0x7<<1) // These bits have …
30651 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE_OW_O_2_0_K2_E5_SHIFT 1
30652 … (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is l…
30654 … (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is l…
30656 … (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is l…
30658 … (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is l…
30661 …1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: en…
30664 …1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: en…
30714 …IMIT_O_K2_E5 (0xf<<1) // Max limit value for BOOST auto-cal…
30715 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X143_BOOST_MAX_LIMIT_O_K2_E5_SHIFT 1
30716 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
30727 …_E5 (0xf<<4) // boost_adj_val This register Is not bit reversed
30755 … for comparator calibration select. Enabled by rxeq_ovr_en_o: 1: Calibrate DFE comparator 1 2: Cal…
30757 … (0x3<<3) // Override the value of rx_att_gain output to PMA when rx_att_gain_autocal_dis=1
30759 … (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_autocal_dis=1
30775 …FE_TAP1_OVR_VAL_O_6_0_K2_E5 (0x7f<<0) // DFE Tap 1 Override Value
30792 …1_X157_TXEQ_ERR_SIGN_O_1_K2_E5 (0x1<<1) // TX Equalizer Err…
30793 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X157_TXEQ_ERR_SIGN_O_1_K2_E5_SHIFT 1
30794 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
30800 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
30802 … 0x000a80UL //Access:R DataWidth:0x8 // Over equalization count 7-0
30804 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
30806 … 0x000a88UL //Access:R DataWidth:0x8 // Under equalization count 7-0
30811 … 0x000a94UL //Access:RW DataWidth:0x8 // Mask bit for Txeq training p…
30813 …DONT_CARE_O_8_K2_E5 (0x1<<0) // Mask bit for Txeq training p…
30816 … (0x1<<0) // This bit has similar function as txeq_rxrecal_init in COMLANE CSR. It is l…
30821 …1_X168_RECAL_RX_PRESET_HINT_EN_O_K2_E5 (0x1<<1) // Enable for prima…
30822 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X168_RECAL_RX_PRESET_HINT_EN_O_K2_E5_SHIFT 1
30824 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
30830 …_E5 (0x1<<0) // cdfe enable bit. 1: enable cdfe when…
30832 …1) // The cdfe input word_i overwrite. …
30833 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X201_CDFE_WORD_OV_O_1_0_K2_E5_SHIFT 1
30834 … 0 10-bit or 20-bit mode. 2'b11: the mode_8b_…
30836 …1:0] overwrite. …
30842 …e calibration enable. 1: enable force cdfe calibration. 0: disable force cdfe calibration. Note…
30844 …e calibration enable. 1: enable force cdfe calibration. 0: disable force cdfe calibration. Note…
30846 …1: the cdfe calibration is enabled when EI exits and when rate is 2'b01 or 2'b10. …
30849 …1: the continuous cdfe calibration is enabled when the rate is 2'b01 or 2'b10. …
30851 …1) // Enables cdfe calibration during Txeq adaptation phase. …
30852 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL_K2_E5_SHIFT 1
30853 … 1: the cdfe calibratio…
30855 … (0x1<<3) // Enables the cdfe calibration in rate3. 1: enables cdfe calibr…
30857 … (0x1<<4) // Enables the cdfe calibration in rate2. 1: enables cdfe calibr…
30859 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
30860 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
30861 …-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
30863 … (0x1<<7) // cdfe coarse dll overwrite enable. 1: enable coarse dll o…
30865 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
30866 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
30867 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
30868 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
30869 …-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
30872 …bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enabl…
30875 …bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enabl…
30878 …) // Override for CMP1 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[1]
30893 …) // Override for CMP2 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[1]
30908 …) // Override for CMP3 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[1]
30923 …) // Override for CMP4 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[1]
30950 … (0x1<<4) // cdfe fine dll overwrite enable. 1: enable fine dll ove…
30955 …REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_K2_E5 (0x1<<1) //
30956 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_K2_E5_SHIFT 1
30968 …1_X255_CDFE_DIR_OV_VAL_K2_E5 (0x1<<1) // Override value f…
30969 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_VAL_K2_E5_SHIFT 1
30970 … (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed…
30972 … (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed…
30974 … (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed…
30976 … (0x1<<5) // cdfe eye delay overwrite enable. 1: enable eye delay ov…
30978 … (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed…
30984 …_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_K2_E5 (0x7f<<1) // This register re…
30985 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_K2_E5_SHIFT 1
30990 …EV_OV_EN_K2_E5 (0x1<<1) // cdfe dlev overwrite enable. 1: en…
30991 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_DLEV_OV_EN_K2_E5_SHIFT 1
30992 …ister override for overriding adaptation comparator select bit [0] : override enable bit [4:1] : o…
30994 …override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : o…
30996 …override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : o…
30999 …Bit[0]: enable tap1 overwrite for cdfe. Bit[1]: enable tap2 overwrite for cdfe Bit[2]: enable tap3…
31021 …REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_K2_E5 (0x1<<1) //
31022 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_K2_E5_SHIFT 1
31030 …REG_AHB_LANE_CSR_1_X269_AHB_CDFE_STROBE_EN_O_K2_E5 (0x1<<1) //
31031 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_STROBE_EN_O_K2_E5_SHIFT 1
31068 …K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_ra Bit …
31070 …_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_p2s Bit…
31072 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_reset_lnregh Bi…
31074 …O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_reset_lnreg Bi…
31077 …_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_cdr Bit…
31079 …_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_dfe Bit…
31081 …_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_pd_lnregh Bit…
31083 …_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_pd_vco_buf Bit…
31086 …_O_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_cdr_gcrx B…
31088 …_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_rxgate_en Bit…
31090 …_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_reset_vco Bit…
31092 …K2_E5 (0x3<<6) // Bit 0: Override enable for msm_iddq_sd Bit …
31095 …2_E5 (0x3<<0) // Bit 0: Override enable for msm_pd_dfe Bit 1…
31097 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_pd_dfe_bias Bi…
31099 …_O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_txdrv_lp_idle B…
31101 …R_O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_txreg_bleed_ena …
31104 …K2_E5 (0x3<<0) // Bit 0: Override enable for msm_pd_txreg Bit …
31106 …K2_E5 (0x3<<2) // Bit 0: Override enable for msm_pd_lnreg Bit …
31108 …_K2_E5 (0x3<<4) // Bit 0: Override enable for pd_p2s Bit 1: …
31110 …_K2_E5 (0x3<<6) // Bit 0: Override enable for pd_ra Bit 1: …
31113 …R_O_K2_E5 (0x3<<2) // Bit 0: Override enable for pd_slv_bias Bit …
31115 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for pd_txdrv Bit 1:…
31117 …2_E5 (0x3<<6) // Bit 0: Override enable for msm_pd_vco Bit 1…
31120 …2_E5 (0x3<<0) // Bit 0: Override enable for msm_cdr_en Bit 1…
31122 …_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_s2p Bit…
31124 …K2_E5 (0x3<<4) // Bit 0: Override enable for msm_rxclk_en Bit …
31126 …_E5 (0x3<<6) // Bit 0: Override enable for msm_word Bit 1:…
31129 …E5 (0x7<<0) // Bit 0: Override enable for msm_rate Bit [2:…
31131 …2_E5 (0x7<<3) // Bit 0: Override enable for msm_rxvcodiv Bit […
31136 …2_E5 (0x7<<0) // Bit 0: Override enable for msm_txvcodiv Bit […
31139 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
31141 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmo…
31142 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_TREG0_POL_O_K2_E5_SHIFT 1
31143 …0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
31145 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31149 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
31152 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
31154 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmod…
31155 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_TREG1_BIT_O_K2_E5_SHIFT 1
31156 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31158 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
31160 …(0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
31162 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31167 …(0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
31169 … (0x1<<1) // Reg0 data bank word order select. 0 - Normal word order used - words are not …
31170 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_REG0_WORD_O_K2_E5_SHIFT 1
31173 …3_TX_CTRL_O_24_K2_E5 (0x1<<5) // Bit 24: txdrv_c2_in[3]
31175 …HNG_EN_O_K2_E5 (0x1<<6) // Enable bit for width_chng modu…
31182 … (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2�b00: no bit stripping 2�b01: 2x bit st…
31187 … communication between the external 64-bit data and the internal 20-bit data. The reading operatio…
31189 …Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2�b00: no bit stuf…
31191 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
31200 …bit. 1: in NORM state, lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA or it…
31212 …1_X308_BLOCK_ENC_CLR_ERR_O_K2_E5 (0x1<<1) // 128b/130b encode…
31213 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_ENC_CLR_ERR_O_K2_E5_SHIFT 1
31228 …1_X310_ALIGN_RSTN_O_K2_E5 (0x1<<1) // Synchronous clea…
31229 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_ALIGN_RSTN_O_K2_E5_SHIFT 1
31244 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
31246 …_RXVALID_DIS_AT_RATE_CHG_O_0_K2_E5 (0x1<<1) // Value 1 forces rxvalid…
31247 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X312_RXVALID_DIS_AT_RATE_CHG_O_0_K2_E5_SHIFT 1
31251 …BLE_O_K2_E5 (0x1<<0) // 0: enable rx_gearbox, 1: disable rx_gearbox
31253 …GEARBOX_DISABLE_O_K2_E5 (0x1<<1) // 0: enable tx_gearbox, 1: disab…
31254 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X313_AHB_TX_GEARBOX_DISABLE_O_K2_E5_SHIFT 1
31256 … (0x1<<0) // Mux select for data input to polbit_reg0 0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i
31258 … (0x1<<1) // To skip cdr calibration routines for PCIe gen3. Can be used when P…
31259 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN3_O_K2_E5_SHIFT 1
31273 …R_1_X317_AHB_BEACON_ENA_OVR_O_K2_E5 (0x1<<1) // Beacon Override
31274 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_O_K2_E5_SHIFT 1
31279 …f<<4) // Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty…
31282 …1_0_K2_E5 (0x3<<0) // Bit[0]: Overide value. Bit[1] :Overr…
31284 …x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the override, while bit 0 …
31286 … (0x3<<4) // Override enable for DFE signal detect indicator input. Bit 1 is overide enable …
31289 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override enable, bit 0 is …
31291 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override enable, bit 0 is …
31293 …x3<<4) // Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 …
31299 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
31300 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
31301 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
31302 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
31303 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
31304 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
31306 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
31308 … (0x1<<1) // Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is …
31309 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_AHB_LN_IN_OVR_CHG_FLAG_O_K2_E5_SHIFT 1
31310 …it_regp1 Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty…
31317 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
31325 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
31328 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
31330 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
31333 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
31336 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
31338 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 C…
31339 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X3_PMA_TXCLK_SEL_O_1_K2_E5_SHIFT 1
31341 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
31343 … (0x3<<2) // Static divider control for Lane GCFSM clock The only access to this divi…
31345 … 2'b00: lnX_ck_txb_o is divided by 1 version of the tx by…
31350 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
31352 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
31357 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
31359 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
31365 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
31367 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
31372 …3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends norm…
31374 …/ Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ev…
31376 … 0x001024UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
31377 … 0x001028UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
31378 … 0x00102cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
31379 … 0x001030UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
31380 …// Bist generator - Number of words between insert word insertions. Insertions are done in both pr…
31382 …// Bist generator - Number of words between insert word insertions. Insertions are done in both pr…
31389 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
31397 …checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be…
31399 …checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be…
31403 …ON_ZEROS_K2_E5 (0x1<<5) // Setting this bit allows BIST to sync…
31409 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
31410 … 0x001054UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31411 … 0x001058UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31412 … 0x00105cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31413 … 0x001060UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31421 … 0x001080UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
31422 … 0x001084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
31423 … 0x001088UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
31424 … 0x00108cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
31425 … 0x001090UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
31426 … 0x001094UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
31427 … 0x001098UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
31428 … 0x00109cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
31429 … 0x0010a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
31430 … 0x0010a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
31431 … 0x0010a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
31432 … 0x0010acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
31433 … 0x0010b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
31434 … 0x0010b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
31435 … 0x0010b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
31436 … 0x0010bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
31437 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA me…
31438 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
31439 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA me…
31440 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
31443 … (0x1f<<0) // The start length of DFE offset calibration, except for the 1st cycle.
31445 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
31447 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
31449 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
31451 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
31452 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
31453 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
31455 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
31457 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
31469 …lect, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion…
31470 …lect, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion…
31472 …_E5 (0x3<<0) // Bit 0: Override enable for msm_ln_req Bit 1…
31474 …_MSM_FUNC_IN_OVR_O_K2_E5 (0x3f<<2) // Bit 2: Override enable…
31501 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
31503 …1) // ATT wait control. Upon detection of signal, DFE ATT calibration is enabled, without CISEL be…
31504 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_CDR_CONTROL_ATT_CTRL_O_K2_E5_SHIFT 1
31505 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
31509 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
31510 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
31511 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
31513 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
31515 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
31545 … (0x3<<2) // EI Exit time cycles = timer_len_sel[1:0]+1*exit_timer_len_i[9…
31552 …2_X86_NES_LB_ENA_O_K2_E5 (0x1<<1) // NES loopback ena…
31553 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X86_NES_LB_ENA_O_K2_E5_SHIFT 1
31559 …_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O_K2_E5 (0x7f<<1) // RX boost overrid…
31560 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O_K2_E5_SHIFT 1
31565 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
31567 … (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye …
31572 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
31599 …e_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
31614 …x3<<6) // CDR phase detector proportional path enable bit 0: enables D4/D3 data/edge samplers bit …
31616 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
31618 …-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2…
31622 … (0x1<<3) // RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth
31624 …rides the ck_270 DFE clock "right" eye edge clock with the shifted clock. Only assert one of pma_l…
31626 …errides the ck_90 DFE clock "left" eye edge clock with the shifted clock. Only assert one of pma_l…
31634 …(0xf<<4) // TX coefficient polarity enable. Set to "1" for negative polarity. bit 0: Cm bit 1: C0 …
31649 …_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O_K2_E5 (0x7f<<1) // RX boost overrid…
31650 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O_K2_E5_SHIFT 1
31657 … (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye …
31682 …e_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
31707 …4) // when 1, the final tx term value is calibrated txterm value + tx_cxp_margin; when 0, the fina…
31709 …5) // when 1, the final tx term value is calibrated txterm value + tx_cxn_margin; when 0, the fina…
31721 … (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not c…
31723 … (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_slew_sld[1:0]
31726 …11f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx_slew_sld3f[2…
31730 …2_X126_RXEQ_LN_RATE_OW_O_2_0_K2_E5 (0x7<<1) // These bits have …
31731 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_RATE_OW_O_2_0_K2_E5_SHIFT 1
31732 … (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is l…
31734 … (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is l…
31736 … (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is l…
31738 … (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is l…
31741 …1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: en…
31744 …1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: en…
31794 …IMIT_O_K2_E5 (0xf<<1) // Max limit value for BOOST auto-cal…
31795 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X143_BOOST_MAX_LIMIT_O_K2_E5_SHIFT 1
31796 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
31807 …_E5 (0xf<<4) // boost_adj_val This register Is not bit reversed
31835 … for comparator calibration select. Enabled by rxeq_ovr_en_o: 1: Calibrate DFE comparator 1 2: Cal…
31837 … (0x3<<3) // Override the value of rx_att_gain output to PMA when rx_att_gain_autocal_dis=1
31839 … (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_autocal_dis=1
31855 …FE_TAP1_OVR_VAL_O_6_0_K2_E5 (0x7f<<0) // DFE Tap 1 Override Value
31872 …2_X157_TXEQ_ERR_SIGN_O_1_K2_E5 (0x1<<1) // TX Equalizer Err…
31873 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X157_TXEQ_ERR_SIGN_O_1_K2_E5_SHIFT 1
31874 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
31880 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
31882 … 0x001280UL //Access:R DataWidth:0x8 // Over equalization count 7-0
31884 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
31886 … 0x001288UL //Access:R DataWidth:0x8 // Under equalization count 7-0
31891 … 0x001294UL //Access:RW DataWidth:0x8 // Mask bit for Txeq training p…
31893 …DONT_CARE_O_8_K2_E5 (0x1<<0) // Mask bit for Txeq training p…
31896 … (0x1<<0) // This bit has similar function as txeq_rxrecal_init in COMLANE CSR. It is l…
31901 …2_X168_RECAL_RX_PRESET_HINT_EN_O_K2_E5 (0x1<<1) // Enable for prima…
31902 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X168_RECAL_RX_PRESET_HINT_EN_O_K2_E5_SHIFT 1
31904 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
31910 …_E5 (0x1<<0) // cdfe enable bit. 1: enable cdfe when…
31912 …1) // The cdfe input word_i overwrite. …
31913 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X201_CDFE_WORD_OV_O_1_0_K2_E5_SHIFT 1
31914 … 0 10-bit or 20-bit mode. 2'b11: the mode_8b_…
31916 …1:0] overwrite. …
31922 …e calibration enable. 1: enable force cdfe calibration. 0: disable force cdfe calibration. Note…
31924 …e calibration enable. 1: enable force cdfe calibration. 0: disable force cdfe calibration. Note…
31926 …1: the cdfe calibration is enabled when EI exits and when rate is 2'b01 or 2'b10. …
31929 …1: the continuous cdfe calibration is enabled when the rate is 2'b01 or 2'b10. …
31931 …1) // Enables cdfe calibration during Txeq adaptation phase. …
31932 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL_K2_E5_SHIFT 1
31933 … 1: the cdfe calibratio…
31935 … (0x1<<3) // Enables the cdfe calibration in rate3. 1: enables cdfe calibr…
31937 … (0x1<<4) // Enables the cdfe calibration in rate2. 1: enables cdfe calibr…
31939 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
31940 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
31941 …-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
31943 … (0x1<<7) // cdfe coarse dll overwrite enable. 1: enable coarse dll o…
31945 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
31946 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
31947 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
31948 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
31949 …-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
31952 …bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enabl…
31955 …bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enabl…
31958 …) // Override for CMP1 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[1]
31973 …) // Override for CMP2 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[1]
31988 …) // Override for CMP3 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[1]
32003 …) // Override for CMP4 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[1]
32030 … (0x1<<4) // cdfe fine dll overwrite enable. 1: enable fine dll ove…
32035 …REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_K2_E5 (0x1<<1) //
32036 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_K2_E5_SHIFT 1
32048 …2_X255_CDFE_DIR_OV_VAL_K2_E5 (0x1<<1) // Override value f…
32049 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_CDFE_DIR_OV_VAL_K2_E5_SHIFT 1
32050 … (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed…
32052 … (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed…
32054 … (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed…
32056 … (0x1<<5) // cdfe eye delay overwrite enable. 1: enable eye delay ov…
32058 … (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed…
32064 …_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_K2_E5 (0x7f<<1) // This register re…
32065 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_K2_E5_SHIFT 1
32070 …EV_OV_EN_K2_E5 (0x1<<1) // cdfe dlev overwrite enable. 1: en…
32071 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_AHB_CDFE_DLEV_OV_EN_K2_E5_SHIFT 1
32072 …ister override for overriding adaptation comparator select bit [0] : override enable bit [4:1] : o…
32074 …override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : o…
32076 …override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : o…
32079 …Bit[0]: enable tap1 overwrite for cdfe. Bit[1]: enable tap2 overwrite for cdfe Bit[2]: enable tap3…
32101 …REG_AHB_LANE_CSR_2_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_K2_E5 (0x1<<1) //
32102 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_K2_E5_SHIFT 1
32110 …REG_AHB_LANE_CSR_2_X269_AHB_CDFE_STROBE_EN_O_K2_E5 (0x1<<1) //
32111 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X269_AHB_CDFE_STROBE_EN_O_K2_E5_SHIFT 1
32148 …K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_ra Bit …
32150 …_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_p2s Bit…
32152 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_reset_lnregh Bi…
32154 …O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_reset_lnreg Bi…
32157 …_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_cdr Bit…
32159 …_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_dfe Bit…
32161 …_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_pd_lnregh Bit…
32163 …_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_pd_vco_buf Bit…
32166 …_O_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_cdr_gcrx B…
32168 …_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_rxgate_en Bit…
32170 …_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_reset_vco Bit…
32172 …K2_E5 (0x3<<6) // Bit 0: Override enable for msm_iddq_sd Bit …
32175 …2_E5 (0x3<<0) // Bit 0: Override enable for msm_pd_dfe Bit 1…
32177 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_pd_dfe_bias Bi…
32179 …_O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_txdrv_lp_idle B…
32181 …R_O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_txreg_bleed_ena …
32184 …K2_E5 (0x3<<0) // Bit 0: Override enable for msm_pd_txreg Bit …
32186 …K2_E5 (0x3<<2) // Bit 0: Override enable for msm_pd_lnreg Bit …
32188 …_K2_E5 (0x3<<4) // Bit 0: Override enable for pd_p2s Bit 1: …
32190 …_K2_E5 (0x3<<6) // Bit 0: Override enable for pd_ra Bit 1: …
32193 …R_O_K2_E5 (0x3<<2) // Bit 0: Override enable for pd_slv_bias Bit …
32195 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for pd_txdrv Bit 1:…
32197 …2_E5 (0x3<<6) // Bit 0: Override enable for msm_pd_vco Bit 1…
32200 …2_E5 (0x3<<0) // Bit 0: Override enable for msm_cdr_en Bit 1…
32202 …_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_s2p Bit…
32204 …K2_E5 (0x3<<4) // Bit 0: Override enable for msm_rxclk_en Bit …
32206 …_E5 (0x3<<6) // Bit 0: Override enable for msm_word Bit 1:…
32209 …E5 (0x7<<0) // Bit 0: Override enable for msm_rate Bit [2:…
32211 …2_E5 (0x7<<3) // Bit 0: Override enable for msm_rxvcodiv Bit […
32216 …2_E5 (0x7<<0) // Bit 0: Override enable for msm_txvcodiv Bit […
32219 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
32221 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmo…
32222 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_TREG0_POL_O_K2_E5_SHIFT 1
32223 …0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
32225 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32229 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
32232 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
32234 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmod…
32235 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_TREG1_BIT_O_K2_E5_SHIFT 1
32236 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32238 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
32240 …(0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
32242 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32247 …(0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
32249 … (0x1<<1) // Reg0 data bank word order select. 0 - Normal word order used - words are not …
32250 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_REG0_WORD_O_K2_E5_SHIFT 1
32253 …3_TX_CTRL_O_24_K2_E5 (0x1<<5) // Bit 24: txdrv_c2_in[3]
32255 …HNG_EN_O_K2_E5 (0x1<<6) // Enable bit for width_chng modu…
32262 … (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2�b00: no bit stripping 2�b01: 2x bit st…
32267 … communication between the external 64-bit data and the internal 20-bit data. The reading operatio…
32269 …Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2�b00: no bit stuf…
32271 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
32280 …bit. 1: in NORM state, lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA or it…
32292 …2_X308_BLOCK_ENC_CLR_ERR_O_K2_E5 (0x1<<1) // 128b/130b encode…
32293 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_ENC_CLR_ERR_O_K2_E5_SHIFT 1
32308 …2_X310_ALIGN_RSTN_O_K2_E5 (0x1<<1) // Synchronous clea…
32309 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_ALIGN_RSTN_O_K2_E5_SHIFT 1
32324 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
32326 …_RXVALID_DIS_AT_RATE_CHG_O_0_K2_E5 (0x1<<1) // Value 1 forces rxvalid…
32327 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X312_RXVALID_DIS_AT_RATE_CHG_O_0_K2_E5_SHIFT 1
32331 …BLE_O_K2_E5 (0x1<<0) // 0: enable rx_gearbox, 1: disable rx_gearbox
32333 …GEARBOX_DISABLE_O_K2_E5 (0x1<<1) // 0: enable tx_gearbox, 1: disab…
32334 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X313_AHB_TX_GEARBOX_DISABLE_O_K2_E5_SHIFT 1
32336 … (0x1<<0) // Mux select for data input to polbit_reg0 0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i
32338 … (0x1<<1) // To skip cdr calibration routines for PCIe gen3. Can be used when P…
32339 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_SKIP_CDR_GEN3_O_K2_E5_SHIFT 1
32353 …R_2_X317_AHB_BEACON_ENA_OVR_O_K2_E5 (0x1<<1) // Beacon Override
32354 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_AHB_BEACON_ENA_OVR_O_K2_E5_SHIFT 1
32359 …f<<4) // Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty…
32362 …1_0_K2_E5 (0x3<<0) // Bit[0]: Overide value. Bit[1] :Overr…
32364 …x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the override, while bit 0 …
32366 … (0x3<<4) // Override enable for DFE signal detect indicator input. Bit 1 is overide enable …
32369 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override enable, bit 0 is …
32371 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override enable, bit 0 is …
32373 …x3<<4) // Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 …
32379 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
32380 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
32381 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
32382 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
32383 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
32384 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
32386 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
32388 … (0x1<<1) // Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is …
32389 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_AHB_LN_IN_OVR_CHG_FLAG_O_K2_E5_SHIFT 1
32390 …it_regp1 Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty…
32397 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
32405 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
32408 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
32410 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
32413 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
32416 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
32418 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 C…
32419 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X3_PMA_TXCLK_SEL_O_1_K2_E5_SHIFT 1
32421 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
32423 … (0x3<<2) // Static divider control for Lane GCFSM clock The only access to this divi…
32425 … 2'b00: lnX_ck_txb_o is divided by 1 version of the tx by…
32430 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
32432 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
32437 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
32439 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
32445 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
32447 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
32452 …3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends norm…
32454 …/ Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ev…
32456 … 0x001824UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
32457 … 0x001828UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
32458 … 0x00182cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
32459 … 0x001830UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
32460 …// Bist generator - Number of words between insert word insertions. Insertions are done in both pr…
32462 …// Bist generator - Number of words between insert word insertions. Insertions are done in both pr…
32469 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
32477 …checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be…
32479 …checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be…
32483 …ON_ZEROS_K2_E5 (0x1<<5) // Setting this bit allows BIST to sync…
32489 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
32490 … 0x001854UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32491 … 0x001858UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32492 … 0x00185cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32493 … 0x001860UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32501 … 0x001880UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
32502 … 0x001884UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
32503 … 0x001888UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
32504 … 0x00188cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
32505 … 0x001890UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
32506 … 0x001894UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
32507 … 0x001898UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
32508 … 0x00189cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
32509 … 0x0018a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
32510 … 0x0018a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
32511 … 0x0018a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
32512 … 0x0018acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
32513 … 0x0018b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
32514 … 0x0018b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
32515 … 0x0018b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
32516 … 0x0018bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
32517 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA me…
32518 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
32519 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA me…
32520 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
32523 … (0x1f<<0) // The start length of DFE offset calibration, except for the 1st cycle.
32525 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
32527 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
32529 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
32531 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
32532 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
32533 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
32535 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
32537 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
32549 …lect, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion…
32550 …lect, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion…
32552 …_E5 (0x3<<0) // Bit 0: Override enable for msm_ln_req Bit 1…
32554 …_MSM_FUNC_IN_OVR_O_K2_E5 (0x3f<<2) // Bit 2: Override enable…
32581 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
32583 …1) // ATT wait control. Upon detection of signal, DFE ATT calibration is enabled, without CISEL be…
32584 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_CDR_CONTROL_ATT_CTRL_O_K2_E5_SHIFT 1
32585 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
32589 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
32590 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
32591 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
32593 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
32595 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
32625 … (0x3<<2) // EI Exit time cycles = timer_len_sel[1:0]+1*exit_timer_len_i[9…
32632 …3_X86_NES_LB_ENA_O_K2_E5 (0x1<<1) // NES loopback ena…
32633 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X86_NES_LB_ENA_O_K2_E5_SHIFT 1
32639 …_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O_K2_E5 (0x7f<<1) // RX boost overrid…
32640 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O_K2_E5_SHIFT 1
32645 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
32647 … (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye …
32652 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
32679 …e_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
32694 …x3<<6) // CDR phase detector proportional path enable bit 0: enables D4/D3 data/edge samplers bit …
32696 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
32698 …-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2…
32702 … (0x1<<3) // RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth
32704 …rides the ck_270 DFE clock "right" eye edge clock with the shifted clock. Only assert one of pma_l…
32706 …errides the ck_90 DFE clock "left" eye edge clock with the shifted clock. Only assert one of pma_l…
32714 …(0xf<<4) // TX coefficient polarity enable. Set to "1" for negative polarity. bit 0: Cm bit 1: C0 …
32729 …_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O_K2_E5 (0x7f<<1) // RX boost overrid…
32730 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O_K2_E5_SHIFT 1
32737 … (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye …
32762 …e_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
32787 …4) // when 1, the final tx term value is calibrated txterm value + tx_cxp_margin; when 0, the fina…
32789 …5) // when 1, the final tx term value is calibrated txterm value + tx_cxn_margin; when 0, the fina…
32801 … (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not c…
32803 … (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_slew_sld[1:0]
32806 …19f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx_slew_sld3f[2…
32810 …3_X126_RXEQ_LN_RATE_OW_O_2_0_K2_E5 (0x7<<1) // These bits have …
32811 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_RATE_OW_O_2_0_K2_E5_SHIFT 1
32812 … (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is l…
32814 … (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is l…
32816 … (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is l…
32818 … (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is l…
32821 …1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: en…
32824 …1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: en…
32874 …IMIT_O_K2_E5 (0xf<<1) // Max limit value for BOOST auto-cal…
32875 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X143_BOOST_MAX_LIMIT_O_K2_E5_SHIFT 1
32876 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
32887 …_E5 (0xf<<4) // boost_adj_val This register Is not bit reversed
32915 … for comparator calibration select. Enabled by rxeq_ovr_en_o: 1: Calibrate DFE comparator 1 2: Cal…
32917 … (0x3<<3) // Override the value of rx_att_gain output to PMA when rx_att_gain_autocal_dis=1
32919 … (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_autocal_dis=1
32935 …FE_TAP1_OVR_VAL_O_6_0_K2_E5 (0x7f<<0) // DFE Tap 1 Override Value
32952 …3_X157_TXEQ_ERR_SIGN_O_1_K2_E5 (0x1<<1) // TX Equalizer Err…
32953 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X157_TXEQ_ERR_SIGN_O_1_K2_E5_SHIFT 1
32954 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
32960 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
32962 … 0x001a80UL //Access:R DataWidth:0x8 // Over equalization count 7-0
32964 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
32966 … 0x001a88UL //Access:R DataWidth:0x8 // Under equalization count 7-0
32971 … 0x001a94UL //Access:RW DataWidth:0x8 // Mask bit for Txeq training p…
32973 …DONT_CARE_O_8_K2_E5 (0x1<<0) // Mask bit for Txeq training p…
32976 … (0x1<<0) // This bit has similar function as txeq_rxrecal_init in COMLANE CSR. It is l…
32981 …3_X168_RECAL_RX_PRESET_HINT_EN_O_K2_E5 (0x1<<1) // Enable for prima…
32982 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X168_RECAL_RX_PRESET_HINT_EN_O_K2_E5_SHIFT 1
32984 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
32990 …_E5 (0x1<<0) // cdfe enable bit. 1: enable cdfe when…
32992 …1) // The cdfe input word_i overwrite. …
32993 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X201_CDFE_WORD_OV_O_1_0_K2_E5_SHIFT 1
32994 … 0 10-bit or 20-bit mode. 2'b11: the mode_8b_…
32996 …1:0] overwrite. …
33002 …e calibration enable. 1: enable force cdfe calibration. 0: disable force cdfe calibration. Note…
33004 …e calibration enable. 1: enable force cdfe calibration. 0: disable force cdfe calibration. Note…
33006 …1: the cdfe calibration is enabled when EI exits and when rate is 2'b01 or 2'b10. …
33009 …1: the continuous cdfe calibration is enabled when the rate is 2'b01 or 2'b10. …
33011 …1) // Enables cdfe calibration during Txeq adaptation phase. …
33012 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL_K2_E5_SHIFT 1
33013 … 1: the cdfe calibratio…
33015 … (0x1<<3) // Enables the cdfe calibration in rate3. 1: enables cdfe calibr…
33017 … (0x1<<4) // Enables the cdfe calibration in rate2. 1: enables cdfe calibr…
33019 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
33020 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
33021 …-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
33023 … (0x1<<7) // cdfe coarse dll overwrite enable. 1: enable coarse dll o…
33025 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
33026 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
33027 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
33028 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
33029 …-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
33032 …bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enabl…
33035 …bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enabl…
33038 …) // Override for CMP1 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[1]
33053 …) // Override for CMP2 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[1]
33068 …) // Override for CMP3 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[1]
33083 …) // Override for CMP4 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[1]
33110 … (0x1<<4) // cdfe fine dll overwrite enable. 1: enable fine dll ove…
33115 …REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_K2_E5 (0x1<<1) //
33116 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_K2_E5_SHIFT 1
33128 …3_X255_CDFE_DIR_OV_VAL_K2_E5 (0x1<<1) // Override value f…
33129 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_CDFE_DIR_OV_VAL_K2_E5_SHIFT 1
33130 … (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed…
33132 … (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed…
33134 … (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed…
33136 … (0x1<<5) // cdfe eye delay overwrite enable. 1: enable eye delay ov…
33138 … (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed…
33144 …_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_K2_E5 (0x7f<<1) // This register re…
33145 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_K2_E5_SHIFT 1
33150 …EV_OV_EN_K2_E5 (0x1<<1) // cdfe dlev overwrite enable. 1: en…
33151 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_AHB_CDFE_DLEV_OV_EN_K2_E5_SHIFT 1
33152 …ister override for overriding adaptation comparator select bit [0] : override enable bit [4:1] : o…
33154 …override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : o…
33156 …override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : o…
33159 …Bit[0]: enable tap1 overwrite for cdfe. Bit[1]: enable tap2 overwrite for cdfe Bit[2]: enable tap3…
33181 …REG_AHB_LANE_CSR_3_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_K2_E5 (0x1<<1) //
33182 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_K2_E5_SHIFT 1
33190 …REG_AHB_LANE_CSR_3_X269_AHB_CDFE_STROBE_EN_O_K2_E5 (0x1<<1) //
33191 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X269_AHB_CDFE_STROBE_EN_O_K2_E5_SHIFT 1
33228 …K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_ra Bit …
33230 …_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_p2s Bit…
33232 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_reset_lnregh Bi…
33234 …O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_reset_lnreg Bi…
33237 …_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_cdr Bit…
33239 …_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_dfe Bit…
33241 …_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_pd_lnregh Bit…
33243 …_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_pd_vco_buf Bit…
33246 …_O_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_cdr_gcrx B…
33248 …_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_rxgate_en Bit…
33250 …_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_reset_vco Bit…
33252 …K2_E5 (0x3<<6) // Bit 0: Override enable for msm_iddq_sd Bit …
33255 …2_E5 (0x3<<0) // Bit 0: Override enable for msm_pd_dfe Bit 1…
33257 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_pd_dfe_bias Bi…
33259 …_O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_txdrv_lp_idle B…
33261 …R_O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_txreg_bleed_ena …
33264 …K2_E5 (0x3<<0) // Bit 0: Override enable for msm_pd_txreg Bit …
33266 …K2_E5 (0x3<<2) // Bit 0: Override enable for msm_pd_lnreg Bit …
33268 …_K2_E5 (0x3<<4) // Bit 0: Override enable for pd_p2s Bit 1: …
33270 …_K2_E5 (0x3<<6) // Bit 0: Override enable for pd_ra Bit 1: …
33273 …R_O_K2_E5 (0x3<<2) // Bit 0: Override enable for pd_slv_bias Bit …
33275 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for pd_txdrv Bit 1:…
33277 …2_E5 (0x3<<6) // Bit 0: Override enable for msm_pd_vco Bit 1…
33280 …2_E5 (0x3<<0) // Bit 0: Override enable for msm_cdr_en Bit 1…
33282 …_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_s2p Bit…
33284 …K2_E5 (0x3<<4) // Bit 0: Override enable for msm_rxclk_en Bit …
33286 …_E5 (0x3<<6) // Bit 0: Override enable for msm_word Bit 1:…
33289 …E5 (0x7<<0) // Bit 0: Override enable for msm_rate Bit [2:…
33291 …2_E5 (0x7<<3) // Bit 0: Override enable for msm_rxvcodiv Bit […
33296 …2_E5 (0x7<<0) // Bit 0: Override enable for msm_txvcodiv Bit […
33299 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
33301 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmo…
33302 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_TREG0_POL_O_K2_E5_SHIFT 1
33303 …0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
33305 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33309 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
33312 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
33314 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmod…
33315 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_TREG1_BIT_O_K2_E5_SHIFT 1
33316 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33318 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
33320 …(0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
33322 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33327 …(0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
33329 … (0x1<<1) // Reg0 data bank word order select. 0 - Normal word order used - words are not …
33330 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_REG0_WORD_O_K2_E5_SHIFT 1
33333 …3_TX_CTRL_O_24_K2_E5 (0x1<<5) // Bit 24: txdrv_c2_in[3]
33335 …HNG_EN_O_K2_E5 (0x1<<6) // Enable bit for width_chng modu…
33342 … (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2�b00: no bit stripping 2�b01: 2x bit st…
33347 … communication between the external 64-bit data and the internal 20-bit data. The reading operatio…
33349 …Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2�b00: no bit stuf…
33351 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
33360 …bit. 1: in NORM state, lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA or it…
33372 …3_X308_BLOCK_ENC_CLR_ERR_O_K2_E5 (0x1<<1) // 128b/130b encode…
33373 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_ENC_CLR_ERR_O_K2_E5_SHIFT 1
33388 …3_X310_ALIGN_RSTN_O_K2_E5 (0x1<<1) // Synchronous clea…
33389 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_ALIGN_RSTN_O_K2_E5_SHIFT 1
33404 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
33406 …_RXVALID_DIS_AT_RATE_CHG_O_0_K2_E5 (0x1<<1) // Value 1 forces rxvalid…
33407 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X312_RXVALID_DIS_AT_RATE_CHG_O_0_K2_E5_SHIFT 1
33411 …BLE_O_K2_E5 (0x1<<0) // 0: enable rx_gearbox, 1: disable rx_gearbox
33413 …GEARBOX_DISABLE_O_K2_E5 (0x1<<1) // 0: enable tx_gearbox, 1: disab…
33414 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X313_AHB_TX_GEARBOX_DISABLE_O_K2_E5_SHIFT 1
33416 … (0x1<<0) // Mux select for data input to polbit_reg0 0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i
33418 … (0x1<<1) // To skip cdr calibration routines for PCIe gen3. Can be used when P…
33419 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_SKIP_CDR_GEN3_O_K2_E5_SHIFT 1
33433 …R_3_X317_AHB_BEACON_ENA_OVR_O_K2_E5 (0x1<<1) // Beacon Override
33434 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_AHB_BEACON_ENA_OVR_O_K2_E5_SHIFT 1
33439 …f<<4) // Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty…
33442 …1_0_K2_E5 (0x3<<0) // Bit[0]: Overide value. Bit[1] :Overr…
33444 …x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the override, while bit 0 …
33446 … (0x3<<4) // Override enable for DFE signal detect indicator input. Bit 1 is overide enable …
33449 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override enable, bit 0 is …
33451 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override enable, bit 0 is …
33453 …x3<<4) // Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 …
33459 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
33460 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
33461 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
33462 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
33463 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
33464 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
33466 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
33468 … (0x1<<1) // Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is …
33469 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_AHB_LN_IN_OVR_CHG_FLAG_O_K2_E5_SHIFT 1
33470 …it_regp1 Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty…
33477 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
33485 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
33488 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
33490 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
33493 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
33496 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
33498 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 C…
33499 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X3_PMA_TXCLK_SEL_O_1_K2_E5_SHIFT 1
33501 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
33503 … (0x3<<2) // Static divider control for Lane GCFSM clock The only access to this divi…
33505 … 2'b00: lnX_ck_txb_o is divided by 1 version of the tx by…
33510 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
33512 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
33517 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
33519 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
33525 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
33527 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
33532 …3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends norm…
33534 …/ Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ev…
33536 … 0x002024UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
33537 … 0x002028UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
33538 … 0x00202cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
33539 … 0x002030UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
33540 …// Bist generator - Number of words between insert word insertions. Insertions are done in both pr…
33542 …// Bist generator - Number of words between insert word insertions. Insertions are done in both pr…
33549 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
33557 …checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be…
33559 …checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be…
33563 …ON_ZEROS_K2_E5 (0x1<<5) // Setting this bit allows BIST to sync…
33569 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
33570 … 0x002054UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33571 … 0x002058UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33572 … 0x00205cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33573 … 0x002060UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33581 … 0x002080UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
33582 … 0x002084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
33583 … 0x002088UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
33584 … 0x00208cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
33585 … 0x002090UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
33586 … 0x002094UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
33587 … 0x002098UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
33588 … 0x00209cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
33589 … 0x0020a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
33590 … 0x0020a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
33591 … 0x0020a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
33592 … 0x0020acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
33593 … 0x0020b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
33594 … 0x0020b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
33595 … 0x0020b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
33596 … 0x0020bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
33597 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA me…
33598 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
33599 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA me…
33600 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
33603 … (0x1f<<0) // The start length of DFE offset calibration, except for the 1st cycle.
33605 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
33607 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
33609 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
33611 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
33612 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
33613 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
33615 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
33617 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
33629 …lect, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion…
33630 …lect, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion…
33632 …_E5 (0x3<<0) // Bit 0: Override enable for msm_ln_req Bit 1…
33634 …_MSM_FUNC_IN_OVR_O_K2_E5 (0x3f<<2) // Bit 2: Override enable…
33661 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
33663 …1) // ATT wait control. Upon detection of signal, DFE ATT calibration is enabled, without CISEL be…
33664 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_CDR_CONTROL_ATT_CTRL_O_K2_E5_SHIFT 1
33665 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
33669 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
33670 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
33671 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
33673 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
33675 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
33705 … (0x3<<2) // EI Exit time cycles = timer_len_sel[1:0]+1*exit_timer_len_i[9…
33712 …4_X86_NES_LB_ENA_O_K2_E5 (0x1<<1) // NES loopback ena…
33713 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X86_NES_LB_ENA_O_K2_E5_SHIFT 1
33719 …_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O_K2_E5 (0x7f<<1) // RX boost overrid…
33720 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O_K2_E5_SHIFT 1
33725 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
33727 … (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye …
33732 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
33759 …e_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
33774 …x3<<6) // CDR phase detector proportional path enable bit 0: enables D4/D3 data/edge samplers bit …
33776 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
33778 …-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2…
33782 … (0x1<<3) // RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth
33784 …rides the ck_270 DFE clock "right" eye edge clock with the shifted clock. Only assert one of pma_l…
33786 …errides the ck_90 DFE clock "left" eye edge clock with the shifted clock. Only assert one of pma_l…
33794 …(0xf<<4) // TX coefficient polarity enable. Set to "1" for negative polarity. bit 0: Cm bit 1: C0 …
33809 …_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O_K2_E5 (0x7f<<1) // RX boost overrid…
33810 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O_K2_E5_SHIFT 1
33817 … (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye …
33842 …e_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
33867 …4) // when 1, the final tx term value is calibrated txterm value + tx_cxp_margin; when 0, the fina…
33869 …5) // when 1, the final tx term value is calibrated txterm value + tx_cxn_margin; when 0, the fina…
33881 … (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not c…
33883 … (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_slew_sld[1:0]
33886 …21f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx_slew_sld3f[2…
33890 …4_X126_RXEQ_LN_RATE_OW_O_2_0_K2_E5 (0x7<<1) // These bits have …
33891 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_RATE_OW_O_2_0_K2_E5_SHIFT 1
33892 … (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is l…
33894 … (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is l…
33896 … (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is l…
33898 … (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is l…
33901 …1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: en…
33904 …1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: en…
33954 …IMIT_O_K2_E5 (0xf<<1) // Max limit value for BOOST auto-cal…
33955 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X143_BOOST_MAX_LIMIT_O_K2_E5_SHIFT 1
33956 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
33967 …_E5 (0xf<<4) // boost_adj_val This register Is not bit reversed
33995 … for comparator calibration select. Enabled by rxeq_ovr_en_o: 1: Calibrate DFE comparator 1 2: Cal…
33997 … (0x3<<3) // Override the value of rx_att_gain output to PMA when rx_att_gain_autocal_dis=1
33999 … (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_autocal_dis=1
34015 …FE_TAP1_OVR_VAL_O_6_0_K2_E5 (0x7f<<0) // DFE Tap 1 Override Value
34032 …4_X157_TXEQ_ERR_SIGN_O_1_K2_E5 (0x1<<1) // TX Equalizer Err…
34033 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X157_TXEQ_ERR_SIGN_O_1_K2_E5_SHIFT 1
34034 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
34040 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
34042 … 0x002280UL //Access:R DataWidth:0x8 // Over equalization count 7-0
34044 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
34046 … 0x002288UL //Access:R DataWidth:0x8 // Under equalization count 7-0
34051 … 0x002294UL //Access:RW DataWidth:0x8 // Mask bit for Txeq training p…
34053 …DONT_CARE_O_8_K2_E5 (0x1<<0) // Mask bit for Txeq training p…
34056 … (0x1<<0) // This bit has similar function as txeq_rxrecal_init in COMLANE CSR. It is l…
34061 …4_X168_RECAL_RX_PRESET_HINT_EN_O_K2_E5 (0x1<<1) // Enable for prima…
34062 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X168_RECAL_RX_PRESET_HINT_EN_O_K2_E5_SHIFT 1
34064 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
34070 …_E5 (0x1<<0) // cdfe enable bit. 1: enable cdfe when…
34072 …1) // The cdfe input word_i overwrite. …
34073 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X201_CDFE_WORD_OV_O_1_0_K2_E5_SHIFT 1
34074 … 0 10-bit or 20-bit mode. 2'b11: the mode_8b_…
34076 …1:0] overwrite. …
34082 …e calibration enable. 1: enable force cdfe calibration. 0: disable force cdfe calibration. Note…
34084 …e calibration enable. 1: enable force cdfe calibration. 0: disable force cdfe calibration. Note…
34086 …1: the cdfe calibration is enabled when EI exits and when rate is 2'b01 or 2'b10. …
34089 …1: the continuous cdfe calibration is enabled when the rate is 2'b01 or 2'b10. …
34091 …1) // Enables cdfe calibration during Txeq adaptation phase. …
34092 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL_K2_E5_SHIFT 1
34093 … 1: the cdfe calibratio…
34095 … (0x1<<3) // Enables the cdfe calibration in rate3. 1: enables cdfe calibr…
34097 … (0x1<<4) // Enables the cdfe calibration in rate2. 1: enables cdfe calibr…
34099 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
34100 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
34101 …-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
34103 … (0x1<<7) // cdfe coarse dll overwrite enable. 1: enable coarse dll o…
34105 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
34106 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
34107 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
34108 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
34109 …-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
34112 …bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enabl…
34115 …bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enabl…
34118 …) // Override for CMP1 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[1]
34133 …) // Override for CMP2 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[1]
34148 …) // Override for CMP3 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[1]
34163 …) // Override for CMP4 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[1]
34190 … (0x1<<4) // cdfe fine dll overwrite enable. 1: enable fine dll ove…
34195 …REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_K2_E5 (0x1<<1) //
34196 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_K2_E5_SHIFT 1
34208 …4_X255_CDFE_DIR_OV_VAL_K2_E5 (0x1<<1) // Override value f…
34209 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_CDFE_DIR_OV_VAL_K2_E5_SHIFT 1
34210 … (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed…
34212 … (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed…
34214 … (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed…
34216 … (0x1<<5) // cdfe eye delay overwrite enable. 1: enable eye delay ov…
34218 … (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed…
34224 …_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_K2_E5 (0x7f<<1) // This register re…
34225 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_K2_E5_SHIFT 1
34230 …EV_OV_EN_K2_E5 (0x1<<1) // cdfe dlev overwrite enable. 1: en…
34231 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_AHB_CDFE_DLEV_OV_EN_K2_E5_SHIFT 1
34232 …ister override for overriding adaptation comparator select bit [0] : override enable bit [4:1] : o…
34234 …override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : o…
34236 …override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : o…
34239 …Bit[0]: enable tap1 overwrite for cdfe. Bit[1]: enable tap2 overwrite for cdfe Bit[2]: enable tap3…
34261 …REG_AHB_LANE_CSR_4_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_K2_E5 (0x1<<1) //
34262 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_K2_E5_SHIFT 1
34270 …REG_AHB_LANE_CSR_4_X269_AHB_CDFE_STROBE_EN_O_K2_E5 (0x1<<1) //
34271 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X269_AHB_CDFE_STROBE_EN_O_K2_E5_SHIFT 1
34308 …K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_ra Bit …
34310 …_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_p2s Bit…
34312 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_reset_lnregh Bi…
34314 …O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_reset_lnreg Bi…
34317 …_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_cdr Bit…
34319 …_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_dfe Bit…
34321 …_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_pd_lnregh Bit…
34323 …_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_pd_vco_buf Bit…
34326 …_O_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_cdr_gcrx B…
34328 …_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_rxgate_en Bit…
34330 …_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_reset_vco Bit…
34332 …K2_E5 (0x3<<6) // Bit 0: Override enable for msm_iddq_sd Bit …
34335 …2_E5 (0x3<<0) // Bit 0: Override enable for msm_pd_dfe Bit 1…
34337 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_pd_dfe_bias Bi…
34339 …_O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_txdrv_lp_idle B…
34341 …R_O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_txreg_bleed_ena …
34344 …K2_E5 (0x3<<0) // Bit 0: Override enable for msm_pd_txreg Bit …
34346 …K2_E5 (0x3<<2) // Bit 0: Override enable for msm_pd_lnreg Bit …
34348 …_K2_E5 (0x3<<4) // Bit 0: Override enable for pd_p2s Bit 1: …
34350 …_K2_E5 (0x3<<6) // Bit 0: Override enable for pd_ra Bit 1: …
34353 …R_O_K2_E5 (0x3<<2) // Bit 0: Override enable for pd_slv_bias Bit …
34355 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for pd_txdrv Bit 1:…
34357 …2_E5 (0x3<<6) // Bit 0: Override enable for msm_pd_vco Bit 1…
34360 …2_E5 (0x3<<0) // Bit 0: Override enable for msm_cdr_en Bit 1…
34362 …_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_s2p Bit…
34364 …K2_E5 (0x3<<4) // Bit 0: Override enable for msm_rxclk_en Bit …
34366 …_E5 (0x3<<6) // Bit 0: Override enable for msm_word Bit 1:…
34369 …E5 (0x7<<0) // Bit 0: Override enable for msm_rate Bit [2:…
34371 …2_E5 (0x7<<3) // Bit 0: Override enable for msm_rxvcodiv Bit […
34376 …2_E5 (0x7<<0) // Bit 0: Override enable for msm_txvcodiv Bit […
34379 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
34381 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmo…
34382 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_TREG0_POL_O_K2_E5_SHIFT 1
34383 …0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
34385 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34389 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
34392 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
34394 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmod…
34395 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_TREG1_BIT_O_K2_E5_SHIFT 1
34396 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34398 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
34400 …(0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
34402 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34407 …(0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
34409 … (0x1<<1) // Reg0 data bank word order select. 0 - Normal word order used - words are not …
34410 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_REG0_WORD_O_K2_E5_SHIFT 1
34413 …3_TX_CTRL_O_24_K2_E5 (0x1<<5) // Bit 24: txdrv_c2_in[3]
34415 …HNG_EN_O_K2_E5 (0x1<<6) // Enable bit for width_chng modu…
34422 … (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2�b00: no bit stripping 2�b01: 2x bit st…
34427 … communication between the external 64-bit data and the internal 20-bit data. The reading operatio…
34429 …Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2�b00: no bit stuf…
34431 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
34440 …bit. 1: in NORM state, lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA or it…
34452 …4_X308_BLOCK_ENC_CLR_ERR_O_K2_E5 (0x1<<1) // 128b/130b encode…
34453 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_ENC_CLR_ERR_O_K2_E5_SHIFT 1
34468 …4_X310_ALIGN_RSTN_O_K2_E5 (0x1<<1) // Synchronous clea…
34469 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_ALIGN_RSTN_O_K2_E5_SHIFT 1
34484 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
34486 …_RXVALID_DIS_AT_RATE_CHG_O_0_K2_E5 (0x1<<1) // Value 1 forces rxvalid…
34487 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X312_RXVALID_DIS_AT_RATE_CHG_O_0_K2_E5_SHIFT 1
34491 …BLE_O_K2_E5 (0x1<<0) // 0: enable rx_gearbox, 1: disable rx_gearbox
34493 …GEARBOX_DISABLE_O_K2_E5 (0x1<<1) // 0: enable tx_gearbox, 1: disab…
34494 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X313_AHB_TX_GEARBOX_DISABLE_O_K2_E5_SHIFT 1
34496 … (0x1<<0) // Mux select for data input to polbit_reg0 0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i
34498 … (0x1<<1) // To skip cdr calibration routines for PCIe gen3. Can be used when P…
34499 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_SKIP_CDR_GEN3_O_K2_E5_SHIFT 1
34513 …R_4_X317_AHB_BEACON_ENA_OVR_O_K2_E5 (0x1<<1) // Beacon Override
34514 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_AHB_BEACON_ENA_OVR_O_K2_E5_SHIFT 1
34519 …f<<4) // Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty…
34522 …1_0_K2_E5 (0x3<<0) // Bit[0]: Overide value. Bit[1] :Overr…
34524 …x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the override, while bit 0 …
34526 … (0x3<<4) // Override enable for DFE signal detect indicator input. Bit 1 is overide enable …
34529 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override enable, bit 0 is …
34531 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override enable, bit 0 is …
34533 …x3<<4) // Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 …
34539 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
34540 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
34541 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
34542 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
34543 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
34544 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
34546 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
34548 … (0x1<<1) // Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is …
34549 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_AHB_LN_IN_OVR_CHG_FLAG_O_K2_E5_SHIFT 1
34550 …it_regp1 Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty…
34557 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
34565 … (0x1<<0) // Lane Reference Clock Enable. 0 - gcfsm_refmux_clk = pma_cm_ref_clk_i 1 - …
34568 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
34570 …1) // Enable/Disable the internal PRBS data pattern inverter. 0x0 � Invert the PRBS data pattern f…
34571 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_GEN_INV_PRBS_O_K2_E5_SHIFT 1
34577 …818UL //Access:RW DataWidth:0x8 // Symbol aligner alignment word. Expects bit 0 received first
34579 … (0x3<<0) // Symbol aligner alignment word. Expects bit 0 received first
34589 … 0x002830UL //Access:RW DataWidth:0x8 // The remaining 16 bit words of an EIEOS i…
34590 … 0x002834UL //Access:RW DataWidth:0x8 // The remaining 16 bit words of an EIEOS i…
34593 … 0x002840UL //Access:RW DataWidth:0x8 // The remaining 16 bit words of an SDSOS i…
34594 … 0x002844UL //Access:RW DataWidth:0x8 // The remaining 16 bit words of an SDSOS i…
34597 … 0x002850UL //Access:RW DataWidth:0x8 // The remaining 16 bit words of a SKPOS in…
34598 … 0x002854UL //Access:RW DataWidth:0x8 // The remaining 16 bit words of a SKPOS in…
34621 … 0x002880UL //Access:RW DataWidth:0x8 // SKP symbol for PCIe Gen3 SKP OS ---8'hAA
34631 … 0x002898UL //Access:RW DataWidth:0x8 // 10-bit align symbol for eb…
34633 …0_LB_P_O_9_8_K2_E5 (0x3<<0) // 10-bit align symbol for eb…
34635 … 0x0028a0UL //Access:RW DataWidth:0x8 // 10-bit align symbol for eb…
34637 …1_LB_P_O_9_8_K2_E5 (0x3<<0) // 10-bit align symbol for eb…
34640 …SR_5_X43_CDR_CTRL_DLPF_RAIL_RST_EN_O_K2_E5 (0x1<<1) // Enable resetting…
34641 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X43_CDR_CTRL_DLPF_RAIL_RST_EN_O_K2_E5_SHIFT 1
34645 …R_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_VAL_O_K2_E5 (0x1f<<1) // Default DOSC adj…
34646 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_VAL_O_K2_E5_SHIFT 1
34659 …REG_AHB_COMLANE_CSR_5_X46_CPUCLK_SEL_O_K2_E5 (0x1<<1) //
34660 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_CPUCLK_SEL_O_K2_E5_SHIFT 1
34673 …REG_AHB_COMLANE_CSR_5_X48_LOS_LN1_INTRPT_I_1_K2_E5 (0x1<<1) //
34674 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN1_INTRPT_I_1_K2_E5_SHIFT 1
34682 …SR_5_X49_EYE_SCAN_RUN_O_K2_E5 (0x1<<1) // Run eye scan cou…
34683 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_RUN_O_K2_E5_SHIFT 1
34700 … (0x3<<0) // Static divider control for Lane GCFSM clock The only access to this divi…
34702 … 0x0028e0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
34703 … 0x0028e4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
34704 … 0x0028e8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
34705 … 0x0028ecUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
34706 … 0x0028f0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
34707 … 0x0028f4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
34708 … 0x0028f8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
34709 … 0x0028fcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
34710 … 0x002900UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
34711 … 0x002904UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
34712 … 0x002908UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
34713 … 0x00290cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
34714 … 0x002910UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
34715 … 0x002914UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
34716 … 0x002918UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
34717 … 0x00291cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
34720 …nction. Varies depending on function number. Bits 15-7: Address of first command to run Bits: 6-…
34789 …M state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to rec…
34790 …M state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to rec…
34794 …SR_5_X143_MSM_SAPI_IDDQ_PD_DFE_O_K2_E5 (0x1<<1) // MSM Function IDD…
34795 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_O_K2_E5_SHIFT 1
34811 …SR_5_X144_MSM_SAPI_IDDQ_PD_TXDRV_O_K2_E5 (0x1<<1) // MSM Function IDD…
34812 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXDRV_O_K2_E5_SHIFT 1
34828 …SR_5_X145_MSM_SAPI_IDDQ_RESET_LNREGH_O_K2_E5 (0x1<<1) // MSM Function IDD…
34829 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREGH_O_K2_E5_SHIFT 1
34845 …SR_5_X146_MSM_SAPI_IDDQ_RXBCLK_EN_O_K2_E5 (0x1<<1) // MSM Function IDD…
34846 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RXBCLK_EN_O_K2_E5_SHIFT 1
34854 …SR_5_X147_MSM_SAPI_RST_PD_DFE_O_K2_E5 (0x1<<1) // MSM Function RES…
34855 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_O_K2_E5_SHIFT 1
34871 …SR_5_X148_MSM_SAPI_RST_PD_TXDRV_O_K2_E5 (0x1<<1) // MSM Function RES…
34872 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXDRV_O_K2_E5_SHIFT 1
34888 …SR_5_X149_MSM_SAPI_RST_RESET_LNREGH_O_K2_E5 (0x1<<1) // MSM Function RES…
34889 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREGH_O_K2_E5_SHIFT 1
34905 …SR_5_X150_MSM_SAPI_RST_RXBCLK_EN_O_K2_E5 (0x1<<1) // MSM Function RES…
34906 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RXBCLK_EN_O_K2_E5_SHIFT 1
34914 …SR_5_X151_MSM_SAPI_NORM_PD_DFE_O_K2_E5 (0x1<<1) // MSM Function NOR…
34915 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_O_K2_E5_SHIFT 1
34931 …SR_5_X152_MSM_SAPI_NORM_PD_TXDRV_O_K2_E5 (0x1<<1) // MSM Function NOR…
34932 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXDRV_O_K2_E5_SHIFT 1
34948 …SR_5_X153_MSM_SAPI_NORM_RESET_LNREGH_O_K2_E5 (0x1<<1) // MSM Function NOR…
34949 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREGH_O_K2_E5_SHIFT 1
34965 …SR_5_X154_MSM_SAPI_NORM_RXBCLK_EN_O_K2_E5 (0x1<<1) // MSM Function NOR…
34966 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RXBCLK_EN_O_K2_E5_SHIFT 1
34974 …SR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_O_K2_E5 (0x1<<1) // MSM Function PAR…
34975 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_O_K2_E5_SHIFT 1
34991 …SR_5_X156_MSM_SAPI_PARTIAL_PD_TXDRV_O_K2_E5 (0x1<<1) // MSM Function PAR…
34992 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXDRV_O_K2_E5_SHIFT 1
35008 …SR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREGH_O_K2_E5 (0x1<<1) // MSM Function PAR…
35009 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREGH_O_K2_E5_SHIFT 1
35025 …SR_5_X158_MSM_SAPI_PARTIAL_RXBCLK_EN_O_K2_E5 (0x1<<1) // MSM Function PAR…
35026 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RXBCLK_EN_O_K2_E5_SHIFT 1
35034 …SR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_O_K2_E5 (0x1<<1) // MSM Function SLU…
35035 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_O_K2_E5_SHIFT 1
35051 …SR_5_X160_MSM_SAPI_SLUMBER_PD_TXDRV_O_K2_E5 (0x1<<1) // MSM Function SLU…
35052 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXDRV_O_K2_E5_SHIFT 1
35068 …SR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREGH_O_K2_E5 (0x1<<1) // MSM Function SLU…
35069 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREGH_O_K2_E5_SHIFT 1
35085 …SR_5_X162_MSM_SAPI_SLUMBER_RXBCLK_EN_O_K2_E5 (0x1<<1) // MSM Function SLU…
35086 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RXBCLK_EN_O_K2_E5_SHIFT 1
35199 …ANE_CSR_5_X197_TXCTRL_PREEM_1LSB_MODE_K2_E5 (0x1<<0) // TX 1lsb mode
35201 …7_TXCTRL_MASTER_PREEM_1LSB_MODE_OVR_K2_E5 (0x1<<1) // TX master 1lsb mode over…
35202 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X197_TXCTRL_MASTER_PREEM_1LSB_MODE_OVR_K2_E5_SHIFT 1
35203 …E1_TX_SLEW_SLD3F_2_0_K2_E5 (0x7<<2) // TX enable fastest slew rate set to 1.
35205 …E2_TX_SLEW_SLD3F_2_0_K2_E5 (0x7<<5) // TX enable fastest slew rate set to 1.
35208 …E3_TX_SLEW_SLD3F_2_0_K2_E5 (0x7<<0) // TX enable fastest slew rate set to 1.
35260 …LOW_EN_O_K2_E5 (0x1<<6) // Brings the TxEq pre-cursor down to a prog…
35262 …OW_EN_O_K2_E5 (0x1<<7) // Brings the TxEq pre-cursor down to a prog…
35280 … (0x1<<6) // Set all DFE calibration values to mid-scale instead of usin…
35282 … 0x002b5cUL //Access:RW DataWidth:0x8 // DFE block -continuous calibratio…
35284 …NT_LENGTH_O_14_8_K2_E5 (0x7f<<0) // DFE block -continuous calibratio…
35286 … 0x002b64UL //Access:RW DataWidth:0x8 // DFE block - ATT calibration cycl…
35287 … 0x002b68UL //Access:RW DataWidth:0x8 // DFE block - Boost calibration cy…
35288 … 0x002b6cUL //Access:RW DataWidth:0x8 // DFE block - TAP1 calibration cyc…
35289 … 0x002b70UL //Access:RW DataWidth:0x8 // DFE block - TAP2 calibration cyc…
35290 … 0x002b74UL //Access:RW DataWidth:0x8 // DFE block - TAP3 calibration cyc…
35291 … 0x002b78UL //Access:RW DataWidth:0x8 // DFE block - TAP4 calibration cyc…
35292 … 0x002b7cUL //Access:RW DataWidth:0x8 // DFE block - TAP5 calibration cyc…
35296 …_RXEQ_RECAL_O_6_0_K2_E5 (0x7f<<1) // Enables re-calibration f…
35297 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X224_RXEQ_RECAL_O_6_0_K2_E5_SHIFT 1
35299 …bit [0]: Enables ATT calibration when asserted bit [1]: Enables Boost calibration when asserted bi…
35302 …bit [0]: Enables ATT calibration when asserted bit [1]: Enables Boost calibration when asserted bi…
35305 …TE2_RECAL_O_6_0_K2_E5 (0x7f<<0) // Enables re-calibration for { Tap…
35331 …R_5_X233_RXEQ_FIN_HIGH_O_6_0_K2_E5 (0x7f<<1) // Enable final cal…
35332 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X233_RXEQ_FIN_HIGH_O_6_0_K2_E5_SHIFT 1
35336 … (0x1<<7) // Testbus select for comp_offset and tap_offset 1: Raw output from i_d…
35339 …bit [0]: Reverses polarity of ATT calibration when asserted bit [1]: Reverses polarity of Boost ca…
35446 …SR_5_X273_TXEQ_ADAPT_RUN_1_0_K2_E5 (0x3<<1) // TxEQ Adapt 2 TAPs
35447 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X273_TXEQ_ADAPT_RUN_1_0_K2_E5_SHIFT 1
35452 …SR_5_X275_TXEQ_ADAPT_INIT_O_1_K2_E5 (0x1<<1) // Initiate TXEQ ad…
35453 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X275_TXEQ_ADAPT_INIT_O_1_K2_E5_SHIFT 1
35464 …E_I_3_0_K2_E5 (0xf<<0) // RXEQ calibration done status - per lane
35466 …DAPT_DONE_I_3_0_K2_E5 (0xf<<4) // TXEQ Adapt Done status - per lane
35475 …O_K2_E5 (0x1f<<0) // Bit 4 - latency check control enable Bit 3:0 …
35547 …g bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern b…
35550 …g bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern b…
35553 …g bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern b…
35556 …g bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern b…
35559 …g bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern b…
35562 …g bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern b…
35582 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
35585 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
35588 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
35591 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
35594 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
35597 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
35600 …bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enabl…
35603 …bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enabl…
35606 …bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enabl…
35609 …bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enabl…
35624 …/ Level of averaging used during cdfe dll coarse calibration 0: last data, 1: avg of last two dat…
35626 … // Level of averaging used during cdfe dll fine calibration 0: last data, 1: avg of last two dat…
35628 …<<4) // Level of averaging used during cdfe dlev calibration 0: last data, 1: avg of last two dat…
35633 …REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_COARSE_OV_FINE_EN_K2_E5 (0x1<<1) //
35634 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_COARSE_OV_FINE_EN_K2_E5_SHIFT 1
35689 …R_5_X369_QAHB_TAP1_CM1_DONT_CARE_O_K2_E5 (0x3f<<1) // Mask bits for CM…
35690 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_TAP1_CM1_DONT_CARE_O_K2_E5_SHIFT 1
35710 …SR_5_X376_MSM_PIPE_RST_PD_DFE_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
35711 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_O_K2_E5_SHIFT 1
35727 …SR_5_X377_MSM_PIPE_RST_PD_TXDRV_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
35728 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXDRV_O_K2_E5_SHIFT 1
35744 …SR_5_X378_MSM_PIPE_RST_RESET_LNREGH_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
35745 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREGH_O_K2_E5_SHIFT 1
35761 …SR_5_X379_MSM_PIPE_RST_RXBCLK_EN_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
35762 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RXBCLK_EN_O_K2_E5_SHIFT 1
35770 …SR_5_X380_MSM_PIPE_P0_PD_DFE_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
35771 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_O_K2_E5_SHIFT 1
35787 …SR_5_X381_MSM_PIPE_P0_PD_TXDRV_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
35788 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXDRV_O_K2_E5_SHIFT 1
35804 …SR_5_X382_MSM_PIPE_P0_RESET_LNREGH_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
35805 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREGH_O_K2_E5_SHIFT 1
35821 …SR_5_X383_MSM_PIPE_P0_RXBCLK_EN_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
35822 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RXBCLK_EN_O_K2_E5_SHIFT 1
35830 …SR_5_X384_MSM_PIPE_P1_PD_DFE_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
35831 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_O_K2_E5_SHIFT 1
35847 …SR_5_X385_MSM_PIPE_P1_PD_TXDRV_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
35848 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXDRV_O_K2_E5_SHIFT 1
35864 …SR_5_X386_MSM_PIPE_P1_RESET_LNREGH_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
35865 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREGH_O_K2_E5_SHIFT 1
35881 …SR_5_X387_MSM_PIPE_P1_RXBCLK_EN_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
35882 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RXBCLK_EN_O_K2_E5_SHIFT 1
35890 …SR_5_X388_MSM_PIPE_P2_PD_DFE_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
35891 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_O_K2_E5_SHIFT 1
35907 …SR_5_X389_MSM_PIPE_P2_PD_TXDRV_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
35908 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXDRV_O_K2_E5_SHIFT 1
35924 …SR_5_X390_MSM_PIPE_P2_RESET_LNREGH_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
35925 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREGH_O_K2_E5_SHIFT 1
35941 …SR_5_X391_MSM_PIPE_P2_RXBCLK_EN_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
35942 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RXBCLK_EN_O_K2_E5_SHIFT 1
35956 …SR_5_X401_L1_MASTER_CDN_O_K2_E5 (0x1<<1) // Lane1 master res…
35957 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L1_MASTER_CDN_O_K2_E5_SHIFT 1
35973 …_I_2_0_K2_E5 (0x7<<0) // 1000Base-KX Mode status for CPU
35982 …407_LN1_SIG_LEVEL_VALID_I_1_K2_E5 (0x1<<1) // Lane 1 Signal Detect V…
35983 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_SIG_LEVEL_VALID_I_1_K2_E5_SHIFT 1
35990 …CSR_5_X407_LN1_OK_I_5_K2_E5 (0x1<<5) // Lane 1 OK Status
35999 …408_LN1_RX_LOCKED_I_3_2_K2_E5 (0x3<<2) // Lane 1 RX Locked Status
36009 …_GEN12_ONLY_O_K2_E5 (0x1<<0) // Newly added for PCIe3 1CMU
36011 …_LANE_RESETN_RESET_CMU_EN_O_K2_E5 (0x1<<1) // Newly added for PCIe3 1CMU
36012 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RESETN_RESET_CMU_EN_O_K2_E5_SHIFT 1
36013 …_LANE_RATE_CHNG_OVR_EN_O_K2_E5 (0x1<<2) // Newly added for PCIe3 1CMU
36015 …_LANE_RATE_CHNG_OVR_O_K2_E5 (0x1<<3) // Newly added for PCIe3 1CMU
36017 …_LANE_GEN3_CAL_DONE_OVR_EN_O_K2_E5 (0x1<<4) // Newly added for PCIe3 1CMU
36019 …_LANE_GEN3_CAL_DONE_OVR_O_K2_E5 (0x1<<5) // Newly added for PCIe3 1CMU
36021 …_LANE_RATE_IS_GEN3_OVR_EN_O_K2_E5 (0x1<<6) // Newly added for PCIe3 1CMU
36023 …_LANE_RATE_IS_GEN3_OVR_O_K2_E5 (0x1<<7) // Newly added for PCIe3 1CMU
36026 …_LANE_EN_O_3_0_K2_E5 (0xf<<0) // Newly added for PCIe3 1CMU
36028 …_LANE_RESETN_OVR_EN_O_K2_E5 (0x1<<4) // Newly added for PCIe3 1CMU
36030 …_LANE_RESETN_OVR_O_K2_E5 (0x1<<5) // Newly added for PCIe3 1CMU
36036 …X414_TXPRESET_COEFF_P0CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P0 C-1
36039 …X415_TXPRESET_COEFF_P0CP1_O_K2_E5 (0x3f<<0) // txpreset_coeff P0 C+1
36045 …X417_TXPRESET_COEFF_P1CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P1 C-1
36048 …X418_TXPRESET_COEFF_P1CP1_O_K2_E5 (0x3f<<0) // txpreset_coeff P1 C+1
36054 …X420_TXPRESET_COEFF_P2CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P2 C-1
36057 …X421_TXPRESET_COEFF_P2CP1_O_K2_E5 (0x3f<<0) // txpreset_coeff P2 C+1
36063 …X423_TXPRESET_COEFF_P3CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P3 C-1
36066 …X424_TXPRESET_COEFF_P3CP1_O_K2_E5 (0x3f<<0) // txpreset_coeff P3 C+1
36072 …X426_TXPRESET_COEFF_P4CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P4 C-1
36075 …X427_TXPRESET_COEFF_P4CP1_O_K2_E5 (0x3f<<0) // txpreset_coeff P4 C+1
36081 …X429_TXPRESET_COEFF_P5CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P5 C-1
36084 …X430_TXPRESET_COEFF_P5CP1_O_K2_E5 (0x3f<<0) // txpreset_coeff P5 C+1
36090 …X432_TXPRESET_COEFF_P6CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P6 C-1
36093 …X433_TXPRESET_COEFF_P6CP1_O_K2_E5 (0x3f<<0) // txpreset_coeff P6 C+1
36099 …X435_TXPRESET_COEFF_P7CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P7 C-1
36102 …X436_TXPRESET_COEFF_P7CP1_O_K2_E5 (0x3f<<0) // txpreset_coeff P7 C+1
36108 …X438_TXPRESET_COEFF_P8CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P8 C-1
36111 …X439_TXPRESET_COEFF_P8CP1_O_K2_E5 (0x3f<<0) // txpreset_coeff P8 C+1
36117 …X441_TXPRESET_COEFF_P9CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P9 C-1
36120 …X442_TXPRESET_COEFF_P9CP1_O_K2_E5 (0x3f<<0) // txpreset_coeff P9 C+1
36126 …444_TXPRESET_COEFF_P10CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P10 C-1
36129 …445_TXPRESET_COEFF_P10CP1_O_K2_E5 (0x3f<<0) // txpreset_coeff P10 C+1
36171 …SR_5_X483_MSM_PIPE_P1_0_PD_VCO_BUF_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
36172 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_VCO_BUF_O_K2_E5_SHIFT 1
36188 …SR_5_X484_MSM_PIPE_P1_0_RESET_VCO_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
36189 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_VCO_O_K2_E5_SHIFT 1
36205 …SR_5_X485_MSM_PIPE_P1_0_PD_SLV_BIAS_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
36206 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_SLV_BIAS_O_K2_E5_SHIFT 1
36222 …SR_5_X486_MSM_PIPE_P1_0_TXREG_BLEED_ENA_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
36223 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TXREG_BLEED_ENA_O_K2_E5_SHIFT 1
36231 …SR_5_X487_MSM_PIPE_P1_1_PD_VCO_BUF_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
36232 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_VCO_BUF_O_K2_E5_SHIFT 1
36248 …SR_5_X488_MSM_PIPE_P1_1_RESET_VCO_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
36249 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_VCO_O_K2_E5_SHIFT 1
36265 …SR_5_X489_MSM_PIPE_P1_1_PD_SLV_BIAS_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
36266 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_SLV_BIAS_O_K2_E5_SHIFT 1
36282 …SR_5_X490_MSM_PIPE_P1_1_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
36283 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 1
36291 …SR_5_X491_MSM_PIPE_P1_2_PD_VCO_BUF_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
36292 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_VCO_BUF_O_K2_E5_SHIFT 1
36308 …SR_5_X492_MSM_PIPE_P1_2_RESET_DFE_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
36309 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_DFE_O_K2_E5_SHIFT 1
36325 …SR_5_X493_MSM_PIPE_P1_2_PD_S2P_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
36326 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_S2P_O_K2_E5_SHIFT 1
36342 …SR_5_X494_MSM_PIPE_P1_2_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<1) // MFSM's PMA pd/re…
36343 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 1
36355 …- no auto deassertion; 1 - auto deassertion); [1] rst_pswrd_auto_mode (0- no auto deassertion; 1 -…
36356 …-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out…
36358 …-shared blocks which can be reset also by driver in HV (PL=HV); Read: read one = the specific bloc…
36360 …-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers…
36362 …-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers…
36364 …-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers…
36366 …-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out…
36372 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
36380 …ccess:RW DataWidth:0x1 // Set/clr general attention 0; this will set/clr bit 48 in AEU vector.
36381 …UL //Access:RW DataWidth:0x1 // Set/clr general attention 1; this will set/clr bit 49 in AEU…
36382 …cess:RW DataWidth:0x1 // Set/clr general attention 2; this will set/clr bit 50 in AEU vector.
36383 …cess:RW DataWidth:0x1 // Set/clr general attention 3; this will set/clr bit 51 in AEU vector.
36384 …ccess:RW DataWidth:0x1 // Set/clr general attention 4; this will set/clr bit 52 in AEU vector.
36385 …ccess:RW DataWidth:0x1 // Set/clr general attention 5; this will set/clr bit 53 in AEU vector.
36386 …ccess:RW DataWidth:0x1 // Set/clr general attention 6; this will set/clr bit 54 in AEU vector.
36387 …ccess:RW DataWidth:0x1 // Set/clr general attention 7; this will set/clr bit 55 in AEU vector.
36388 …ccess:RW DataWidth:0x1 // Set/clr general attention 8; this will set/clr bit 56 in AEU vector.
36389 …ccess:RW DataWidth:0x1 // Set/clr general attention 9; this will set/clr bit 57 in AEU vector.
36390 …cess:RW DataWidth:0x1 // Set/clr general attention 10; this will set/clr bit 58 in AEU vector.
36391 …cess:RW DataWidth:0x1 // Set/clr general attention 11; this will set/clr bit 59 in AEU vector.
36392 …cess:RW DataWidth:0x1 // Set/clr general attention 12; this will set/clr bit 60 in AEU vector.
36393 …cess:RW DataWidth:0x1 // Set/clr general attention 13; this will set/clr bit 61 in AEU vector.
36394 …cess:RW DataWidth:0x1 // Set/clr general attention 14; this will set/clr bit 62 in AEU vector.
36395 …cess:RW DataWidth:0x1 // Set/clr general attention 15; this will set/clr bit 63 in AEU vector.
36396 …cess:RW DataWidth:0x1 // Set/clr general attention 16; this will set/clr bit 64 in AEU vector.
36397 …cess:RW DataWidth:0x1 // Set/clr general attention 17; this will set/clr bit 65 in AEU vector.
36398 …cess:RW DataWidth:0x1 // Set/clr general attention 18; this will set/clr bit 66 in AEU vector.
36399 …cess:RW DataWidth:0x1 // Set/clr general attention 19; this will set/clr bit 67 in AEU vector.
36400 …cess:RW DataWidth:0x1 // Set/clr general attention 20; this will set/clr bit 68 in AEU vector.
36401 …cess:RW DataWidth:0x1 // Set/clr general attention 21; this will set/clr bit 69 in AEU vector.
36402 …cess:RW DataWidth:0x1 // Set/clr general attention 22; this will set/clr bit 70 in AEU vector.
36403 …cess:RW DataWidth:0x1 // Set/clr general attention 23; this will set/clr bit 71 in AEU vector.
36404 …cess:RW DataWidth:0x1 // Set/clr general attention 24; this will set/clr bit 72 in AEU vector.
36405 …cess:RW DataWidth:0x1 // Set/clr general attention 25; this will set/clr bit 73 in AEU vector.
36406 …cess:RW DataWidth:0x1 // Set/clr general attention 26; this will set/clr bit 74 in AEU vector.
36407 …cess:RW DataWidth:0x1 // Set/clr general attention 27; this will set/clr bit 75 in AEU vector.
36408 …cess:RW DataWidth:0x1 // Set/clr general attention 28; this will set/clr bit 76 in AEU vector.
36409 …cess:RW DataWidth:0x1 // Set/clr general attention 29; this will set/clr bit 77 in AEU vector.
36410 …cess:RW DataWidth:0x1 // Set/clr general attention 30; this will set/clr bit 78 in AEU vector.
36411 …cess:RW DataWidth:0x1 // Set/clr general attention 31; this will set/clr bit 79 in AEU vector.
36412 …cess:RW DataWidth:0x1 // Set/clr general attention 32; this will set/clr bit 80 in AEU vector.
36413 …cess:RW DataWidth:0x1 // Set/clr general attention 33; this will set/clr bit 81 in AEU vector.
36414 …cess:RW DataWidth:0x1 // Set/clr general attention 34; this will set/clr bit 82 in AEU vector.
36415 …cess:RW DataWidth:0x1 // Set/clr general attention 35; this will set/clr bit 83 in AEU vector.
36416 …008490UL //Access:RW DataWidth:0x1 // Event_enable control; when this bit is clear the event …
36417 …:RW DataWidth:0x8 // [7:0] = mask 8 attention output signals toward IGU; 0 = mask; 1 = unmask.
36419 …rst 32b for enabling the output for output0. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36420 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36421 …for enabling the output for output0. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36422 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36423 … enabling the output for output0. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36424 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36425 …enabling the output for output0. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36426 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36427 … the output for output0. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36428 …rst 32b for enabling the output for output1. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36429 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36430 …for enabling the output for output1. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36431 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36432 … enabling the output for output1. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36433 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36434 …enabling the output for output1. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36435 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36436 … the output for output1. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36437 …rst 32b for enabling the output for output2. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36438 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36439 …for enabling the output for output2. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36440 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36441 … enabling the output for output2. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36442 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36443 …enabling the output for output2. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36444 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36445 … the output for output2. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36446 …rst 32b for enabling the output for output3. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36447 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36448 …for enabling the output for output3. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36449 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36450 … enabling the output for output3. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36451 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36452 …enabling the output for output3. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36453 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36454 … the output for output3. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36455 …rst 32b for enabling the output for output4. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36456 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36457 …for enabling the output for output4. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36458 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36459 … enabling the output for output4. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36460 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36461 …enabling the output for output4. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36462 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36463 … the output for output4. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36464 …rst 32b for enabling the output for output5. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36465 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36466 …for enabling the output for output5. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36467 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36468 … enabling the output for output5. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36469 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36470 …enabling the output for output5. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36471 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36472 … the output for output5. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36473 …rst 32b for enabling the output for output6. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36474 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36475 …for enabling the output for output6. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36476 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36477 … enabling the output for output6. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36478 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36479 …enabling the output for output6. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36480 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36481 … the output for output6. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36482 …rst 32b for enabling the output for output7. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36483 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36484 …for enabling the output for output7. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36485 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36486 … enabling the output for output7. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36487 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36488 …enabling the output for output7. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36489 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36490 … the output for output7. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36491 … enabling the output for close the gate nig. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36492 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36493 …g the output for close the gate nig. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36494 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36495 …he output for close the gate nig. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36496 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36497 …e output for close the gate nig. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36498 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36499 … for close the gate nig. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36500 … enabling the output for close the gate pxp. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36501 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36502 …g the output for close the gate pxp. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36503 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36504 …he output for close the gate pxp. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36505 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36506 …e output for close the gate pxp. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36507 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36508 … for close the gate pxp. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36509 …32b for enabling the output for system kill. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36510 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36511 …enabling the output for system kill. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36512 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36513 …bling the output for system kill. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36514 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36515 …ling the output for system kill. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36516 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36517 … output for system kill. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36518 …rst 32b for enabling the output for output0. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36519 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36520 …for enabling the output for output0. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36521 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36522 … enabling the output for output0. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36523 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36524 …enabling the output for output0. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36525 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36526 … the output for output0. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36527 …rst 32b for enabling the output for output1. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36528 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36529 …for enabling the output for output1. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36530 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36531 … enabling the output for output1. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36532 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36533 …enabling the output for output1. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36534 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36535 … the output for output1. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36536 …rst 32b for enabling the output for output2. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36537 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36538 …for enabling the output for output2. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36539 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36540 … enabling the output for output2. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36541 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36542 …enabling the output for output2. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36543 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36544 … the output for output2. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36545 …rst 32b for enabling the output for output3. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36546 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36547 …for enabling the output for output3. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36548 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36549 … enabling the output for output3. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36550 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36551 …enabling the output for output3. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36552 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36553 … the output for output3. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36554 …rst 32b for enabling the output for output4. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36555 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36556 …for enabling the output for output4. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36557 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36558 … enabling the output for output4. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36559 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36560 …enabling the output for output4. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36561 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36562 … the output for output4. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36563 …rst 32b for enabling the output for output5. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36564 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36565 …for enabling the output for output5. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36566 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36567 … enabling the output for output5. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36568 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36569 …enabling the output for output5. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36570 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36571 … the output for output5. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36572 …rst 32b for enabling the output for output6. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36573 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36574 …for enabling the output for output6. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36575 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36576 … enabling the output for output6. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36577 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36578 …enabling the output for output6. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36579 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36580 … the output for output6. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36581 …rst 32b for enabling the output for output7. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36582 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36583 …for enabling the output for output7. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36584 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36585 … enabling the output for output7. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36586 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36587 …enabling the output for output7. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36588 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36589 … the output for output7. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36590 …ng the output for global uncorrectable eror. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36591 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36592 …utput for global uncorrectable eror. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36593 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36594 …ut for global uncorrectable eror. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36595 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36596 …t for global uncorrectable eror. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36597 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36598 …obal uncorrectable eror. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36599 …0x20 // First 32b for inverting the input. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36600 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36601 …/ Third 32b for inverting the input. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36602 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36603 …ifth 32b for inverting the input. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36604 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36605 …nth 32b for inverting the input. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36606 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36607 …for inverting the input. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36608 …0x20 // First 32b for inverting the input. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36609 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36610 …/ Third 32b for inverting the input. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36611 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36612 …ifth 32b for inverting the input. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36613 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36614 …nth 32b for inverting the input. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36615 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36616 …for inverting the input. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36617 …0 // First 32b read after invert of input. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36618 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36619 …hird 32b read after invert of input. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36620 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36621 …h 32b read after invert of input. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36622 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36623 … 32b read after invert of input. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36624 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36625 …d after invert of input. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36626 …0 // First 32b read after invert of input. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36627 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36628 …hird 32b read after invert of input. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36629 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36630 …h 32b read after invert of input. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36631 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36632 … 32b read after invert of input. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36633 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36634 …d after invert of input. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36636 …0x008800UL //Access:RW DataWidth:0x1 // The System Kill enable: 0 - none; 1 - hard reset. Res…
36637 …ctor to the AEU when a system kill occurred. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; […
36638 …1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp…
36639 …the AEU when a system kill occurred. Mapped as follows: [0] General attn0; [1] General attn1; [2] …
36640 …1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interr…
36641 … AEU when a system kill occurred. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; […
36642 …1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM…
36643 …AEU when a system kill occurred. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; …
36644 …1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_cl…
36645 … a system kill occurred. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratch…
36647 … (0x1<<0) // Pxp close the gate mask bit; 0 = masked; 1 = unmasked.
36649 … (0x1<<1) // Nig close the gate mask bit; 0 = masked;…
36650 …ISC_REG_AEU_GENERAL_MASK_AEU_NIG_CLOSE_MASK_SHIFT 1
36651 … (0x1<<2) // System kill mask bit; 0 = masked; 1 = unmasked.
36653 … (0x1<<3) // Global uncorrectable error mask bit; 0 = masked; 1 = unmasked.
36655 …1] one clears Latched MCP Scratchpad Cache attention; [3:2] reserved; [4] one clears pglue_misc_mp…
36657 …with the clear of the latched signals; [0] - clears pglue_misc_vpd_attn[0], [1] - clears pglue_mis…
36659 …- latches first attention number within attentions vector. The number is produced as the index of …
36660 … 0x008c00UL //Access:RW DataWidth:0x2 // Port mode. 0 - single port; 1 - 2 ports; 2 - 4 por…
36661 … core. 00 - Single Port Mode; 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for …
36662 …- Single Port Mode; 01 - Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap …
36663 …- disabled, 1 - enabled. When OPTE mode is enabled, it connects two engines to one MAC port. Port…
36664 …bit; 1: clk_nw and main clk are asynchronous and sync FIFOs should be used. (clk_nw = 425 MHz); 0…
36665 …mmed to 1) or 128 byte (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G and 5…
36667 …- Storms stall is disallowed; AEU unifier bit[7] output to MCP is disabled; 1 - All Storms are for…
36668 … 0x008c20UL //Access:RW DataWidth:0x17 // 23 bit GRC address where the scratch-pad o…
36669 …1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-…
36670 …1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-…
36671 …1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-…
36672 …1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-…
36673 …1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-…
36674 …1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-…
36675 …1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-…
36676 …1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-…
36677 … counter 1 if reload; the value will be reload if the counter reached zero and the reload bit ( MI…
36678 …reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_2.SW_TIMER_CFG…
36679 …reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_3.SW_TIMER_CFG…
36680 …reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_4.SW_TIMER_CFG…
36681 …reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_1.SW_TIMER_CFG…
36682 …reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_1.SW_TIMER_CFG…
36683 … counter 1 if reload; the value will be reload if the counter reached zero and the reload bit ( MI…
36684 …reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_1.SW_TIMER_CFG…
36685 …bit will clear the appropriate event to the AEU (if the attn bit (bit 2) in the MISC_REGISTERS_SW_…
36686 … DataWidth:0x8 // The appropriate timer had reach to zero. [0] timer1; [1]timer2; [2] timer3; …
36688 … 0x008c70UL //Access:RW DataWidth:0x20 // Debug only: spare RW register …
36689 … 0x008c74UL //Access:RW DataWidth:0x20 // Debug only: spare RW register …
36690 … 0x008c78UL //Access:RW DataWidth:0x20 // Debug only: spare RW register …
36691 … 0x008c7cUL //Access:RW DataWidth:0x20 // Debug only: spare RW register …
36692 … 0x008c80UL //Access:RW DataWidth:0x20 // Debug only: spare RW register …
36693 … 0x008c84UL //Access:RW DataWidth:0x20 // Debug only: spare RW register …
36694 … 0x008c88UL //Access:RW DataWidth:0x20 // Debug only: spare RW register …
36695 … 0x008c8cUL //Access:RW DataWidth:0x20 // Debug only: spare RW register …
36696 … 0x008c90UL //Access:RW DataWidth:0x20 // Debug only: spare RW register …
36697 … 0x008c94UL //Access:RW DataWidth:0x20 // Debug only: spare RW register …
36698 … 0x008c98UL //Access:RW DataWidth:0x20 // Debug only: spare RW register …
36699 … 0x008c9cUL //Access:RW DataWidth:0x20 // Debug only: spare RW register …
36701 …he counter for sw timers1-8. there are 8 addresses in this register. address 0 - timer 1; address …
36703 …- no auto deassertion; 1 - auto deassertion); [1] rst_umac_on_core_rst (0- no auto deassertion; 1 …
36704 …- is not reset on hard reset; 1 - is reset on hard reset); [1] rst_n_hard_misc_rbc_pcie (0 - is no…
36705 …only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the spec…
36707 …1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the c…
36709 …ency (when programmed to 1) or is the same as main clock frequency (when programmed to 0). In E4 (…
36710 … size is 256 byte (when programmed to 1) or 128 byte (when programmed to 0). In E4 (BigBear) it sh…
36711 …- source of privilege level, 0 - the source is external pin, 1 - the source are bits[2:1] of this …
36712 … // Privilege level as defined by external pin. 0 - non-secured mode; 1 - secured mode; 2 - full…
36713 …-disable to the NVM block is generated. '0' - PROTECT: This value protects the NVM from any writes…
36714 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36716 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36718 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36720 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36722 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36724 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36726 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36728 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36730 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36732 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36734 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36736 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36738 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36740 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36742 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36744 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36746 …only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set …
36748 …only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set …
36750 …only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set …
36752 …only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set …
36754 …only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set …
36756 …only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set …
36758 …only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set …
36760 …only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set …
36762 …1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the c…
36772 …W (0x1<<1) // Generic sw overr…
36773 …ISCS_REG_INT_STS_0_GENERIC_SW_SHIFT 1
36777 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
36779 … (0x1<<1) // This bit masks, when set, the Interrupt …
36780 …ISCS_REG_INT_MASK_0_GENERIC_SW_SHIFT 1
36781 … (0x1<<2) // This bit masks, when set, the Interrupt bit: M…
36786 …C_SW (0x1<<1) // Generic sw overr…
36787 …ISCS_REG_INT_STS_WR_0_GENERIC_SW_SHIFT 1
36793 …IC_SW (0x1<<1) // Generic sw overr…
36794 …ISCS_REG_INT_STS_CLR_0_GENERIC_SW_SHIFT 1
36798 … (0x1<<0) // DORQ FIFO error interrupt for engine 1
36800 …_FIFO_ERR_ENG0_BB (0x1<<1) // DORQ FIFO error …
36801 …ISCS_REG_INT_STS_1_OPTE_DORQ_FIFO_ERR_ENG0_BB_SHIFT 1
36802 … (0x1<<2) // DBG FIFO error interrupt for engine 1
36806 … (0x1<<4) // BTB_IF1 FIFO error interrupt for engine 1
36810 … (0x1<<6) // BTB_IF0 FIFO error interrupt for engine 1
36814 … (0x1<<8) // BTB_SOP FIFO error interrupt for engine 1
36821 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
36823 … (0x1<<1) // This bit masks, when set, the Interrupt …
36824 …ISCS_REG_INT_MASK_1_OPTE_DORQ_FIFO_ERR_ENG0_BB_SHIFT 1
36825 … (0x1<<2) // This bit masks, when set, the Interrupt bit: M…
36827 … (0x1<<3) // This bit masks, when set, the Interrupt bit: M…
36829 … (0x1<<4) // This bit masks, when set, the Interrupt bit: M…
36831 … (0x1<<5) // This bit masks, when set, the Interrupt bit: M…
36833 … (0x1<<6) // This bit masks, when set, the Interrupt bit: M…
36835 … (0x1<<7) // This bit masks, when set, the Interrupt bit: M…
36837 … (0x1<<8) // This bit masks, when set, the Interrupt bit: M…
36839 … (0x1<<9) // This bit masks, when set, the Interrupt bit: M…
36841 … (0x1<<10) // This bit masks, when set, the Interrupt bit: M…
36844 … (0x1<<0) // DORQ FIFO error interrupt for engine 1
36846 …ORQ_FIFO_ERR_ENG0_BB (0x1<<1) // DORQ FIFO error …
36847 …ISCS_REG_INT_STS_WR_1_OPTE_DORQ_FIFO_ERR_ENG0_BB_SHIFT 1
36848 … (0x1<<2) // DBG FIFO error interrupt for engine 1
36852 … (0x1<<4) // BTB_IF1 FIFO error interrupt for engine 1
36856 … (0x1<<6) // BTB_IF0 FIFO error interrupt for engine 1
36860 … (0x1<<8) // BTB_SOP FIFO error interrupt for engine 1
36867 … (0x1<<0) // DORQ FIFO error interrupt for engine 1
36869 …DORQ_FIFO_ERR_ENG0_BB (0x1<<1) // DORQ FIFO error …
36870 …ISCS_REG_INT_STS_CLR_1_OPTE_DORQ_FIFO_ERR_ENG0_BB_SHIFT 1
36871 … (0x1<<2) // DBG FIFO error interrupt for engine 1
36875 … (0x1<<4) // BTB_IF1 FIFO error interrupt for engine 1
36879 … (0x1<<6) // BTB_IF0 FIFO error interrupt for engine 1
36883 … (0x1<<8) // BTB_SOP FIFO error interrupt for engine 1
36890 … (0x1<<0) // This bit masks, when set, the Parity bit: MI…
36892 …state of the ptw_miscs_pcie_link_up signal which is driven by the PCIE core - a pulse at the begin…
36893 …ate of the ptw_miscs_pcie_hot_reset signal which is driven by the PCIE core - a pulse at the begin…
36895 … DataWidth:0x10 // Accounts for HOT RESET assertion when the chip is in un-prepared state. Is re…
36897 … //Access:RW DataWidth:0x1 // Set to 1 when main PLL lock indication is de-asserted when hard…
36898 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36899 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36900 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36901 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36902 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36903 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36904 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36905 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36906 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36907 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36908 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36909 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36910 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36911 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36912 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36913 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36914 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36915 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36916 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36917 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36918 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36919 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36920 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36921 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36922 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36923 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36924 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36925 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36926 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36927 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36928 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36929 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36930 …dth:0x20 // FLOAT: When any of these bits is written as a '1'; the corresponding GPIO bit will t…
36931 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36932 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36933 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36934 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36935 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36936 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36937 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36938 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36939 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36940 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36941 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36942 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36943 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36944 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36945 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36946 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36947 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36948 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36949 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36950 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36951 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36952 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36953 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36954 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36955 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36956 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36957 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36958 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36959 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36960 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36961 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36962 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36963 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36964 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36965 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36966 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36967 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36968 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36969 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36970 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36971 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36972 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36973 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36974 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36975 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36976 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36977 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36978 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36979 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36980 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36981 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36982 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36983 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36984 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36985 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36986 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36987 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36988 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36989 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36990 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36991 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36992 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36993 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36994 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36996 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
36997 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
36998 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
36999 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37000 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37001 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37002 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37003 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37004 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37005 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37006 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37007 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37008 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37009 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37010 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37011 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37012 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37013 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37014 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37015 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37016 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37017 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37018 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37019 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37020 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37021 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37022 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37023 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37024 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37025 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37026 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37027 …1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an i…
37029 …only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set …
37031 …only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set …
37033 …only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set …
37035 …only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set …
37037 …only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set …
37039 …only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set …
37041 …only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set …
37043 …only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set …
37046 …Bit[0]: PERST# IO de-assertion. If == 1, triggers chip core reset. If == 0, doesn't trigger chip c…
37047 …Bit[0]: Out of the Box (OOB) WOL enable. Set to 1 to enable use of NIC magic packet detection to a…
37050 …0x0096b8UL //Access:R DataWidth:0x1 // Chip core_rst_n status. 0 - asserted; 1 - de-asserted.
37051 …1. Bit 0 : LINK_HOLDOFF_SUCCESS When =1, indicates the PCIE link is successfully being held from …
37052 …bit is written to a '1' to request that the PCIE link not begin training yet. Software should set …
37053 … 0x0096c4UL //Access:RW DataWidth:0x20 // Debug only: spare RW register …
37054 … 0x0096c8UL //Access:RW DataWidth:0x20 // Debug only: spare RW register …
37055 … 0x0096ccUL //Access:RW DataWidth:0x20 // Debug only: spare RW register …
37056 … 0x0096d0UL //Access:RW DataWidth:0x20 // Debug only: spare RW register …
37057 … 0x0096d4UL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by por reset. b…
37058 … 0x0096d8UL //Access:RW DataWidth:0x20 // Debug only: spare RW register …
37059 …Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to use all of the 32 Extended GPIO p…
37060 … 0x0096e0UL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by core reset. B…
37061 …only: [31:11] - spare RW register reset by por reset; [10:8] : PCIe Device Type: 3'b000 - Endpoint…
37063 …-bypass the Vmain PORBG. for Vmain POR; if sel=1 the output wil be MISC_REGISTERS_VMAIN_POR.VMAIN_…
37064 …Bit 0 - bypass select; Bits[15:1] - bypass value per function (1 - function 1; 2 -function 2; etc.…
37065 … 0x0096f4UL //Access:RW DataWidth:0x1 // This bit indicates that a Vm…
37069 … DataWidth:0x1 // NIG debug mux vector control. 0 - NIG0 debug vector is output to IFMUX; 1 -…
37070 …Drives misc_cnig_mux_4port_shared_mdio_en output. Applicable both in 2-port and 4-port mode. TBD: …
37071 …1 // NIG EMAC debug source selector. If 0 - path0 gmii/mii emac debug outputs are selected by N…
37072 …s:R DataWidth:0x2 // SEL_VAUX_B - Control to power switching logic. [0] - output value drive…
37073 … 0x009714UL //Access:RW DataWidth:0x1 // PCIE disable register bit. PCIE DIS. Has same…
37074 …1, HiGig is supported on 40G and the nw mac clock frequency is higher than the main clock frequenc…
37075 …bit corresponds to a PF pair i.e. bit 0 for global PFs 0 and 1; bit 1 for global PFs 2 and 3. If t…
37076 … 0x009720UL //Access:RW DataWidth:0x1 // This bit will be set by the …
37078 …-chip PHY devices and MAC ports to the four MDIO domains. It is only used when MISC_REGISTERS_MDIO…
37079 …ataWidth:0x1 // Set to 1 when pcie_hot_reset is asserted (Hot Reset / SBR / Link Down / Link Di…
37081 … 0x009734UL //Access:RW DataWidth:0x1 // Debug only : parity mode to MCP. Setting this bit…
37082 …W DataWidth:0x1 // Writing this bit as a '1' will cause the chip to do an internal reset exac…
37083 …only. main_sequencer_bypass select. For each bit; when set; the compatible bit in the MISC_REGISTE…
37084 …only. main_sequencer_bypass values. For each bit; the written value affects the control only if th…
37087 …-less mux control source: 0-management power sequencer output; 1-glich-less mux manual setting (bi…
37088 …0UL //Access:RW DataWidth:0x1 // [0]clock storm bypass: 0-select Storm SPLL clock; 1-select e…
37089 … by the MCP to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset…
37090 … by the MCP to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset…
37091 … the Driver to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset…
37092 …//Access:R DataWidth:0x1 // 0 - VAUX is not present (external pin is 0); 1 - VAUX is present…
37093 …-6] RESERVED (FLOAT: these IOs are outputs only). [5-4] CLR: When any of these bits is written as …
37096 … the chip. This value starts at 0x0 for the A0 tape-out and increments by one for each all-layer t…
37097 …f the chip. This value starts at 0x00 for each all-layer tape-out and increments by one for each t…
37099 … 0x00977cUL //Access:R DataWidth:0x1 // When this bit is 1 it indicates that…
37100 …bit reports the current state of the PCIE_DIS pin. If this bit is 1 it means that the LOM design h…
37103 … 0x00978cUL //Access:RW DataWidth:0x10 // Accounts for Hard reset de-assertion. Is reset o…
37105 … 0x009794UL //Access:RW DataWidth:0x10 // Accounts for Core de-reset assertion. Is r…
37107 … 0x00979cUL //Access:RW DataWidth:0x10 // Accounts for PERST_B reset de-assertion. Is reset o…
37109 … DataWidth:0x10 // Accounts for PCI_RST_N assertion when the chip is in un-prepared state. Is re…
37110 … 0x0097a8UL //Access:RW DataWidth:0x10 // Accounts for PCI_RST_N de-assertion. Is reset o…
37111 …1, when ptw_miscs_pcie_hot_reset is asserted (Hot Reset / SBR / Link Down / Link Disable) and the …
37113 …- used to programm loopback into Emulation (3\|2\|1\|0 (Enable loopback within the same port\|Enab…
37116 …8:6] OTP_VTRAP_TRIM_CODE: MIN1_adj [5:2] OTP_VTRAP_TRIM_CODE: MIN0_adj [1] OTP_VTRAP_ENABL…
37117 …8:6] OTP_VTRAP_TRIM_CODE: MIN1_adj [5:2] OTP_VTRAP_TRIM_CODE: MIN0_adj [1] OTP_VTRAP_ENABL…
37120 …r-ride: When set, over-ride DAC code from AVS monitor with on from this register [20:11] VMgmt DAC…
37121 …- Per-TC packet available status; [10] - STORM FIFO; [9] - BTB SOP FIFO for engine 0; [8] - BTB S…
37122 …- STORM FIFO almost full; [10] - STORM FIFO full; [9] - BTB SOP FIFO full for engine 0; [8] - …
37123 …bit for each statistics. [7] - Received packet from BTB IF0 of engine 0; [6] - Received packet f…
37124 …- storm_init_crd: Credits for the output STORM Packet interface. [3:2] - storm_pkt_dst: Select t…
37125 …-full Threshold. [29:25] - Btb_if0_fifo_almfull_thr: Almost-full threshold for BTB main traffic F…
37127 … 0x0097f0UL //Access:RW DataWidth:0x3 // [31:3] Reserved [2] Enable [1:0] Select
37131 … (0x1<<0) // This bit will always read '1', as it i…
37133 …1) // This bit will read '1' if a byte has been received with a framing error. It will continue to…
37134 …BU_REG_CMD_RX_ERROR_SHIFT 1
37135 …s bit will read '1' of a receive overflow has occurred. It will continue to read as a '1' until th…
37138 … (0x1<<0) // This bit will read '1' if there is a valid byte to read in dbu_rxdata. Once …
37140 … (0x1<<1) // This bit will read '1' if there is data pending to be transmitted i…
37141 …BU_REG_STATUS_TXDATA_OCCUPIED_SHIFT 1
37143 … (0x1<<0) // When this bit is set, the UART timing will be determined by the values in the dbu_…
37145 … (0x1<<1) // When this bit is set, the…
37146 …BU_REG_CONFIG_DEBUGSM_ENABLE_SHIFT 1
37147 … (0x1<<2) // When this bit is set, all line feeds shall be preceded by a carriage retur…
37150 …core_clock cycles after the falling edge of the rx_data pin that the start bit should be sampled. …
37154 …idth:0x8 // This bit indicates that the data currently in bits 7:0 of this register was receive…
37155 … of data on the serial interface. Firmware should poll the txdata_occupied bit in the status regis…
37161 … (0x1<<16) // The vfid_value bits are valid only if this bit is set. If this bit is …
37163 … (0x1<<20) // Set the path ID if the access is forced as indicated by bit 31.
37165 … (0x1<<31) // When 0, the path selection is done by PFID[0]. When 1, the path selection…
37167 … // Debug only. Initialises specific states and statuses. To initialise the state - write 1 int…
37168 … enable. If 0 - the acknowledge input is disregarded; valid is deasserted; full is asserted; all o…
37169 …t;Master) enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
37171 … 0x00c04cUL //Access:RW DataWidth:0x1 // Command 1 go.
37206 …RR (0x1<<1) // PCI read buffer …
37207 …MAE_REG_INT_STS_PCI_RD_BUF_ERR_SHIFT 1
37209 … (0x1<<0) // This bit masks, when set, the Interrupt bit: D…
37211 … (0x1<<1) // This bit masks, when set, the Interrupt …
37212 …MAE_REG_INT_MASK_PCI_RD_BUF_ERR_SHIFT 1
37216 …F_ERR (0x1<<1) // PCI read buffer …
37217 …MAE_REG_INT_STS_WR_PCI_RD_BUF_ERR_SHIFT 1
37221 …UF_ERR (0x1<<1) // PCI read buffer …
37222 …MAE_REG_INT_STS_CLR_PCI_RD_BUF_ERR_SHIFT 1
37224 … (0x1<<0) // This bit masks, when set, the Parity bit: DM…
37226 … (0x1<<1) // This bit masks, when set, the Parity bi…
37227 …MAE_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT 1
37228 … (0x1<<2) // This bit masks, when set, the Parity bit: DM…
37231 … 0x00c400UL //Access:RW DataWidth:0x4 // DMAE- PCI Request Interfac…
37232 …404UL //Access:RW DataWidth:0x1 // Relaxed ordering. 0-strict PCI ordering is used;1-PCI-X re…
37233 … 0x00c408UL //Access:RW DataWidth:0x1 // 0-PCI type cache snoop protection is required;…
37234 …00c40cUL //Access:RW DataWidth:0x1 // If 0 - the CRC-16 initial value is all zeroes; if 1 - t…
37235 … //Access:RW DataWidth:0x1 // If 0 - the CRC-16 final calculation result isn't byte swapped; …
37236 …0c414UL //Access:RW DataWidth:0x1 // If 0 - the CRC-16c initial value is all zeroes; if 1 - t…
37237 …c418UL //Access:RW DataWidth:0x1 // If 0 - the CRC-16 T10 initial value is all zeroes; if 1 -…
37238 …00c41cUL //Access:RW DataWidth:0x1 // If 0 - the CRC-32 initial value is all zeroes; if 1 - t…
37239 … //Access:RW DataWidth:0x1 // If 0 - the CRC-32 final calculation result isn't byte swapped; …
37240 …0c424UL //Access:RW DataWidth:0x1 // If 0 - the CRC-32c initial value is all zeroes; if 1 - t…
37241 …//Access:RW DataWidth:0x1 // If 0 - the CRC-32c final calculation result isn't byte swapped; …
37242 …0x00c42cUL //Access:RW DataWidth:0x1 // If 0 - the final checksum equal 0 won't be changed;if…
37243 …equest ATC Flags[1:0]: 00 - Do nothing; 01 - Search only; 10 - Search & Cache; 11 - Search & Relea…
37244 …equest ATC Flags[1:0]: 00 - Do nothing; 01 - Search only; 10 - Search & Cache; 11 - Search & Relea…
37245 … 0x00c438UL //Access:RW DataWidth:0x1 // When set discards 1- or 2-Dword PCI transact…
37246 … 0x00c43cUL //Access:RW DataWidth:0x14 // GRC address in case 1- or 2-Dword PCI transact…
37250 …- Bidirectional shared data structure; 01 - Device writes/reads then device reads/writes soon; 10 …
37255 …: 0 - VN Virtualized NIC (Used for VF access); 1 - PDA Physical Device Assignment (Assigned to VM-…
37262 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
37263 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
37264 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
37265 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
37272 …- RBCN; 1- RBCP; 2-RBCR; 3- RBCT; 4- RBCU; 5- RBCF; 6- RBCX; 7- RBCS; 8-RBCH; 9-RBCZ; 10 - other e…
37273 …- RBCN; 1- RBCP; 2-RBCR; 3- RBCT; 4- RBCU; 5- RBCF; 6- RBCX; 7- RBCS; 8-RBCH; 9-RBCZ; 10 - other e…
37275 … (0x1<<0) // Debug only: This bit is an enable to PCI output request interf…
37277 … (0x1<<1) // Debug only: This bit is an enable to PCI output data i…
37278 …BG_REG_OUTPUT_ENABLE_PCI_DATA_ENABLE_SHIFT 1
37279 …only: This bit is an enable to NIG output data interface. When DBG_REGISTERS_OUTPUT_ENABLE.PCI_RE…
37281 …as follows: 0-NONE; 1-DoubleBwTx (DoubleBw the TX side); 2-DoubleBwRx (DoubleBw the RX side); 3-Cr…
37282 … // Debug only: These bits are a client index for slot 0 in calendar as follows: 0 is TSEM; 1- MSE…
37283 … // Debug only: These bits are a client index for slot 1 in calendar as follows: 0 is TSEM; 1- MSE…
37284 … // Debug only: These bits are a client index for slot 2 in calendar as follows: 0 is TSEM; 1- MSE…
37285 … // Debug only: These bits are a client index for slot 3 in calendar as follows: 0 is TSEM; 1- MSE…
37286 … // Debug only: These bits are a client index for slot 4 in calendar as follows: 0 is TSEM; 1- MSE…
37287 … // Debug only: These bits are a client index for slot 5 in calendar as follows: 0 is TSEM; 1- MSE…
37288 … // Debug only: These bits are a client index for slot 6 in calendar as follows: 0 is TSEM; 1- MSE…
37289 … // Debug only: These bits are a client index for slot 7 in calendar as follows: 0 is TSEM; 1- MSE…
37290 … // Debug only: These bits are a client index for slot 8 in calendar as follows: 0 is TSEM; 1- MSE…
37291 … // Debug only: These bits are a client index for slot 9 in calendar as follows: 0 is TSEM; 1- MSE…
37292 …// Debug only: These bits are a client index for slot 10 in calendar as follows: 0 is TSEM; 1- MSE…
37293 …// Debug only: These bits are a client index for slot 11 in calendar as follows: 0 is TSEM; 1- MSE…
37294 …// Debug only: These bits are a client index for slot 12 in calendar as follows: 0 is TSEM; 1- MSE…
37295 …// Debug only: These bits are a client index for slot 13 in calendar as follows: 0 is TSEM; 1- MSE…
37296 …// Debug only: These bits are a client index for slot 14 in calendar as follows: 0 is TSEM; 1- MSE…
37297 …// Debug only: These bits are a client index for slot 15 in calendar as follows: 0 is TSEM; 1- MSE…
37298 …only: This bit indicates the calendar pacing which is the number of cycles the calendar stays on t…
37299 …- 128b STORM (A and B) data is logged 1 - 64b STORM (A and B) data + 4 different (in general case)…
37300 … DataWidth:0x2 // Debug only: These bits indicate the target of the debug data: 0 - interna…
37301 …only: This bit indicates whether data will be wrapped (oldest data is thrown) or overflowed-one sh…
37306 … (0x1<<0) // This bit masks, when set, the Interrupt bit: D…
37315 … (0x1<<0) // This bit masks, when set, the Parity bit: DB…
37318 … 0x010400UL //Access:R DataWidth:0x8 // Debug only: These bits indicat…
37319 … 0x010404UL //Access:R DataWidth:0x8 // Debug only: These bits indica…
37320 …only: These bits indicate the value of the read pointer for the external pci buffer; relevant on…
37322 …only: These bits indicate the value of the write pointer for the external pci buffer when DBG_REG…
37324 …ataWidth:0x1 // Debug only: This bit indicates wheter the internal buffer was wrapped (oldest d…
37325 …only: This bit indicates wheter indicates that external buffer was wrapped (oldest data was thro…
37326 …only: This bit indicates that the internal buffer was overflowed (newest data was thrown); Not re…
37327 …only: This bit indicates that the external buffer was overflowed (newest data was thrown); Relevan…
37328 … 0x010428UL //Access:R DataWidth:0x1 // Debug only: This bit indicates tha…
37329 …/Access:R DataWidth:0x1 // Debug only: This bit indicates that the external buffer was fille…
37330 … 0x010430UL //Access:RW DataWidth:0x20 // Debug only: LSB of external PC…
37331 … 0x010434UL //Access:RW DataWidth:0x20 // Debug only: MSB of external PC…
37332 … 0x010438UL //Access:RW DataWidth:0x18 // Debug only: These bits indica…
37333 …only: These bits indicate the max value of target_packet_size data chunks sent through the NIG (Th…
37334 … 0x010440UL //Access:RW DataWidth:0x2 // Debug only: These bits indica…
37335 … 0x010444UL //Access:RW DataWidth:0x5 // Debug only: This bit is a handle gi…
37336 … 0x010448UL //Access:RW DataWidth:0x20 // Debug only: These bits indica…
37337 … 0x01044cUL //Access:RW DataWidth:0x1 // Debug only: This bit indicate the f…
37338 … 0x010450UL //Access:RW DataWidth:0x1 // Debug only: Timeout operation …
37339 …4UL //Access:RW DataWidth:0x1 // Debug only: This bit enables the operation of the debug bloc…
37340 …only: This bit indicate whether grant will be issued by the dbg block towards the storms in case t…
37341 …only: These bits indicate the value of the internal buffer almost full threshold used for deciding…
37342 …idth:0x1 // Debug only: This bit indicates logical/physical address in PCI request as follows:…
37343 …only: Selects 32b of data, valid and frame from the input stream to internal buffer to be output t…
37344 …only: together with DBG_REG_BUFFER_THR provides histerezis-like mechanism to set SEMI grant. When …
37345 …only: These bits indicate the value of the sop; data; frame and valid output of the calendar; The …
37347 …only: For pattern recognition usage: These bits represent the pattern to be compared with the ve…
37349 …only: For pattern recognition usage: These bits represent a mask bit vector that refers to the DBG…
37351 …only: For pattern recognition usage: This bit indicates whether the pattern recognition feature is…
37352 …only: For pattern recognition usage: This bit indicates the trigger behavior of the pattern recog…
37353 …only: For pattern recognition usage: This bit indicates whether data is continously stored in the…
37354 … // (a) 0 - trigger machine is off (all data will bypass the triggering machine); dbg_sem_trgr_…
37355 …- triggering interleaved messages is disabled. (b) 1 - triggering interleaved messages is enabled;…
37356 …or HW block only bits[2:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what S…
37357 …or HW block only bits[2:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what S…
37358 …or HW block only bits[2:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what S…
37359 …cess:RW DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant sta…
37360 …cess:RW DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant sta…
37361 …cess:RW DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant sta…
37374 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37375 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37376 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37377 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37378 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37379 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37380 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37381 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37382 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37383 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37384 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37385 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37386 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37387 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37388 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37389 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37390 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37391 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37392 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37393 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37394 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37395 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37396 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37397 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37398 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37399 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37400 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37401 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37402 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37403 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37404 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37405 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37406 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37407 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37408 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37409 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37410 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37411 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37412 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37413 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37414 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37415 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37416 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37417 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37418 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37419 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37420 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37421 …//Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determin…
37422 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37423 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37424 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37425 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37426 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37427 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37428 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37429 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37430 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37431 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37432 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37433 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37434 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37435 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37436 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37437 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37438 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37439 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37440 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37441 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37442 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37443 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37444 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37445 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37446 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37447 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37448 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37449 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37450 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37451 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37452 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37453 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37454 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37455 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37456 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37457 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37458 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37459 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37460 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37461 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37462 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37463 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37464 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37465 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37466 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37467 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37468 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37469 …:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compare…
37470 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37471 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37472 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37473 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37474 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37475 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37476 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37477 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37478 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37479 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37480 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37481 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37482 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37483 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37484 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37485 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37486 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37487 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37488 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37489 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37490 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37491 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37492 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37493 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37495 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37497 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37500 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37502 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37505 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37507 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37510 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37512 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37515 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37517 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37520 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37522 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37525 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37527 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37530 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37532 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37535 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37537 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37540 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37542 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37545 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37547 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37550 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37552 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37555 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37557 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37560 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37562 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37565 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37567 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37570 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37572 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37575 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37577 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37580 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37582 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37585 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37587 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37590 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37592 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37595 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37597 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37600 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37602 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37605 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37607 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37610 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37612 …eld of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37614 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37615 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37616 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37617 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37618 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37619 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37620 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37621 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37622 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37623 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37624 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37625 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37626 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37627 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37628 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37629 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37630 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37631 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37632 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37633 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37634 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37635 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37636 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37637 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37638 … 0x01083cUL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37639 … 0x010840UL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37640 … 0x010844UL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37641 … 0x010848UL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37642 … 0x01084cUL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37643 … 0x010850UL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37644 … 0x010854UL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37645 … 0x010858UL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37646 … 0x01085cUL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37647 … 0x010860UL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37648 … 0x010864UL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37649 … 0x010868UL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37650 … 0x01086cUL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37651 … 0x010870UL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37652 … 0x010874UL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37653 … 0x010878UL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37654 … 0x01087cUL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37655 … 0x010880UL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37656 … 0x010884UL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37657 … 0x010888UL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37658 … 0x01088cUL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37659 … 0x010890UL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37660 … 0x010894UL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37661 … 0x010898UL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37686 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37687 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37688 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37689 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37690 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37691 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37692 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37693 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37694 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37695 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37696 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37697 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37698 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37699 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37700 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37701 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37702 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37703 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37704 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37705 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37706 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37707 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37708 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37709 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37710 …th:0x1 // (a) 1: use trigger_state_msg_lengthi to determine message boundary. (b) 0: use maski…
37711 …th:0x1 // (a) 1: use trigger_state_msg_lengthi to determine message boundary. (b) 0: use maski…
37712 …th:0x1 // (a) 1: use trigger_state_msg_lengthi to determine message boundary. (b) 0: use maski…
37713 …-1 in terms of numbers of 128-bit cycles. NOTE: (a) if for example trigger_state_msg_lengthi=0 th…
37714 …-1 in terms of numbers of 128-bit cycles. NOTE: (a) if for example trigger_state_msg_lengthi=0 th…
37715 …-1 in terms of numbers of 128-bit cycles. NOTE: (a) if for example trigger_state_msg_lengthi=0 th…
37718 …1) then data[32*(trigger_indirect0_offseti[2:0]+1)-1:32*trigger_indirect0_offseti[2:0]] in cycle t…
37719 …1) then data[32*(trigger_indirect0_offseti[2:0]+1)-1:32*trigger_indirect0_offseti[2:0]] in cycle t…
37720 …1) then data[32*(trigger_indirect0_offseti[2:0]+1)-1:32*trigger_indirect0_offseti[2:0]] in cycle t…
37721 … 0x010988UL //Access:RW DataWidth:0x5 // Shift vector (bit resolution) for the…
37722 … 0x01098cUL //Access:RW DataWidth:0x5 // Shift vector (bit resolution) for the…
37723 … 0x010990UL //Access:RW DataWidth:0x5 // Shift vector (bit resolution) for the…
37724 …bit will be zeroed; if clear then the relevant bit will be registered with its exact data. NOTE: (…
37725 …bit will be zeroed; if clear then the relevant bit will be registered with its exact data. NOTE: (…
37726 …bit will be zeroed; if clear then the relevant bit will be registered with its exact data. NOTE: (…
37729 …1) then data[32*(trigger_indirect1_offseti[2:0]+1)-1:32*trigger_indirect1_offseti[2:0]] in cycle t…
37730 …1) then data[32*(trigger_indirect1_offseti[2:0]+1)-1:32*trigger_indirect1_offseti[2:0]] in cycle t…
37731 …1) then data[32*(trigger_indirect1_offseti[2:0]+1)-1:32*trigger_indirect1_offseti[2:0]] in cycle t…
37732 … 0x0109b4UL //Access:RW DataWidth:0x5 // Shift vector (bit resolution) for the…
37733 … 0x0109b8UL //Access:RW DataWidth:0x5 // Shift vector (bit resolution) for the…
37734 … 0x0109bcUL //Access:RW DataWidth:0x5 // Shift vector (bit resolution) for the…
37735 …bit will be zeroed; if clear then the relevant bit will be registered with its exact data. NOTE: …
37736 …bit will be zeroed; if clear then the relevant bit will be registered with its exact data. NOTE: …
37737 …bit will be zeroed; if clear then the relevant bit will be registered with its exact data. NOTE: …
37739 …- Filter off; in that case all data should be transmitted to the internal buffer without any filte…
37740 …or HW block only bits[2:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what S…
37741 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37742 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37743 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37744 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37749 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37750 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37751 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37752 …th:0x20 // If specific bit is 1 then the matched bit in the above data vector is masked (not com…
37753 … DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; …
37754 … DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; …
37755 … DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; …
37756 … DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; …
37757 … The filtering is implemented according to the data on the first 4 cycles only. The above value ve…
37758 … The filtering is implemented according to the data on the first 4 cycles only. The above value ve…
37759 … The filtering is implemented according to the data on the first 4 cycles only. The above value ve…
37760 … The filtering is implemented according to the data on the first 4 cycles only. The above value ve…
37761 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37762 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37763 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37764 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37766 …ion on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37768 …ion on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37771 …ion on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37773 …ion on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37776 …ion on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37778 …ion on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37781 …ion on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37783 …ion on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data fro…
37785 … 0x010a48UL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37786 … 0x010a4cUL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37787 … 0x010a50UL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37788 … 0x010a54UL //Access:RW DataWidth:0x1 // (a) 1: the above data vect…
37789 …rigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value 1 from of fsm triggeri…
37790 …rigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value 1 from of fsm triggeri…
37791 …rigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value 1 from of fsm triggeri…
37792 …rigger_indirect0_recorded_data). (c) 10: indirect: use the recorded value 1 from of fsm triggeri…
37793 …0 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37794 …0 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37795 …0 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37796 …0 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37797 …Access:RW DataWidth:0x1 // (a) 1: use filter_msg_length to determine message boundary. (b) 0:…
37798 …-1 in terms of numbers of 128-bit cycles. NOTE: (a) if for example filter_msg_length=0 then Mess…
37799 …1 (Filter on prior to trigger_event) the messages are partially recorded not only before the trigg…
37800 …h-1 of the recorded part size in terms of numbers of 128-bit cycles: 0 is 1 cycle; 1 is 2 cycles; …
37801 …- record from time=0; (b) 01 - record rcrd_on_window_pre_num_chunks chunks to internal buffer pri…
37802 …- enable recording data upon triggering event; in that case record for rcrd_on_window_post_num_cyc…
37803 …bit each within the internal buffer) that should be recorded to the internal buffer prior to trigg…
37804 …alid cycles that should be recorded upon triggering event. NOTE: (1) applicable only when rcrd_on…
37805 … 0x010a98UL //Access:RW DataWidth:0x10 // 16-bit opaque FID for pci …
37806 …umber of wraps on internal buffer; NOTE: valid only when debug_target=0 (internal buffer) and full…
37815 …ccess:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset;…
37816 …ccess:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset;…
37817 …ccess:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset;…
37818 …ccess:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset;…
37819 …ccess:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset;…
37820 …ccess:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset;…
37821 …ccess:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset;…
37822 …ccess:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset;…
37823 …ccess:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset;…
37824 …ccess:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset;…
37825 …- bits[31:0]; [5:3] - bits[63:32]; [8:6] - bits[95:64]; [11:9] - bits[127:96]; [14:12] - bits…
37826 …ll be added to trailer when STORM will be selected: B2:0 - TSEM; B5:3- MSEM; B8:6- USEM; B11:9- XS…
37835 …0x4 // Ethernet header width: 0 - 14 MSB bytes; 1- 16 MSB bytes; .. ; 8 - 30 MSB bytes; 9 -32 M…
37836 …s in granularity of chunks. The allowed range is 1-48 that suits to packet size of 256B-12KB. Valu…
37837 … 0x010b40UL //Access:RW DataWidth:0x1 // When 1 enables inserting pa…
37842 …bit[0] is set and frame[1] is set or bit[1] is set and frame[2] is set or bit[2] is set and frame[…
37843 …bit[0] is set and valid[1] is set or bit[1] is set and valid[2] is set or bit[2] is set and valid[…
37844 …tput from DBG to SEM block as result of trigger event: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is …
37845 … // Current state machine status of trigger block in dbg_trigger.v: states 0-2 are functional stat…
37846 …ock in dbg_trigger_state.v: : state 0 - NOT_HNDLR_MSG; state 1- FRST_HNDLR_MSG; state 2- SCND_HNDL…
37848 …x010b6cUL //Access:R DataWidth:0x10 // Counter for number of times set 1 appeared in current …
37849 …- constraint 0 set0; B1 - constraint 1 set0; B2 - constraint 2 set0; B3 - constraint 3 set0; B4 - …
37851 …010b78UL //Access:RC DataWidth:0x20 // Debug only: These bits represent the total number of 12…
37852 … 0x010b7cUL //Access:R DataWidth:0x10 // Debug only: Number of transiti…
37853 … 0x010b80UL //Access:R DataWidth:0x10 // Debug only: Number of transiti…
37854 … 0x010b84UL //Access:R DataWidth:0x10 // Debug only: Number of transiti…
37855 …ebug only: Current state status in trailer block : 0 - WAIT_FOR_NEW_LINE; 1- END_OF_CHUNK; 2 - SEN…
37856 … 0x010b8cUL //Access:R DataWidth:0x6 // Debug only: number of valid dw…
37857 … // Statistics. Match constraint status. B0 - constraint 0; B1 - constraint 1; B2 - constraint …
37863 …1 // When set to 0 - only client which HW ID is defined in DBG_REGISTERS_FILTER_ID_NUM.FILTER_I…
37864 …ccess:RW DataWidth:0x1 // When 0 - SEMI core A is selected for all trigger/filter related act…
37865 … 0x014000UL //Access:WB DataWidth:0x200 // Debug only: Internal buffer o…
37868 …cess:RW DataWidth:0x1 // 0: output clock comes from core_pll (default) 1: output clock is buf…
37870 … // Select line for MDIO Voltage Select 0 : MDIO VDDIO is 1.8V or below. 1 : MDIO VDDIO is 1.8+…
37871 … DataWidth:0x1 // 0: bypass clock level converter power down (default) 1: bypass clock level …
37873 …bit will execute the OTP "command" in the next field. This bit should be set to Low and high agai…
37876 …bit is used to sample READ data in burst mode; [1]: cmd_done: Command Done, This signal indicates …
37878 …er Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 0…
37882 …/Access:RW DataWidth:0x1 // 0: bandgap gap chopping disabled (default) 1: bandgap gap choppin…
37885 …RW DataWidth:0x1 // 0: bandgap clock freq = ref clock freq/4 (default) 1: bandgap clock freq …
37887 … XCORE_BIAS in normal operation is controlled by straps on the board. This bit allows it SW to ove…
37888 … 0x02021cUL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf s…
37890 …Filter Corner Frequency control 0: 27Mhz 1: 50Mhz Device will be using 50Mhz crytal, so defaults t…
37893 … // HIPASS in normal operation is controlled by straps on the board. This bit allows it SW to ove…
37894 …0: divide core_pll clock by 2/4/8/16 according to postdiv setting (default) 1: no division on the …
37896 …ss:RW DataWidth:0x1 // 0: ref clock not from the bypass path (default) 1: ref clock from the …
37897 …// Used for debug, will be set when pll_lock_detect_filter_status went from 1 to 0. This scenario …
37899 …isable HCSL ref clock termination (default) 1: enable HCSL ref clock termination when pll_ref_oct …
37902 …ss:RW DataWidth:0x1 // 0: disable 50 Ohm on chip termination (default) 1: enable 50 Ohm on ch…
37904 …aWidth:0x1 // Divide by 2 Selection for pad_op/n_cml output 0=XTAL Freq. 1=XTAL Freq. / 2 Globa…
37905 …0x020234UL //Access:RW DataWidth:0x1 // 0: power down disabled (default) 1: power down enabled
37907 …34UL //Access:RW DataWidth:0x4 // [3:2] LDO Output Stage Bias Control [1:0] LDO Output Voltag…
37908 … 0x020238UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): ref…
37909 …er Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 0…
37910 …All CMOS Outputs 0=o_xtal_ck[5:0] depends on i_resetb and i_cmos_en_ch[5:0] 1=o_xtal_ck[5:0] ALL O…
37911 … 0x02023cUL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3): refer …
37913 …tput DISABLED 1=CMOS output ENABLED Bit[0] = o_xtal_ck0 Bit[1] = o_xtal_ck1 Bit[2] = o_xtal_ck2 Bi…
37916 …Channel Power Down 0=CML output ON 1=CML output OFF Bit[0] = o_cml_p/n 0 Bit[1] = o_cml_p/n 1 Bit[…
37919 … (0x1<<0) // 0: pll reset disabled 1: pll reset enabled
37921 … (0x1<<4) // 1 : Override the init state machine and control the PLL r…
37924 … //Access:RW DataWidth:0x1 // 50ohm Driver Power Down 0=Driver ENABLED 1=Driver DISABLED Glob…
37926 … (0x1<<0) // 0: post scaler reset disabled 1: post scaler reset e…
37928 … (0x1<<4) // 1 : Override the init state machine and control the PLL logi…
37934 …SC_E28_BIAS_BB (0x7<<1) // Future Use
37935 …PC_REG_OSC_E28_MISC_OSC_E28_BIAS_BB_SHIFT 1
37938 …cess:RW DataWidth:0x1 // 0: output clock comes from core_pll (default) 1: output clock is buf…
37940 … //Access:RW DataWidth:0x1 // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. T…
37941 … DataWidth:0x1 // 0: bypass clock level converter power down (default) 1: bypass clock level …
37944 …MAIN_RESET_VCO_BB (0x1<<0) // 1 : Reset the VCO of t…
37946 … (0x1<<4) // 1 : Override the init state machine and control the PLL r…
37949 …// Used for debug, will be set when pll_lock_detect_filter_status went from 1 to 0. This scenario …
37951 …_MAIN_RESET_POST_BB (0x1<<0) // 1 : Reset the Post Div…
37953 … (0x1<<4) // 1 : Override the init state machine and control the PLL r…
37957 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
37960 …-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= di…
37961 …/Access:RW DataWidth:0x1 // 0: bandgap gap chopping disabled (default) 1: bandgap gap choppin…
37963 …s:RW DataWidth:0x14 // Fractional feedback divider control. Resolution= 1/(2^20). Global regis…
37964 …RW DataWidth:0x1 // 0: bandgap clock freq = ref clock freq/4 (default) 1: bandgap clock freq …
37965 …er Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 0…
37966 …0x020264UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 00000000: 256 000000…
37967 … 0x020268UL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf s…
37968 …0x020268UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 00000000: 256 000000…
37970 …0x02026cUL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-2 00000000: 256 000000…
37971 …0: divide core_pll clock by 2/4/8/16 according to postdiv setting (default) 1: no division on the …
37973 …0x020270UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-3 00000000: 256 000000…
37974 …ss:RW DataWidth:0x1 // 0: ref clock not from the bypass path (default) 1: ref clock from the …
37976 …0x020274UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-4 00000000: 256 000000…
37977 …isable HCSL ref clock termination (default) 1: enable HCSL ref clock termination when pll_ref_oct …
37979 …0x020278UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-5 00000000: 256 000000…
37980 …ss:RW DataWidth:0x1 // 0: disable 50 Ohm on chip termination (default) 1: enable 50 Ohm on ch…
37983 …0x020280UL //Access:RW DataWidth:0x1 // 0: power down disabled (default) 1: power down enabled
37984 …// Used for debug, will be set when pll_lock_detect_filter_status went from 1 to 0. This scenario …
37986 … 0x020284UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): ref…
37988 … 0x020288UL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3): refer …
37991 … 0x02028cUL //Access:R DataWidth:0x4 // Delay for each channel 2-5 is completed.
37993 … (0x1<<0) // 0: pll reset disabled 1: pll reset enabled
37995 … (0x1<<4) // 1 : Override the init state machine and control the PLL r…
37999 … (0x1<<0) // 0: post scaler reset disabled 1: post scaler reset e…
38001 … (0x1<<4) // 1 : Override the init state machine and control the PLL logi…
38003 …1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset …
38005 …cess:RW DataWidth:0x1 // 0: output clock comes from core_pll (default) 1: output clock is buf…
38006 …1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset …
38007 … DataWidth:0x1 // 0: bypass clock level converter power down (default) 1: bypass clock level …
38012 … following transformation to program this register. For 0, Write 0 For 1, Write 1 For 2, Write 4 F…
38014 …a8UL //Access:R DataWidth:0x1 // LOCK detector output 0= PLL unlocked 1= PLL locked Global r…
38015 …/Access:RW DataWidth:0x1 // 0: bandgap gap chopping disabled (default) 1: bandgap gap choppin…
38017 …RW DataWidth:0x1 // 0: bandgap clock freq = ref clock freq/4 (default) 1: bandgap clock freq …
38018 … //Access:RW DataWidth:0x1 // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. T…
38019 … 0x0202b4UL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf s…
38023 …0: divide core_pll clock by 2/4/8/16 according to postdiv setting (default) 1: no division on the …
38024 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
38025 …ss:RW DataWidth:0x1 // 0: ref clock not from the bypass path (default) 1: ref clock from the …
38026 …-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= di…
38027 …isable HCSL ref clock termination (default) 1: enable HCSL ref clock termination when pll_ref_oct …
38028 …s:RW DataWidth:0x14 // Fractional feedback divider control. Resolution= 1/(2^20). Global regis…
38029 …ss:RW DataWidth:0x1 // 0: disable 50 Ohm on chip termination (default) 1: enable 50 Ohm on ch…
38030 …0x0202c8UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 00000000: 256 000000…
38031 …0x0202ccUL //Access:RW DataWidth:0x1 // 0: power down disabled (default) 1: power down enabled
38032 …0x0202ccUL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 00000000: 256 000000…
38033 … 0x0202d0UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): ref…
38035 … 0x0202d4UL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3): refer …
38036 …1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset …
38038 …1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset …
38040 … 0x0202dcUL //Access:RW DataWidth:0x1 // 0: pll reset disabled 1: pll reset enabled
38042 … 0x0202e0UL //Access:RW DataWidth:0x1 // 0: post scaler reset disabled 1: post scaler reset e…
38044 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38045 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38046 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38047 … following transformation to program this register. For 0, Write 0 For 1, Write 1 For 2, Write 4 F…
38048 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38049 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38050 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38051 …e8UL //Access:R DataWidth:0x1 // LOCK detector output 0= PLL unlocked 1= PLL locked Global r…
38052 …-> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the…
38053 …-> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the…
38054 …-> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the…
38058 … //Access:RW DataWidth:0x1 // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. T…
38062 … // Setting this bit high will result in the HW to capture the frequency of Main, STORM and NW …
38063 … // Setting this bit high will result in the HW to capture the frequency of Main, STORM and NWM …
38064 … // Setting this bit high will result in the HW to capture the frequency of Main, STORM and NWM …
38071 … (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in freq_cnt f…
38073 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
38079 … (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in freq_cnt f…
38086 … (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in freq_cnt f…
38088 …//Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 00000000 = divide by 256 000000…
38089 … 0x0204b4UL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 1us r…
38090 … 0x0202a8UL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 1us r…
38091 … 0x020308UL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 1us r…
38092 …//Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 00000000 = divide by 256 000000…
38093 … 0x0204b8UL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38094 … 0x0202acUL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38095 … 0x02030cUL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38097 … 0x0204bcUL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38098 … 0x0202b0UL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38099 … 0x020310UL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38100 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38101 … 0x0204c0UL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38102 … 0x0202b4UL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38103 … 0x020314UL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38104 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38105 … 0x0204c4UL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38106 … 0x0202b8UL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38107 … 0x020318UL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38108 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38109 … // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
38110 … // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
38111 … // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
38117 …aWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would …
38118 …aWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would …
38119 …aWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would …
38120 … 0x020324UL //Access:RW DataWidth:0x4 // Control of the non-zero pole in the PLL …
38121 … This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-ass…
38122 … This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-ass…
38123 … This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-ass…
38124 …28UL //Access:R DataWidth:0x1 // LOCK detector output 0= PLL unlocked 1= PLL locked Global r…
38129 …//Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted
38130 …//Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted
38131 …//Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted
38132 … //Access:RW DataWidth:0x1 // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. T…
38133 …-> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone…
38134 …-> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone…
38135 …-> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone…
38150 … (0x1<<4) // This bit generates an interr…
38152 … (0x1<<5) // This bit generates an interrupt when VMAIN POR is d…
38154 … (0x1<<6) // This bit generates an interr…
38156 … (0x1<<7) // This bit generates an interrupt when PERST# is de…
38158 … (0x1<<8) // This bit generates an interr…
38160 … (0x1<<9) // This bit generates an interrupt when Fdone Double Error Detection sta…
38162 … (0x1<<10) // This bit generates an interr…
38164 … (0x1<<11) // This bit generates an interr…
38166 … (0x1<<12) // This bit generates an interr…
38168 … (0x1<<13) // This bit generates an interr…
38170 … (0x1<<14) // This bit generates an interr…
38172 … (0x1<<15) // This bit generates an interr…
38174 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
38178 … (0x1<<0) // This bit masks, when set, the Interrupt bit: I…
38180 … (0x1<<4) // This bit masks, when set, the Interrupt bit: I…
38182 … (0x1<<5) // This bit masks, when set, the Interrupt bit: I…
38184 … (0x1<<6) // This bit masks, when set, the Interrupt bit: I…
38186 … (0x1<<7) // This bit masks, when set, the Interrupt bit: I…
38188 … (0x1<<8) // This bit masks, when set, the Interrupt bit: I…
38190 … (0x1<<9) // This bit masks, when set, the Interrupt bit: I…
38192 … (0x1<<10) // This bit masks, when set, the Interrupt bit: I…
38194 … (0x1<<11) // This bit masks, when set, the Interrupt bit: I…
38196 … (0x1<<12) // This bit masks, when set, the Interrupt bit: I…
38198 … (0x1<<13) // This bit masks, when set, the Interrupt bit: I…
38200 … (0x1<<14) // This bit masks, when set, the Interrupt bit: I…
38202 … (0x1<<15) // This bit masks, when set, the Interrupt bit: I…
38210 … (0x1<<4) // This bit generates an interr…
38212 … (0x1<<5) // This bit generates an interrupt when VMAIN POR is d…
38214 … (0x1<<6) // This bit generates an interr…
38216 … (0x1<<7) // This bit generates an interrupt when PERST# is de…
38218 … (0x1<<8) // This bit generates an interr…
38220 … (0x1<<9) // This bit generates an interrupt when Fdone Double Error Detection sta…
38222 … (0x1<<10) // This bit generates an interr…
38224 … (0x1<<11) // This bit generates an interr…
38226 … (0x1<<12) // This bit generates an interr…
38228 … (0x1<<13) // This bit generates an interr…
38230 … (0x1<<14) // This bit generates an interr…
38232 … (0x1<<15) // This bit generates an interr…
38234 …//Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 00000000 = divide by 256 000000…
38240 … (0x1<<4) // This bit generates an interr…
38242 … (0x1<<5) // This bit generates an interrupt when VMAIN POR is d…
38244 … (0x1<<6) // This bit generates an interr…
38246 … (0x1<<7) // This bit generates an interrupt when PERST# is de…
38248 … (0x1<<8) // This bit generates an interr…
38250 … (0x1<<9) // This bit generates an interrupt when Fdone Double Error Detection sta…
38252 … (0x1<<10) // This bit generates an interr…
38254 … (0x1<<11) // This bit generates an interr…
38256 … (0x1<<12) // This bit generates an interr…
38258 … (0x1<<13) // This bit generates an interr…
38260 … (0x1<<14) // This bit generates an interr…
38262 … (0x1<<15) // This bit generates an interr…
38264 …//Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 00000000 = divide by 256 000000…
38268 …-bit compliance enable pins on the ballout. These bits are used to override the pins if needed. 2'…
38270 … (0x1<<4) // Set this bit to override the pins on the chip with bits…
38273 …ss:RW DataWidth:0x1 // 0 - control of the tcam bist is from the IPC register tcam_bist_contro…
38274 …ss:RW DataWidth:0x1 // 0 - control of the tcam bist is from the IPC register tcam_bist_contro…
38275 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38276 …instance when reading the status of the cam in tcam_bist_status 0 ccfc_ccam 1 ccfc_scam 2 igu 3 ms…
38277 …instance when reading the status of the cam in tcam_bist_status 0 ccfc_ccam 1 ccfc_scam 2 igu 3 ms…
38278 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38279 … tcam bist status bus bit 0 - bist_pass bit 1 - bist_failed bit 2 - bist_paused bit 3 - reserved(b…
38280 … tcam bist status bus bit 0 - bist_pass bit 1 - bist_failed bit 2 - bist_paused bit 3 - reserved(b…
38281 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38282 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38283 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38285 …bit 0 - bist_run bit 1 - retention_en bit 3 - reserved(connected the bist_shi,should be zero) bit …
38286 …bit 0 - bist_run bit 1 - retention_en bit 3 - reserved(connected the bist_shi,should be zero) bit …
38288 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38289 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38290 … 0x020364UL //Access:RW DataWidth:0x4 // Control of the non-zero pole in the PLL …
38291 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38292 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38293 …68UL //Access:R DataWidth:0x1 // LOCK detector output 0= PLL unlocked 1= PLL locked Global r…
38294 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38295 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38297 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38298 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38300 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38301 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38303 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38304 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38306 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38307 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38309 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38310 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38312 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38313 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38315 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38316 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38318 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38319 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38321 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38322 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38323 … 0x020390UL //Access:RW DataWidth:0x1 // 1 : Disable high volta…
38324 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38325 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38327 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38328 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38329 … 0x020398UL //Access:R DataWidth:0x1 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38330 …ue. this value is output at ipc_clkdec_clk_dft_ms_125m_div 0 - no division 1- divide by 2 2- divid…
38331 …ue. this value is output at ipc_clkdec_clk_dft_ms_125m_div 0 - no division 1- divide by 2 2- divid…
38332 … 0x02039cUL //Access:R DataWidth:0x4 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38362 … 0x0203c4UL //Access:R DataWidth:0x1 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38363 …ess:RW DataWidth:0x6 // Sets the CTL# (# in [0..5]) I/Os of the PADS in non - scan/mbist modes
38365 … 0x0203c8UL //Access:R DataWidth:0x4 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38366 …6cUL //Access:RW DataWidth:0x2 // Sets the SL# (# in [0..1]) I/Os of the PADS in non - scan/m…
38368 … 0x0203ccUL //Access:R DataWidth:0x8 // PCIe lock signals. 0-unlocked; 1-locked. Global …
38372 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
38373 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
38377 …B (0x1<<0) // 1 : Reset the entire S…
38379 …DIO_BB (0x1<<1) // 1 : Reset the MDIO …
38380 …PC_REG_SGMII_RESETS_SGMII_RST_MDIO_BB_SHIFT 1
38381 …BB (0x1<<2) // 1 : Resets the PLL and…
38384 … 0x0203e4UL //Access:RW DataWidth:0x1 // 0 : CL22 1 : CL45 Global Regist…
38386 … 0x0203ecUL //Access:RW DataWidth:0x1 // 1 : powers down for th…
38387 … 0x0203f0UL //Access:RW DataWidth:0x1 // 1 : iddq enable, power…
38390 … (0x1<<0) // Link Status 1: Link has been achie…
38392 …_SIGDET_BB (0x1<<1) // Signal Detect Gl…
38393 …PC_REG_SGMII_STATUS_SGMII_RX_SIGDET_BB_SHIFT 1
38394 …G_BB (0x1<<2) // 1: Bit Alignment Done Glo…
38396 …TUS_BB (0x1<<3) // 1: Symbol Alignment Gl…
38398 …_BB (0x1<<4) // 1: Speed is 10M Global…
38400 …0_BB (0x1<<5) // 1: Speed is 100M Globa…
38402 … (0x1<<6) // 1: Speed is 1G Global Regist…
38404 …CK_BB (0x1<<8) // 1: PLL is locked Globa…
38406 … (0x1<<12) // 1: Running in SGMII mo…
38410 …B (0x1<<0) // 1 : Reset the VTMON re…
38412 …N_BB (0x1<<1) // 1 : Hold the VTMON …
38413 …PC_REG_PM_TMON_ENA_PM_TMON_PWRDN_BB_SHIFT 1
38414 …//Access:RW DataWidth:0x1 // Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the…
38418 …ET_BB (0x1<<0) // 1 : Reset the VTMON re…
38420 …PWRDN_BB (0x1<<1) // 1 : Hold the VTMON …
38421 …PC_REG_PCIE_TMON_ENA_PCIE_TMON_PWRDN_BB_SHIFT 1
38422 …//Access:RW DataWidth:0x1 // Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the…
38424 … // Powerdown the Rescal 0: Normal Operation Mode 1: Powerdown the RESCAL block Transition from …
38425 …ss:RW DataWidth:0x1 // Reset the RESCAL block 0: Normal Operation Mode 1: Reset the RESCAL bl…
38426 …g this bit, FW takes control of the RESCAL block manitpulates the pwrdn and reset signals to start…
38427 …h:0x1 // Setting this bit starts the HW based calibration engine to recalibrate the rescal bloc…
38428 … 0x02042cUL //Access:RW DataWidth:0x1 // 0: Normal Operation Mode 1: Freeze Internal Dig…
38429 …1:0] to analog [10] inversion of vrefs to analog [9] wait time after increasing pon 1'b0: 8 refclk…
38431 …/ Indicates if the calibraion operation is done. 0: Calibration in progress 1: Calibration Done Gl…
38433 … (0x1<<1) // Indicates if the pon data is valid when calib_done is set …
38434 …PC_REG_RESCAL_E28_STATUS_RESCAL_E28_VALID_BB_SHIFT 1
38435 … On-chip Sheet Resistance 0000 -24% ~ -21% 0001 -21% ~ -18% 0010 -18% ~ -15% 0011 -15% ~ -12% 0100…
38440 …cUL //Access:R DataWidth:0x3 // Internal State machine status 0: INIT 1: WAIT_PWRUP 2: COMP_…
38441 …50UL //Access:R DataWidth:0x3 // External State machine status 0: POR 1: INIT 2: RESET 3: PW…
38442 … // Powerdown the VManagement Switching Regulator 0: Normal Operation Mode 1: Powerdown the SWREG…
38443 …t the Registers in VManagement Switching Regulator 0: Normal Operation Mode 1: Reset the switchin …
38444 … 0x02045cUL //Access:R DataWidth:0x1 // 1: PMU is stable Globa…
38445 …:0x1 // Powerdown the VMain Switching Regulator 0: Normal Operation Mode 1: Powerdown the SWREG…
38446 …/ Reset the Registers in VMain Switching Regulator 0: Normal Operation Mode 1: Reset the switchin …
38447 … 0x020468UL //Access:R DataWidth:0x1 // 1: PMU is stable Globa…
38448 …x1 // Powerdown the VAnalog Switching Regulator 0: Normal Operation Mode 1: Powerdown the SWREG…
38449 …Reset the Registers in VAnalog Switching Regulator 0: Normal Operation Mode 1: Reset the switchin …
38450 … 0x020474UL //Access:R DataWidth:0x1 // 1: PMU is stable Globa…
38451 …h:0x1 // Powerdown the V1p8 Switching Regulator 0: Normal Operation Mode 1: Powerdown the SWREG…
38452 …// Reset the Registers in V1p8 Switching Regulator 0: Normal Operation Mode 1: Reset the switchin …
38453 … 0x020480UL //Access:R DataWidth:0x1 // 1: PMU is stable Globa…
38454 … phases of alternate clock. This lowers the overall power consumption. 1: Select 1Mhz Clock 0: Sel…
38455 … 0x020488UL //Access:RW DataWidth:0x1 // Setting this bit to "1" will enable the…
38456 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38457 …-> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the…
38458 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38462 … (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in freq_cnt f…
38464 … 0x0204e8UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38465 … 0x0204ecUL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38466 … 0x0204f0UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38467 … 0x0204f4UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38468 … 0x0204f8UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38469 … 0x0204fcUL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38470 … 0x020500UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38471 … 0x020504UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38473 … (0x1<<0) // This bit masks, when set, the Parity bit: IP…
38475 … for the PLL 0= CMOS Reference clock, output of the differential oscillator 1= CML reference clock…
38478 … If Single Error Correction status flag was 1, this bit is latched with value 1.
38480 … 0x030200UL //Access:RW DataWidth:0x1 // 0 : LPI is not enabled. 1 : LPI is enabled, LP…
38481 … 0x030204UL //Access:RW DataWidth:0x1 // Setting this bit will enable a speci…
38482 …I request to the map. The resolution of this register is 40ns. Values of 0 and 1 are not supported.
38483 …e before exiting LPI. The resolution of this register is 40ns. Values of 0 and 1 are not supported.
38485 … (0x1<<0) // 0 : PBF Empty is not part of LPI request generation logic. 1 : PBF Empty is part …
38487 … (0x1<<1) // 0 : QM Empty is not part of LPI request generation logic. 1 : QM Empty is part of…
38488 …PMU_REG_LPI_MODE_ENTRY_EN_LPI_QM_EMPTY_EN_SHIFT 1
38489 …2) // 0 : All Send Queue Empty is not part of LPI request generation logic. 1 : All Send Queue Emp…
38491 …<<3) // 0 : Management Traffic is not part of LPI request generation logic. 1 : Management Traffic…
38493 …<<4) // 0 : LPI receive status is not part of LPI request generation logic. 1 : LPI receive status…
38495 … : OBFF State (non CPU_ACTIVE) is not part of LPI request generation logic. 1 : OBFF State (non CP…
38497 …x1<<6) // 0 : PCIe in D3 State is not part of LPI request generation logic. 1 : PCIe in D3 State i…
38499 …0x1<<7) // 0 : NIG Tx is empty is not part of LPI request generation logic. 1 : NIG Tx is empty is…
38502 … (0x1<<0) // 0 : DORQ Event is not part of the equation to exit LPI. 1 : DORQ Event is part…
38504 … (0x1<<1) // 0 : NCSI Event is not part of the equation to e…
38505 …PMU_REG_LPI_MODE_EXIT_EN_LPI_NCSI_EVENT_EN_SHIFT 1
38506 … (0x1<<2) // 0 : PCIe L1 exit is not part of the equation to exit LPI. 1 : PCIe L1 exit is pa…
38508 …x1<<3) // This bit will be used in the Batch and Burst mode. In this mode, 0 : pbf almost full is …
38510 …x1<<4) // This bit will be used in the Batch and Burst mode. In this mode, 0 : BMB almost full is …
38512 …) // This bit will be used in the Normal mode. In this mode, 0 : Early exit indication from X or U…
38514 … (0x1<<6) // 0 : LPI receive status is not part of LPI request exit logic. 1 : LPI receive status…
38516 …taWidth:0x1 // Setting this bit to "1" will allow software to force an LPI request on the inter…
38517 …bit to "1" will allow software to provide an early indication to exit LPI state. HW will generate …
38518 … 0x030220UL //Access:RW DataWidth:0x1 // 0 : OBFF is not enabled. 1 : OBFF is enabled, D…
38522 … (0x1<<1) // 0: Engine IDLE is not part of the OBFF state …
38523 …PMU_REG_OBFF_MODE_CONTROL_OBFF_ENGINE_IDLE_EN_SHIFT 1
38524 … (0x1<<2) // Setting this bit forces the CPMU to …
38526 …// 0 : IGU Pending Interrupt is not part of OBFF logic w.r.t. IGU requests. 1 : IGU Pending Interr…
38528 … // 0 : VOQ for IGU requests is not part of OBFF logic w.r.t. IGU requests. 1 : VOQ for IGU reques…
38530 … (0x1<<5) // 0 : Interrupts are not part of OBFF logic w.r.t. IGU requests. 1 : Interrupts are par…
38534 …stall_mem control, the control set logic is not conditioned with VOQ empty. 1 : For the FSM that d…
38536 …t conditioned with VOQ empty / Interrupt Deasserted / No Pending Interrupt. 1 : For the FSM that d…
38538 …bit to "1" will allow software to force an exit from the OBFF related stalls. HW will generate a p…
38539 …pires when it reaches this threshold and stall state is exited. Values of 0 and 1 are not supported
38540 …ires when it reaches this threshold and stall state is exited. Values of 0 and 1 are not supported.
38541 …ires when it reaches this threshold and stall state is exited. Values of 0 and 1 are not supported.
38542 …ires when it reaches this threshold and stall state is exited. Values of 0 and 1 are not supported.
38543 … bit in this register to "1" will cause the CPMU to launch a timer when the corresponding VOQ is n…
38544 … bit in this register to "1" will cause the CPMU to launch a timer when the corresponding VOQ is n…
38545 … bit in this register to "1" will cause the CPMU to launch a timer when the corresponding VOQ is n…
38546 … bit in this register to "1" will cause the CPMU to launch a timer when the corresponding VOQ is n…
38547 … entry to OBFF state. The resolution of this register is 40ns. Values of 0 and 1 are not supported.
38549 … (0x1<<0) // 0 : PBF Empty is not part of OBFF logic. 1 : PBF Empty is not p…
38551 … (0x1<<1) // 0 : QM Tx Empty is not part of OBFF logic…
38552 …PMU_REG_OBFF_MODE_ENTRY_EN_OBFF_QM_EMPTY_TX_EN_SHIFT 1
38553 …// 0 : QM Global Empty is not part of main clock slowdown generation logic. 1 : QM Global Empty is…
38555 … (0x1<<3) // 0 : All Send Queue Empty is not part of OBFF logic. 1 : All Send Queue Emp…
38557 … (0x1<<4) // 0 : Management Traffic is not part of OBFF logic. 1 : Management Traffic…
38559 … (0x1<<5) // 0 : BRB empty is not part of OBFF logic. 1 : BRB empty is part …
38561 … (0x1<<6) // 0 : PXP empty is not part of OBFF logic. 1 : PXP empty is part …
38563 … (0x1<<7) // 0 : CAU IDLE is not part of OBFF logic. 1 : CAU IDLE is part o…
38565 … (0x1<<8) // 0 : Timer Scan status is not part of OBFF logic. 1 : Timer Scan status …
38567 … (0x1<<9) // 0 : OBFF State (non CPU_ACTIVE) is not part of OBFF logic. 1 : OBFF State (non CP…
38569 … (0x1<<10) // 0 : TSEM IDLE is not part of OBFF logic. 1 : TSEM IDLE is part …
38571 … (0x1<<11) // 0 : MSEM IDLE is not part of OBFF logic. 1 : MSEM IDLE is part …
38573 … (0x1<<12) // 0 : USEM IDLE is not part of OBFF logic. 1 : USEM IDLE is part …
38575 … (0x1<<13) // 0 : XSEM IDLE is not part of OBFF logic. 1 : XSEM IDLE is part …
38577 … (0x1<<14) // 0 : YSEM IDLE is not part of OBFF logic. 1 : YSEM IDLE is part …
38579 … (0x1<<15) // 0 : PSEM IDLE is not part of OBFF logic. 1 : PSEM IDLE is part …
38581 … (0x1<<16) // 0 : LPI receive status is not part of OBFF logic. 1 : LPI receive status…
38583 … (0x1<<17) // 0 : Network Link Down is not part of OBFF logic. 1 : Network Link Down …
38585 … (0x1<<18) // 0 : NIG Rx Empty is not part of OBFF logic. 1 : NIG Rx Empty is pa…
38587 … (0x1<<19) // 0 : NIG Tx Empty is not part of OBFF logic. 1 : NIG Tx Empty is pa…
38589 … (0x1<<20) // 0 : NIG lb Empty is not part of OBFF logic. 1 : NIG lb Empty is pa…
38592 … (0x1<<0) // 0 : PCIe L1 exit is not part of exit from OBFF logic 1 : PCIe L1 exit is pa…
38594 … (0x1<<1) // 0 : DORQ Event is not part of exit from OBFF …
38595 …PMU_REG_OBFF_MODE_EXIT_EN_OBFF_DORQ_EVENT_EN_SHIFT 1
38596 … // This bit will be used in the Normal mode. In this mode, 0 : Early exit indication from X or US…
38599 …idth:0x20 // 0 : use the short timer threshold for the corresponding VOQ. 1 : use the long timer…
38600 …idth:0x2 // 0 : use the short timer threshold for the corresponding VOQ. 1 : use the long timer…
38601 …64UL //Access:RW DataWidth:0x1 // 0 : Entry to PCIe L1 is not enabled. 1 : Entry to PCIe L1 i…
38602 …shold for the L1 mode. The resolution of this register is 40ns. Value of 0 and 1 are not supported.
38604 … (0x1<<0) // 0 : PBF Empty is not part of L1 request generation logic. 1 : PBF Empty is part …
38606 … (0x1<<1) // 0 : QM Tx Empty is not part of L1 request generat…
38607 …PMU_REG_L1_MODE_ENTRY_EN_L1_QM_EMPTY_TX_EN_SHIFT 1
38608 …(0x1<<2) // 0 : QM Global Empty is not part of L1 request generation logic. 1 : QM Global Empty is…
38610 …<3) // 0 : All Send Queue Empty is not part of L1 request generation logic. 1 : All Send Queue Emp…
38612 …1<<4) // 0 : Management Traffic is not part of L1 request generation logic. 1 : Management Traffic…
38614 … (0x1<<5) // 0 : BRB empty is not part of L1 request generation logic. 1 : BRB empty is part …
38616 … (0x1<<6) // 0 : PXP empty is not part of L1 request generation logic. 1 : PXP empty is part …
38618 … (0x1<<7) // 0 : PGL empty is not part of L1 request generation logic. 1 : PGL empty is part …
38620 … (0x1<<8) // 0 : CAU IDLE is not part of L1 request generation logic. 1 : CAU IDLE is part o…
38622 …x1<<9) // 0 : Timer Scan status is not part of L1 request generation logic. 1 : Timer Scan status …
38624 …<<10) // 0 : LPI receive status is not part of L1 request generation logic. 1 : LPI receive status…
38627 … (0x1<<0) // 0 : LPI recive status is not part of the L1 exit. 1 : LPI recive status …
38629 …0x1<<1) // This bit will be used in the Normal mode. In this mode, 0 : Early exit indication from …
38630 …PMU_REG_L1_MODE_EXIT_EN_L1_SQ_EARLY_EXIT_EN_SHIFT 1
38631 …ataWidth:0x1 // Setting this bit to "1" will allow software to force an L1 request on the inter…
38632 …bit to "1" will allow software to provide an early indication to exit L1 state. HW will generate a…
38633 …cUL //Access:RW DataWidth:0x1 // 0 : Entry to PCIe LTR is not enabled. 1 : Entry to PCIe LTR …
38634 …old for the LTR mode. The resolution of this register is 40ns. Values of 0 and 1 are not supported.
38636 … (0x1<<0) // 0 : PBF Empty is not part of LTR request generation logic. 1 : PBF Empty is part …
38638 … (0x1<<1) // 0 : QM Tx Empty is not part of LTR request generat…
38639 …PMU_REG_LTR_MODE_ENTRY_EN_LTR_QM_EMPTY_TX_EN_SHIFT 1
38640 …0x1<<2) // 0 : QM Global Empty is not part of LTR request generation logic. 1 : QM Global Empty is…
38642 …3) // 0 : All Send Queue Empty is not part of LTR request generation logic. 1 : All Send Queue Emp…
38644 …<<4) // 0 : Management Traffic is not part of LTR request generation logic. 1 : Management Traffic…
38646 …<5) // 0 : BRB above threshold is not part of LTR request generation logic. 1 : BRB above threshol…
38648 … (0x1<<6) // 0 : PXP empty is not part of LTR request generation logic. 1 : PXP empty is part …
38650 … (0x1<<7) // 0 : PGL empty is not part of LTR request generation logic. 1 : PGL empty is part …
38652 … (0x1<<8) // 0 : CAU IDLE is not part of LTR request generation logic. 1 : CAU IDLE is part o…
38654 …1<<9) // 0 : Timer Scan status is not part of LTR request generation logic. 1 : Timer Scan status …
38656 …<10) // 0 : LPI receive status is not part of LTR request generation logic. 1 : LPI receive status…
38658 …/ 0 : OBFF Memory access stall is not part of LTR request generation logic. 1 : OBFF Memory access…
38660 … : OBFF interrupt access stall is not part of LTR request generation logic. 1 : OBFF interrupt acc…
38663 … (0x1<<0) // 0 : LPI recive status is not part of the LTR exit. 1 : LPI recive status …
38665 …x1<<1) // This bit will be used in the Normal mode. In this mode, 0 : Early exit indication from X…
38666 …PMU_REG_LTR_MODE_EXIT_EN_LTR_SQ_EARLY_EXIT_EN_SHIFT 1
38667 …taWidth:0x1 // Setting this bit to "1" will allow software to force an LTR request on the inter…
38668 …bit to "1" will allow software to provide an early indication to exit LTR state. HW will generate …
38670 … (0x1<<0) // 0 : Shutdown Main Clock to Path 0 1 : Enable Main Clock …
38672 … (0x1<<1) // 0 : Shutdown Main Clock to Path 1 1 : Enable Main C…
38673 …PMU_REG_CLK_EN_CONFIG_MAIN_CLK_E1_EN_SHIFT 1
38674 … (0x1<<2) // 0 : Shutdown Main Clock to Path 0 on the Network side 1 : Enable Main Clock …
38676 … (0x1<<3) // 0 : Shutdown Main Clock to Path 1 on the Network side 1 : Enable Main Clock to P…
38678 … (0x1<<4) // 0 : Shutdown Main Clock to Common Logic on the Network side 1 : Enable Main Clock …
38680 … (0x1<<5) // 0 : Shutdown Main Clock to Common Logic on the Host side 1 : Enable Main Clock …
38682 … (0x1<<6) // 0 : Shutdown STORM Clock to Path 0 1 : Enable STORM Clock…
38684 … (0x1<<7) // 0 : Shutdown STORM Clock to Path 1 1 : Enable STORM Clock to Path 1
38686 … (0x1<<8) // 0 : Shutdown Network Clock to Path 0 1 : Enable Network Clo…
38688 … (0x1<<9) // 0 : Shutdown Network Clock to Path 1 1 : Enable Network Clock to Path 1
38690 … (0x1<<10) // 0 : Shutdown Network Clock to Common logic 1 : Enable Network Clo…
38692 … (0x1<<11) // 0 : Shutdown Configuration Clock to PCIe Core 1 : Enable Configurati…
38694 … (0x1<<12) // 0 : Shutdown PCI Clock to Path 0 1 : Enable PCI clock t…
38696 … (0x1<<13) // 0 : Shutdown PCI Clock to Path 1 1 : Enable PCI clock to Path 1
38698 … (0x1<<14) // 0 : Shutdown PCI Clock to Common logic on the host side 1 : Enable PCI clock t…
38700 … (0x1<<15) // 0 : Shutdown all clocks to the Falcon based Port Macro 1 : Enable all clocks …
38702 … (0x1<<16) // 0 : Shutdown all clocks to the Eagle based Port Macro 1 : Enable all clocks …
38704 … (0x1<<17) // 0 : Shutdown NWM clock to the NW MAC 1 : Enable NWM clock t…
38706 … (0x1<<18) // 0 : Shutdown Main Clock to the BMB PD 1 : Enable Main Clock …
38708 … (0x1<<19) // 0 : Shutdown Network Clock to the BMB PD 1 : Enable Network Clo…
38710 … (0x1<<20) // 0 : Shutdown Main Clock to the NW PD 1 : Enable Main Clock …
38712 … (0x1<<21) // 0 : Shutdown Main Clock to the NMC PD 1 : Enable Main Clock …
38714 … (0x1<<22) // 0 : Shutdown Network Clock to the NMC PD 1 : Enable Network Clo…
38716 … (0x1<<23) // 0 : Shutdown AHB Clock to the NMC PD 1 : Enable AHB Clock t…
38718 … (0x1<<24) // 0 : Shutdown Main Clock to the TOP 1 : Enable Main Clock …
38721 … (0x1<<0) // 0 : Slowdown of Main Clock is not enabled. 1 : Slowdown of Main C…
38723 … (0x1<<1) // 0 : Slowdown of STORM Clock is not enable…
38724 …PMU_REG_CLK_PM_CONFIG_SLOWDOWN_STORM_CLK_EN_SHIFT 1
38725 … (0x1<<2) // 0 : Slowdown of Network Clock is not enabled. 1 : Slowdown of Networ…
38727 … (0x1<<3) // 0 : Slowdown of PCI Clock is not enabled. 1 : Slowdown of PCI Cl…
38730 … (0x1<<0) // 0 : Slowdown of Main Clock for common logic is not enabled. 1 : Slowdown of Main C…
38732 … (0x1<<1) // 0 : Slowdown of Network Clock for common logic is n…
38733 …PMU_REG_CLK_PM_CMN_CONFIG_SLOWDOWN_NW_CLK_CMN_EN_SHIFT 1
38734 … (0x1<<2) // 0 : Slowdown of PCI Clock for common logic is not enabled. 1 : Slowdown of PCI Cl…
38736 … Clock slowdown mode. The resolution of this register is 40ns. Values of 0 and 1 are not supported.
38737 … Clock slowdown mode. The resolution of this register is 40ns. Values of 0 and 1 are not supported.
38738 … Clock slowdown mode. The resolution of this register is 40ns. Values of 0 and 1 are not supported.
38739 … Clock slowdown mode. The resolution of this register is 40ns. Values of 0 and 1 are not supported.
38740 …lue of 15 in the register will result in the clock generation logic to send 1 clock pulse through …
38741 …lue of 15 in the register will result in the clock generation logic to send 1 clock pulse through …
38742 …lue of 15 in the register will result in the clock generation logic to send 1 clock pulse through …
38743 …lue of 15 in the register will result in the clock generation logic to send 1 clock pulse through …
38745 … (0x1<<0) // 0 : PBF Empty is not part of main clock slowdown logic. 1 : PBF Empty is not p…
38747 … (0x1<<1) // 0 : QM Tx Empty is not part of main clock slowdown gen…
38748 …PMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_QM_EMPTY_TX_EN_SHIFT 1
38749 …// 0 : QM Global Empty is not part of main clock slowdown generation logic. 1 : QM Global Empty is…
38751 …1<<3) // 0 : All Send Queue Empty is not part of Main Clock slowdown logic. 1 : All Send Queue Emp…
38753 …0x1<<4) // 0 : Management Traffic is not part of Main Clock slowdown logic. 1 : Management Traffic…
38755 … (0x1<<5) // 0 : BRB empty is not part of Main Clock slowdown logic. 1 : BRB empty is part …
38757 … (0x1<<6) // 0 : PXP empty is not part of Main Clock slowdown logic. 1 : PXP empty is part …
38759 … (0x1<<7) // 0 : CAU IDLE is not part of Main Clock slowdown logic. 1 : CAU IDLE is part o…
38761 …(0x1<<8) // 0 : Timer Scan status is not part of Main Clock slowdown logic. 1 : Timer Scan status …
38763 …/ 0 : OBFF State (non CPU_ACTIVE) is not part of Main Clock slowdown logic. 1 : OBFF State (non CP…
38765 … (0x1<<10) // 0 : TSEM IDLE is not part of Main Clock slowdown logic. 1 : TSEM IDLE is part …
38767 … (0x1<<11) // 0 : MSEM IDLE is not part of Main Clock slowdown logic. 1 : MSEM IDLE is part …
38769 … (0x1<<12) // 0 : USEM IDLE is not part of Main Clock slowdown logic. 1 : USEM IDLE is part …
38771 … (0x1<<13) // 0 : XSEM IDLE is not part of Main Clock slowdown logic. 1 : XSEM IDLE is part …
38773 … (0x1<<14) // 0 : YSEM IDLE is not part of Main Clock slowdown logic. 1 : YSEM IDLE is part …
38775 … (0x1<<15) // 0 : PSEM IDLE is not part of Main Clock slowdown logic. 1 : PSEM IDLE is part …
38777 …x1<<16) // 0 : LPI receive status is not part of Main Clock slowdown logic. 1 : LPI receive status…
38779 …0x1<<17) // 0 : Network Link Down is not part of Main Clock slowdown logic. 1 : Network Link Down …
38781 … (0x1<<18) // 0 : NIG Rx Empty is not part of Main Clock slowdown logic. 1 : NIG Rx Empty is pa…
38783 … (0x1<<19) // 0 : NIG Tx Empty is not part of Main Clock slowdown logic. 1 : NIG Tx Empty is pa…
38785 …x1<<20) // 0 : NIG Loopback Empty is not part of Main Clock slowdown logic. 1 : NIG Loopback Empty…
38787 … (0x1<<21) // 0 : PCIE in D3 is not part of Main Clock slowdown logic. 1 : PCIE in D3 is part…
38790 …<<0) // 0 : PCIe L1 exit is not part of exit from main clock slowdown logic 1 : PCIe L1 exit is pa…
38792 … (0x1<<1) // 0 : DORQ Event is not part of exit from main clock s…
38793 …PMU_REG_MAIN_CLK_SLOWDOWN_EXIT_EN_MCS_DORQ_EVENT_EN_SHIFT 1
38794 …x1<<2) // 0 : NCSI Event is not part of exit from main clock slowdown logic 1 : NCSI Event is part…
38796 … 0x0302c8UL //Access:RW DataWidth:0x1 // Setting this bit to "1" will allow soft…
38797 … 0x0302ccUL //Access:W DataWidth:0x1 // Setting this bit to "1" will allow soft…
38799 … (0x1<<0) // 0 : PBF Empty is not part of storm clock slowdown logic. 1 : PBF Empty is not p…
38801 … (0x1<<1) // 0 : QM Tx Empty is not part of storm clock slowdown ge…
38802 …PMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_QM_EMPTY_TX_EN_SHIFT 1
38803 …/ 0 : QM Global Empty is not part of storm clock slowdown generation logic. 1 : QM Global Empty is…
38805 …<<3) // 0 : All Send Queue Empty is not part of Storm Clock slowdown logic. 1 : All Send Queue Emp…
38807 …x1<<4) // 0 : Management Traffic is not part of Storm Clock slowdown logic. 1 : Management Traffic…
38809 … (0x1<<5) // 0 : BRB empty is not part of Storm Clock slowdown logic. 1 : BRB empty is part …
38811 … (0x1<<6) // 0 : PXP empty is not part of Storm Clock slowdown logic. 1 : PXP empty is part …
38813 … (0x1<<7) // 0 : CAU IDLE is not part of Storm Clock slowdown logic. 1 : CAU IDLE is part o…
38815 …0x1<<8) // 0 : Timer Scan status is not part of Storm Clock slowdown logic. 1 : Timer Scan status …
38817 … 0 : OBFF State (non CPU_ACTIVE) is not part of Storm Clock slowdown logic. 1 : OBFF State (non CP…
38819 … (0x1<<10) // 0 : TSEM IDLE is not part of Storm Clock slowdown logic. 1 : TSEM IDLE is part …
38821 … (0x1<<11) // 0 : MSEM IDLE is not part of Storm Clock slowdown logic. 1 : MSEM IDLE is part …
38823 … (0x1<<12) // 0 : USEM IDLE is not part of Storm Clock slowdown logic. 1 : USEM IDLE is part …
38825 … (0x1<<13) // 0 : XSEM IDLE is not part of Storm Clock slowdown logic. 1 : XSEM IDLE is part …
38827 … (0x1<<14) // 0 : YSEM IDLE is not part of Storm Clock slowdown logic. 1 : YSEM IDLE is part …
38829 … (0x1<<15) // 0 : PSEM IDLE is not part of Storm Clock slowdown logic. 1 : PSEM IDLE is part …
38831 …1<<16) // 0 : LPI receive status is not part of Storm Clock slowdown logic. 1 : LPI receive status…
38833 …x1<<17) // 0 : Network Link Down is not part of Storm Clock slowdown logic. 1 : Network Link Down …
38835 … (0x1<<18) // 0 : NIG Rx Empty is not part of Storm Clock slowdown logic. 1 : NIG Rx Empty is pa…
38837 … (0x1<<19) // 0 : NIG Tx Empty is not part of Storm Clock slowdown logic. 1 : NIG Tx Empty is pa…
38839 …1<<20) // 0 : NIG Loopback Empty is not part of Storm Clock slowdown logic. 1 : NIG Loopback Empty…
38841 … (0x1<<21) // 0 : PCIE in D3 is not part of Storm Clock slowdown logic. 1 : PCIE in D3 is part…
38844 …<0) // 0 : PCIe L1 exit is not part of exit from storm clock slowdown logic 1 : PCIe L1 exit is pa…
38846 … (0x1<<1) // 0 : DORQ Event is not part of exit from storm clock s…
38847 …PMU_REG_STORM_CLK_SLOWDOWN_EXIT_EN_SCS_DORQ_EVENT_EN_SHIFT 1
38848 …1<<2) // 0 : NCSI Event is not part of exit from storm clock slowdown logic 1 : NCSI Event is part…
38850 … 0x0302d8UL //Access:RW DataWidth:0x1 // Setting this bit to "1" will allow soft…
38851 … 0x0302dcUL //Access:W DataWidth:0x1 // Setting this bit to "1" will allow soft…
38853 … (0x1<<0) // 0 : PBF Empty is not part of nw clock slowdown logic. 1 : PBF Empty is not p…
38855 … (0x1<<1) // 0 : QM Tx Empty is not part of nw clock slowdown gene…
38856 …PMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_QM_EMPTY_TX_EN_SHIFT 1
38857 …) // 0 : QM Global Empty is not part of nw clock slowdown generation logic. 1 : QM Global Empty is…
38859 …0x1<<3) // 0 : All Send Queue Empty is not part of Nw Clock slowdown logic. 1 : All Send Queue Emp…
38861 … (0x1<<4) // 0 : Management Traffic is not part of Nw Clock slowdown logic. 1 : Management Traffic…
38863 … (0x1<<5) // 0 : BRB empty is not part of Nw Clock slowdown logic. 1 : BRB empty is part …
38865 … (0x1<<6) // 0 : PXP empty is not part of Nw Clock slowdown logic. 1 : PXP empty is part …
38867 … (0x1<<7) // 0 : CAU IDLE is not part of Nw Clock slowdown logic. 1 : CAU IDLE is part o…
38869 … (0x1<<8) // 0 : Timer Scan status is not part of Nw Clock slowdown logic. 1 : Timer Scan status …
38871 … // 0 : OBFF State (non CPU_ACTIVE) is not part of Nw Clock slowdown logic. 1 : OBFF State (non CP…
38873 … (0x1<<10) // 0 : TSEM IDLE is not part of Nw Clock slowdown logic. 1 : TSEM IDLE is part …
38875 … (0x1<<11) // 0 : MSEM IDLE is not part of Nw Clock slowdown logic. 1 : MSEM IDLE is part …
38877 … (0x1<<12) // 0 : USEM IDLE is not part of Nw Clock slowdown logic. 1 : USEM IDLE is part …
38879 … (0x1<<13) // 0 : XSEM IDLE is not part of Nw Clock slowdown logic. 1 : XSEM IDLE is part …
38881 … (0x1<<14) // 0 : YSEM IDLE is not part of Nw Clock slowdown logic. 1 : YSEM IDLE is part …
38883 … (0x1<<15) // 0 : PSEM IDLE is not part of Nw Clock slowdown logic. 1 : PSEM IDLE is part …
38885 …(0x1<<16) // 0 : LPI receive status is not part of Nw Clock slowdown logic. 1 : LPI receive status…
38887 … (0x1<<17) // 0 : Network Link Down is not part of Nw Clock slowdown logic. 1 : Network Link Down …
38889 … (0x1<<18) // 0 : NIG Rx Empty is not part of Nw Clock slowdown logic. 1 : NIG Rx Empty is pa…
38891 … (0x1<<19) // 0 : NIG Tx Empty is not part of Nw Clock slowdown logic. 1 : NIG Tx Empty is pa…
38893 …(0x1<<20) // 0 : NIG Loopback Empty is not part of Nw Clock slowdown logic. 1 : NIG Loopback Empty…
38895 … (0x1<<21) // 0 : PCIE in D3 is not part of NW Clock slowdown logic. 1 : PCIE in D3 is part…
38898 …x1<<0) // 0 : PCIe L1 exit is not part of exit from nw clock slowdown logic 1 : PCIe L1 exit is pa…
38900 … (0x1<<1) // 0 : DORQ Event is not part of exit from nw clock sl…
38901 …PMU_REG_NW_CLK_SLOWDOWN_EXIT_EN_NCS_DORQ_EVENT_EN_SHIFT 1
38902 …(0x1<<2) // 0 : NCSI Event is not part of exit from nw clock slowdown logic 1 : NCSI Event is part…
38904 … 0x0302e8UL //Access:RW DataWidth:0x1 // Setting this bit to "1" will allow soft…
38905 … 0x0302ecUL //Access:W DataWidth:0x1 // Setting this bit to "1" will allow soft…
38907 … (0x1<<0) // 0 : PBF Empty is not part of pci clock slowdown logic. 1 : PBF Empty is not p…
38909 … (0x1<<1) // 0 : QM Tx Empty is not part of pci clock slowdown gen…
38910 …PMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_QM_EMPTY_TX_EN_SHIFT 1
38911 … // 0 : QM Global Empty is not part of pci clock slowdown generation logic. 1 : QM Global Empty is…
38913 …x1<<3) // 0 : All Send Queue Empty is not part of PCI Clock slowdown logic. 1 : All Send Queue Emp…
38915 …(0x1<<4) // 0 : Management Traffic is not part of PCI Clock slowdown logic. 1 : Management Traffic…
38917 … (0x1<<5) // 0 : BRB empty is not part of PCI Clock slowdown logic. 1 : BRB empty is part …
38919 … (0x1<<6) // 0 : PXP empty is not part of PCI Clock slowdown logic. 1 : PXP empty is part …
38921 … (0x1<<7) // 0 : CAU IDLE is not part of PCI Clock slowdown logic. 1 : CAU IDLE is part o…
38923 … (0x1<<8) // 0 : Timer Scan status is not part of PCI Clock slowdown logic. 1 : Timer Scan status …
38925 …// 0 : OBFF State (non CPU_ACTIVE) is not part of PCI Clock slowdown logic. 1 : OBFF State (non CP…
38927 … (0x1<<10) // 0 : TSEM IDLE is not part of PCI Clock slowdown logic. 1 : TSEM IDLE is part …
38929 … (0x1<<11) // 0 : MSEM IDLE is not part of PCI Clock slowdown logic. 1 : MSEM IDLE is part …
38931 … (0x1<<12) // 0 : USEM IDLE is not part of PCI Clock slowdown logic. 1 : USEM IDLE is part …
38933 … (0x1<<13) // 0 : XSEM IDLE is not part of PCI Clock slowdown logic. 1 : XSEM IDLE is part …
38935 … (0x1<<14) // 0 : YSEM IDLE is not part of PCI Clock slowdown logic. 1 : YSEM IDLE is part …
38937 … (0x1<<15) // 0 : PSEM IDLE is not part of PCI Clock slowdown logic. 1 : PSEM IDLE is part …
38939 …0x1<<16) // 0 : LPI receive status is not part of PCI Clock slowdown logic. 1 : LPI receive status…
38941 …(0x1<<17) // 0 : Network Link Down is not part of PCI Clock slowdown logic. 1 : Network Link Down …
38943 … (0x1<<18) // 0 : NIG Rx Empty is not part of PCI Clock slowdown logic. 1 : NIG Rx Empty is pa…
38945 … (0x1<<19) // 0 : NIG Tx Empty is not part of PCI Clock slowdown logic. 1 : NIG Tx Empty is pa…
38947 …0x1<<20) // 0 : NIG Loopback Empty is not part of PCI Clock slowdown logic. 1 : NIG Loopback Empty…
38949 … (0x1<<21) // 0 : PCIE in D3 is not part of PCI Clock slowdown logic. 1 : PCIE in D3 is part…
38952 …1<<0) // 0 : PCIe L1 exit is not part of exit from pci clock slowdown logic 1 : PCIe L1 exit is pa…
38954 … (0x1<<1) // 0 : DORQ Event is not part of exit from pci clock sl…
38955 …PMU_REG_PCI_CLK_SLOWDOWN_EXIT_EN_PCS_DORQ_EVENT_EN_SHIFT 1
38956 …0x1<<2) // 0 : NCSI Event is not part of exit from pci clock slowdown logic 1 : NCSI Event is part…
38958 … 0x0302f8UL //Access:RW DataWidth:0x1 // Setting this bit to "1" will allow soft…
38959 … 0x0302fcUL //Access:W DataWidth:0x1 // Setting this bit to "1" will allow soft…
38962 … 0x030308UL //Access:R DataWidth:0x20 // First 32bits of VQ empty for Engine 1
38963 … 0x03030cUL //Access:R DataWidth:0x2 // Bits [33:32] of VQ empty for engine 1
39008 …S_1_CNIG_RX_LPI_P1_E0_ISIG_STATUS (0x1<<1) // Current status o…
39009 …PMU_REG_CPMU_INPUT_SIG_STATUS_1_CNIG_RX_LPI_P1_E0_ISIG_STATUS_SHIFT 1
39057 …S_2_PGLUE_INT_DEASSERT_E1_ISIG_STATUS (0x1<<1) // Current status o…
39058 …PMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_INT_DEASSERT_E1_ISIG_STATUS_SHIFT 1
39104 …S_3_XSEM_SEM_IDLE_E0_ISIG_STATUS (0x1<<1) // Current status o…
39105 …PMU_REG_CPMU_INPUT_SIG_STATUS_3_XSEM_SEM_IDLE_E0_ISIG_STATUS_SHIFT 1
39141 …US_CNIG_LPI_REQ_P0_E1_OSIG_STATUS (0x1<<1) // Current status o…
39142 …PMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P0_E1_OSIG_STATUS_SHIFT 1
39236 … (0x1<<0) // This bit masks, when set, the Interrupt bit: C…
39245 … 0x0303f4UL //Access:R DataWidth:0x20 // SDM SQ counter value for Engine 0, port 1.
39246 … 0x0303f8UL //Access:R DataWidth:0x20 // SDM SQ counter value for Engine 1, port 0.
39247 … 0x0303fcUL //Access:R DataWidth:0x20 // SDM SQ counter value for Engine 1, port 1.
39251 … (0x1<<0) // This bit masks, when set, the Parity bit: NC…
39253 … (0x1<<1) // This bit masks, when set, the Parity bi…
39254 …CSI_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_E5_SHIFT 1
39255 … (0x1<<2) // This bit masks, when set, the Parity bit: NC…
39259 … (0x1<<0) // Setting this bit to a '1' will result in…
39261 … (0x1<<1) // Setting this bit to a '1' will …
39262 …CSI_REG_CONFIG_ALL_MCP_SHIFT 1
39263 … (0x1<<2) // 0 -> Send all broadcast packets to the appropriate networ…
39265 … (0x1<<3) // 0 -> Send all multicast packets to the appropriate networ…
39267 … (0x1<<4) // 0 -> only MAC address is used for comparison to detect Host2B…
39269 … (0x1<<5) // 0 -> Do not enable source MAC address learning for packets from…
39271 … (0x1<<6) // 0 -> Entries in SA Learning Cache are valid even after they…
39273 … (0x1<<7) // Setting this bit to a '1' will result in…
39275 … (0x1<<8) // Setting this bit to a '1' will result in XOFF to be sent out to BMC. Clearing this re…
39277 … (0x1<<9) // Setting this bit to a '1' tells the HW t…
39279 … (0x1<<10) // 0 -> Select NCSI RMII interface as the MII port …
39281 … (0x1<<11) // 0 -> Select NCSI RMII interface as the Management Po…
39283 … (0x1<<12) // 1 -> When BMB asserts any full condition, drop all the packets 0 -> D…
39285 … (0x1<<13) // 1 -> When this bit is set, all pass through traffic will be directed to ho…
39287 … 0x040204UL //Access:RW DataWidth:0x1 // When set, this bit indicates that the …
39289 …bit shows whether the corresponding entry in the BMC MAC address + VLAN is valid or not. A '1' ind…
39290 …bit shows whether the corresponding entry in the BMC MAC address + VLAN is valid or not. A '1' ind…
39291 …bit shows whether the corresponding entry in the BMC MAC address + VLAN is valid or not. A '1' ind…
39292 …bit shows whether the corresponding entry in the BMC MAC address + VLAN is valid or not. A '1' ind…
39305 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39306 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39307 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39308 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39309 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39310 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39311 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39312 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39313 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39314 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39315 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39316 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39317 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39318 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39319 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39320 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39369 …bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware s…
39370 …bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replac…
39371 …bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware s…
39372 …bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replac…
39373 …bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware s…
39374 …bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replac…
39375 …bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware s…
39376 …bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replac…
39377 …bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware s…
39378 …bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replac…
39379 …bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware s…
39380 …bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replac…
39381 …bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware s…
39382 …bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replac…
39383 …bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware s…
39384 …bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replac…
39401 …only register. it captures which of the four channels in the host, the MAC address was learnt from…
39402 …only register. it captures which of the four channels in the host, the MAC address was learnt from…
39403 …only register. it captures which of the four channels in the host, the MAC address was learnt from…
39404 …only register. it captures which of the four channels in the host, the MAC address was learnt from…
39405 …only register. it captures which of the four channels in the host, the MAC address was learnt from…
39406 …only register. it captures which of the four channels in the host, the MAC address was learnt from…
39407 …only register. it captures which of the four channels in the host, the MAC address was learnt from…
39408 …only register. it captures which of the four channels in the host, the MAC address was learnt from…
39417 …eshold. When the timer expires, the entry can be replaced. The resolution of the aging timer is 1ms
39418 … 0x040410UL //Access:RW DataWidth:0x1 // When this bit is set, all the ent…
39420 … (0x1<<0) // Setting this bit to "1" will result in …
39422 …1) // NCSI block has the capability to remove up-to six TAGs present in a packet. This field sets …
39423 …CSI_REG_TAG_RM_CONFIG_PER_TAG_RM_SHIFT 1
39424 …-> Use the configuration bit associated with the Inner VLAN tag to decide whether to remove the ta…
39426 …from the packet before sending it out to BMC. it is expected that once a non-zero value is set, al…
39428 …L //Access:RW DataWidth:0x3 // The length of the info field for L2 tag 1. The length is betw…
39436 …T_OUTER_TAG (0x1<<1) // Tells HW to set …
39437 …CSI_REG_TAG_INS_CONFIG_INSERT_OUTER_TAG_SHIFT 1
39438 …criptor for a BMC to Network packet if there is a VLAN header in the packet and VLAN ID is non-zero
39449 … // Setting this field to '1' causes the hardware arbitration scheme to be disabled. This bit shou…
39451 … (0x1<<5) // Setting this field to '1' causes the hardware arbitration scheme to begin. Any NC…
39453 …1' the HW arbitration logic to function in bypass mode. This allows NCSI ports that don't have the…
39455 … (0x1<<7) // Setting this field to '1' causes the NCSI por…
39457 … (0x1f<<8) // This field is a programmable inter-packet gap for when t…
39461 … (0x1<<14) // Setting this bit disables the featur…
39463 … (0x1<<15) // Toggle this bit to update this register. Write "1" a…
39465 …mber of Ingress clock cycles that the arbitration master will wait before re-starting the arbitrat…
39467 … 0x04043cUL //Access:R DataWidth:0x1 // This bit indicates if the ar…
39470 … (0x1<<0) // Setting this bit will create an asychronous reset to the egress logic. Sh…
39472 … (0x1<<1) // Setting this bit will create an asychronous reset to the ingress…
39473 …CSI_REG_NCSI_RESET_INGRESS_RESET_SHIFT 1
39484 …transfer to NCSI has started. Setting a value of all 1s in this register will guarantee a store-an…
39486 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
39487 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
39488 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
39489 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
39499 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
39507 …ataWidth:0x1 // Reset the protection override window memory. When set to 1, protection override…
39508 … 0x050004UL //Access:R DataWidth:0x1 // When = 1, the self init for t…
39509 …s resolution). Bits [23]: Wr/rd. If = 1 it is write, If = 0 it is read. Bits [27:24]: Master. T…
39510 …Bit [13:12]: Port. Bits [15:14]: Privilege. The decoding: 0 - VN: Virtualized NIC (Used for VF ac…
39511 …1, indicates that the rsv_attn_access_data_0 and rsv_attn_access_data_1 registers contain valid da…
39512 …dress (4 bytes resolution). Bit [23]: Wr/rd. If = 1 it is write, if = 0 it is read. Bits [27:2…
39513 …Bit [13:12]: Port. Bits [15:14]: Privilege. The decoding: 0 - VN: Virtualized NIC (Used for VF ac…
39514 …1, indicates that the timeout_attn_access_data_0 and timeout_attn_access_data_1 registers contain …
39515 …dress (4 bytes resolution). Bit [23]: Wr/rd. If = 1 it is write, if = 0 it is read. Bits [27:2…
39516 …Bit [13:12]: Port. Bits [15:14]: Privilege. The decoding: 0 - VN: Virtualized NIC (Used for VF ac…
39517 …1, indicates that the path_isolation_error_data_0 and path_isolation_error_data_1 registers contai…
39518 …1, indicates that the trace FIFO contains at least one valid data. If = …
39519 …only if the read value is 1, this FIFO has at least one valid data, and this register can be read …
39521 … 0x050070UL //Access:RW DataWidth:0x1 // If = 1, the trace fifo feat…
39522 …1, the master is enabled and its accesses are written to the trace FIFO. If = 0, the master is mas…
39523 …1 the error is enabled, access with applicable error is written to the trace FIFO. If = 0 the erro…
39524 …1 the wr/rd access is enabled, wr/rd access is written to the trace FIFO. If = 0 the wr/rd access …
39525 …1 the PF is enabled, access with the PF is written to the trace FIFO. If = 0 the PF is masked, acc…
39526 … 0x050084UL //Access:RW DataWidth:0x1 // If = 1, selects only the VF in GRC…
39527 …e FIFO. Applicable only if GRC_REG_TRACE_FIFO_VF_SEL = 1. Value of all 1s is applicable and repres…
39528 …1 the port is enabled, access with the port is written to the trace FIFO. If = 0 the port is maske…
39529 …1 the privilege is enabled, access with the privilege is written to the trace FIFO. If = 0 the pri…
39530 …1 the privilege override is enabled, access with the privilege override is written to the trace FI…
39531 …lects for each address bit if this bit is enforced. The register GRC_REG_TRACE_FIFO_ADDRESS select…
39532 …lue for each address bit. The register GRC_REG_TRACE_FIFO_ADDRESS_SEL selects for each address bit…
39533 …first 32 GRC accesses. When the FIFO is full new accesses are dropped. If = 1, keeps the last 32 G…
39535 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
39536 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
39537 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
39538 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
39544 … 0x0500ecUL //Access:RW DataWidth:0x4 // Debug only: If more than this …
39548 …_EVENT (0x1<<1) // Timeout event
39549 …RC_REG_INT_STS_0_TIMEOUT_EVENT_SHIFT 1
39557 … (0x1<<0) // This bit masks, when set, the Interrupt bit: G…
39559 … (0x1<<1) // This bit masks, when set, the Interrupt …
39560 …RC_REG_INT_MASK_0_TIMEOUT_EVENT_SHIFT 1
39561 … (0x1<<2) // This bit masks, when set, the Interrupt bit: G…
39563 … (0x1<<3) // This bit masks, when set, the Interrupt bit: G…
39565 … (0x1<<4) // This bit masks, when set, the Interrupt bit: G…
39570 …OUT_EVENT (0x1<<1) // Timeout event
39571 …RC_REG_INT_STS_WR_0_TIMEOUT_EVENT_SHIFT 1
39581 …EOUT_EVENT (0x1<<1) // Timeout event
39582 …RC_REG_INT_STS_CLR_0_TIMEOUT_EVENT_SHIFT 1
39590 … (0x1<<0) // This bit masks, when set, the Parity bit: GR…
39592 … (0x1<<1) // This bit masks, when set, the Parity bi…
39593 …RC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT 1
39596 …his bit enables a timer in the GRC block to timeout any access that does not finish within GRC_REG…
39599 …Bit [47]: Rd access. If = 1, the window is applicable for rd access. If = 0, the window is not ap…
39611 …1<<16) // Transmit packets to PHY while in MAC local loopback; when set to '1'; otherwise transmit…
39613 …cket by the PHY are Transmitted by the PHY (remote loopback); when set to '1'; otherwise transmit…
39615 …et to '0' (Reset value); the MAC transmit function is disable. When set to '1'; the MAC transmit f…
39617 … (0x1<<1) // Enable/Disable MAC receive path. When set to '0' (Reset value); the MAC rece…
39618 …MAC_REG_COMMAND_CONFIG_RX_ENA_BB_SHIFT 1
39619 …<<2) // Set MAC speed. Ignored when the register bit ENA_EXT_CONFIG is set to '1'. When the Regist…
39621 …0x1<<4) // Enable/Disable MAC promiscuous operation. When asserted (Set to '1'); all frames are re…
39623 …1'); then padding is removed from the received frame before it is transmitted to the user applicat…
39625 …1) the CRC field of received frames are transmitted to the user application. If disabled (Set to r…
39627 … (0x1<<7) // Terminate/Forward Pause Frames. If enabled (Set to '1') pause frames are f…
39629 … (0x1<<8) // Ignore Pause Frame Quanta. If enabled (Set to '1') received pause fra…
39631 … (0x1<<9) // Set MAC address on transmit. If enabled (Set to '1') the MAC overwrites…
39633 …1'; enables half duplex mode; when set to '0'; the MAC operates in full duplex mode. Ignored at et…
39635 … (0x1<<11) // This works only when runt filter is…
39637 …1] register bit is not operational (always set to 0). If cleared; disables RX FIFO overflow logic.…
39639 …X are disabled. Config registers are not affected by sw reset. Write a 0 to de-assert the sw reset.
39641 … (0x1<<14) // Corrupt Tx FCS; on underrun; when set to '1'; No FCS corruption …
39643 … (0x1<<15) // Enable GMII/MII loopback when set to '1'; normal operation w…
39645 …1<<16) // Transmit packets to PHY while in MAC local loopback; when set to '1'; otherwise transmit…
39653 …d with the register bits ETH_SPEED(1:0) and HD_ENA. When set to '1'; the Core is configured with t…
39655 … (0x1<<23) // MAC Control Frame Enable. When set to '1'; MAC Control frames…
39657 …s the frame's payload length with the Frame Length/Type field; when set to '1'(Reset value); the p…
39659 …(0x1<<25) // Enable Line Loopback i.e. MAC FIFO side loopback; when set to '1'; normal operation w…
39661 …1'; any frame received with an error is discarded in the Core and not forwarded to the Client inte…
39667 …-of-band egress flow control is enabled. When this bit is set and input pin ext_tx_flow_control is…
39671 …L //Access:RW DataWidth:0x20 // Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refe…
39672 …ccess:RW DataWidth:0x10 // Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1 r…
39673 … 0x051014UL //Access:RW DataWidth:0x10 // Defines a 16-Bit maximum frame lengt…
39674 … 0x051018UL //Access:RW DataWidth:0x10 // 16-Bit value; sets; in increment of 512 Ethernet …
39675 …fines the length of the EFM preamble between 5 and 15 Bytes. When set to 0; 1; 2; 3 or 4; the Prea…
39677 …/ Rx Flow. Setting this bit will cause the receive MAC control to detect and act on PAUSE flow con…
39679 …w. Setting this bit will allow the transmit MAC control to send PAUSE flow control frames when req…
39683 … (0x1<<2) // MAC Duplex. 0: Full Duplex Mode enabled 1: Half Duplex Mode en…
39685 … (0x1<<3) // MAC Pause Enabled in Receive. 0: MAC Pause Disabled in Receive 1: MAC Pause Enabled i…
39687 …0x1<<4) // MAC Pause Enabled in Transmit. 0: MAC Pause Disabled in Transmit 1: MAC Pause Enabled i…
39689 … Link Status Indication. Set to '0'; when link_status input is low. Set to '1'; when link_status i…
39708 …to be programmable from min of 2 bytes to the max allowable of 7 bytes; with granularity of 1 byte.
39709 …G between Back-to-Back packets. This is the IPG parameter used exclusively in Full-Duplex mode whe…
39710 …dth:0x10 // Time value sent in the Timer Field for classes in XOFF state (Unit is 512 bit-times).
39712 …onfiguration. Reset default depends on EEE_en_strap input; which if tied to 1; defaults to enabled…
39714 …the RX line and Unimac Rx FIFO is empty. By default; lpi_rx_detect is set only when whenever the L…
39718 … (0x1<<6) // When this bit is set and link is …
39720 …BB (0x1<<7) // When set to 1; enables LP_IDLE Pre…
39722 …at the end of which MAC transitions to LPI State. The decrement unit is 1 micro-second. This regis…
39723 …at the end of which MAC transitions to LPI State. The decrement unit is 1 micro-second. This regis…
39724 …1us reference pulses used by EEE timers. It specifies integer number of timer clock cycles contain…
39725 …eceives an IPG less than programmed RX IPG or less than four bytes. Sticky bit. Clears when SW wri…
39727 …I state when it receives packet for transmission. The decrement unit is 1 micro-second. This regis…
39728 …I state when it receives packet for transmission. The decrement unit is 1 micro-second. This regis…
39737 … (0x7f<<16) // Non Back-to-Back Transmit IPG part 1 (carrie…
39739 … (0x7f<<24) // Non Back-to-Back Transmit IPG pa…
39743 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
39744 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
39745 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
39746 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
39754 …_K2_E5 (0x1<<1) // TX fifo overflow
39755 …MAC_REG_INT_STS_TX_OVERFLOW_K2_E5_SHIFT 1
39757 … (0x1<<0) // This bit masks, when set, the Interrupt bit: U…
39759 … (0x1<<1) // This bit masks, when set, the Interrupt …
39760 …MAC_REG_INT_MASK_TX_OVERFLOW_K2_E5_SHIFT 1
39764 …LOW_K2_E5 (0x1<<1) // TX fifo overflow
39765 …MAC_REG_INT_STS_WR_TX_OVERFLOW_K2_E5_SHIFT 1
39769 …FLOW_K2_E5 (0x1<<1) // TX fifo overflow
39770 …MAC_REG_INT_STS_CLR_TX_OVERFLOW_K2_E5_SHIFT 1
39782 … (0x1<<0) // Set the bit 0 (Tx_Launch_en) lo…
39784 …1) // Setting this field enables the CRC corruption on the transmitted packets. The options of how…
39785 …MAC_REG_MACSEC_CNTRL_TX_CRC_CORUPT_EN_BB_SHIFT 1
39786 …ruption feature in enabled (TX_CRC_CORUPT_EN set); then in case where this bit when set; replaces …
39788 …bit is 1; IPG between pause and data frame is as per the original design; i.e.; 13B or 12B; fixed.…
39790 …:RW DataWidth:0x20 // This register contains the bits [31:0] in the 48-bit MAC address. The M…
39792 …BB (0x1<<0) // Read-only field assertion sh…
39794 …EMPTY_BB (0x1<<1) // Read-only field asserti…
39795 …MAC_REG_TS_STATUS_CNTRL_TX_TS_FIFO_EMPTY_BB_SHIFT 1
39798 …RW DataWidth:0x10 // This register contains the bits [47:32] in the 48-bit MAC address. The M…
39799 …orresponding to the preceding seq_id read from the transmit FIFO. Every 49 bit; val_bit + seq_id +…
39801 … frame with the Pause Time Field specified in rf_omac_pause_time. If this bit is cleared send a P…
39803 … frame with the Pause Time Field specified in rf_omac_pause_time. If this bit is cleared send a P…
39805 … (0x1<<18) // Pause mode 0 = Standard Pause, 1 = PFC Pause.
39809 …riority Pause Frame. Each bit in this field corresponds to a priority that should be set in a Per…
39811 … (0x1ffff<<0) // Each bit in this register represents 512 bit times independent of the port…
39815 …- skipped (unsupported) 1 - stackvlan (unsupported) 2 - carrerr (on by default) 3 - codeerr (on by…
39816 … 0x051334UL //Access:RW DataWidth:0x1 // Flush enable bit to drop out all pac…
39817 … 0x051338UL //Access:RW DataWidth:0x8 // probe address bit 7 - U/L bit 6 - GMII/XMGII …
39819 … (0x1<<0) // RXFIFO Underrun occurred. Cleared by only reset.
39821 … (0x1<<1) // RXFIFO Overrun occurred. Cleared by onl…
39822 …MAC_REG_RXFIFO_STAT_RXFIFO_OVERRUN_BB_SHIFT 1
39825 … (0x1<<0) // TXFIFO Underrun occurred. Cleared by only reset.
39827 … (0x1<<1) // TXFIFO Overrun occurred. Cleared by onl…
39828 …MAC_REG_TXFIFO_STAT_TXFIFO_OVERRUN_BB_SHIFT 1
39830 … (0x1<<0) // Enables the PPP-Tx functionality.
39832 … (0x1<<1) // Enables the PPP-Rx function…
39833 …MAC_REG_MAC_PFC_CTRL_PFC_RX_ENBL_BB_SHIFT 1
39838 …nters is in full function. Note: it is programming requirement to set this bit when PFC function i…
39846 … (0x1<<0) // This bit masks, when set, the Parity bit: MC…
39848 … 0x052200UL //Access:RW DataWidth:0x8 // Debug only: Reserved bits for …
39850 … (0x1<<0) // This bit masks, when set, the Parity bit: MC…
39852 … (0x1<<1) // This bit masks, when set, the Parity bi…
39853 …CP2_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_E5_SHIFT 1
39854 … (0x1<<2) // This bit masks, when set, the Parity bit: MC…
39856 … (0x1<<3) // This bit masks, when set, the Parity bit: MC…
39858 … (0x1<<4) // This bit masks, when set, the Parity bit: MC…
39860 … (0x1<<5) // This bit masks, when set, the Parity bit: MC…
39862 … (0x1<<6) // This bit masks, when set, the Parity bit: MC…
39864 … (0x1<<7) // This bit masks, when set, the Parity bit: MC…
39866 … (0x1<<8) // This bit masks, when set, the Parity bit: MC…
39868 … (0x1<<9) // This bit masks, when set, the Parity bit: MC…
39870 … (0x1<<10) // This bit masks, when set, the Parity bit: MC…
39872 … (0x1<<11) // This bit masks, when set, the Parity bit: MC…
39874 … (0x1<<12) // This bit masks, when set, the Parity bit: MC…
39876 … (0x1<<13) // This bit masks, when set, the Parity bit: MC…
39878 … (0x1<<14) // This bit masks, when set, the Parity bit: MC…
39880 … (0x1<<15) // This bit masks, when set, the Parity bit: MC…
39882 … (0x1<<8) // This bit masks, when set, the Parity bit: MC…
39884 … (0x1<<16) // This bit masks, when set, the Parity bit: MC…
39886 … (0x1<<0) // This bit masks, when set, the Parity bit: MC…
39888 … (0x1<<1) // This bit masks, when set, the Parity bi…
39889 …CP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT_BB_K2_SHIFT 1
39890 … (0x1<<2) // This bit masks, when set, the Parity bit: MC…
39892 … (0x1<<3) // This bit masks, when set, the Parity bit: MC…
39894 … (0x1<<4) // This bit masks, when set, the Parity bit: MC…
39896 … (0x1<<5) // This bit masks, when set, the Parity bit: MC…
39898 … (0x1<<6) // This bit masks, when set, the Parity bit: MC…
39900 … (0x1<<7) // This bit masks, when set, the Parity bit: MC…
39902 … (0x1<<9) // This bit masks, when set, the Parity bit: MC…
39904 … (0x1<<11) // This bit masks, when set, the Parity bit: MC…
39906 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
39907 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
39908 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
39909 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
39910 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
39911 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
39912 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
39913 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
39914 …1].i_mcp_scratchpad_mem_0.rf_ecc_error_connect_0 Includes 2 words of 5 bits each. The msb of each …
39915 …1].i_mcp_scratchpad_mem_0.rf_ecc_error_connect_1 Includes 2 words of 5 bits each. The msb of each …
39916 …1].i_mcp_scratchpad_mem_0.rf_ecc_error_connect_2 Includes 2 words of 5 bits each. The msb of each …
39917 …1].i_mcp_scratchpad_mem_0.rf_ecc_error_connect_3 Includes 2 words of 5 bits each. The msb of each …
39922 …009_I_ECC_EN_E5 (0x1<<1) // Enable ECC for m…
39923 …CP2_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN_E5_SHIFT 1
39932 … (0x1<<6) // Enable ECC for memory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_me…
39934 … (0x1<<7) // Enable ECC for memory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_me…
39936 … (0x1<<8) // Enable ECC for memory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_me…
39938 … (0x1<<9) // Enable ECC for memory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_me…
39942 …006_I_ECC_0_EN_BB_K2 (0x1<<1) // Enable ECC for m…
39943 …CP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_0_EN_BB_K2_SHIFT 1
39954 …_E5 (0x1<<0) // Set parity only for memory ecc inst…
39956 …_ECC_PRTY_E5 (0x1<<1) // Set parity only for memory…
39957 …CP2_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY_E5_SHIFT 1
39958 …TY_E5 (0x1<<2) // Set parity only for memory ecc inst…
39960 …TY_E5 (0x1<<3) // Set parity only for memory ecc inst…
39962 …TY_E5 (0x1<<4) // Set parity only for memory ecc inst…
39964 …TY_E5 (0x1<<5) // Set parity only for memory ecc inst…
39966 … (0x1<<6) // Set parity only for memory ecc instance mcp.gen_scratchpad_…
39968 … (0x1<<7) // Set parity only for memory ecc instance mcp.gen_scratchpad_…
39970 … (0x1<<8) // Set parity only for memory ecc instance mcp.gen_scratchpad_…
39972 … (0x1<<9) // Set parity only for memory ecc instance mcp.gen_scratchpad_…
39974 …_BB_K2 (0x1<<0) // Set parity only for memory ecc inst…
39976 …_ECC_0_PRTY_BB_K2 (0x1<<1) // Set parity only for memory…
39977 …CP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_0_PRTY_BB_K2_SHIFT 1
39978 …TY_BB_K2 (0x1<<2) // Set parity only for memory ecc inst…
39980 …TY_BB_K2 (0x1<<3) // Set parity only for memory ecc inst…
39982 …TY_BB_K2 (0x1<<4) // Set parity only for memory ecc inst…
39984 …_BB_K2 (0x1<<5) // Set parity only for memory ecc inst…
39990 …TED_0_MEM009_I_ECC_CORRECT_E5 (0x1<<1) // Record if a corr…
39991 …CP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT_E5_SHIFT 1
40000 … a correctable error occurred on memory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_me…
40002 … a correctable error occurred on memory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_me…
40004 … a correctable error occurred on memory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_me…
40006 … a correctable error occurred on memory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_me…
40010 …TED_0_MEM006_I_ECC_0_CORRECT_BB_K2 (0x1<<1) // Record if a corr…
40011 …CP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_0_CORRECT_BB_K2_SHIFT 1
40023 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
40024 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
40027 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
40028 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
40032 … (0x1<<0) // This bit masks, when set, the Parity bit: OP…
40034 … (0x1<<1) // This bit masks, when set, the Parity bi…
40035 …PTE_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2_SHIFT 1
40036 … (0x1<<2) // This bit masks, when set, the Parity bit: OP…
40038 … (0x1<<3) // This bit masks, when set, the Parity bit: OP…
40040 … (0x1<<4) // This bit masks, when set, the Parity bit: OP…
40042 … (0x1<<5) // This bit masks, when set, the Parity bit: OP…
40044 … (0x1<<6) // This bit masks, when set, the Parity bit: OP…
40046 … (0x1<<7) // This bit masks, when set, the Parity bit: OP…
40048 … (0x1<<8) // This bit masks, when set, the Parity bit: OP…
40050 … (0x1<<9) // This bit masks, when set, the Parity bit: OP…
40052 … (0x1<<10) // This bit masks, when set, the Parity bit: OP…
40056 … DORQ FIFO. When the occupancy is more than that number, local edpm_en is de-asserted. It is than …
40058 … (0x1<<0) // This bit masks, when set, the Parity bit: OP…
40061 … (0x1<<4) // This bit masks, when set, the Parity bit: PC…
40063 … (0x1<<0) // This bit masks, when set, the Parity bit: PC…
40065 … (0x1<<1) // This bit masks, when set, the Parity bi…
40066 …CIE_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_K2_E5_SHIFT 1
40067 … (0x1<<7) // This bit masks, when set, the Parity bit: PC…
40069 … (0x1<<2) // This bit masks, when set, the Parity bit: PC…
40071 … (0x1<<3) // This bit masks, when set, the Parity bit: PC…
40073 … (0x1<<4) // This bit masks, when set, the Parity bit: PC…
40075 … (0x1<<16) // This bit masks, when set, the Parity bit: PC…
40077 … (0x1<<5) // This bit masks, when set, the Parity bit: PC…
40079 … (0x1<<6) // This bit masks, when set, the Parity bit: PC…
40081 … (0x1<<6) // This bit masks, when set, the Parity bit: PC…
40083 … (0x1<<7) // This bit masks, when set, the Parity bit: PC…
40085 … (0x1<<0) // This bit masks, when set, the Parity bit: PC…
40087 … (0x1<<1) // This bit masks, when set, the Parity bi…
40088 …CIE_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_BB_SHIFT 1
40089 … (0x1<<2) // This bit masks, when set, the Parity bit: PC…
40091 … (0x1<<3) // This bit masks, when set, the Parity bit: PC…
40093 … (0x1<<5) // This bit masks, when set, the Parity bit: PC…
40095 … (0x1<<8) // This bit masks, when set, the Parity bit: PC…
40097 … (0x1<<9) // This bit masks, when set, the Parity bit: PC…
40099 … (0x1<<10) // This bit masks, when set, the Parity bit: PC…
40101 … (0x1<<11) // This bit masks, when set, the Parity bit: PC…
40103 … (0x1<<12) // This bit masks, when set, the Parity bit: PC…
40105 … (0x1<<13) // This bit masks, when set, the Parity bit: PC…
40107 … (0x1<<14) // This bit masks, when set, the Parity bit: PC…
40109 … (0x1<<15) // This bit masks, when set, the Parity bit: PC…
40116 …004_I_ECC_EN_K2_E5 (0x1<<1) // Enable ECC for m…
40117 …CIE_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_K2_E5_SHIFT 1
40120 …005_I_ECC_EN_BB (0x1<<1) // Enable ECC for m…
40121 …CIE_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_BB_SHIFT 1
40129 …_BB (0x1<<4) // Set parity only for memory ecc inst…
40131 …_K2_E5 (0x1<<0) // Set parity only for memory ecc inst…
40133 …_ECC_PRTY_K2_E5 (0x1<<1) // Set parity only for memory…
40134 …CIE_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_K2_E5_SHIFT 1
40135 …_BB (0x1<<0) // Set parity only for memory ecc inst…
40137 …_ECC_PRTY_BB (0x1<<1) // Set parity only for memory…
40138 …CIE_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_BB_SHIFT 1
40139 …_BB (0x1<<2) // Set parity only for memory ecc inst…
40141 …_BB (0x1<<3) // Set parity only for memory ecc inst…
40143 …_BB (0x1<<5) // Set parity only for memory ecc inst…
40150 …TED_0_MEM004_I_ECC_CORRECT_K2_E5 (0x1<<1) // Record if a corr…
40151 …CIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_K2_E5_SHIFT 1
40154 …TED_0_MEM005_I_ECC_CORRECT_BB (0x1<<1) // Record if a corr…
40155 …CIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_BB_SHIFT 1
40173 …ER_ALLOW_GEN3_BB (0x1<<1) // Set to allow Gen…
40174 …CIE_REG_PCIE_CONTROL_BITS_USER_ALLOW_GEN3_BB_SHIFT 1
40175 …P_L1SUB_BB (0x1<<5) // Stop L1Sub control bit.
40178 …L0 (0x1<<1) // Link in L0 Status bit.
40179 …CIE_REG_PCIE_STATUS_BITS_LINK_IN_L0_SHIFT 1
40180 …23 (0x1<<4) // Link in L23 Status bit.
40184 …11_BB (0x1<<2) // Link in L11 Status bit.
40186 …12_BB (0x1<<3) // Link in L12 Status bit.
40190 …L_LOCK_BB (0x1<<8) // PLL Lock status bit.
40195 …RTBL_TL_PERR (0x1<<1) // Force Parity Err…
40196 …CIE_REG_PCIE_DEBUG_BITS_TIMERTBL_TL_PERR_SHIFT 1
40200 …T_RESET_CONTROL_SOFT_WAKE_REF_RST_N_K2_E5 (0x1<<1) //
40201 …CIE_REG_SOFT_RESET_CONTROL_SOFT_WAKE_REF_RST_N_K2_E5_SHIFT 1
40215 … (0x1<<1) // This bit is set by firmware when host system sets OBFF Enable to 2'b1…
40216 …CIE_REG_OBFF_CONTROL_1_OBFFSIGNALENABLE_K2_E5_SHIFT 1
40217 … (0x1<<2) // Set to 1 to indicate that the pcore WakeIn input is active high. Thi…
40219 …RCING_K2_E5 (0x1<<3) // Set to 1 to prevent incoming …
40231 …F_STATUS_1_RXOBFFCODE_K2_E5 (0xf<<1) //
40232 …CIE_REG_OBFF_STATUS_1_RXOBFFCODE_K2_E5_SHIFT 1
40258 … 0x054224UL //Access:RW DataWidth:0x20 // 32 bit value to be sent in…
40259 … 0x054228UL //Access:RW DataWidth:0x20 // 32 bit value to be sent in…
40266 …L_TX_LANE_FLIP_EN_K2_E5 (0x1<<1) // Performs manual …
40267 …CIE_REG_SII_LANE_FLIP_CONTROL_TX_LANE_FLIP_EN_K2_E5_SHIFT 1
40272 …DELAY_ENABLE_K2_E5 (0x1<<1) // When set to 1, HW delay a…
40273 …CIE_REG_HW_INIT_CONFIG_HOT_RESET_PRE_DELAY_ENABLE_K2_E5_SHIFT 1
40278 …PHY_CLK_REQ_N_K2_E5 (0x1<<1) // Acknowledge from…
40279 …CIE_REG_CLK_RST_APM_CONTROL_PHY_CLK_REQ_N_K2_E5_SHIFT 1
40285 …LK_REQ_N_K2_E5 (0x1<<1) // Clock Turnoff re…
40286 …CIE_REG_CLK_RST_APM_STATUS_CLK_REQ_N_K2_E5_SHIFT 1
40294 … (0x1<<1) // Indicates that the core should update the PTM Requester Context and Clock now. FW m…
40295 …CIE_REG_PTM_CONTROL_PTM_MANUAL_UPDATE_PULSE_K2_E5_SHIFT 1
40299 …_STATUS_PTM_CLOCK_UPDATED_K2_E5 (0x1<<1) //
40300 …CIE_REG_PTM_STATUS_PTM_CLOCK_UPDATED_K2_E5_SHIFT 1
40310 …ET_STATUS_1_SQUELCH_RST_N_K2_E5 (0x1<<1) //
40311 …CIE_REG_RESET_STATUS_1_SQUELCH_RST_N_K2_E5_SHIFT 1
40327 …K_DEBUG_STATUS_RDLH_LINK_UP_K2_E5 (0x1<<1) //
40328 …CIE_REG_LINK_DEBUG_STATUS_RDLH_LINK_UP_K2_E5_SHIFT 1
40331 …vel indicating that the receive queues contain TLP header/data.There is a 1 bit indication for eac…
40337 … (0x1<<17) // Autonomous speed disable. Used in downstream ports only.
40342 …MSG_UNLOCK_K2_E5 (0x1<<16) // One-cycle pulse that indi…
40344 …TURNOFF_K2_E5 (0x1<<17) // One-clock-cycle pulse that i…
40349 … to wake up the PMC state machine from a D1, D2 or D3 power state. Upon wake-up, the core sends a …
40352 … (0xffff<<0) // PME Status bit from the PMCSR. There is 1 bit of p…
40357 …_E5 (0x1<<0) // WARNING: this bit should not be used …
40359 … (0xffff<<1) // PME Enable bit in the PMCSR. There is 1 …
40360 …CIE_REG_SII_TRANSMIT_CONTROL_PM_PME_EN_K2_E5_SHIFT 1
40368 … (0xffff<<0) // This is the value of the No Soft Reset bit in the Power Manage…
40373 … (0xffff<<0) // Auxiliary Power Enable bit in the Device Control register. There is 1 …
40377 …taWidth:0x2 // Controls the start/end of time based analysis. You must only set the pins to the…
40378 …L //Access:R DataWidth:0x20 // State of selected internal signals, for debugging purposes only
40379 …L //Access:R DataWidth:0x20 // State of selected internal signals, for debugging purposes only
40415 … 0x054328UL //Access:R DataWidth:0x5 // pm_dev_num[4:0]- Device number
40416 … 0x05432cUL //Access:R DataWidth:0x8 // pm_bus_num[7:0]- Bus Number
40421 … 0x054340UL //Access:RW DataWidth:0x15 // Power Budget Table entry 1
40430 …x054364UL //Access:RW DataWidth:0x4 // If 0 or 1, trigger on first occurrence. If greater tha…
40450 … 0x0543b4UL //Access:RC DataWidth:0x1 // Is set to 1 if at least 1 MSIX synchron…
40454 …TECT_K2_E5 (0x1<<1) // Data Link Down d…
40455 …CIE_REG_INT_STS_LINK_DOWN_DETECT_K2_E5_SHIFT 1
40472 … (0x1<<10) // Do not use -- keep mask bit set to 1.
40478 … (0x1<<13) // Non-Fatal Error Message s…
40484 … (0x1<<16) // Vendor-Defined Message recei…
40487 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
40489 … (0x1<<1) // This bit masks, when set, the Interrupt …
40490 …CIE_REG_INT_MASK_LINK_DOWN_DETECT_K2_E5_SHIFT 1
40491 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
40493 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
40495 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
40497 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
40499 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
40501 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
40503 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
40505 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
40507 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
40509 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
40511 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
40513 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
40515 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
40517 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
40519 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
40524 …_DETECT_K2_E5 (0x1<<1) // Data Link Down d…
40525 …CIE_REG_INT_STS_WR_LINK_DOWN_DETECT_K2_E5_SHIFT 1
40542 … (0x1<<10) // Do not use -- keep mask bit set to 1.
40548 …E5 (0x1<<13) // Non-Fatal Error Message s…
40554 … (0x1<<16) // Vendor-Defined Message recei…
40559 …N_DETECT_K2_E5 (0x1<<1) // Data Link Down d…
40560 …CIE_REG_INT_STS_CLR_LINK_DOWN_DETECT_K2_E5_SHIFT 1
40577 … (0x1<<10) // Do not use -- keep mask bit set to 1.
40583 …_E5 (0x1<<13) // Non-Fatal Error Message s…
40589 … (0x1<<16) // Vendor-Defined Message recei…
40592 … (0x1<<0) // This bit masks, when set, the Parity bit: PC…
40594 … (0x1<<1) // This bit masks, when set, the Parity bi…
40595 …CIE_REG_PRTY_MASK_APP_PARITY_ERRS_1_K2_E5_SHIFT 1
40596 … (0x1<<2) // This bit masks, when set, the Parity bit: PC…
40603 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
40604 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
40605 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
40606 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
40608 …_E5 (0x1<<0) // Power-on reset occurred.
40610 …REF_RST_2_K2_E5 (0x1<<1) // Wake Ref reset o…
40611 …CIE_REG_RESET_STATUS_2_WAKE_REF_RST_2_K2_E5_SHIFT 1
40618 …_2_K2_E5 (0x1<<5) // Non-sticky register reset…
40630 …_STATUS_REG_SPARE_11_2_K2_E5 (0x1<<11) // Spare status bit
40632 …_STATUS_REG_SPARE_12_2_K2_E5 (0x1<<12) // Spare status bit
40634 …_STATUS_REG_SPARE_13_2_K2_E5 (0x1<<13) // Spare status bit
40636 …_STATUS_REG_SPARE_14_2_K2_E5 (0x1<<14) // Spare status bit
40638 …_STATUS_REG_SPARE_15_2_K2_E5 (0x1<<15) // Spare status bit
40640 …(0x1<<16) // Soft power-on reset occurred. NOTE: This bit is unreliable for indication of a soft p…
40650 …2_K2_E5 (0x1<<21) // Soft non-sticky register reset…
40656 …:0x18 // Corresponding bits of Reset Status Register 2 will be cleared for bits written with a 1.
40658 … (0x1<<3) // This bit masks, when set, the Parity bit: PX…
40660 … (0x1<<0) // This bit masks, when set, the Parity bit: PX…
40662 … (0x1<<1) // This bit masks, when set, the Parity bi…
40663 …XPREQBUS_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_E5_SHIFT 1
40664 … (0x1<<13) // This bit masks, when set, the Parity bit: PX…
40666 … (0x1<<2) // This bit masks, when set, the Parity bit: PX…
40668 … (0x1<<4) // This bit masks, when set, the Parity bit: PX…
40670 … (0x1<<3) // This bit masks, when set, the Parity bit: PX…
40672 … (0x1<<4) // This bit masks, when set, the Parity bit: PX…
40674 … (0x1<<5) // This bit masks, when set, the Parity bit: PX…
40676 … (0x1<<6) // This bit masks, when set, the Parity bit: PX…
40678 … (0x1<<7) // This bit masks, when set, the Parity bit: PX…
40680 … (0x1<<2) // This bit masks, when set, the Parity bit: PX…
40682 … (0x1<<8) // This bit masks, when set, the Parity bit: PX…
40684 … (0x1<<8) // This bit masks, when set, the Parity bit: PX…
40686 … (0x1<<9) // This bit masks, when set, the Parity bit: PX…
40688 … (0x1<<10) // This bit masks, when set, the Parity bit: PX…
40690 … (0x1<<11) // This bit masks, when set, the Parity bit: PX…
40692 … (0x1<<12) // This bit masks, when set, the Parity bit: PX…
40694 … (0x1<<13) // This bit masks, when set, the Parity bit: PX…
40696 … (0x1<<14) // This bit masks, when set, the Parity bit: PX…
40698 … (0x1<<15) // This bit masks, when set, the Parity bit: PX…
40700 … (0x1<<16) // This bit masks, when set, the Parity bit: PX…
40702 … (0x1<<17) // This bit masks, when set, the Parity bit: PX…
40704 … (0x1<<18) // This bit masks, when set, the Parity bit: PX…
40706 … (0x1<<19) // This bit masks, when set, the Parity bit: PX…
40708 … (0x1<<0) // This bit masks, when set, the Parity bit: PX…
40710 … (0x1<<20) // This bit masks, when set, the Parity bit: PX…
40712 … (0x1<<9) // This bit masks, when set, the Parity bit: PX…
40714 … (0x1<<21) // This bit masks, when set, the Parity bit: PX…
40718 … // Debug only. Initialises specific states and statuses. To initialise the state - write 1 int…
40719 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
40723 … (0x1<<1) // Doorbell drop.
40724 …ORQ_REG_INT_STS_DB_DROP_SHIFT 1
40737 … (0x1<<8) // CFC load request FIFO under-run
40741 …-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or b) Non-fir…
40746 … (0x1<<0) // This bit masks, when set, the Interrupt bit: D…
40748 … (0x1<<1) // This bit masks, when set, the Interrupt …
40749 …ORQ_REG_INT_MASK_DB_DROP_SHIFT 1
40750 … (0x1<<2) // This bit masks, when set, the Interrupt bit: D…
40752 … (0x1<<3) // This bit masks, when set, the Interrupt bit: D…
40754 … (0x1<<4) // This bit masks, when set, the Interrupt bit: D…
40756 … (0x1<<5) // This bit masks, when set, the Interrupt bit: D…
40758 … (0x1<<6) // This bit masks, when set, the Interrupt bit: D…
40760 … (0x1<<7) // This bit masks, when set, the Interrupt bit: D…
40762 … (0x1<<8) // This bit masks, when set, the Interrupt bit: D…
40764 … (0x1<<9) // This bit masks, when set, the Interrupt bit: D…
40766 … (0x1<<10) // This bit masks, when set, the Interrupt bit: D…
40768 … (0x1<<11) // This bit masks, when set, the Interrupt bit: D…
40773 …P (0x1<<1) // Doorbell drop.
40774 …ORQ_REG_INT_STS_WR_DB_DROP_SHIFT 1
40787 …RR (0x1<<8) // CFC load request FIFO under-run
40791 …-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or b) Non-fir…
40798 …OP (0x1<<1) // Doorbell drop.
40799 …ORQ_REG_INT_STS_CLR_DB_DROP_SHIFT 1
40812 …ERR (0x1<<8) // CFC load request FIFO under-run
40816 …-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or b) Non-fir…
40821 … (0x1<<0) // This bit masks, when set, the Parity bit: DO…
40824 … (0x1<<0) // This bit masks, when set, the Parity bit: DO…
40826 … (0x1<<1) // This bit masks, when set, the Parity bi…
40827 …ORQ_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_E5_SHIFT 1
40828 … (0x1<<2) // This bit masks, when set, the Parity bit: DO…
40830 … (0x1<<1) // This bit masks, when set, the Parity bi…
40831 …ORQ_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT 1
40832 … (0x1<<3) // This bit masks, when set, the Parity bit: DO…
40834 … (0x1<<4) // This bit masks, when set, the Parity bit: DO…
40836 … (0x1<<5) // This bit masks, when set, the Parity bit: DO…
40838 … (0x1<<6) // This bit masks, when set, the Parity bit: DO…
40840 … (0x1<<7) // This bit masks, when set, the Parity bit: DO…
40842 … (0x1<<2) // This bit masks, when set, the Parity bit: DO…
40844 … (0x1<<8) // This bit masks, when set, the Parity bit: DO…
40846 … (0x1<<3) // This bit masks, when set, the Parity bit: DO…
40848 … (0x1<<9) // This bit masks, when set, the Parity bit: DO…
40850 … (0x1<<4) // This bit masks, when set, the Parity bit: DO…
40852 … (0x1<<10) // This bit masks, when set, the Parity bit: DO…
40854 … (0x1<<5) // This bit masks, when set, the Parity bit: DO…
40856 … (0x1<<11) // This bit masks, when set, the Parity bit: DO…
40859 … 0x100214UL //Access:RW DataWidth:0x1 // Set parity only for memory ecc inst…
40862 …in units of 4KB from the start of the doorbell space to the start of region 1 (PWM region). This i…
40863 …in units of 4KB from the start of the doorbell space to the start of region 1 (PWM region). This i…
40864 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 0…
40865 …gister, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 1. This is p…
40866 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 2…
40867 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 3…
40868 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 4…
40869 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 5…
40870 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 6…
40871 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 7…
40872 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 0…
40873 …gister, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 1. This is p…
40874 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 2…
40875 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 3…
40876 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 4…
40877 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 5…
40878 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 6…
40879 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 7…
40880 …connection doorbell space footprint in DWORD-s. I.e. value of 0 means 1 DWord (4B) per connection,…
40881 …connection doorbell space footprint in DWORD-s. I.e. value of 0 means 1 DWord (4B) per connection,…
40882 …. This is the LOG2 of PWM page size in units of 4KB, i.e. 0 means 4KB page, 1 means 8KB pages and …
40883 …. This is the LOG2 of PWM page size in units of 4KB, i.e. 0 means 4KB page, 1 means 8KB pages and …
40886 … 0x100460UL //Access:RW DataWidth:0x2 // Target value used in DEMS mode for DEMS = 1.
40887 … DataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 1. Bit 2 of AggValSel is always 1 in D…
40888 …468UL //Access:RW DataWidth:0x2 // AggCmd used in DEMS mode for DEMS = 1. Reset value = SET_A…
40890 …ataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 2. Bit 2 of AggValSel is always 1 in DEM…
40893 …ataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 3. Bit 2 of AggValSel is always 1 in DEM…
40896 …ataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 4. Bit 2 of AggValSel is always 1 in DEM…
40899 …ataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 5. Bit 2 of AggValSel is always 1 in DEM…
40902 …ataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 6. Bit 2 of AggValSel is always 1 in DEM…
40905 …ataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 7. Bit 2 of AggValSel is always 1 in DEM…
40907 … 0x1004f4UL //Access:RW DataWidth:0x2 // AGG command value in PWM non-DPM mode.
40910 …n 2 port mode it is equal to 0 for all PF-s. In 4 port mode, it is equal to 0 for even PF-s and to…
40915 …ccess:RW DataWidth:0x1 // Enable DPM doorbells for all this PF child VF-s. In case not set th…
40929 … 0x100810UL //Access:RW DataWidth:0x1 // If set then CCFC mini-cache is enabled.
40931 …and first DPM doorbell appears it is truncated to one entry and aborted; non-first doorbell is dro…
40932 … doorbell appears it is truncated to one entry and DpmAbort flag is set; non-first doorbell is sil…
40933 …x100824UL //Access:RW DataWidth:0x1 // If set, then XCM bypass enable bit will be masked (XCM…
40934 …0x100828UL //Access:RW DataWidth:0x1 // If set, then QM bypass enable bit will be masked (con…
40935 …x10082cUL //Access:RW DataWidth:0x1 // If set, then PBF bypass enable bit will be masked (con…
40936 …0x100830UL //Access:RW DataWidth:0x1 // If set, then QM bypass enable bit will be masked (con…
40938 …icates which ExistInQm bits are taken into account in the EDPM check. If a bit equals 0 then the c…
40939 … 0x10083cUL //Access:RW DataWidth:0x1 // If 1, then full is assert…
40940 …. If DORQ FIFO fill level is equal or greater than it and dq_pxp_full_en is 1, then full is assert…
40942 … 0x100884UL //Access:RW DataWidth:0x10 // Tag 1 Ethertype used for p…
40946 …ize of the Tag 1 used for packet generation in RDMA EDPM mode not including Ethertype itself. 0 - …
40947 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40948 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40949 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40952 … 0x1008acUL //Access:RW DataWidth:0x20 // Enable bit per each RoCE Opcode 5 LSB-s. N-th bit …
40953 …Access:RW DataWidth:0x1 // If 0 - the RoCE CRC-32 final calculation result isn't byte swapped…
40954 …1 � External VLAN Id only override 2 � External VLAN Id + PCP override 3 � Internal VLAN Id only o…
40955 …1 � External VLAN Id only override 2 � External VLAN Id + PCP override 3 � Internal VLAN Id only o…
40956 …1 � External VLAN Id only override 2 � External VLAN Id + PCP override 3 � Internal VLAN Id only o…
40957 …1 � External VLAN Id only override 2 � External VLAN Id + PCP override 3 � Internal VLAN Id only o…
40958 … 0x1008c4UL //Access:RW DataWidth:0x4 // The priority value and DEI bit of RoCE frames per …
40961 …ype used for RoCE packet generation in EDPM mode. addr=0 � plain ROCE; addr=1 � RROCE (ROCEv2)/iWA…
40969 … 0x100918UL //Access:RW DataWidth:0x2 // TPH Hint value in case of non-inline L2 EDPM.
40970 … 0x10091cUL //Access:RW DataWidth:0x3 // ATC attribute value of non-inline L2 EDPM.
40972 … 0x100924UL //Access:RW DataWidth:0xe // Maximum non-inline L2 EDPM PktSiz…
40973 … 0x100928UL //Access:RW DataWidth:0x8 // The maximum number of WORD-s which the PBF may a…
40974 … 0x10092cUL //Access:RW DataWidth:0x1 // Set to 1 if IP over NGE heade…
40975 … 0x100930UL //Access:RW DataWidth:0x1 // Set to 1 if Ethernet over NGE…
40980 …DataWidth:0xb // Counter of DORQ FIFO entries used by corresponding PF or any of its child VF-s.
40982 … number of DORQ FIFO entries used by corresponding PF or any of its child VF-s. This is a per PF c…
40987 …h:0x14 // A bit mask per doorbell drop reason. If a bit is set (1), then corresponding drop reas…
40988 …ng CFC load requests. The freeze mode will remain until auto_drop_rel (Write Only) register is set.
40990 …09e8UL //Access:W DataWidth:0x1 // Release the freeze mode set by auto_freeze_en. Write only.
40991 …FO is not full anymore. The drop mode will remain until auto_drop_rel (Write Only) register is set.
40992 …de is active and all doorbells are dropped at the entrance to DORQ FIFO. De-asserted when auto_di…
40993 … 0x1009f4UL //Access:W DataWidth:0x1 // Releases the auto_drop mode. Write only.
40995 … 0x1009fcUL //Access:R DataWidth:0x20 // Accounts for any non-DPM doorbell or first…
41001 … 0x100a14UL //Access:R DataWidth:0x5 // Debug only: read from DORQ FIF…
41003 …0 // Stores the details of the first dropped doorbell after logging was re-armed by db_drop_deta…
41004 …-armed by db_drop_details_rel. The following details of the transaction will be recorded: Doorbell…
41005 …7 // Stores the details of the first dropped doorbell after logging was re-armed by db_drop_deta…
41006 …Width:0x1 // Clears db_drop_details and makes it ready for the next details capture. Write only.
41007 …bit per reason). It is reset on write to db_drop_details_rel. 0 - Size of the data is not equal to…
41013 …- DPM doorbell and rewind configuration of DPM timer (dpm_timeout) is 0; 1 - PF DPM doorbell and i…
41014 …idth:0x1 // Clears db_abort_details and makes it ready for the next details capture. Write only.
41015 …bit per reason). It is reset on write to db_abort_details_rel. 0 - DPM doorbell and rewind configu…
41027 …Only first DPM doorbells, which are silently dropped or early aborted will be considered. The incr…
41028 …on FIFO pop. Only silent drops and aborts that can be distinguished at the moment of DORQ FIFO pop…
41032 …only: In case of LCID validation error or load error, the current value of the single entry in the…
41034 …only: CFC Response error in case mini-cache was used. 36 - CDU Validation Error; 35 - CFC Load Can…
41039 …Width:0x1 // comment="Selects IEDPM payload endianity. 0 - little endian (lsB first); 1 - big e…
41045 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
41046 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
41047 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
41048 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
41053 …- DPM FSM state [194:192] - DbAggValSel [191:190] - DbAggCmd [189:182] - DbAggFlgCmd [181] - IEDPM…
41056 …/ 1) Debug read access to WQE buffer. 2) Initialization write access: write all the addresses modu…
41058 …1) Debug read access to WQE buffer. 2) Initialization write access: write all the addresses modulo…
41060 … value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of ICID range 0.
41061 … value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of ICID range 1.
41063 … 0x10280cUL //Access:RW DataWidth:0x4 // Maps range 1 to connection type.
41064 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of range 2. This is …
41065 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of range 3. This is …
41066 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of range 4. This is …
41067 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of range 5. This is …
41068 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of range 2. This is …
41069 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of range 3. This is …
41070 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of range 4. This is …
41071 …e in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of range 5. This is …
41080 …cates which ExistInQm bits are taken into account in the IEDPM check. If a bit equals 0 then the c…
41087 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41088 …used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for RDMA doorbell. P…
41089 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41090 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41091 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41092 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41093 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41094 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41095 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41096 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41097 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41098 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41099 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41100 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41101 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41102 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41104 …lect which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per connection type 1.
41121 …//Access:RW DataWidth:0x1 // QM Bypass mode is enabled for XCM messages for connection type 1.
41122 …th:0x1 // QM Bypass mode is enabled for XCM messages for connection type 1. Per connection type.
41145 …ccess:RW DataWidth:0x1 // Indicates whether DPI validation is supported for connection type 1.
41146 …0x1 // Indicates whether DPI validation is supported for connection type 1. Per connection type.
41169 …UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell for connection type 1.
41170 …UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell for connection type 1.
41193 …text to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 1.
41194 …text to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 1.
41217 … 0x100618UL //Access:RW DataWidth:0x8 // Enable for XCM counter flag command for connection 1.
41218 … 0x1029ecUL //Access:RW DataWidth:0x8 // Enable for XCM counter flag command for connection 1.
41241 … 0x100638UL //Access:RW DataWidth:0x8 // Enable for TCM counter flag command for connection 1.
41242 … 0x102a2cUL //Access:RW DataWidth:0x8 // Enable for TCM counter flag command for connection 1.
41265 … 0x100658UL //Access:RW DataWidth:0x8 // Enable for UCM counter flag command for connection 1.
41266 … 0x102a6cUL //Access:RW DataWidth:0x8 // Enable for UCM counter flag command for connection 1.
41289 …0678UL //Access:RW DataWidth:0x8 // Enable for XCM aggregation value command for connection 1.
41290 …2aacUL //Access:RW DataWidth:0x8 // Enable for XCM aggregation value command for connection 1.
41313 …0698UL //Access:RW DataWidth:0x8 // Enable for TCM aggregation value command for connection 1.
41314 …2aecUL //Access:RW DataWidth:0x8 // Enable for TCM aggregation value command for connection 1.
41337 …06b8UL //Access:RW DataWidth:0x8 // Enable for UCM aggregation value command for connection 1.
41338 …2b2cUL //Access:RW DataWidth:0x8 // Enable for UCM aggregation value command for connection 1.
41360 … 0x102b6cUL //Access:RW DataWidth:0x20 // Used to set TCP RTC. Debug only.
41364 …Access:RW DataWidth:0x1 // If 0 - the iWARP CRC-32 final calculation result isn't byte swappe…
41365 … 0x102b80UL //Access:RW DataWidth:0x20 // Enable bit per each iWARP Opcode 5 LSB-s. N-th bit…
41366 … 0x102b84UL //Access:RW DataWidth:0x4 // The priority value and DEI bit in external VLAN TA…
41367 … 0x102b88UL //Access:RW DataWidth:0x4 // The priority value and DEI bit in external VLAN TA…
41368 … 0x102b8cUL //Access:RW DataWidth:0x4 // The priority value and DEI bit in internal VLAN TA…
41369 … 0x102b90UL //Access:RW DataWidth:0x4 // The priority value and DEI bit internal VLAN TAG o…
41374 …ataWidth:0x4 // Enable special flag indications to affect RDMA RoCE EDPM. Enables when set to 1.
41375 …taWidth:0x4 // Enable special flag indications to affect RDMA iWARP EDPM. Enables when set to 1.
41376 …:RW DataWidth:0x4 // Enable special flag indications to affect L2 EDPM. Enables when set to 1.
41377 …cates which ExistInQm bits are taken into account in RoCE EDPM check. If a bit equals 0 then the c…
41378 …ates which ExistInQm bits are taken into account in iWARP EDPM check. If a bit equals 0 then the c…
41379 …dicates which ExistInQm bits are taken into account in L2 EDPM check. If a bit equals 0 then the c…
41380 …the transaction will be recorded: Doorbell DPM type. 0 - Legacy 1 - RDMA 2 - L2 Inline 3 - L2 Non-…
41385 …- First DPM doorbell does not match DPM global start conditions at CFC load response for Internal …
41386 …h:0x1 // Clears iedpm_abort_details and makes it ready for the next details capture. Write only.
41387 …bit per reason). It is reset on write to db_abort_details_rel. 0 - First DPM doorbell does not mat…
41388 …-armed by iedpm_drop_details_rel. The following details of the transaction will be recorded: IEDPM…
41389 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41390 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41391 …gging was re-armed by iedpm_drop_details_rel. The following details of the transaction will be rec…
41392 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41393 …th:0x1 // Clears iedpm_drop_details and makes it ready for the next details capture. Write only.
41394 …bit per reason). It is reset on write to iedpm_drop_details_rel. 4 - First QWord (offset 0) arives…
41395 …h:0x5 // A bit mask per doorbell drop reason. If a bit is set (1), then corresponding drop reas…
41410 …ty type in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 1.
41426 …ve flag in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 1.
41442 …ffinity in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 1.
41459 … 0x108000UL //Access:R DataWidth:0x20 // Debug only: Read access to DQ …
41461 …bit resets the appropriate memory. When the memory reset finished the appropriate bit is cleared. …
41463 …// If enabled the IGU forwards write/read requests to the TPH interface. 1 - enabled; 0 - disabled.
41465 … (0x1<<1) // If enabled the IGU allows to VF to send cleanup commands on the int…
41466 …GU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN_SHIFT 1
41467 …the IGU allows bypass mode of the rate limiter when the system is empty. 1 - enabled; 0 - disabled.
41469 …redit. The max number of outstanding messages to the PXP request. The value can be one or two only.
41473 … 0x18006cUL //Access:R DataWidth:0x20 // Provides read-only access to the BIST…
41480 …OR_ERR (0x1<<1) // Debug FIFO error…
41481 …GU_REG_INT_STS_CTRL_FIFO_ERROR_ERR_SHIFT 1
41486 … (0x1<<4) // VFID bit is set and the command is to attention bi…
41501 … (0x1<<0) // This bit masks, when set, the Interrupt bit: I…
41503 … (0x1<<1) // This bit masks, when set, the Interrupt …
41504 …GU_REG_INT_MASK_CTRL_FIFO_ERROR_ERR_SHIFT 1
41505 … (0x1<<2) // This bit masks, when set, the Interrupt bit: I…
41507 … (0x1<<3) // This bit masks, when set, the Interrupt bit: I…
41509 … (0x1<<4) // This bit masks, when set, the Interrupt bit: I…
41511 … (0x1<<5) // This bit masks, when set, the Interrupt bit: I…
41513 … (0x1<<6) // This bit masks, when set, the Interrupt bit: I…
41515 … (0x1<<7) // This bit masks, when set, the Interrupt bit: I…
41517 … (0x1<<8) // This bit masks, when set, the Interrupt bit: I…
41519 … (0x1<<9) // This bit masks, when set, the Interrupt bit: I…
41521 … (0x1<<10) // This bit masks, when set, the Interrupt bit: I…
41526 …ERROR_ERR (0x1<<1) // Debug FIFO error…
41527 …GU_REG_INT_STS_WR_CTRL_FIFO_ERROR_ERR_SHIFT 1
41532 … (0x1<<4) // VFID bit is set and the command is to attention bi…
41549 …_ERROR_ERR (0x1<<1) // Debug FIFO error…
41550 …GU_REG_INT_STS_CLR_CTRL_FIFO_ERROR_ERR_SHIFT 1
41555 … (0x1<<4) // VFID bit is set and the command is to attention bi…
41570 … (0x1<<0) // This bit masks, when set, the Parity bit: IG…
41573 … (0x1<<0) // This bit masks, when set, the Parity bit: IG…
41575 … (0x1<<6) // This bit masks, when set, the Parity bit: IG…
41577 … (0x1<<1) // This bit masks, when set, the Parity bi…
41578 …GU_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_E5_SHIFT 1
41579 … (0x1<<7) // This bit masks, when set, the Parity bit: IG…
41581 … (0x1<<2) // This bit masks, when set, the Parity bit: IG…
41583 … (0x1<<8) // This bit masks, when set, the Parity bit: IG…
41585 … (0x1<<3) // This bit masks, when set, the Parity bit: IG…
41587 … (0x1<<9) // This bit masks, when set, the Parity bit: IG…
41589 … (0x1<<4) // This bit masks, when set, the Parity bit: IG…
41591 … (0x1<<10) // This bit masks, when set, the Parity bit: IG…
41593 … (0x1<<5) // This bit masks, when set, the Parity bit: IG…
41595 … (0x1<<11) // This bit masks, when set, the Parity bit: IG…
41597 … (0x1<<6) // This bit masks, when set, the Parity bit: IG…
41599 … (0x1<<7) // This bit masks, when set, the Parity bit: IG…
41601 … (0x1<<13) // This bit masks, when set, the Parity bit: IG…
41603 … (0x1<<8) // This bit masks, when set, the Parity bit: IG…
41605 … (0x1<<19) // This bit masks, when set, the Parity bit: IG…
41607 … (0x1<<9) // This bit masks, when set, the Parity bit: IG…
41609 … (0x1<<19) // This bit masks, when set, the Parity bit: IG…
41611 … (0x1<<10) // This bit masks, when set, the Parity bit: IG…
41613 … (0x1<<11) // This bit masks, when set, the Parity bit: IG…
41615 … (0x1<<12) // This bit masks, when set, the Parity bit: IG…
41617 … (0x1<<13) // This bit masks, when set, the Parity bit: IG…
41619 … (0x1<<14) // This bit masks, when set, the Parity bit: IG…
41621 … (0x1<<15) // This bit masks, when set, the Parity bit: IG…
41623 … (0x1<<26) // This bit masks, when set, the Parity bit: IG…
41625 … (0x1<<22) // This bit masks, when set, the Parity bit: IG…
41627 … (0x1<<16) // This bit masks, when set, the Parity bit: IG…
41629 … (0x1<<27) // This bit masks, when set, the Parity bit: IG…
41631 … (0x1<<23) // This bit masks, when set, the Parity bit: IG…
41633 … (0x1<<17) // This bit masks, when set, the Parity bit: IG…
41635 … (0x1<<28) // This bit masks, when set, the Parity bit: IG…
41637 … (0x1<<24) // This bit masks, when set, the Parity bit: IG…
41639 … (0x1<<18) // This bit masks, when set, the Parity bit: IG…
41641 … (0x1<<26) // This bit masks, when set, the Parity bit: IG…
41643 … (0x1<<19) // This bit masks, when set, the Parity bit: IG…
41645 … (0x1<<20) // This bit masks, when set, the Parity bit: IG…
41647 … (0x1<<21) // This bit masks, when set, the Parity bit: IG…
41649 … (0x1<<22) // This bit masks, when set, the Parity bit: IG…
41651 … (0x1<<23) // This bit masks, when set, the Parity bit: IG…
41653 … (0x1<<24) // This bit masks, when set, the Parity bit: IG…
41655 … (0x1<<3) // This bit masks, when set, the Parity bit: IG…
41657 … (0x1<<4) // This bit masks, when set, the Parity bit: IG…
41659 … (0x1<<25) // This bit masks, when set, the Parity bit: IG…
41661 … (0x1<<4) // This bit masks, when set, the Parity bit: IG…
41663 … (0x1<<5) // This bit masks, when set, the Parity bit: IG…
41665 … (0x1<<26) // This bit masks, when set, the Parity bit: IG…
41667 … (0x1<<5) // This bit masks, when set, the Parity bit: IG…
41669 … (0x1<<27) // This bit masks, when set, the Parity bit: IG…
41671 … (0x1<<28) // This bit masks, when set, the Parity bit: IG…
41673 … (0x1<<29) // This bit masks, when set, the Parity bit: IG…
41675 … (0x1<<30) // This bit masks, when set, the Parity bit: IG…
41677 … (0x1<<0) // This bit masks, when set, the Parity bit: IG…
41679 … (0x1<<1) // This bit masks, when set, the Parity bi…
41680 …GU_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_SHIFT 1
41681 … (0x1<<1) // This bit masks, when set, the Parity bi…
41682 …GU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_SHIFT 1
41683 … (0x1<<2) // This bit masks, when set, the Parity bit: IG…
41685 … (0x1<<2) // This bit masks, when set, the Parity bit: IG…
41687 … (0x1<<3) // This bit masks, when set, the Parity bit: IG…
41689 … (0x1<<7) // This bit masks, when set, the Parity bit: IG…
41691 … (0x1<<9) // This bit masks, when set, the Parity bit: IG…
41693 … (0x1<<8) // This bit masks, when set, the Parity bit: IG…
41695 … (0x1<<10) // This bit masks, when set, the Parity bit: IG…
41697 … (0x1<<11) // This bit masks, when set, the Parity bit: IG…
41699 … (0x1<<12) // This bit masks, when set, the Parity bit: IG…
41701 … (0x1<<14) // This bit masks, when set, the Parity bit: IG…
41703 … (0x1<<15) // This bit masks, when set, the Parity bit: IG…
41705 … (0x1<<14) // This bit masks, when set, the Parity bit: IG…
41707 … (0x1<<16) // This bit masks, when set, the Parity bit: IG…
41709 … (0x1<<15) // This bit masks, when set, the Parity bit: IG…
41711 … (0x1<<17) // This bit masks, when set, the Parity bit: IG…
41713 … (0x1<<18) // This bit masks, when set, the Parity bit: IG…
41715 … (0x1<<20) // This bit masks, when set, the Parity bit: IG…
41717 … (0x1<<21) // This bit masks, when set, the Parity bit: IG…
41719 … (0x1<<29) // This bit masks, when set, the Parity bit: IG…
41721 … (0x1<<25) // This bit masks, when set, the Parity bit: IG…
41723 … (0x1<<30) // This bit masks, when set, the Parity bit: IG…
41725 … (0x1<<27) // This bit masks, when set, the Parity bit: IG…
41727 … (0x1<<12) // This bit masks, when set, the Parity bit: IG…
41729 … (0x1<<16) // This bit masks, when set, the Parity bit: IG…
41731 … (0x1<<17) // This bit masks, when set, the Parity bit: IG…
41733 … (0x1<<18) // This bit masks, when set, the Parity bit: IG…
41735 … (0x1<<22) // This bit masks, when set, the Parity bit: IG…
41737 … (0x1<<23) // This bit masks, when set, the Parity bit: IG…
41739 … (0x1<<24) // This bit masks, when set, the Parity bit: IG…
41741 … (0x1<<25) // This bit masks, when set, the Parity bit: IG…
41745 … (0x1<<0) // This bit masks, when set, the Parity bit: IG…
41747 … (0x1<<0) // This bit masks, when set, the Parity bit: IG…
41752 … 0x180224UL //Access:RW DataWidth:0x1 // Set parity only for memory ecc inst…
41753 … 0x180214UL //Access:RW DataWidth:0x1 // Set parity only for memory ecc inst…
41754 … 0x180224UL //Access:RW DataWidth:0x1 // Set parity only for memory ecc inst…
41761 …r of MSI/MSIX/ATTN messages sent for the PF: address 0 - number of MSI/MSIX messages; address 1 - …
41771 …Debug: count the number of PXP requests sent on behalf of a specific MSI/MSI-X vector on the SB in…
41785 … 0x180600UL //Access:RW DataWidth:0x14 // IPS statistics - number of messages s…
41787 …- function enable; b1 - MSI/MSIX enable; b2 - INT enable; b3 - attention enable; b4 - single ISR m…
41788 …h:0x9 // d0 - function enable; d1 - MSI/MSIX enable; d3:d2 reserved; d4 - single ISR mode enabl…
41816 …th:0x1 // PF MSIX function mask status. Shadow of PCI config register. 0 - unmasked; 1 - masked.
41818 …th:0x1 // VF MSIX function mask status. Shadow of PCI config register. 0 - unmasked; 1 - masked.
41819 …80820UL //Access:RW DataWidth:0x20 // For attention message: Attention bit destination address…
41820 …80824UL //Access:RW DataWidth:0x20 // For attention message: Attention bit destination address…
41821 …ss:RW DataWidth:0x10 // Value of attention bit status index (posted toward the driver as atten…
41822 … Attention signals leading edge. attn bit condition monitoring; each bit that is set will lock a c…
41823 …/ Attention signals trailing edge. attn bit condition monitoring; each bit that is set will lock a…
41824 … 0x180834UL //Access:RW DataWidth:0x20 // 32 bit register with the l…
41825 … 0x180838UL //Access:RW DataWidth:0x20 // 32 bit register with the a…
41826 …tor is 12 bit. If the bit is set to 1, the corresponding bit in the attention vector is enabled. I…
41827 …bit means PBA message wasnt sent due to mask). If address = SIMD with mask 64b/32LSB: 32 LSB of th…
41828 …only register. If the last command sent to the command_reg_ctrl was a read command, this register …
41829 …- function number: opaque fid. [28:16] - PXP BAR address; [30:29] - Reserved; [31] command type - …
41831 … DataWidth:0x20 // Address 0 - MSI address low (two Lsbit are zero). Address 1 - MSI address hig…
41834 …1, hit scrubbing is enabled. When hit scrubbing is enabled, the match…
41836 …1) // IF = 1, miss scrubbing is enabled. When miss scrubbing is enabl…
41837 …GU_REG_CAM_PARITY_SCRUBBING_CAM_SCRUB_MISS_EN_SHIFT 1
41838 … 0x180864UL //Access:RW DataWidth:0x1 // Enable the RL statistic. 0 - disabled; 1 - enabled.
41840 …UL //Access:R DataWidth:0x20 // Each bit represents the pending bits status for that SB. 0 = …
41844 … // Each bit represent write done pending bits status for that SB (MSI/MSIX message was sent and w…
41848 …0980UL //Access:R DataWidth:0x20 // Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanu…
41852 …0a00UL //Access:R DataWidth:0x20 // Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanu…
41856 …0a80UL //Access:R DataWidth:0x20 // Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanu…
41860 …0b00UL //Access:R DataWidth:0x20 // Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanu…
41864 …0b80UL //Access:R DataWidth:0x20 // Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanu…
41868 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41869 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41870 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41871 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41872 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41873 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41874 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41875 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41876 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41877 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41878 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41879 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41880 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41881 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41882 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41883 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41884 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41885 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41886 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41887 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41888 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41889 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41890 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41891 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41892 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41893 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41894 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41895 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41896 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41897 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41898 …he appropriate vector in the MSIX table (write zero to all fields except the mask bit that is set).
41899 …- prod equal cons. 1 - prod not equal cons or last command for this SB was prod update. The bits o…
41901 …- prod equal cons. 1 - prod not equal cons or last command for this SB was prod update. The bits o…
41902 …- prod equal cons. 1 - prod not equal cons or last command for this SB was prod update. The bits o…
41903 …/ SB interrupt mask. 0 - unmasked. 1 - masked. The bits order is according to the vector number of…
41905 …- unmasked. 1 - masked. The bits order is according to the vector number of each SB in that functi…
41906 …- unmasked. 1 - masked. The bits order is according to the vector number of each SB in that functi…
41907 …- PBA clear, 1 - PBA set - the appropriate MSIX message was not set due to mask bit (function or v…
41909 …- PBA clear, 1 - PBA set - the appropriate MSIX message was not set due to mask bit (function or v…
41910 …- PBA clear, 1 - PBA set - the appropriate MSIX message was not set due to mask bit (function or v…
41911 …- sets the max value that the rate_counter can reach; [19:10] tick_interval - define the max inter…
41913 …- receives the tick_interval value when reaching zero; or when writing to the tick_interval. The t…
41923 …er - incremented by one when Tick_value reaches zero and decremented whenever a message from that …
41924 … 0x18120cUL //Access:W DataWidth:0x1 // Writing 1 to this register wil…
41925 …/Access:W DataWidth:0x1 // Writing 1 to this register will clear the PF statistics and clean…
41926 …1 usec. In case this configuration should be changed, the change flow is done in several phases of…
41927 …Tph field for attention message. Bits 8:0 - steering tag; bits 12:9 - reserved; bits 14:13 - st hi…
41928 … Rate Limiter group enable status bit for groups 0-31. For each bit: 0 - the rate limiter of the g…
41929 …Rate Limiter group enable status bit for groups 32-63. For each bit: 0 - the rate limiter of the g…
41930 …0x20 // Rate Limiter group credit status bit for groups 0-31. For each bit: 0 - the group has no…
41931 …x20 // Rate Limiter group credit status bit for groups 32-63. For each bit: 0 - the group has no…
41932 …/ Rate Limiter group pending status bit for groups 0-31. For each bit: 0 - there are no pending SB…
41933 … Rate Limiter group pending status bit for groups 32-63. For each bit: 0 - there are no pending SB…
41934 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port0.
41935 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port1.
41936 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port2.
41937 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port3.
41938 …Width:0x10 // Debug: messages that wait to be sent; but were not sent yet. One bit for each PFID.
41939 …L //Access:R DataWidth:0x5 // Debug: [4] - attention write done message is pending (0-no pen…
41940 …x181518UL //Access:RW DataWidth:0x1 // Debug only: 0 - FIFO collects 64 first error messages;…
41942 …- fid ([8] - if set - PF; else VF, [7:0] - FID). [12:9] - source (values 0-7 according to PXP sour…
41944 …//Access:R DataWidth:0x1 // Data available for error memory. If this bit is clear do not rea…
41966 … (0x1ff<<0) // Debug: FID number for debug . if VF - [8] = 0; [7:0] = VF number; if PF - [8] = …
41973 … (0xf<<0) // Debug: source index for the debug. 0=TSTORM; 1=MSTORM; 2=USTORM; 3=…
41978 …Bit [0] - MSIX read/write; Bit [1] - PBA read/write; Bit [2] - Producer update (or cleanup command…
41980 … Debug: if set the debug information is collected for the marked commands only according to debug_…
41982 …/Access:R DataWidth:0x2 // The misc port mode signal value. 0 = SPPE; 1 = DPPE; 2 = QPPE; 3 …
41985 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
41986 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
41987 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
41988 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
41993 …ccess:RW DataWidth:0x18 // Producers only. Address 0-511 match to the mapping memory. Address …
41997 …ccess:RW DataWidth:0x18 // Consumers only. Address 0-511 match to the mapping memory. Address …
42001 …- valid. [8:1] - vector number (0-128 for PF; 0-63 for VF). [17:9] - FID (if VF: [17] = 0; [16:9] …
42005 …- MSIX message address (bit [1:0] are always zero); [95:64] - MSIX message data; [96] - MSIX mask …
42012 …PXP_RD_CMD (0x1<<1) // PXP read request…
42013 …AU_REG_INT_STS_UNAUTHORIZED_PXP_RD_CMD_SHIFT 1
42014 … (0x1<<2) // PXP write request without CQA and with length >1 arrived.
42035 …ZED_PXP_RD_CMD (0x1<<1) // PXP read request…
42036 …AU_REG_INT_STS_CLR_UNAUTHORIZED_PXP_RD_CMD_SHIFT 1
42037 … (0x1<<2) // PXP write request without CQA and with length >1 arrived.
42058 …ED_PXP_RD_CMD (0x1<<1) // PXP read request…
42059 …AU_REG_INT_STS_WR_UNAUTHORIZED_PXP_RD_CMD_SHIFT 1
42060 … (0x1<<2) // PXP write request without CQA and with length >1 arrived.
42079 … (0x1<<0) // This bit masks, when set, the Interrupt bit: C…
42081 … (0x1<<1) // This bit masks, when set, the Interrupt …
42082 …AU_REG_INT_MASK_UNAUTHORIZED_PXP_RD_CMD_SHIFT 1
42083 … (0x1<<2) // This bit masks, when set, the Interrupt bit: C…
42085 … (0x1<<3) // This bit masks, when set, the Interrupt bit: C…
42087 … (0x1<<4) // This bit masks, when set, the Interrupt bit: C…
42089 … (0x1<<5) // This bit masks, when set, the Interrupt bit: C…
42091 … (0x1<<6) // This bit masks, when set, the Interrupt bit: C…
42093 … (0x1<<8) // This bit masks, when set, the Interrupt bit: C…
42095 … (0x1<<9) // This bit masks, when set, the Interrupt bit: C…
42097 … (0x1<<10) // This bit masks, when set, the Interrupt bit: C…
42099 … (0x1<<7) // This bit masks, when set, the Interrupt bit: C…
42102 … (0x1<<1) // This bit masks, when set, the Parity bi…
42103 …AU_REG_PRTY_MASK_H_0_MEM001_I_ECC_0_RF_INT_BB_K2_SHIFT 1
42104 … (0x1<<0) // This bit masks, when set, the Parity bit: CA…
42106 … (0x1<<2) // This bit masks, when set, the Parity bit: CA…
42108 … (0x1<<1) // This bit masks, when set, the Parity bi…
42109 …AU_REG_PRTY_MASK_H_0_MEM001_I_ECC_1_RF_INT_E5_SHIFT 1
42110 … (0x1<<3) // This bit masks, when set, the Parity bit: CA…
42112 … (0x1<<2) // This bit masks, when set, the Parity bit: CA…
42114 … (0x1<<4) // This bit masks, when set, the Parity bit: CA…
42116 … (0x1<<3) // This bit masks, when set, the Parity bit: CA…
42118 … (0x1<<3) // This bit masks, when set, the Parity bit: CA…
42120 … (0x1<<5) // This bit masks, when set, the Parity bit: CA…
42122 … (0x1<<4) // This bit masks, when set, the Parity bit: CA…
42124 … (0x1<<5) // This bit masks, when set, the Parity bit: CA…
42126 … (0x1<<4) // This bit masks, when set, the Parity bit: CA…
42128 … (0x1<<6) // This bit masks, when set, the Parity bit: CA…
42130 … (0x1<<5) // This bit masks, when set, the Parity bit: CA…
42132 … (0x1<<7) // This bit masks, when set, the Parity bit: CA…
42134 … (0x1<<10) // This bit masks, when set, the Parity bit: CA…
42136 … (0x1<<11) // This bit masks, when set, the Parity bit: CA…
42138 … (0x1<<8) // This bit masks, when set, the Parity bit: CA…
42140 … (0x1<<11) // This bit masks, when set, the Parity bit: CA…
42142 … (0x1<<12) // This bit masks, when set, the Parity bit: CA…
42144 … (0x1<<9) // This bit masks, when set, the Parity bit: CA…
42146 … (0x1<<0) // This bit masks, when set, the Parity bit: CA…
42148 … (0x1<<6) // This bit masks, when set, the Parity bit: CA…
42150 … (0x1<<8) // This bit masks, when set, the Parity bit: CA…
42152 … (0x1<<7) // This bit masks, when set, the Parity bit: CA…
42154 … (0x1<<9) // This bit masks, when set, the Parity bit: CA…
42156 … (0x1<<8) // This bit masks, when set, the Parity bit: CA…
42158 … (0x1<<10) // This bit masks, when set, the Parity bit: CA…
42160 … (0x1<<9) // This bit masks, when set, the Parity bit: CA…
42162 … (0x1<<12) // This bit masks, when set, the Parity bit: CA…
42165 …01_I_ECC_0_EN_BB_K2 (0x1<<1) // Enable ECC for m…
42166 …AU_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_0_EN_BB_K2_SHIFT 1
42171 …01_I_ECC_1_EN_E5 (0x1<<1) // Enable ECC for m…
42172 …AU_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_1_EN_E5_SHIFT 1
42184 …ECC_0_PRTY_BB_K2 (0x1<<1) // Set parity only for memory…
42185 …AU_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_0_PRTY_BB_K2_SHIFT 1
42186 …Y_E5 (0x1<<0) // Set parity only for memory ecc inst…
42188 …Y_BB_K2 (0x1<<2) // Set parity only for memory ecc inst…
42190 …ECC_1_PRTY_E5 (0x1<<1) // Set parity only for memory…
42191 …AU_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_1_PRTY_E5_SHIFT 1
42192 …K2 (0x1<<3) // Set parity only for memory ecc inst…
42194 …E5 (0x1<<2) // Set parity only for memory ecc inst…
42196 …K2 (0x1<<4) // Set parity only for memory ecc inst…
42198 …E5 (0x1<<3) // Set parity only for memory ecc inst…
42200 …BB_K2 (0x1<<0) // Set parity only for memory ecc inst…
42203 …ED_0_MEM001_I_ECC_0_CORRECT_BB_K2 (0x1<<1) // Record if a corr…
42204 …AU_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_0_CORRECT_BB_K2_SHIFT 1
42209 …ED_0_MEM001_I_ECC_1_CORRECT_E5 (0x1<<1) // Record if a corr…
42210 …AU_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_1_CORRECT_E5_SHIFT 1
42222 … The number of Protocol Index per Status Block. Value can be even numbers only from 2 to 32. numbe…
42244 …0408UL //Access:RW DataWidth:0x1 // Enabling pi value of command N+2/N+1 as part of sb_dma me…
42245 … number of outstanding write requests without receiving write done. Values 1-128. Zero is not a va…
42246 …bit will reset the whole memory. When the memory reset finished the appropriate bit will be clear.…
42247 …p on the written SB number. [8:0] - SB absolute index; [9] - Cleanup set/clr (0-clr; 1 - set); [12…
42249 …nput arbiter (sp with anti starvation) priority for the input clients: bits 1:0 PXP input commands…
42251 … 0x1c0600UL //Access:RW DataWidth:0x1 // Indicate the size of the CQE. 0 - 32B; 1 - 64B.
42252 …W DataWidth:0x2 // Indicate the size of the AGG unit. 0 - 64B; 1 - 128B; 2 - 256B; 3 - illega…
42253 … 0x1c0608UL //Access:RW DataWidth:0x1 // Flush all command - will flush all the C…
42254 … 0x1c060cUL //Access:R DataWidth:0x1 // Read clear register. 1 means the the cqe_fl…
42256 …ollowed by a read. For example to change the reset value of (binary) 11001 (1usec) to (binary) 110…
42259 …DataWidth:0x1 // Setting this bit will disable the timer expiration mechanism. Should be used i…
42260 … 0x1c0780UL //Access:R DataWidth:0x20 // Rx timers status. 0 - inactive 1 - active.
42262 … 0x1c0800UL //Access:R DataWidth:0x20 // Tx timers status. 0 - inactive 1 - active.
42266 …980UL //Access:R DataWidth:0x1 // Debug: IGU-CAU request interface credit. In idle should …
42267 …984UL //Access:R DataWidth:0x1 // Debug: IGU-CAU command interface credit. In idle should …
42279 … (0xf<<0) // Statistic: client index to collect statistics on. 0=TSTORM; 1=MSTORM; 2=USTORM; 3=…
42289 … (0xff<<0) // Statistic: Line number of FSM 1 to collect statistic…
42291 … (0x1<<8) // Statistic: enable FSM 1 line statistics.
42293 …/ Statistic: enable timer command type. One bit for each timer command type: [0] - rewind; [1] - c…
42311 …- FIFO empty; 1 - FIFO not empty. [0] - PXP command FIFO; [1] - reserved; [2] - timers expiration …
42312 …- error typ (1- read request; 2 - reserved; 3 - sb_index >= CAU_NUM_SB or SB index > CAU_NUM_PI/n…
42313 …- source (0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM)…
42314 … // Debug; [9] if set data valid; [8] previous FSM_sel; [7:4] - previous state; [3:0] - previous…
42316 …h:0x19 // comment="Debug: [15:0] The PF that caused the error- one bit per PF; [24:16] - SB inde…
42317 … 0x1c0c98UL //Access:W DataWidth:0x1 // Debug: write only. Writing to this re…
42318 …e was writing to agg_units_state_read_en register. (i =0-15). 0 - free; 1 - dirty; 2 - clean; 3 - …
42319 …was writing to agg_units_state_read_en register. (i = 16-31). 0 - free; 1 - dirty; 2 - clean; 3 - …
42320 …was writing to agg_units_state_read_en register. (i = 32-47). 0 - free; 1 - dirty; 2 - clean; 3 - …
42321 …was writing to agg_units_state_read_en register. (i = 48-63). 0 - free; 1 - dirty; 2 - clean; 3 - …
42334 … (0x1ff<<0) // Debug: FID number for debug . if VF - [8] = 1; [7:0] = VF number; if PF - [8…
42341 … (0xf<<0) // Debug: source index for the debug. 0=TSTORM; 1=MSTORM; 2=USTORM; 3=…
42346 … (0x7<<0) // Debug: command type for the debug. [0] - PI producer update; [1] - cleanup; [2] - …
42348 …g: if set the debug information will be collected for the marked commands only according to debug_…
42358 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
42359 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
42360 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
42361 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
42365 … 0x1c0f0cUL //Access:R DataWidth:0x5 // Debug: FSM state for debug.Idle state value are 0-2
42367 … 0x1c2000UL //Access:WB_R DataWidth:0x80 // Debug: Provides read-only access of the CQE …
42369 … 0x1c2200UL //Access:WB_R DataWidth:0x35 // Debug: Provides read-only access of the IGU …
42371 … 0x1c2300UL //Access:WB_R DataWidth:0x62 // Debug: Provides read-only access of the PXP …
42373 …2400UL //Access:WB_R DataWidth:0x84 // Debug: Provides read-only access of the PXP write-data FI…
42375 … and PI relative number of each aggregation unit. [0] - valid; [9:1] - absolute SB index; [14:10] …
42377 …- next state; [5:4] - timer cmd (0 - None; 1 - Rewind; 2 - Clear; 3 - Rewind to shorter); [6] - SB…
42379 …-2 only); [49:48] TimerRes1 (This value will determine the TX FSM timer resolution in ticks. Valid…
42387 …ry.[15:0] - protocol producer; [22:16] - PiTimeSet (This value determines the TimeSet that the PI …
42391 …1), then N = 8 addresses If (cqe_agg_unit_size = 2), then N = 16 addresses Address calculation: I…
42394 …- address; [71:64] - valid slots; [84:72] - FID ([13:9] - PF number (in case of VF the parent PF);…
42396 …h:0x18 // The SB timers. For each SB there are two timers: [11:0] - RX timer; [23:12] - TX timer.
42400 … 0x1f0000UL //Access:RW DataWidth:0x1 // Soft reset - reset all FSM.
42401 …UL //Access:W DataWidth:0x1 // Any write to this register triggers MAC-VLAN Cache initializa…
42403 … 0x1f000cUL //Access:RW DataWidth:0x1 // When set to 1 the cam hit parity s…
42404 … 0x1f0010UL //Access:RW DataWidth:0x1 // When set to 1 the cam miss parity …
42408 … (0x1<<1) // Load Request Mini-cache vali…
42409 …RS_REG_INT_STS_0_LCID_VALIDATION_ERR_SHIFT 1
42411 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
42413 … (0x1<<1) // This bit masks, when set, the Interrupt …
42414 …RS_REG_INT_MASK_0_LCID_VALIDATION_ERR_SHIFT 1
42418 … (0x1<<1) // Load Request Mini-cache vali…
42419 …RS_REG_INT_STS_WR_0_LCID_VALIDATION_ERR_SHIFT 1
42423 … (0x1<<1) // Load Request Mini-cache vali…
42424 …RS_REG_INT_STS_CLR_0_LCID_VALIDATION_ERR_SHIFT 1
42426 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
42428 … (0x1<<1) // This bit masks, when set, the Parity bi…
42429 …RS_REG_PRTY_MASK_GFT_CAM_PARITY_SHIFT 1
42432 …0168UL //Access:RW DataWidth:0x10 // Per-PF: If OX_ID exceeds this value on a PF packet, task-…
42433 …016cUL //Access:RW DataWidth:0x10 // Per-PF: If OX_ID exceeds this value on a VF packet, task-…
42434 …0170UL //Access:RW DataWidth:0x10 // Per-PF: If RX_ID exceeds this value on a PF packet, task-…
42435 …0174UL //Access:RW DataWidth:0x10 // Per-PF: If RX_ID exceeds this value on a VF packet, task-…
42442 … 0x1f0190UL //Access:RW DataWidth:0x1 // Per-PF: If set, override …
42443 … 0x1f0194UL //Access:RW DataWidth:0x20 // Per-opcode requester/responder bit to be…
42444 … 0x1f0198UL //Access:RW DataWidth:0x1 // Per-PF: If set, a load re…
42445 … 0x1f019cUL //Access:RW DataWidth:0x1 // If set, CFC load mini-cache is enabled.
42446 … 0x1f01a0UL //Access:RW DataWidth:0x1 // 0-search response initiator type,1-Excha…
42447 … 0x1f01a4UL //Access:RW DataWidth:0x1 // 0-Exchange Context field in the fcoe search req is z…
42448 … 0x1f0200UL //Access:RW DataWidth:0x20 // Debug only: Reserved bits for …
42450 … (0x1<<4) // This bit masks, when set, the Parity bit: PR…
42452 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
42454 … (0x1<<5) // This bit masks, when set, the Parity bit: PR…
42456 … (0x1<<1) // This bit masks, when set, the Parity bi…
42457 …RS_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT_E5_SHIFT 1
42458 … (0x1<<2) // This bit masks, when set, the Parity bit: PR…
42460 … (0x1<<3) // This bit masks, when set, the Parity bit: PR…
42462 … (0x1<<4) // This bit masks, when set, the Parity bit: PR…
42464 … (0x1<<14) // This bit masks, when set, the Parity bit: PR…
42466 … (0x1<<5) // This bit masks, when set, the Parity bit: PR…
42468 … (0x1<<13) // This bit masks, when set, the Parity bit: PR…
42470 … (0x1<<6) // This bit masks, when set, the Parity bit: PR…
42472 … (0x1<<10) // This bit masks, when set, the Parity bit: PR…
42474 … (0x1<<7) // This bit masks, when set, the Parity bit: PR…
42476 … (0x1<<23) // This bit masks, when set, the Parity bit: PR…
42478 … (0x1<<8) // This bit masks, when set, the Parity bit: PR…
42480 … (0x1<<9) // This bit masks, when set, the Parity bit: PR…
42482 … (0x1<<19) // This bit masks, when set, the Parity bit: PR…
42484 … (0x1<<10) // This bit masks, when set, the Parity bit: PR…
42486 … (0x1<<18) // This bit masks, when set, the Parity bit: PR…
42488 … (0x1<<20) // This bit masks, when set, the Parity bit: PR…
42490 … (0x1<<11) // This bit masks, when set, the Parity bit: PR…
42492 … (0x1<<22) // This bit masks, when set, the Parity bit: PR…
42494 … (0x1<<12) // This bit masks, when set, the Parity bit: PR…
42496 … (0x1<<30) // This bit masks, when set, the Parity bit: PR…
42498 … (0x1<<13) // This bit masks, when set, the Parity bit: PR…
42500 … (0x1<<14) // This bit masks, when set, the Parity bit: PR…
42502 … (0x1<<15) // This bit masks, when set, the Parity bit: PR…
42504 … (0x1<<21) // This bit masks, when set, the Parity bit: PR…
42506 … (0x1<<16) // This bit masks, when set, the Parity bit: PR…
42508 … (0x1<<17) // This bit masks, when set, the Parity bit: PR…
42510 … (0x1<<26) // This bit masks, when set, the Parity bit: PR…
42512 … (0x1<<18) // This bit masks, when set, the Parity bit: PR…
42514 … (0x1<<27) // This bit masks, when set, the Parity bit: PR…
42516 … (0x1<<19) // This bit masks, when set, the Parity bit: PR…
42518 … (0x1<<12) // This bit masks, when set, the Parity bit: PR…
42520 … (0x1<<20) // This bit masks, when set, the Parity bit: PR…
42522 … (0x1<<21) // This bit masks, when set, the Parity bit: PR…
42524 … (0x1<<20) // This bit masks, when set, the Parity bit: PR…
42526 … (0x1<<22) // This bit masks, when set, the Parity bit: PR…
42528 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
42530 … (0x1<<1) // This bit masks, when set, the Parity bi…
42531 …RS_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_K2_SHIFT 1
42532 … (0x1<<2) // This bit masks, when set, the Parity bit: PR…
42534 … (0x1<<3) // This bit masks, when set, the Parity bit: PR…
42536 … (0x1<<6) // This bit masks, when set, the Parity bit: PR…
42538 … (0x1<<7) // This bit masks, when set, the Parity bit: PR…
42540 … (0x1<<8) // This bit masks, when set, the Parity bit: PR…
42542 … (0x1<<9) // This bit masks, when set, the Parity bit: PR…
42544 … (0x1<<10) // This bit masks, when set, the Parity bit: PR…
42546 … (0x1<<4) // This bit masks, when set, the Parity bit: PR…
42548 … (0x1<<11) // This bit masks, when set, the Parity bit: PR…
42550 … (0x1<<25) // This bit masks, when set, the Parity bit: PR…
42552 … (0x1<<12) // This bit masks, when set, the Parity bit: PR…
42554 … (0x1<<16) // This bit masks, when set, the Parity bit: PR…
42556 … (0x1<<13) // This bit masks, when set, the Parity bit: PR…
42558 … (0x1<<17) // This bit masks, when set, the Parity bit: PR…
42560 … (0x1<<14) // This bit masks, when set, the Parity bit: PR…
42562 … (0x1<<15) // This bit masks, when set, the Parity bit: PR…
42564 … (0x1<<29) // This bit masks, when set, the Parity bit: PR…
42566 … (0x1<<16) // This bit masks, when set, the Parity bit: PR…
42568 … (0x1<<30) // This bit masks, when set, the Parity bit: PR…
42570 … (0x1<<17) // This bit masks, when set, the Parity bit: PR…
42572 … (0x1<<18) // This bit masks, when set, the Parity bit: PR…
42574 … (0x1<<24) // This bit masks, when set, the Parity bit: PR…
42576 … (0x1<<19) // This bit masks, when set, the Parity bit: PR…
42578 … (0x1<<28) // This bit masks, when set, the Parity bit: PR…
42580 … (0x1<<21) // This bit masks, when set, the Parity bit: PR…
42582 … (0x1<<22) // This bit masks, when set, the Parity bit: PR…
42584 … (0x1<<23) // This bit masks, when set, the Parity bit: PR…
42586 … (0x1<<24) // This bit masks, when set, the Parity bit: PR…
42588 … (0x1<<25) // This bit masks, when set, the Parity bit: PR…
42590 … (0x1<<26) // This bit masks, when set, the Parity bit: PR…
42592 … (0x1<<27) // This bit masks, when set, the Parity bit: PR…
42594 … (0x1<<28) // This bit masks, when set, the Parity bit: PR…
42596 … (0x1<<29) // This bit masks, when set, the Parity bit: PR…
42598 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
42600 … (0x1<<1) // This bit masks, when set, the Parity bi…
42601 …RS_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_BB_SHIFT 1
42602 … (0x1<<2) // This bit masks, when set, the Parity bit: PR…
42604 … (0x1<<3) // This bit masks, when set, the Parity bit: PR…
42606 … (0x1<<5) // This bit masks, when set, the Parity bit: PR…
42608 … (0x1<<6) // This bit masks, when set, the Parity bit: PR…
42610 … (0x1<<7) // This bit masks, when set, the Parity bit: PR…
42612 … (0x1<<8) // This bit masks, when set, the Parity bit: PR…
42614 … (0x1<<9) // This bit masks, when set, the Parity bit: PR…
42616 … (0x1<<11) // This bit masks, when set, the Parity bit: PR…
42618 … (0x1<<15) // This bit masks, when set, the Parity bit: PR…
42628 …22_I_ECC_EN_E5 (0x1<<1) // Enable ECC for m…
42629 …RS_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_EN_E5_SHIFT 1
42638 …12_I_ECC_EN_K2 (0x1<<1) // Enable ECC for m…
42639 …RS_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN_K2_SHIFT 1
42650 …10_I_ECC_EN_BB (0x1<<1) // Enable ECC for m…
42651 …RS_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN_BB_SHIFT 1
42658 …K2 (0x1<<4) // Set parity only for memory ecc inst…
42660 …E5 (0x1<<0) // Set parity only for memory ecc inst…
42662 …K2 (0x1<<5) // Set parity only for memory ecc inst…
42664 …ECC_PRTY_E5 (0x1<<1) // Set parity only for memory…
42665 …RS_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_PRTY_E5_SHIFT 1
42666 …E5 (0x1<<2) // Set parity only for memory ecc inst…
42668 …E5 (0x1<<3) // Set parity only for memory ecc inst…
42670 …E5 (0x1<<4) // Set parity only for memory ecc inst…
42672 …K2 (0x1<<0) // Set parity only for memory ecc inst…
42674 …ECC_PRTY_K2 (0x1<<1) // Set parity only for memory…
42675 …RS_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY_K2_SHIFT 1
42676 …K2 (0x1<<2) // Set parity only for memory ecc inst…
42678 …K2 (0x1<<3) // Set parity only for memory ecc inst…
42680 …K2 (0x1<<6) // Set parity only for memory ecc inst…
42682 …K2 (0x1<<7) // Set parity only for memory ecc inst…
42684 …BB (0x1<<0) // Set parity only for memory ecc inst…
42686 …ECC_PRTY_BB (0x1<<1) // Set parity only for memory…
42687 …RS_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY_BB_SHIFT 1
42688 …BB (0x1<<2) // Set parity only for memory ecc inst…
42690 …BB (0x1<<3) // Set parity only for memory ecc inst…
42693 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
42695 … (0x1<<1) // This bit masks, when set, the Parity bi…
42696 …RS_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_K2_SHIFT 1
42697 … (0x1<<2) // This bit masks, when set, the Parity bit: PR…
42699 … (0x1<<3) // This bit masks, when set, the Parity bit: PR…
42701 … (0x1<<4) // This bit masks, when set, the Parity bit: PR…
42703 … (0x1<<5) // This bit masks, when set, the Parity bit: PR…
42705 … (0x1<<6) // This bit masks, when set, the Parity bit: PR…
42707 … (0x1<<7) // This bit masks, when set, the Parity bit: PR…
42709 … (0x1<<8) // This bit masks, when set, the Parity bit: PR…
42711 … (0x1<<9) // This bit masks, when set, the Parity bit: PR…
42713 … (0x1<<10) // This bit masks, when set, the Parity bit: PR…
42715 … (0x1<<11) // This bit masks, when set, the Parity bit: PR…
42717 … (0x1<<12) // This bit masks, when set, the Parity bit: PR…
42719 … (0x1<<13) // This bit masks, when set, the Parity bit: PR…
42721 … (0x1<<14) // This bit masks, when set, the Parity bit: PR…
42723 … (0x1<<15) // This bit masks, when set, the Parity bit: PR…
42725 … (0x1<<16) // This bit masks, when set, the Parity bit: PR…
42727 … (0x1<<17) // This bit masks, when set, the Parity bit: PR…
42729 … (0x1<<18) // This bit masks, when set, the Parity bit: PR…
42731 … (0x1<<19) // This bit masks, when set, the Parity bit: PR…
42733 … (0x1<<20) // This bit masks, when set, the Parity bit: PR…
42735 … (0x1<<21) // This bit masks, when set, the Parity bit: PR…
42737 … (0x1<<22) // This bit masks, when set, the Parity bit: PR…
42739 … (0x1<<23) // This bit masks, when set, the Parity bit: PR…
42741 … (0x1<<24) // This bit masks, when set, the Parity bit: PR…
42743 … (0x1<<25) // This bit masks, when set, the Parity bit: PR…
42745 … (0x1<<26) // This bit masks, when set, the Parity bit: PR…
42747 … (0x1<<27) // This bit masks, when set, the Parity bit: PR…
42749 … (0x1<<28) // This bit masks, when set, the Parity bit: PR…
42751 … (0x1<<3) // This bit masks, when set, the Parity bit: PR…
42753 … (0x1<<29) // This bit masks, when set, the Parity bit: PR…
42755 … (0x1<<4) // This bit masks, when set, the Parity bit: PR…
42757 … (0x1<<30) // This bit masks, when set, the Parity bit: PR…
42759 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
42761 … (0x1<<1) // This bit masks, when set, the Parity bi…
42762 …RS_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_BB_SHIFT 1
42763 … (0x1<<2) // This bit masks, when set, the Parity bit: PR…
42773 …ED_0_MEM022_I_ECC_CORRECT_E5 (0x1<<1) // Record if a corr…
42774 …RS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_CORRECT_E5_SHIFT 1
42783 …ED_0_MEM012_I_ECC_CORRECT_K2 (0x1<<1) // Record if a corr…
42784 …RS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT_K2_SHIFT 1
42795 …ED_0_MEM010_I_ECC_CORRECT_BB (0x1<<1) // Record if a corr…
42796 …RS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT_BB_SHIFT 1
42803 … 0x1f0400UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42804 … 0x1f0404UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42805 … 0x1f0408UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42806 … 0x1f040cUL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42809 …IPV4 (0x1<<0) // If this bit is 0, the dest_ip_a…
42811 …DDRESS_IPV6 (0x1<<1) // If this bit is 0, the de…
42812 …RS_REG_TCP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV6_SHIFT 1
42813 …S_IPV4 (0x1<<2) // If this bit is 0, the source_ip…
42815 …S_IPV6 (0x1<<3) // If this bit is 0, the source_ip…
42817 … (0x1<<4) // If this bit is 0, the tcp_dest_…
42819 … (0x1<<5) // If this bit is 0, the tcp_sourc…
42821 … (0x1<<6) // If this bit is 0, the ip_versio…
42824 …IPV4 (0x1<<0) // If this bit is 0, the dest_ip_a…
42826 …DDRESS_IPV6 (0x1<<1) // If this bit is 0, the de…
42827 …RS_REG_UDP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV6_SHIFT 1
42828 …S_IPV4 (0x1<<2) // If this bit is 0, the source_ip…
42830 …S_IPV6 (0x1<<3) // If this bit is 0, the source_ip…
42832 … (0x1<<4) // If this bit is 0, the udp_dest_…
42834 … (0x1<<5) // If this bit is 0, the udp_sourc…
42836 … (0x1<<6) // If this bit is 0, the ip_versio…
42838 … 0x1f041cUL //Access:RW DataWidth:0x1 // Per-PF: If set, search requests on FCoE packets are…
42839 … 0x1f0420UL //Access:RW DataWidth:0x1 // Per-PF: Enables VF_ID (if…
42840 … 0x1f0424UL //Access:RW DataWidth:0x1 // Per-PF: Enables load requ…
42842 … 0x1f042cUL //Access:RW DataWidth:0x11 // Per-PF: Max value for tem…
42843 … 0x1f0430UL //Access:RW DataWidth:0x11 // Per-PF: Max value for tem…
42844 … 0x1f0434UL //Access:RW DataWidth:0x1 // Per-PF: Enables openflow …
42845 … 0x1f0438UL //Access:RW DataWidth:0x1 // Per-PF: Enables openflow search for non-IP packets.…
42846 … //Access:RW DataWidth:0x1 // Per-PF: If this field is 1, Over-IPv4-protocol field of Openflo…
42848 …PORT (0x1<<0) // If this bit is 0, the tcp_sourc…
42850 …SOURCE_PORT (0x1<<1) // If this bit is 0, the ud…
42851 …RS_REG_OPENFLOW_SEARCH_KEY_MASK_UDP_SOURCE_PORT_SHIFT 1
42852 …_PORT (0x1<<2) // If this bit is 0, the sctp_sour…
42854 … (0x1<<3) // If this bit is 0, the icmp_type…
42856 …RT (0x1<<4) // If this bit is 0, the tcp_dest_…
42858 …RT (0x1<<5) // If this bit is 0, the udp_dest_…
42860 …ORT (0x1<<6) // If this bit is 0, the sctp_dest…
42862 … (0x1<<7) // If this bit is 0, the icmp_code…
42864 … (0x1<<8) // If this bit is 0, the priority …
42866 …YPE (0x1<<9) // If this bit is 0, the ipv4_frag…
42868 …RESS (0x1<<10) // If this bit is 0, the dest_mac_…
42870 …OTOCOL (0x1<<11) // If this bit is 0, the over_ipv4…
42872 … (0x1<<12) // If this bit is 0, the arp_opcod…
42874 … (0x1<<13) // If this bit is 0, the ipv4_dscp…
42876 …DDRESS (0x1<<14) // If this bit is 0, the source_ma…
42878 …DRESS_IPV4 (0x1<<15) // If this bit is 0, the source_ip…
42880 …DRESS_ARP (0x1<<16) // If this bit is 0, the source_ip…
42882 …ESS_IPV4 (0x1<<17) // If this bit is 0, the dest_ip_a…
42884 …ESS_ARP (0x1<<18) // If this bit is 0, the dest_ip_a…
42886 … (0x1<<19) // If this bit is 0, the ethertype…
42888 …/ Per-PF: Indicates whether to include the Inner VLAN in the search for each protocol. 0 - TCP, 1 …
42889 …/ Per-PF: Indicates whether to include the Outer TAG in the search for each protocol. 0 - TCP, 1 -…
42890 …-PF: Indicates whether to include Tenant ID (if it exists) in the search for each encapsulation ty…
42891 …ID Exists bit in the search request to be 0 if the ID matches the default value. 0 - L2 GRE, 1 - …
42892 …Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated Ethernet ov…
42893 …Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated IP over GRE…
42894 …Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated VXLAN packe…
42895 …Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated T-tag packe…
42896 …capsulated Ethernet over GRE packet and does not match this value the Tenant ID exists bit is set.
42897 …the encapsulated IP over GRE packet and does not match this value the Tenant ID exists bit is set.
42898 …sts in the encapsulated VXLAN packet and does not match this value the Tenant ID exists bit is set.
42899 … the Tenant ID exists in the encapsulated T-Tag packet and does not match this value the Tenant ID…
42900 …ataWidth:0x3 // Per-Port: Specifies the flexible L2 tag to be used for T-tag. The T-tag bit of …
42901 …Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated nge packet.…
42902 …Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated nge packet.…
42903 …s in the encapsulated ETH NGE packet and does not match this value the Tenant ID exists bit is set.
42904 …ts in the encapsulated IP NGE packet and does not match this value the Tenant ID exists bit is set.
42905 …DataWidth:0x1 // MAC port arbitration guarantees fairness at byte-level (0) or packet-level (1).
42906 … DataWidth:0x1 // Main/LB arbitration guarantees fairness at byte-level (0) or packet-level (1).
42909 … 0x1f0510UL //Access:RW DataWidth:0x8 // Size of inter-packet gap and FCS us…
42910 …ority_client): 0-TC0 traffic; 1-TC1 traffic; 2-TC2 traffic; 3-TC3 traffic; 4-TC4 traffic; 5-TC5 tr…
42911 …ority_client): 0-TC0 traffic; 1-TC1 traffic; 2-TC2 traffic; 3-TC3 traffic; 4-TC4 traffic; 5-TC5 tr…
42912 …-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the …
42913 …bits are for priority 8 client. The clients are assigned the IDs corresponding to their TC # (0-8)
42914 …bits are for priority 8 client. The clients are assigned the IDs corresponding to their TC # (0-8)
42915 …-robin arbiter stays on the winning input instead of moving to the next one. Bit 0 is for the mai…
42916 … 0x1f052cUL //Access:RW DataWidth:0x1 // Enables pseudo-random round robin ar…
42919 …1f0538UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42920 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 1 is allowed to reach.
42921 …idth:0x20 // Specify the weight (in bytes) to be added to credit register 1 when it is time to i…
42922 …R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter credit register 1.
42925 …1f0550UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42928 …1f055cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42931 …1f0568UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42934 …1f0574UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42937 …1f0580UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42940 …1f058cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42943 …1f0598UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42946 …1f05a4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit…
42949 …1f05b0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42950 …r bound that the credit register is allowed to reach for main traffic on TC 1 during WFQ Main/Loop…
42951 …weight (in bytes) to be added to the credit register for main traffic on TC 1 when it is time to i…
42952 …Width:0x20 // Current upper 32 bits of the 33-bit value in the credit register for main traffic …
42953 …und that the credit register is allowed to reach for loopback traffic on TC 1 during WFQ Main/Loop…
42954 …ht (in bytes) to be added to the credit register for loopback traffic on TC 1 when it is time to i…
42955 …:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter credit register for loopback tr…
42958 …1f05d4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit…
42961 …1f05e0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42964 …1f05ecUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit…
42967 …1f05f8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42970 …1f0604UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit…
42973 …1f0610UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42976 …1f061cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit…
42979 …1f0628UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42982 …1f0634UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit…
42985 …1f0640UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42988 …1f064cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit…
42991 …1f0658UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42994 …1f0664UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit…
42995 … 0x1f0700UL //Access:RW DataWidth:0x4 // Per-port: Size of the pro…
43005 …nate SCTP in the IPv4 Protocol and IPv6 Next Header fields. Matching can only occur when sctp_ena…
43006 … // Value used to designate ICMP in the IPv4 Protocol field. Matching can only occur when icmp_ena…
43007 …ataWidth:0x6 // Per-port: Flag enabling each encapsulation type. 0 - L2 GRE, 1 - IP GRE, 2 - V…
43010 … 0x1f073cUL //Access:RW DataWidth:0x10 // Per-PF: Base value used i…
43011 … 0x1f0740UL //Access:RW DataWidth:0x10 // Per-PF: Base value used i…
43015 … 0x1f0750UL //Access:RW DataWidth:0x10 // The Ethernet type value for L2 tag 1.
43021 …L //Access:RW DataWidth:0x3 // The length of the info field for L2 tag 1. The length is betw…
43026 …-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port. …
43027 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port. This applies to …
43028 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port. This applies to …
43029 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port. This applies to …
43030 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port. This applies to …
43031 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port. This applies to …
43032 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port. This applies to …
43033 …-port: Bit-map indicating which headers must appear in the packet on this port. This applies to t…
43034 …aWidth:0x8 // Per-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet he…
43035 …RW DataWidth:0x8 // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on …
43036 …RW DataWidth:0x8 // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on …
43037 …RW DataWidth:0x8 // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on …
43038 …RW DataWidth:0x8 // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on …
43039 …RW DataWidth:0x8 // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on …
43040 …RW DataWidth:0x8 // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on …
43041 …RW DataWidth:0x8 // Per-port: Bit-map indicating which headers must appear in the packet on t…
43044 …alue. A zero in this register will cause the corresponding bit to not be included …
43045 …alue. A zero in this register will cause the corresponding bit to not be included …
43046 … 0x1f07ccUL //Access:RW DataWidth:0x20 // Per-PF/Per-port: Destination …
43047 … 0x1f07d0UL //Access:RW DataWidth:0x10 // Per-PF/Per-port: Destination …
43048 …L //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - bit 129 indicate…
43049 …L //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - bit 129 indicate…
43050 …L //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - bit 129 indicate…
43051 …L //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - bit 129 indicate…
43052 …L //Access:RW DataWidth:0x2 // Per-PF: Destination IP address match value - bit 129 indicate…
43053 … 0x1f07e8UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43054 … 0x1f07ecUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43055 … 0x1f07f0UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43056 … 0x1f07f4UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43057 … 0x1f07f8UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43058 … 0x1f07fcUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43059 … 0x1f0800UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43060 … 0x1f0804UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43061 … 0x1f0808UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43062 … 0x1f080cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43063 … 0x1f0810UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43064 … 0x1f0814UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43065 … 0x1f0818UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43066 … 0x1f081cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43067 … 0x1f0820UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43068 … 0x1f0824UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43069 … 0x1f0828UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43070 … 0x1f082cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43071 … 0x1f0830UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43072 … 0x1f0834UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43073 … 0x1f0838UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43074 … 0x1f083cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43075 … 0x1f0840UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43076 … 0x1f0844UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43077 … 0x1f0848UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43078 … 0x1f084cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43079 … 0x1f0850UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43080 … 0x1f0854UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43081 … 0x1f0858UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43082 … 0x1f085cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43083 … 0x1f0860UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43084 … 0x1f0864UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43088 … 0x1f0874UL //Access:RW DataWidth:0x1 // Per-port: Flag enabling …
43089 … 0x1f0878UL //Access:RW DataWidth:0x1 // Per-port: Flag to compar…
43093 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43098 … (0xff<<0) // Event ID for tunneled packets with no match in the mac-vlan cache
43100 …ch in the mac-vlan cache. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg;…
43111 … (0xff<<0) // Event ID for tunneled packets with no match in the mac-vlan cache
43113 …ch in the mac-vlan cache. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg;…
43126 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43139 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43146 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43156 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43157 … 0x1f093cUL //Access:RW DataWidth:0x4 // Connection type for no-match packets.
43158 … 0x1f0940UL //Access:RW DataWidth:0x4 // Per-port: PFID for no-match packet…
43159 … 0x1f0944UL //Access:RW DataWidth:0x1 // Per-PF: If set, the PFID may be overridden for n…
43160 … 0x1f0948UL //Access:RW DataWidth:0x20 // Per-PF: CID for no-match packets.
43161 … 0x1f094cUL //Access:RW DataWidth:0x9 // Per-PF: LCID for no-match packets.
43169 … 0x1f096cUL //Access:RW DataWidth:0x1 // Per-PF: If set, and PF cl…
43170 …f the first (0) or encapsulated (1) header in the output message for each encapsulation type. 0 - …
43171 …f the first (0) or encapsulated (1) header in the output message for each encapsulation type. 0 - …
43172 …f the first (0) or encapsulated (1) header in the output message for each encapsulation type. 0 - …
43173 …-PF: Indicates whether to include Tenant ID (if it exists) in the MAC VLAN Cache entry for each en…
43174 …-VLAN Cache Flexible Field. If two blocks are used, this block is used for the upper bytes. 14:11…
43175 …the MAC-VLAN Cache Flexible Field. This block is only used if the number of bytes in mac_vlan_fle…
43176 … mac_vlan_flex_lower. A zero in this register will mask the corresponding bit in the flexible fie…
43177 … mac_vlan_flex_lower. A zero in this register will mask the corresponding bit in the flexible fie…
43178 … 0x1f09d0UL //Access:RW DataWidth:0x1 // Per-PF: If set, the SACK …
43179 …-FCoE packets. This allows Over-L2-Raw Part2 to be available on non-RoCE packets. The RoCE specifi…
43180 … 0x1f09d8UL //Access:RW DataWidth:0x20 // Per-PF: Mask used in RDMA…
43189 … 0x1f09fcUL //Access:RW DataWidth:0x1 // Per-PF: Enables SYN cooki…
43190 … 0x1f0a00UL //Access:RW DataWidth:0x1 // Per-PF: If set, enables i…
43191 …1 // Per-PF: If set, 4B for Ethernet CRC is included in Packet Length for Statistics field. For…
43192 …-PF: For each bit set, the length of the corresponding tag in the inner header will be subtracted …
43193 …-PF: For each bit set, the length of the corresponding tag in the first header will be subtracted …
43194 … 0x1f0a10UL //Access:RW DataWidth:0x1 // Per-Port: If set and clas…
43195 … 0x1f0a14UL //Access:RW DataWidth:0x8 // Per-Port: If classification failed, for each bi…
43196 …-Port: If classification failed, for each bit set, the length of the corresponding tag in the firs…
43197 … 0x1f0a1cUL //Access:RW DataWidth:0x20 // Per-PF: This value is passed to the per-PF …
43198 … 0x1f0a20UL //Access:RW DataWidth:0x2 // Per-Port: This value goes…
43199 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 0. In …
43200 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 0. In 4…
43201 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 1. In …
43202 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 1. In 4…
43203 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 2. In …
43204 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 2. In 4…
43205 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 3. In …
43206 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 3. In 4…
43207 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 4. In …
43208 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 4. In 4…
43209 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 5. In …
43210 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 5. In 4…
43211 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 6. In …
43212 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 6. In 4…
43213 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 7. In …
43214 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 7. In 4…
43215 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 8. In 4…
43216 … 0x1f0a68UL //Access:RW DataWidth:0x3 // bit 0 - ignore for VXLAN, bit 1 - ignore for NGE, …
43220 …UL //Access:RC DataWidth:0x18 // The number of processed packets for TC 1. Counts packets as …
43228 … 0x1f0b30UL //Access:WB_R DataWidth:0x80 // Debug only: Empty_flag for eac…
43230 … 0x1f0b40UL //Access:WB_R DataWidth:0x80 // Debug only: Full_flag for each…
43232 … 0x1f0b50UL //Access:R DataWidth:0x6 // Debug only: Parser pipeline pa…
43233 …only (per-port): Packet available status of the main and loopback queues of each traffic class, be…
43234 …taWidth:0x18 // Debug only (per-port): STORM backpressure status (blocked priorities) Each set b…
43235 … 0x1f0b5cUL //Access:R DataWidth:0x1 // Debug only: BRB has asserted …
43236 …only: In case of LCID validation error, the current value of the single entry in the CID load mini…
43238 … 0x1f0b68UL //Access:R DataWidth:0xd // Debug only: In the case of a mini-cache L…
43240 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
43241 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
43244 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
43245 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
43250 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
43251 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
43252 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
43253 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
43258 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
43259 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
43260 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
43261 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
43266 …only : Read access to a FIFO containing information from the last 32 pkts sent to TCM: Reserved - …
43269 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
43270 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
43273 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
43274 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
43281 … 0x1f0f0cUL //Access:R DataWidth:0x8 // Debug only: PTLD current credi…
43282 … 0x1f0f0cUL //Access:R DataWidth:0x8 // Debug only: TCM current credit…
43283 … 0x1f0f10UL //Access:R DataWidth:0x8 // Debug only: CCFC search reques…
43284 … 0x1f0f14UL //Access:R DataWidth:0x8 // Debug only: TCFC search reques…
43285 …h:0x1 // Debug only: CCFC load request current credit. Transaction based. Since the credit limi…
43286 …:0x1 // Debug only: TCFC load request current credit. Transaction based. Since the credit limi…
43287 … 0x1f0f20UL //Access:R DataWidth:0x8 // Debug only: The number of outs…
43288 … 0x1f0f24UL //Access:R DataWidth:0x8 // Debug only: The number of outs…
43289 … 0x1f0f28UL //Access:R DataWidth:0x8 // Debug only: The number of outs…
43290 … 0x1f0f2cUL //Access:R DataWidth:0x8 // Debug only: The number of outs…
43291 … 0x1f0f30UL //Access:R DataWidth:0x3 // Debug only: Outstanding SOP re…
43292 … 0x1f0f34UL //Access:R DataWidth:0x3 // Debug only: Outstanding EOP re…
43294 … 0x1f0f3cUL //Access:R DataWidth:0x8 // Debug only: RGFS current credi…
43303 … 0x1f0f8cUL //Access:R DataWidth:0x20 // Provides read-only access to the BIST…
43307 …-encasulated packet): 40.Source MAC 39.Destination MAC 38.VLAN (12b) ) � Tag 1 37.Provider VLAN (1…
43309 …1-14 data 14-11 PF ID (3bit BB 4bit K2) 10-7 Tunnel type (4b) 0000-no tunnel 0001-vxlan 0010-GRE M…
43324 …ld the priority field in the GFT used frame fields inner header 0- use CVLAN priority 1- use SVLAN…
43325 …d the priority field in the GFT used frame fields tunnel header 0- use CVLAN priority 1- use SVLAN…
43326 … 0x1f11bcUL //Access:RW DataWidth:0x1 // Per-PF: Enables gft searc…
43327 … 0x1f11c0UL //Access:RW DataWidth:0x1 // Per-PF: Enables gft search for non-IP packets. On…
43332 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43336 … 0x1f11ccUL //Access:RW DataWidth:0x1 // When set to 1 the gft cam hit pari…
43337 … 0x1f11d0UL //Access:RW DataWidth:0x1 // When set to 1 the gft cam miss par…
43339 …DataWidth:0x3 // compare the GRE version field to gre_version register if compare_gre_version=1.
43379 …// Context region for received Ethernet packet with a match and packet type 1. Used in CFC load re…
43380 …// Context region for received Ethernet packet with a match and packet type 1. Used in CFC load re…
43431 …:0x8 // Context region for pure acknowledge packets with connection type 1. Used in CFC load re…
43432 …:0x8 // Context region for pure acknowledge packets with connection type 1. Used in CFC load re…
43455 …Width:0x8 // The increment value to send in the CCFC load request message for connection type 1.
43456 …Width:0x8 // The increment value to send in the CCFC load request message for connection type 1.
43481 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43487 … (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 1
43489 …d connection type 1. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - …
43497 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43505 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43513 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43521 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43529 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43537 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43544 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43551 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43558 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43565 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43572 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43579 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43586 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43593 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43601 … // Ordered list of building blocks in TSTORM message for connection type 1. Unused blocks must …
43602 …20 // Ordered list of building blocks in PTLD message for connection type 1. Unused blocks must …
43603 … // Ordered list of building blocks in TSTORM message for connection type 1. Unused blocks must …
43604 …10 // Ordered list of building blocks in PTLD message for connection type 1. Unused blocks must …
43648 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43661 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43674 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43685 …Access:RW DataWidth:0x1 // 1- perform L2 CRC hash on TCP 4 tuple. 0- perform L2 CRC hash on I…
43686 …Access:RW DataWidth:0x1 // 1- perform L2 CRC hash on UDP 4 tuple. 0- perform L2 CRC hash on I…
43706 …ataWidth:0x1 // Burst mode enabled. Set this bits to have the main round-robin arbiter stays o…
43711 … (0x1<<1) // Receive enable.
43712 …MAC_REG_CTRL_RX_EN_BB_SHIFT 1
43713 …rom TX to RX. This loopback is on the line side after clock domain crossing - from the last TX pip…
43715 …om TX to RX. This loopback is on the core side before clock domain crossing - from the first TX pi…
43717 …om RX to TX. This loopback is on the line side before clock domain crossing - from the first RX pi…
43719 …rom RX to TX. This loopback is on the core side after clock domain crossing - from the last RX pip…
43721 … (0x1<<6) // Resets the MAC logic annd status registers only.
43729 … (0x1<<10) // Resets the RS layer functionality - fault handling.
43731 …olumn idle/sequence ordered set check before SOP in XGMII mode - effectively supporting 1 byte IPG…
43733 …; indicates that link is active. When this transitions from 0 to 1; EEE FSM waits for 1 second bef…
43766 …LE_LENGTH_BB (0xf<<1) // Number of preamb…
43767 …MAC_REG_TX_CTRL_HI_TX_PREAMBLE_LENGTH_BB_SHIFT 1
43775 … (0x1<<1) // True to allow any non-Idle cha…
43776 …MAC_REG_RX_CTRL_RX_ANY_START_BB_SHIFT 1
43779 …the MAC checks for IEEE Ethernet format premable - K.SOP + 5 '55' premable bytes + 'D5' SFD charac…
43783 … is reduced to 18 bytes from the default 33 bytes - Should be used in MACSEC chips with IEEE mode …
43798 …_VLAN_TAG_ENABLE_BB (0x1<<1) // Enables VLAN tag…
43799 …MAC_REG_RX_VLAN_TAG_HI_OUTER_VLAN_TAG_ENABLE_BB_SHIFT 1
43803 …AULT_DISABLE_BB (0x1<<1) // True to disable …
43804 …MAC_REG_RX_LSS_CTRL_REMOTE_FAULT_DISABLE_BB_SHIFT 1
43805 …; the TX faults inputs are used to send out fault sequences - else receive faults are used -- used…
43820 …_FAULT_STATUS_BB (0x1<<1) // True while 'remo…
43821 …MAC_REG_RX_LSS_STATUS_REMOTE_FAULT_STATUS_BB_SHIFT 1
43825 … (0x1<<0) // A rising edge on this register bit (0->1); clears the sticky LOCAL_FAULT_STATUS…
43827 … (0x1<<1) // A rising edge on this register bit (0->1); clears the sticky …
43828 …MAC_REG_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_BB_SHIFT 1
43829 … (0x1<<2) // A rising edge on this register bit (0->1); clears the sticky LINK_INTERRUPTION_STA…
43832 …<<0) // This field is Threshold for pause timer to cause XOFF to be resent (Unit is 512 bit-times).
43844 …use_xoff_timer register. Time value sent in the Timer Field for XOFF state (Unit is 512 bit-times).
43846 …use_xoff_timer register. Time value sent in the Timer Field for XOFF state (Unit is 512 bit-times).
43848 … (0xffff<<0) // Threshold for pause timer to cause XOFF to be resent (Unit is 512 bit-times).
43850 …xffff<<16) // Time value sent in the Timer Field for classes in XOFF state (Unit is 512 bit-times).
43853 … (0x1<<0) // Enable automatic re-send of PFC packet af…
43855 …C_XON_BB (0x1<<1) // Instructs the MA…
43856 …MAC_REG_PFC_CTRL_HI_FORCE_PFC_XON_BB_SHIFT 1
43870 … (0x1<<0) // This bit enables llfc for Tx…
43872 … (0x1<<1) // This bit enables llfc f…
43873 …MAC_REG_LLFC_CTRL_RX_LLFC_EN_BB_SHIFT 1
43874 … (0x1<<2) // When set; LLFC is inserted only during IPG.
43876 … (0x1<<3) // When set and llfc_in_ipg_only =0; GXPORT operates in cut-through mode.
43878 … (0x1<<4) // This bit if set to 1; disables the…
43901 … (0x1<<0) // This bit enables HCFC for Tx…
43903 … (0x1<<1) // This bit enables HCFC f…
43904 …MAC_REG_HCFC_CTRL_RX_HCFC_EN_BB_SHIFT 1
43905 … (0x1<<2) // The crc check for HCFC messages is ignored if this bit is set.
43909 … (0x1<<4) // If 1; the HCFC packets ar…
43918 …VERFLOW_BB (0x1<<1) // Indicates rx mes…
43919 …MAC_REG_FIFO_STATUS_RX_MSG_OVERFLOW_BB_SHIFT 1
43928 … (0x1<<7) // This bit indicates the link …
43931 … (0x1<<0) // A rising edge on this register bit (0->1); clears the sticky RX_PKT_OVERFLOW stat…
43933 … (0x1<<1) // A rising edge on this register bit (0->1); clears the sticky R…
43934 …MAC_REG_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_BB_SHIFT 1
43935 … (0x1<<2) // A rising edge on this register bit (0->1); clears the sticky TX_PKT_UNDERFLOW sta…
43937 … (0x1<<3) // A rising edge on this register bit (0->1); clears the sticky TX_PKT_OVERFLOW stat…
43939 … (0x1<<4) // A rising edge on this register bit (0->1); clears the sticky TX_HCFC_MSG_OVERFLOW s…
43941 … (0x1<<5) // A rising edge on this register bit (0->1); clears the sticky TX_LLFC_MSG_OVERFLOW s…
43943 … (0x1<<6) // A rising edge on this register bit (0->1); clears the sticky TX_TS_FIFO_OVERFLOW st…
43946 … (0x3f<<0) // Credits for TX FIFO; used by Ports 0/1/2/3 in quad port mod…
43955 …_TX_PAUSE_XOFF_BB (0x1<<1) // If set; EEE FSM …
43956 …MAC_REG_EEE_CTRL_EEE_DISABLE_TX_PAUSE_XOFF_BB_SHIFT 1
43965 …k divider used to generate ~1us reference pulses used by EEE timers. It specifies integer number o…
43967 …transitioning to ACTIVE state. This is in terms of micro seconds. Default value is set to 1 second.
43971 …BB (0x1<<16) // When set to 1; enables LP_IDLE Pre…
43973 … (0x1<<17) // When set to 1; GMII interface will…
43976 … (0x1<<0) // If set; each data frame is transmitted only after the correspon…
43978 …C_TX_CRC_CORRUPT_EN_BB (0x1<<1) // Setting this fie…
43979 …MAC_REG_MACSEC_CTRL_LO_MACSEC_TX_CRC_CORRUPT_EN_BB_SHIFT 1
43980 … (0x1<<2) // In CRC corruption mode; if this bit is set; replaces co…
43985 … 0x210130UL //Access:RW DataWidth:0x10 // XMAC IP Version ID - corresponds to RTL/D…
43986 …thods mus be used at this location. The fields within this WB register are: 1:0=XMAC CRC_MODE; 2:2…
43996 …ion. The fields within this WB register are: 0:0=XMAC MACSEC_TX_LAUNCH_EN; 1:1=XMAC MACSEC_TX_CRC_…
43998 … 0x210800UL //Access:RW DataWidth:0x20 // This is the XMAC for port 1.
44003 … (0x1<<0) // 0: NIG port inactive 1: NIG prot active
44005 … (0x3<<1) // 00: Map to NWM port 0 01: Map to NWM po…
44006 …NIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT 1
44007 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100…
44011 …2_E5 (0x1<<7) // This bit controls the option…
44013 …T_EN_0_K2_E5 (0x1<<8) // This bit controls the option…
44015 …T_ON_ERROR_0_K2_E5 (0x1<<9) // This bit controls the option…
44017 …bit controls the option for enabling rate limitation on the CNIG TX data path via controlling the …
44019 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44021 …1 : 2x50G (BB), 2x20G (K2) 2 : 1x100G (BB), 1x40G (K2) 3 : 4x10G_F (BB) (10G with 4x25 SERDES) NA …
44023 … (0x1<<0) // 0: NIG port inactive 1: NIG prot active
44025 … (0x3<<1) // 00: Map to NWM port 0 01: Map to NWM po…
44026 …NIG_REG_NIG_PORT1_CONF_NIG_PORT_NWM_PORT_MAP_1_K2_E5_SHIFT 1
44027 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100…
44031 …2_E5 (0x1<<7) // This bit controls the option…
44033 …T_EN_1_K2_E5 (0x1<<8) // This bit controls the option…
44035 …T_ON_ERROR_1_K2_E5 (0x1<<9) // This bit controls the option…
44037 …bit controls the option for enabling rate limitation on the CNIG TX data path via controlling the …
44039 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44041 … connects to Engine 0 and 4x10 SERDES connects to Engine 1 1 : 4x25 SERDES connects to Engine 1 an…
44043 … (0x1<<0) // 0: NIG port inactive 1: NIG prot active
44045 … (0x3<<1) // 00: Map to NWM port 0 01: Map to NWM po…
44046 …NIG_REG_NIG_PORT2_CONF_NIG_PORT_NWM_PORT_MAP_2_K2_E5_SHIFT 1
44047 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100…
44051 …2_E5 (0x1<<7) // This bit controls the option…
44053 …T_EN_2_K2_E5 (0x1<<8) // This bit controls the option…
44055 …T_ON_ERROR_2_K2_E5 (0x1<<9) // This bit controls the option…
44057 …bit controls the option for enabling rate limitation on the CNIG TX data path via controlling the …
44059 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44062 …B (0x1<<0) // 1 : Memory Access 0 : …
44064 …_BB (0x1<<1) // Setting this bit to 1 tells t…
44065 …NIG_REG_PMFC_IF_CMD_PMFC_IF_ADDR_AUTO_INC_BB_SHIFT 1
44068 …bit register is considered a single register, the next 64 bit register will be at addr+1. This reg…
44075 … (0x1<<0) // 0: NIG port inactive 1: NIG prot active
44077 … (0x3<<1) // 00: Map to NWM port 0 01: Map to NWM po…
44078 …NIG_REG_NIG_PORT3_CONF_NIG_PORT_NWM_PORT_MAP_3_K2_E5_SHIFT 1
44079 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100…
44083 …2_E5 (0x1<<7) // This bit controls the option…
44085 …T_EN_3_K2_E5 (0x1<<8) // This bit controls the option…
44087 …T_ON_ERROR_3_K2_E5 (0x1<<9) // This bit controls the option…
44089 …bit controls the option for enabling rate limitation on the CNIG TX data path via controlling the …
44091 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44094 …Y_BB (0x1<<0) // 1 : State Machine is b…
44096 …DONE_BB (0x1<<1) // 1 : State Machine h…
44097 …NIG_REG_PMFC_IF_STATUS_PMFC_IF_DONE_BB_SHIFT 1
44098 …OR_BB (0x1<<2) // 1 : Last transaction r…
44101 …1<<0) // This regiseter enables loopback mode (used for debug) 0 - loopback inactive 1 - loopback …
44103 …1) // 0: mode0 is used with the following loopback mapping: NIG TX port 0 => NIG RX port 0 NIG TX …
44104 …NIG_REG_LOOPBACK_MODE_LOOPBACK_MODE_K2_E5_SHIFT 1
44105 … IF transaction. For Register Access 31:26 : Stage ID 25:25 : Register Type 1 = Generic Register, …
44107 … (0x1<<0) // Set to 1 for masking invlaid …
44109 … (0x1<<1) // Set to 1 for masking cr…
44110 …NIG_REG_NWM_ERROR_MASK_CRC_K2_E5_SHIFT 1
44111 … (0x1<<2) // Set to 1 for masking decoding…
44113 … (0x1<<3) // Set to 1 for masking fifo ove…
44115 … (0x1<<4) // Set to 1 for masking remote e…
44117 … (0x1<<5) // Set to 1 for masking vlan tag…
44119 …K2_E5 (0x1<<6) // Set to 1 for masking vlan tra…
44121 …E5 (0x1<<7) // Set to 1 for masking vlan err…
44128 …e ADD CRC PORT STM occurs. It can result if a packet size is less than 256bit is sent by NIG (whi…
44130 …OP_PORT0_K2_E5 (0x1<<1) // This interrupt i…
44131 …NIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT0_K2_E5_SHIFT 1
44134 …e ADD CRC PORT STM occurs. It can result if a packet size is less than 256bit is sent by NIG (whi…
44144 … (0x1<<1) // Interrupt from P…
44145 …NIG_REG_INT_STS_PMEG_INTR_BB_SHIFT 1
44153 … (0x1<<0) // This bit masks, when set, the Interrupt bit: C…
44155 … (0x1<<4) // This bit masks, when set, the Interrupt bit: C…
44157 … (0x1<<1) // This bit masks, when set, the Interrupt …
44158 …NIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT0_K2_E5_SHIFT 1
44159 … (0x1<<2) // This bit masks, when set, the Interrupt bit: C…
44161 … (0x1<<5) // This bit masks, when set, the Interrupt bit: C…
44163 … (0x1<<3) // This bit masks, when set, the Interrupt bit: C…
44165 … (0x1<<4) // This bit masks, when set, the Interrupt bit: C…
44167 … (0x1<<5) // This bit masks, when set, the Interrupt bit: C…
44169 … (0x1<<6) // This bit masks, when set, the Interrupt bit: C…
44171 … (0x1<<1) // This bit masks, when set, the Interrupt …
44172 …NIG_REG_INT_MASK_PMEG_INTR_BB_SHIFT 1
44173 … (0x1<<2) // This bit masks, when set, the Interrupt bit: C…
44175 … (0x1<<3) // This bit masks, when set, the Interrupt bit: C…
44178 …B (0x1<<0) // 1 : Memory Access 0 : …
44180 …_BB (0x1<<1) // Setting this bit to 1 tells t…
44181 …NIG_REG_PMEG_IF_CMD_PMEG_IF_ADDR_AUTO_INC_BB_SHIFT 1
44184 …bit register is considered a single register, the next 64 bit register will be at addr+1. This reg…
44194 …e ADD CRC PORT STM occurs. It can result if a packet size is less than 256bit is sent by NIG (whi…
44196 …L_SOP_PORT0_K2_E5 (0x1<<1) // This interrupt i…
44197 …NIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT0_K2_E5_SHIFT 1
44200 …e ADD CRC PORT STM occurs. It can result if a packet size is less than 256bit is sent by NIG (whi…
44210 …_BB (0x1<<1) // Interrupt from P…
44211 …NIG_REG_INT_STS_WR_PMEG_INTR_BB_SHIFT 1
44217 …Y_BB (0x1<<0) // 1 : State Machine is b…
44219 …DONE_BB (0x1<<1) // 1 : State Machine h…
44220 …NIG_REG_PMEG_IF_STATUS_PMEG_IF_DONE_BB_SHIFT 1
44221 …OR_BB (0x1<<2) // 1 : Last transaction r…
44227 …e ADD CRC PORT STM occurs. It can result if a packet size is less than 256bit is sent by NIG (whi…
44229 …AL_SOP_PORT0_K2_E5 (0x1<<1) // This interrupt i…
44230 …NIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT0_K2_E5_SHIFT 1
44233 …e ADD CRC PORT STM occurs. It can result if a packet size is less than 256bit is sent by NIG (whi…
44243 …R_BB (0x1<<1) // Interrupt from P…
44244 …NIG_REG_INT_STS_CLR_PMEG_INTR_BB_SHIFT 1
44249 … IF transaction. For Register Access 31:26 : Stage ID 25:25 : Register Type 1 = Generic Register, …
44255 … (0x1<<1) // This bit masks, when set, the Parity bi…
44256 …NIG_REG_PRTY_MASK_DATAPATH_TX_SHIFT 1
44257 … (0x1<<0) // This bit masks, when set, the Parity bit: CN…
44262 …re control of the Traffic LED. The Traffic LED will then be controlled via bit LED_CONTROL_TRAFFIC…
44264 …ng with the LED_CONTROL_OVERRIDE_TRAFFIC bit turns on the Traffic LED. If the LED_CONTROL_BLINK_TR…
44266 … Port0: If set along with the LED_CONTROL_OVERRIDE_TRAFFIC bit and LED_CONTROL_TRAFFIC LED bit; th…
44268 … (0x1<<12) // This bit is set to enable the use of the LED_CONTROL_BLINK_RATE field de…
44270 … cycle (on + off) for Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field is …
44272 … DataWidth:0x8 // This register enable to read and write the cosmap 8 bit value for each NWM …
44274 … // Led mode: 0 -> MAC; 1-3 -> PHY1; 4 -> MAC2; 5-7 -> PHY4; 8 -> MAC3; 9 -…
44275 … // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 1…
44276 … // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 1…
44277 … // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 1…
44280 …-> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused Th…
44283 …only two sets of the the bits below are valid. a Four port device has all four sets of bits valid.…
44285 … Network Port 1 to the corresponding Physical function. 0 -> NW1 connects to PF0 1 -> NW1 connec…
44287 … corresponding Physical function. 0 -> NW2 connects to PF0 1 -> NW2 connects to PF1 2 -> NW2 co…
44289 … corresponding Physical function. 0 -> NW3 connects to PF0 1 -> NW3 connects to PF1 2 -> NW3 co…
44291 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
44292 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44293 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
44294 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44295 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
44296 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44297 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
44298 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44299 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44300 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44301 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44302 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44303 …h:0x1 // When set, PMIF block uses values in following registers to configure NIG - PM interface
44304 … // These bits are used to set which NIG Ports are used with the PM4x10. A 1'b0 in these bits ind…
44307 …NIG port is assigned to each PMEG Port. [1:0] -- PMEG Port 0 [3:2] -- PMEG Port 1 [5:4] -- PMEG Po…
44308 …NIG port is assigned to each PMFC Port. [1:0] -- PMFC Port 0 [3:2] -- PMFC Port 1 [5:4] -- PMFC Po…
44309 …MEG Port ID every cycle. Valid values are: 0 -- Only Port 0 is used 1 -- All Ports (0-3) are used …
44310 …MFC Port ID every cycle. Valid values are: 0 -- Only Port 0 is used 1 -- All Ports (0-3) are used …
44313 …th:0x6 // This register sets the Threshold level for Tx Credits from the 1x40 PM. Data will not…
44314 …0x5 // This register latches the FIFO Error bits from the PMFC Rx FIFO (bit [4]) and the NIG Tx…
44372 … // PMEG timestamp local counter reset. If = 0, the timers is reset. If = 1, the timer is out of…
44373 … // PMFC timestamp local counter reset. If = 0, the timers is reset. If = 1, the timer is out of…
44374 …this mode can be active only for PMFC ports 0,2 and should be used for 100G or 2x50G NW modes. Bit…
44375 …this mode can be active only for PMFC ports 0,2 and should be used for 100G or 2x50G NW modes. Bit…
44376 …only for PMFC ports 0,2 and should be used for 100G or 2x50G NW modes. b. As result of parity erro…
44377 …only for PMFC ports 0,2 and should be used for 100G or 2x50G NW modes. b. As result of parity erro…
44387 … (0x1<<1) // Overrun/underrun…
44388 …RM_REG_INT_STS_IFIFO_ERROR_SHIFT 1
44399 … (0x1<<9) // FIFO overflow/underflow error on M-Storm command interfa…
44401 … (0x1<<10) // FIFO overflow/underflow error on U-Storm command interfa…
44403 … (0x1<<7) // End of packet error on M-Storm command interfa…
44405 … (0x1<<8) // End of packet error on U-Storm command interfa…
44408 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
44410 … (0x1<<1) // This bit masks, when set, the Interrupt …
44411 …RM_REG_INT_MASK_IFIFO_ERROR_SHIFT 1
44412 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
44414 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
44416 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
44418 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
44420 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
44422 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
44424 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
44426 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
44428 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
44433 …R (0x1<<1) // Overrun/underrun…
44434 …RM_REG_INT_STS_WR_IFIFO_ERROR_SHIFT 1
44445 … (0x1<<9) // FIFO overflow/underflow error on M-Storm command interfa…
44447 … (0x1<<10) // FIFO overflow/underflow error on U-Storm command interfa…
44449 … (0x1<<7) // End of packet error on M-Storm command interfa…
44451 … (0x1<<8) // End of packet error on U-Storm command interfa…
44456 …OR (0x1<<1) // Overrun/underrun…
44457 …RM_REG_INT_STS_CLR_IFIFO_ERROR_SHIFT 1
44468 … (0x1<<9) // FIFO overflow/underflow error on M-Storm command interfa…
44470 … (0x1<<10) // FIFO overflow/underflow error on U-Storm command interfa…
44472 … (0x1<<7) // End of packet error on M-Storm command interfa…
44474 … (0x1<<8) // End of packet error on U-Storm command interfa…
44477 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
44480 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
44482 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
44484 … (0x1<<1) // This bit masks, when set, the Parity bi…
44485 …RM_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_K2_E5_SHIFT 1
44486 … (0x1<<1) // This bit masks, when set, the Parity bi…
44487 …RM_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_BB_SHIFT 1
44488 … (0x1<<2) // This bit masks, when set, the Parity bit: PR…
44490 … (0x1<<3) // This bit masks, when set, the Parity bit: PR…
44492 … (0x1<<13) // This bit masks, when set, the Parity bit: PR…
44494 … (0x1<<4) // This bit masks, when set, the Parity bit: PR…
44496 … (0x1<<5) // This bit masks, when set, the Parity bit: PR…
44498 … (0x1<<7) // This bit masks, when set, the Parity bit: PR…
44500 … (0x1<<6) // This bit masks, when set, the Parity bit: PR…
44502 … (0x1<<6) // This bit masks, when set, the Parity bit: PR…
44504 … (0x1<<7) // This bit masks, when set, the Parity bit: PR…
44506 … (0x1<<18) // This bit masks, when set, the Parity bit: PR…
44508 … (0x1<<8) // This bit masks, when set, the Parity bit: PR…
44510 … (0x1<<8) // This bit masks, when set, the Parity bit: PR…
44512 … (0x1<<9) // This bit masks, when set, the Parity bit: PR…
44514 … (0x1<<9) // This bit masks, when set, the Parity bit: PR…
44516 … (0x1<<10) // This bit masks, when set, the Parity bit: PR…
44518 … (0x1<<11) // This bit masks, when set, the Parity bit: PR…
44520 … (0x1<<11) // This bit masks, when set, the Parity bit: PR…
44522 … (0x1<<6) // This bit masks, when set, the Parity bit: PR…
44524 … (0x1<<12) // This bit masks, when set, the Parity bit: PR…
44526 … (0x1<<10) // This bit masks, when set, the Parity bit: PR…
44528 … (0x1<<12) // This bit masks, when set, the Parity bit: PR…
44530 … (0x1<<13) // This bit masks, when set, the Parity bit: PR…
44532 … (0x1<<14) // This bit masks, when set, the Parity bit: PR…
44534 … (0x1<<13) // This bit masks, when set, the Parity bit: PR…
44536 … (0x1<<14) // This bit masks, when set, the Parity bit: PR…
44538 … (0x1<<20) // This bit masks, when set, the Parity bit: PR…
44540 … (0x1<<14) // This bit masks, when set, the Parity bit: PR…
44542 … (0x1<<15) // This bit masks, when set, the Parity bit: PR…
44544 … (0x1<<4) // This bit masks, when set, the Parity bit: PR…
44546 … (0x1<<15) // This bit masks, when set, the Parity bit: PR…
44548 … (0x1<<16) // This bit masks, when set, the Parity bit: PR…
44550 … (0x1<<17) // This bit masks, when set, the Parity bit: PR…
44552 … (0x1<<15) // This bit masks, when set, the Parity bit: PR…
44554 … (0x1<<17) // This bit masks, when set, the Parity bit: PR…
44556 … (0x1<<18) // This bit masks, when set, the Parity bit: PR…
44558 … (0x1<<17) // This bit masks, when set, the Parity bit: PR…
44560 … (0x1<<18) // This bit masks, when set, the Parity bit: PR…
44562 … (0x1<<19) // This bit masks, when set, the Parity bit: PR…
44564 … (0x1<<19) // This bit masks, when set, the Parity bit: PR…
44566 … (0x1<<20) // This bit masks, when set, the Parity bit: PR…
44568 … (0x1<<5) // This bit masks, when set, the Parity bit: PR…
44570 … (0x1<<21) // This bit masks, when set, the Parity bit: PR…
44572 … (0x1<<22) // This bit masks, when set, the Parity bit: PR…
44574 … (0x1<<23) // This bit masks, when set, the Parity bit: PR…
44576 … (0x1<<23) // This bit masks, when set, the Parity bit: PR…
44578 … (0x1<<21) // This bit masks, when set, the Parity bit: PR…
44580 … (0x1<<24) // This bit masks, when set, the Parity bit: PR…
44582 … (0x1<<22) // This bit masks, when set, the Parity bit: PR…
44584 … (0x1<<20) // This bit masks, when set, the Parity bit: PR…
44586 … (0x1<<25) // This bit masks, when set, the Parity bit: PR…
44588 … (0x1<<3) // This bit masks, when set, the Parity bit: PR…
44590 … (0x1<<16) // This bit masks, when set, the Parity bit: PR…
44592 … (0x1<<5) // This bit masks, when set, the Parity bit: PR…
44594 … (0x1<<21) // This bit masks, when set, the Parity bit: PR…
44596 … (0x1<<16) // This bit masks, when set, the Parity bit: PR…
44598 … (0x1<<2) // This bit masks, when set, the Parity bit: PR…
44600 … (0x1<<3) // This bit masks, when set, the Parity bit: PR…
44602 … (0x1<<12) // This bit masks, when set, the Parity bit: PR…
44604 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
44605 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
44606 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
44607 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
44608 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
44609 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
44615 …13_I_ECC_EN_K2_E5 (0x1<<1) // Enable ECC for m…
44616 …RM_REG_MEM_ECC_ENABLE_0_MEM013_I_ECC_EN_K2_E5_SHIFT 1
44617 …14_I_ECC_EN_BB (0x1<<1) // Enable ECC for m…
44618 …RM_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN_BB_SHIFT 1
44630 …K2_E5 (0x1<<0) // Set parity only for memory ecc inst…
44632 …BB (0x1<<0) // Set parity only for memory ecc inst…
44634 …ECC_PRTY_K2_E5 (0x1<<1) // Set parity only for memory…
44635 …RM_REG_MEM_ECC_PARITY_ONLY_0_MEM013_I_ECC_PRTY_K2_E5_SHIFT 1
44636 …ECC_PRTY_BB (0x1<<1) // Set parity only for memory…
44637 …RM_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY_BB_SHIFT 1
44638 …K2_E5 (0x1<<2) // Set parity only for memory ecc inst…
44640 …E5 (0x1<<3) // Set parity only for memory ecc inst…
44642 …K2 (0x1<<3) // Set parity only for memory ecc inst…
44644 …BB (0x1<<2) // Set parity only for memory ecc inst…
44646 …BB (0x1<<3) // Set parity only for memory ecc inst…
44653 …ED_0_MEM013_I_ECC_CORRECT_K2_E5 (0x1<<1) // Record if a corr…
44654 …RM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM013_I_ECC_CORRECT_K2_E5_SHIFT 1
44655 …ED_0_MEM014_I_ECC_CORRECT_BB (0x1<<1) // Record if a corr…
44656 …RM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT_BB_SHIFT 1
44668 …to remove in bytes will be defined by the following: size (bytes) = (tag_sz+1)*2. Note: there is n…
44670 … 0x230420UL //Access:RW DataWidth:0x10 // Provides the value of the 16-bit pad that will be in…
44671 … 0x230424UL //Access:RW DataWidth:0x1 // When set, this bit enables the pad ins…
44673 … Initial credit to be used on the RDIF command interface for regular (non-pass-through) requests. …
44674 …on the RDIF command interface for pass-through requests. This value defines the maximum number of …
44678 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
44679 …th:0x9 // Defines the number of occupied entries required in the PXP read-response FIFO before …
44680 … DataWidth:0x20 // Statistics counter provides a count of the number of M-Storm comands that ha…
44681 … DataWidth:0x20 // Statistics counter provides a count of the number of U-Storm comands that ha…
44706 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
44707 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
44708 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
44709 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
44710 … 0x232000UL //Access:WB_R DataWidth:0x80 // Provides read-only access of the M-Storm comma…
44712 … 0x232400UL //Access:WB_R DataWidth:0x80 // Provides read-only access of the U-Storm comma…
44714 … 0x232800UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the BRB …
44716 … 0x232c00UL //Access:R DataWidth:0x7 // Provides read-only access of the BRB …
44718 … 0x233000UL //Access:WB_R DataWidth:0x2c // Provides read-only access of the tag …
44720 … 0x233400UL //Access:R DataWidth:0x11 // Provides read-only access of the pad …
44722 … 0x233600UL //Access:R DataWidth:0xb // Provides read-only access of the PB i…
44724 … 0x233800UL //Access:WB_R DataWidth:0x100 // Provides read-only access of the PRM …
44726 … 0x233c00UL //Access:R DataWidth:0x8 // Provides read-only access of the PXP write-done re…
44730 … 0x236000UL //Access:RW DataWidth:0x1 // Chicken Bit for the NOP without…
44732 … (0xff<<0) // Number of Concurrent Processes (State Machines); Values can be 1 to 25.
44736 …able for VLAN in Hash Address. !!! NOTE : vlan_hash_enable == 1 and vlan_match_disable == 1 is ill…
44738 …uous Mode (vpf) matching logic.!!! NOTE : vlan_hash_enable == 1 and vlan_match_disable == 1 is ill…
44746 …sable Tenant ID Matching Logic.NOTE : tenant_id_in_hash_en == 1 and tenant_id_disable == 1 is ille…
44748 …n Hash address calculation.!!! NOTE : tenant_id_in_hash_en == 1 and tenant_id_disable == 1 is ille…
44760 … (0x1<<0) // This bit masks, when set, the Interrupt bit: S…
44773 … 0x238480UL //Access:RW DataWidth:0x10 // Per-PF Bitmask for inclus…
44774 … 0x238484UL //Access:RW DataWidth:0x8 // Per-StringType Bitmask fo…
44775 …Bit. IF Stat Counters only count when this bit is set. This bit is cleared when any IF Stat C…
44777 …h:0x20 // IF Stat Hit Counter. This register counts all Search Hits on both Table 1 and Table 2.
44778 … DataWidth:0x20 // IF Stat T1 Hit Counter. This register counts all Search Hits on Table 1 only.
44799 … 0x238620UL //Access:RW DataWidth:0x20 // Empty bit per bin 256 bins pe…
44802 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
44803 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
44804 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
44805 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
44817 …_E5 (0x1<<1) // RGFS input inter…
44818 …SS_REG_IF_ENABLE_RGFS_INP_EN_E5_SHIFT 1
44823 …_BB_K2 (0x1<<1) // TSEM input inter…
44824 …SS_REG_IF_ENABLE_TSEM_INP_EN_BB_K2_SHIFT 1
44860 …RROR_BB_K2 (0x1<<1) // Number of cycles…
44861 …SS_REG_INT_STS_MSG_INP_CNT_ERROR_BB_K2_SHIFT 1
44873 … (0x1<<0) // This bit masks, when set, the Interrupt bit: R…
44875 … (0x1<<7) // This bit masks, when set, the Interrupt bit: R…
44877 … (0x1<<8) // This bit masks, when set, the Interrupt bit: R…
44879 … (0x1<<9) // This bit masks, when set, the Interrupt bit: R…
44881 … (0x1<<10) // This bit masks, when set, the Interrupt bit: R…
44883 … (0x1<<11) // This bit masks, when set, the Interrupt bit: R…
44885 … (0x1<<12) // This bit masks, when set, the Interrupt bit: R…
44887 … (0x1<<13) // This bit masks, when set, the Interrupt bit: R…
44889 … (0x1<<14) // This bit masks, when set, the Interrupt bit: R…
44891 … (0x1<<15) // This bit masks, when set, the Interrupt bit: R…
44893 … (0x1<<16) // This bit masks, when set, the Interrupt bit: R…
44895 … (0x1<<17) // This bit masks, when set, the Interrupt bit: R…
44897 … (0x1<<18) // This bit masks, when set, the Interrupt bit: R…
44899 … (0x1<<19) // This bit masks, when set, the Interrupt bit: R…
44901 … (0x1<<20) // This bit masks, when set, the Interrupt bit: R…
44903 … (0x1<<21) // This bit masks, when set, the Interrupt bit: R…
44905 … (0x1<<1) // This bit masks, when set, the Interrupt …
44906 …SS_REG_INT_MASK_MSG_INP_CNT_ERROR_BB_K2_SHIFT 1
44907 … (0x1<<2) // This bit masks, when set, the Interrupt bit: R…
44909 … (0x1<<3) // This bit masks, when set, the Interrupt bit: R…
44911 … (0x1<<4) // This bit masks, when set, the Interrupt bit: R…
44913 … (0x1<<5) // This bit masks, when set, the Interrupt bit: R…
44915 … (0x1<<6) // This bit masks, when set, the Interrupt bit: R…
44950 …T_ERROR_BB_K2 (0x1<<1) // Number of cycles…
44951 …SS_REG_INT_STS_WR_MSG_INP_CNT_ERROR_BB_K2_SHIFT 1
44995 …NT_ERROR_BB_K2 (0x1<<1) // Number of cycles…
44996 …SS_REG_INT_STS_CLR_MSG_INP_CNT_ERROR_BB_K2_SHIFT 1
45008 … (0x1<<0) // This bit masks, when set, the Parity bit: RS…
45010 … (0x1<<1) // This bit masks, when set, the Parity bi…
45011 …SS_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_E5_SHIFT 1
45012 … (0x1<<2) // This bit masks, when set, the Parity bit: RS…
45014 … (0x1<<3) // This bit masks, when set, the Parity bit: RS…
45016 … (0x1<<4) // This bit masks, when set, the Parity bit: RS…
45018 … (0x1<<5) // This bit masks, when set, the Parity bit: RS…
45020 … (0x1<<0) // This bit masks, when set, the Parity bit: RS…
45022 … (0x1<<1) // This bit masks, when set, the Parity bi…
45023 …SS_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_K2_SHIFT 1
45024 … (0x1<<2) // This bit masks, when set, the Parity bit: RS…
45026 … (0x1<<3) // This bit masks, when set, the Parity bit: RS…
45031 …06_I_ECC_EN_E5 (0x1<<1) // Enable ECC for m…
45032 …SS_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN_E5_SHIFT 1
45039 …01_I_ECC_EN_BB_K2 (0x1<<1) // Enable ECC for m…
45040 …SS_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB_K2_SHIFT 1
45042 …E5 (0x1<<0) // Set parity only for memory ecc inst…
45044 …ECC_PRTY_E5 (0x1<<1) // Set parity only for memory…
45045 …SS_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY_E5_SHIFT 1
45046 …E5 (0x1<<2) // Set parity only for memory ecc inst…
45048 …E5 (0x1<<3) // Set parity only for memory ecc inst…
45050 …BB_K2 (0x1<<0) // Set parity only for memory ecc inst…
45052 …ECC_PRTY_BB_K2 (0x1<<1) // Set parity only for memory…
45053 …SS_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB_K2_SHIFT 1
45057 …ED_0_MEM006_I_ECC_CORRECT_E5 (0x1<<1) // Record if a corr…
45058 …SS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT_E5_SHIFT 1
45065 …ED_0_MEM001_I_ECC_CORRECT_BB_K2 (0x1<<1) // Record if a corr…
45066 …SS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB_K2_SHIFT 1
45070 …ccess:WB DataWidth:0x80 // RSS RAM bit enable. It will be used for write operation from RBC. I…
45074 …s. If bit 12 is 1 then bits 11:0 is addr to RSS indirection memory. If bits 12:10 are 0 then bits …
45076 … // Debug register. FIFO empty status: {b0 - MSG FIFO; b1- RSS CMD FIFO; b2- INPUT FIFO; b3 - RSP…
45077 … // Debug register. FIFO empty status: {b0 - MSG FIFO; b1- RSS CMD FIFO; b2- INPUT FIFO; b3 - RSP…
45078 …0x20 // Debug register. FIFO empty status: {b15:8 - inp_fifo_counter; b7:6- cmd_fifo_couter; b5:…
45079 …ster. State of each state machine {b15:12 - calc_cur_state; b11:8 - main_cur_state;b7:4 - msg_cur_…
45082 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
45083 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
45084 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
45085 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
45097 …_HASH_FIFO_FULL_E5 (0x1<<1) // The ind_hash fif…
45098 …SS_REG_FIFO_FULL_STATUS1_IND_HASH_FIFO_FULL_E5_SHIFT 1
45124 …D_HASH_FIFO_EMPTY_E5 (0x1<<1) // The ind_hash fif…
45125 …SS_REG_FIFO_EMPTY_STATUS1_IND_HASH_FIFO_EMPTY_E5_SHIFT 1
45176 … (0xf<<0) // inp_parse_state delayed 1 clock (rss_inp.v)
45178 … (0xf<<4) // inp_mem_state delayed 1 clock (rss_inp.v)
45180 … (0x3<<8) // calc_state delayed 1 clock (rss_calc.v)
45182 … (0x7<<10) // ind_state delayed 1 clock (rss_ind.v)
45184 … (0x7<<13) // ind_state delayed 1 clock (rss_ind.v)
45186 … (0x7<<16) // out_state delayed 1 clock (rss_out.v)
45191 … (0x1<<1) // EOP check error.
45192 …PB_REG_INT_STS_EOP_ERROR_SHIFT 1
45208 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
45210 … (0x1<<1) // This bit masks, when set, the Interrupt …
45211 …PB_REG_INT_MASK_EOP_ERROR_SHIFT 1
45212 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
45214 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
45216 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
45218 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
45220 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
45222 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
45224 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
45229 … (0x1<<1) // EOP check error.
45230 …PB_REG_INT_STS_WR_EOP_ERROR_SHIFT 1
45248 …R (0x1<<1) // EOP check error.
45249 …PB_REG_INT_STS_CLR_EOP_ERROR_SHIFT 1
45265 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
45268 … (0x1<<0) // Indicates if to switch the CRC result byte ordering. 0=don't switch;1=switch.
45270 …OR (0x1<<1) // Indicates if to …
45271 …PB_REG_CONTROL_DB_IGNORE_ERROR_SHIFT 1
45280 … (0x1<<6) // Debug only: Disable PB.
45284 …H (0x1<<11) // Dbug only.
45286 …ived on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
45288 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
45289 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
45290 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
45291 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
45292 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
45293 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
45294 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
45295 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
45296 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
45297 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
45298 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
45299 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
45310 …bit of this register. Bits 31:29 provide additional information about the instruction. Bit 31 in…
45312 …er being executed at the time EOP error is detected. The task passthrough bit is not kept and is …
45320 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
45321 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
45322 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
45323 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
45324 … 0x23e000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the data…
45328 … 0x240000UL //Access:RW DataWidth:0x1 // Driver should write 1 to this register in …
45329 …s initialization is done. Driver should check this register is 1 some time after writing 1 to rbc_…
45330 …idth:0x1 // MCP writes '1' to this bit to indicate PSWRQ to initialize Steering Tag Table with …
45331 …x4 // Page size in L2P table for CDU-Task module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-51…
45332 … // Page size in L2P table for CDU module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45333 …4 // Page size in L2P table for TM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45334 …4 // Page size in L2P table for QM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45335 … // Page size in L2P table for SRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45336 … // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45337 … // Page size in L2P table for SRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45338 … // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45339 … // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45346 … 0x240048UL //Access:RW DataWidth:0xe // First memory address base for cdu-connection in ILT.
45347 … 0x24004cUL //Access:RW DataWidth:0xe // Last memory address base for cdu-connection in ILT.
45348 … 0x240050UL //Access:RW DataWidth:0xe // First memory address base for cdu-task in ILT.
45349 … 0x240054UL //Access:RW DataWidth:0xe // Last memory address base for cdu-task in ILT.
45359 …:RW DataWidth:0x2 // Requests from all SDM's and DMAE with endian mode 1 will receive the end…
45378 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
45379 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
45380 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
45381 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
45387 … (0x1<<1) // Overflow in l2p input fifo - remo…
45388 …SWRQ2_REG_INT_STS_L2P_FIFO_OVERFLOW_SHIFT 1
45391 … (0x1<<3) // Overflow of phy addr fifo - removed in E4.
45393 … (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4.
45395 … (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4.
45397 …tten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset - removed in E5.
45401 … (0x1<<8) // E4: Indicates a request with: 1. Logical address. 2.…
45403 … (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue - removed in E5.
45405 … (0x1<<10) // Underflwoing the treq fifo - removed in E5.
45407 … (0x1<<11) // Overflwoing the treq fifo - removed in E5.
45409 … (0x1<<12) // Underflwoing the icpl fifo - removed in E5.
45411 … (0x1<<13) // Overflwoing the icpl fifo - removed in E5.
45413 … (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5.
45422 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
45424 … (0x1<<1) // This bit masks, when set, the Interrupt …
45425 …SWRQ2_REG_INT_MASK_L2P_FIFO_OVERFLOW_SHIFT 1
45426 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
45428 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
45430 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
45432 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
45434 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
45436 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
45438 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
45440 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
45442 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
45444 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
45446 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
45448 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
45450 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
45452 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
45454 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
45456 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
45461 … (0x1<<1) // Overflow in l2p input fifo - remo…
45462 …SWRQ2_REG_INT_STS_WR_L2P_FIFO_OVERFLOW_SHIFT 1
45465 … (0x1<<3) // Overflow of phy addr fifo - removed in E4.
45467 … (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4.
45469 … (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4.
45471 …tten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset - removed in E5.
45475 … (0x1<<8) // E4: Indicates a request with: 1. Logical address. 2.…
45477 … (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue - removed in E5.
45479 … (0x1<<10) // Underflwoing the treq fifo - removed in E5.
45481 … (0x1<<11) // Overflwoing the treq fifo - removed in E5.
45483 … (0x1<<12) // Underflwoing the icpl fifo - removed in E5.
45485 … (0x1<<13) // Overflwoing the icpl fifo - removed in E5.
45487 … (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5.
45498 … (0x1<<1) // Overflow in l2p input fifo - remo…
45499 …SWRQ2_REG_INT_STS_CLR_L2P_FIFO_OVERFLOW_SHIFT 1
45502 … (0x1<<3) // Overflow of phy addr fifo - removed in E4.
45504 … (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4.
45506 … (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4.
45508 …tten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset - removed in E5.
45512 … (0x1<<8) // E4: Indicates a request with: 1. Logical address. 2.…
45514 … (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue - removed in E5.
45516 … (0x1<<10) // Underflwoing the treq fifo - removed in E5.
45518 … (0x1<<11) // Overflwoing the treq fifo - removed in E5.
45520 … (0x1<<12) // Underflwoing the icpl fifo - removed in E5.
45522 … (0x1<<13) // Overflwoing the icpl fifo - removed in E5.
45524 … (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5.
45533 … (0x1<<1) // This bit masks, when set, the Parity bi…
45534 …SWRQ2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_SHIFT 1
45535 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
45537 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
45539 … (0x1<<1) // This bit masks, when set, the Parity bi…
45540 …SWRQ2_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_E5_SHIFT 1
45541 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
45543 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
45545 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
45547 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
45549 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
45551 … (0x1<<1) // This bit masks, when set, the Parity bi…
45552 …SWRQ2_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_K2_SHIFT 1
45553 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
45555 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
45557 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
45559 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
45561 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
45563 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
45565 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
45567 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
45569 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
45571 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
45573 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
45575 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
45577 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
45578 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
45582 …EM001_I_ECC_EN_BB (0x1<<1) // Enable ECC for m…
45583 …SWRQ2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB_SHIFT 1
45588 …EM002_I_ECC_EN_E5 (0x1<<1) // Enable ECC for m…
45589 …SWRQ2_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_E5_SHIFT 1
45594 …EM005_I_ECC_EN_K2 (0x1<<1) // Enable ECC for m…
45595 …SWRQ2_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_K2_SHIFT 1
45596 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
45600 …_I_ECC_PRTY_BB (0x1<<1) // Set parity only for memory…
45601 …SWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB_SHIFT 1
45602 …TY_K2 (0x1<<2) // Set parity only for memory ecc inst…
45604 …TY_E5 (0x1<<0) // Set parity only for memory ecc inst…
45606 …_I_ECC_PRTY_E5 (0x1<<1) // Set parity only for memory…
45607 …SWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_E5_SHIFT 1
45608 …TY_E5 (0x1<<2) // Set parity only for memory ecc inst…
45610 …TY_BB_K2 (0x1<<0) // Set parity only for memory ecc inst…
45612 …_I_ECC_PRTY_K2 (0x1<<1) // Set parity only for memory…
45613 …SWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_K2_SHIFT 1
45617 …ECTED_0_MEM001_I_ECC_CORRECT_BB (0x1<<1) // Record if a corr…
45618 …SWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB_SHIFT 1
45623 …ECTED_0_MEM002_I_ECC_CORRECT_E5 (0x1<<1) // Record if a corr…
45624 …SWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_E5_SHIFT 1
45629 …ECTED_0_MEM005_I_ECC_CORRECT_K2 (0x1<<1) // Record if a corr…
45630 …SWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_K2_SHIFT 1
45634 …W DataWidth:0x3 // Max burst size filed for write requests port 0; 000 - 128B; 001:256B; 010:…
45635 …x3 // Max burst size filed for read requests port 0; 000 - 128B; 001:256B; 010: 512B;011:1K:100…
45637 … 0x24040cUL //Access:RW DataWidth:0x1 // When '1'; requests will ente…
45638 …n a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B…
45639 …n a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B…
45653 …DataWidth:0x8 // Initial value of global counter; This value MUST be 256 - sum of all clients t…
45660 … 0x240458UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 1 in pswrq memory.
45692 … 0x2404d8UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 1.
45727 …NOOP (0x1<<1) // Nosnoop attribut…
45728 …SWRQ2_REG_QM_PCI_ATTR_QM_NOSNOOP_SHIFT 1
45732 …NOOP (0x1<<1) // Nosnoop attribut…
45733 …SWRQ2_REG_TM_PCI_ATTR_TM_NOSNOOP_SHIFT 1
45737 …OSNOOP (0x1<<1) // Nosnoop attribut…
45738 …SWRQ2_REG_SRC_PCI_ATTR_SRC_NOSNOOP_SHIFT 1
45742 …OSNOOP (0x1<<1) // Nosnoop attribut…
45743 …SWRQ2_REG_CDU_PCI_ATTR_CDU_NOSNOOP_SHIFT 1
45747 …OSNOOP (0x1<<1) // Nosnoop attribut…
45748 …SWRQ2_REG_DBG_PCI_ATTR_DBG_NOSNOOP_SHIFT 1
45752 …NOOP (0x1<<1) // Nosnoop attribut…
45753 …SWRQ2_REG_HC_PCI_ATTR_HC_NOSNOOP_SHIFT 1
45757 …_NOSNOOP (0x1<<1) // Nosnoop attribut…
45758 …SWRQ2_REG_DMAE_PCI_ATTR_DMAE_NOSNOOP_SHIFT 1
46001 … 0x2406a0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ5 Read- currently not used.
46104 … (0xf<<0) // Indicates the number of credits for read sub-requests in th reques…
46106 … (0x1f<<4) // Indicates the number of credits for write sub-requests in th reques…
46111 … 0x240724UL //Access:RW DataWidth:0x5 // Sets which vq head pointer to see out of queues 0-31.
46112 … 0x240728UL //Access:RW DataWidth:0x5 // Sets which vq tail pointer to see out of queues 0-31.
46113 …:0x1 // Will determine how the logical address is calculated; 0: as in E1; 1:with new algorithm.
46146 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46147 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46148 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46149 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46150 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46151 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46152 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46153 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46154 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46155 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46156 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46157 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46158 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46159 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46160 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46161 …- SR from the VQ can send ATC lookup request to the ATC (assuming all other conditions are met). W…
46162 … b0 - PF enable; b1 - VF enable; PF enable bit is relevant when VF_Valid (in the request) bit is 0…
46163 …ues of rq_atc_internal_ats_enable as follows: b0 - PF0; b1 - VF0; b2 - PF1; b3 - VF1; b30 - PF15 ;…
46164 …ONLY. bit per VQ. go translated set means that SR of the matched VQ will be always sent to the GLU…
46165 … bit. when reset all ATC logic is disabled within the PSWRQ. The value of this register must be th…
46166 … 0x240800UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i…
46167 … 0x240804UL //Access:RW DataWidth:0x2 // VQ-s that are enabled (i…
46168 … 0x240808UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i…
46169 … 0x24080cUL //Access:RW DataWidth:0x2 // VQ-s that are enabled (i…
46170 … 0x240810UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i…
46171 … // VQ-s that are enabled (i.e. can be chosen by the GARB) in stall int scenario; VQ32 = TREQ; VQ…
46175 …- assert ilt fail interrupt (rq_elt_addr) in case working in ilt mode and onchip translation fail …
46176 …set as well (rq_hoq_ram_rd_en); upon read completion (rq_hoq_ram_rd_status =1) data_rd_0 data_rd_1…
46178 …FOR DBG: when set - data rd from hoq ram is completed (i.e. data is ready in data_rd_0 data_rd_1 d…
46182 …// FOR DBG: bit 0 relaxed ordering; bit 1 no-snoop; bits 5:2 client id; bit 6 done type; bit 7 res…
46183 … 0x240844UL //Access:R DataWidth:0x20 // The total number of WR SR-s that were sent to t…
46184 … 0x240848UL //Access:R DataWidth:0x20 // The total number of RD SR-s that were sent to t…
46185 … 0x24084cUL //Access:R DataWidth:0x20 // The number of PBF RD SR-s that were sent to t…
46186 … 0x240850UL //Access:R DataWidth:0x20 // The number of USDM-DP WR SR-s that were sent …
46187 … 0x240854UL //Access:R DataWidth:0x20 // The number of TREQ SR-s that were sent to t…
46188 … 0x240858UL //Access:R DataWidth:0x20 // The number of ICPL SR-s that were sent to t…
46189 …20 // The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46190 …9 // The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46191 …20 // The total number of bytes for RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46192 …c // The total number of bytes for RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46193 …0x20 // The number of bytes for PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46194 …0xc // The number of bytes for PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46195 …:0x20 // The number of bytes for USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_…
46196 …:0x9 // The number of bytes for USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_…
46197 … // Counting window mode. 0 - manual window: counting is manually being initiated & stopped by t…
46198 …ow. Valid when working in predefined window mode (i.e. Sr_cnt_window_mode = 1). Granularity of sr…
46200 …Only register. The manual window command sent by the user. Valid when working in manual window mod…
46201 … 0x24088cUL //Access:W DataWidth:0x1 // Write Only register. RBC write…
46202 …global window counter). 0 - start counting upon any first SR that is sent to the PGLUE. 1 - start …
46204 …he number of clk_pci ticks minus 1 between each increment of the global window counter (i.e. 0 is …
46205 …atus of the SR count mechanism: 0 - idle: ready to start new counting. 1 - ongoing: counting is cu…
46206 … 0x2408a0UL //Access:R DataWidth:0x20 // SR address - 32 lsb.
46207 … 0x2408a4UL //Access:R DataWidth:0x20 // SR address - 32 msb.
46208 … 0x2408a8UL //Access:R DataWidth:0x20 // B15-0: reqid; b28-16: SR length; b29 - reserved; b…
46209 …dth:0x20 // B3-0: PFID; b4: vf_valid; b12-b5: VFID; b13: first SR; b14: last SR; b19-15: client …
46210 … 0x2408b0UL //Access:R DataWidth:0x9 // bit 8-0: srid.
46211 … 0x2408b4UL //Access:R DataWidth:0x20 // SR address - 32 lsb.
46212 … 0x2408b8UL //Access:R DataWidth:0x20 // SR address - 32 msb.
46213 … 0x2408bcUL //Access:R DataWidth:0x20 // B15-0: reqid; b28-16: SR length; b29 - reserved; b…
46214 … DataWidth:0x20 // B3-0: PFID; b4: vf_valid; b12-b5: VFID; b13: first SR; b14: last SR; b19-15…
46215 … 0x2408c4UL //Access:R DataWidth:0xa // b1-0: atc code; b2: wdone type; b4-3: endianity; …
46224 …OSNOOP (0x1<<1) // Nosnoop attribut…
46225 …SWRQ2_REG_PTU_PCI_ATTR_PTU_NOSNOOP_SHIFT 1
46230 …OSNOOP (0x1<<1) // Nosnoop attribut…
46231 …SWRQ2_REG_M2P_PCI_ATTR_M2P_NOSNOOP_SHIFT 1
46235 …_NOSNOOP (0x1<<1) // Nosnoop attribut…
46236 …SWRQ2_REG_MULD_PCI_ATTR_MULD_NOSNOOP_SHIFT 1
46241 …_NOSNOOP (0x1<<1) // Nosnoop attribut…
46242 …SWRQ2_REG_XYLD_PCI_ATTR_XYLD_NOSNOOP_SHIFT 1
46243 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46244 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46245 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46246 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46247 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46248 … 0x240908UL //Access:RW DataWidth:0x1 // Debug only. Writing this register from 0 to 1 e…
46249 … 0x24090cUL //Access:R DataWidth:0x20 // Debug only. Round trip measure…
46250 … DataWidth:0x20 // Debug only. Maximal round trip measurement value from the time rmm_enable re…
46251 … DataWidth:0x20 // Debug only. Minimal round trip measurement value from the time rmm_enable re…
46252 … DataWidth:0x20 // Debug only. Number of round trip measurements done from the time rmm_enable r…
46253 … 0x24091cUL //Access:RW DataWidth:0x5 // Debug only. Indicates the clie…
46254 … 0x240920UL //Access:RW DataWidth:0x6 // Debug only. Indicates the VQ f…
46258 …l2p_vf_err or rq_elt_addr interrupt. [12:0] - Length in bytes. [16:13] - PFID. [17] - VF_VALID. …
46259 …:16] client ID. [21] - Error type - 0 - rq_l2p_vf_err; 1 - rq_elt_addr. [22] - w_nr - 0 - read; 1 …
46261 …Access:RW DataWidth:0x9 // Debug only: Total number of available PCI read sub-requests. Must …
46262 … 0x240940UL //Access:RW DataWidth:0xa // Debug only: Total number of av…
46263 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46264 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46265 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46266 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46267 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46268 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46269 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46270 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46271 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46272 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46273 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46274 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46275 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46276 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46277 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46278 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46279 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46280 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46281 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46282 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46283 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46284 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46285 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46286 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46287 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46288 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46289 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46290 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46291 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46294 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46295 … 0x2409c4UL //Access:R DataWidth:0x9 // Debug only: The SR counter - number of …
46296 … 0x2409c8UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46297 … 0x2409ccUL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46298 … 0x2409d0UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46299 … 0x2409d4UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46300 … 0x2409d8UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46301 … 0x2409dcUL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46302 … 0x2409e0UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46303 … 0x2409e4UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46304 … 0x2409e8UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46305 … 0x2409ecUL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46306 … 0x2409f0UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46307 … 0x2409f4UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46308 … 0x2409f8UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46309 … 0x2409fcUL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46310 … 0x240a00UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46311 … 0x240a04UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46312 … 0x240a08UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46313 … 0x240a0cUL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46314 … 0x240a10UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46315 … 0x240a14UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46316 … 0x240a18UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46317 … 0x240a1cUL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46318 … 0x240a20UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46319 … 0x240a24UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46320 … 0x240a28UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46321 … 0x240a2cUL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46322 … 0x240a30UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46323 … 0x240a34UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46324 … 0x240a38UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46325 … 0x240a3cUL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46326 … 0x240a40UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46327 … 0x240a44UL //Access:R DataWidth:0x9 // Debug only: The SR counter per…
46328 … 0x240a48UL //Access:R DataWidth:0xa // Debug only: The blocks counter - number o…
46329 … 0x240a4cUL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46330 … 0x240a50UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46331 … 0x240a54UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46332 … 0x240a58UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46333 … 0x240a5cUL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46334 … 0x240a60UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46335 … 0x240a64UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46336 … 0x240a68UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46337 … 0x240a6cUL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46338 … 0x240a70UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46339 … 0x240a74UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46340 … 0x240a78UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46341 … 0x240a7cUL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46342 … 0x240a80UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46343 … 0x240a84UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46344 … 0x240a88UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46345 … 0x240a8cUL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46346 … 0x240a90UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46347 … 0x240a94UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46348 … 0x240a98UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46349 … 0x240a9cUL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46350 … 0x240aa0UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46351 … 0x240aa4UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46352 … 0x240aa8UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46353 … 0x240aacUL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46354 … 0x240ab0UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46355 … 0x240ab4UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46356 … 0x240ab8UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46357 … 0x240abcUL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46358 … 0x240ac0UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46359 … 0x240ac4UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46360 … 0x240ac8UL //Access:R DataWidth:0xa // Debug only: The blocks counter…
46361 … 0x240accUL //Access:R DataWidth:0xe // Debug only: byte counter per w…
46362 … 0x240ad0UL //Access:R DataWidth:0xe // Debug only: byte counter per w…
46363 … 0x240ad4UL //Access:R DataWidth:0xe // Debug only: byte counter per w…
46364 … 0x240ad8UL //Access:R DataWidth:0xe // Debug only: byte counter per w…
46365 … 0x240adcUL //Access:R DataWidth:0xe // Debug only: byte counter per w…
46366 … 0x240ae0UL //Access:R DataWidth:0xe // Debug only: byte counter per w…
46367 … 0x240ae4UL //Access:R DataWidth:0xe // Debug only: byte counter per w…
46368 … 0x240ae8UL //Access:R DataWidth:0xe // Debug only: byte counter per w…
46369 … 0x240aecUL //Access:R DataWidth:0xe // Debug only: byte counter per w…
46370 … 0x240af0UL //Access:R DataWidth:0xe // Debug only: byte counter per w…
46371 … 0x240af4UL //Access:R DataWidth:0xe // Debug only: byte counter per w…
46372 … 0x240af8UL //Access:R DataWidth:0xe // Debug only: byte counter per w…
46373 … 0x240afcUL //Access:R DataWidth:0xe // Debug only: byte counter per w…
46374 … 0x240b00UL //Access:R DataWidth:0xe // Debug only: byte counter per w…
46375 … 0x240b04UL //Access:R DataWidth:0xe // Debug only: byte counter per w…
46376 … 0x240b08UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr…
46377 … 0x240b0cUL //Access:R DataWidth:0x8 // Debug only: eop counter per wr…
46378 … 0x240b10UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr…
46379 … 0x240b14UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr…
46380 … 0x240b18UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr…
46381 … 0x240b1cUL //Access:R DataWidth:0x8 // Debug only: eop counter per wr…
46382 … 0x240b20UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr…
46383 … 0x240b24UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr…
46384 … 0x240b28UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr…
46385 … 0x240b2cUL //Access:R DataWidth:0x8 // Debug only: eop counter per wr…
46386 … 0x240b30UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr…
46387 … 0x240b34UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr…
46388 … 0x240b38UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr…
46389 … 0x240b3cUL //Access:R DataWidth:0x8 // Debug only: eop counter per wr…
46390 … 0x240b40UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr…
46391 … 0x240b44UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46392 … 0x240b48UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46393 … 0x240b4cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46394 … 0x240b50UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46395 … 0x240b54UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46396 … 0x240b58UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46397 … 0x240b5cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46398 … 0x240b60UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46399 … 0x240b64UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46400 … 0x240b68UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46401 … 0x240b6cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46402 … 0x240b70UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46403 … 0x240b74UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46404 … 0x240b78UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46405 … 0x240b7cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46406 … 0x240b80UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46407 … 0x240b84UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46408 … 0x240b88UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46409 … 0x240b8cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46410 … 0x240b90UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46411 … 0x240b94UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46412 … 0x240b98UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46413 … 0x240b9cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46414 … 0x240ba0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46415 … 0x240ba4UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46416 … 0x240ba8UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46417 … 0x240bacUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46418 … 0x240bb0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46419 … 0x240bb4UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46420 … 0x240bb8UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46421 … 0x240bbcUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46422 … 0x240bc0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46425 …ccUL //Access:R DataWidth:0x1 // MISC close the gate status register. 1 indicates the gates …
46426 …x240bd0UL //Access:R DataWidth:0x1 // MISC stall mem status register. 1 indicates stall mem …
46427 … 0x240bd4UL //Access:RW DataWidth:0x1 // GARB config: 1 indicates read SRs h…
46428 …idth:0x1 // GARB config: 1 indicates BWCs can become negative. Clients with negative BWCs are n…
46429 …1 indicates that only clients with BWC greater or equal to Li are chosen. 0 indicates that clients…
46430 … 0 - the VQ is not associated with any strict priority (i.e. the VQ is associated wth the BW count…
46431 …- the VQ is not associated with any strict priority (i.e. the VQ is associated wth the BW counters…
46432 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46433 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46434 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46435 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46436 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46437 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46438 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46439 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46440 …priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: …
46441 …priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: …
46442 …priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: …
46443 …priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: …
46444 …priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: …
46445 …priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: …
46446 …priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: …
46447 …priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: …
46448 …-PGLUE request interface write credit; 0 - no more credit for wr SR-s (i.e. write SR-s cannot be s…
46449 …-PGLUE request interface read credit; 0 - no more credit for rd SR-s (i.e. read SR-s cannot be sen…
46450 …only enable to submit a write request when eop arrived. This can be a workaround for possible bugs…
46451 …-1] between qc_cmg_add_2_q (indication that new request is written into hoq0) and cmg_qc_del_head …
46452 …-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_…
46453 …-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_…
46454 … 0x240c40UL //Access:R DataWidth:0xe // For debug and Idle-check use. The value …
46455 …ts deadlock prevention. indicating if to submit the first SR of a request only when there are enou…
46456 …ite done for them from the PGLUE). Upon reaching the threshold no more wr SR-s will be sent by the…
46457 … 0x240c4cUL //Access:RW DataWidth:0x6 // Debug only: Reserved bits for …
46460 … 0x240c58UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 1
46491 …bit is set, client can push request to this VQ. Map TSDM to VQs: bit 0 is mapped to VQID 6. bit 1 …
46492 …bit is set, client can push request to this VQ. Map MSDM to VQs: bit 0 is mapped to VQID 6. bit 1 …
46493 …bit is set, client can push request to this VQ. Map USDM to VQs: bit 0 is mapped to VQID 6. bit 1 …
46494 …bit is set, client can push request to this VQ. Map XSDM to VQs: bit 0 is mapped to VQID 6. bit 1 …
46495 …bit is set, client can push request to this VQ. Map YSDM to VQs: bit 0 is mapped to VQID 6. bit 1 …
46496 …bit is set, client can push request to this VQ. Map PSDM to VQs: bit 0 is mapped to VQID 6. bit 1 …
46497 …bit is set, client can push request to this VQ. Map M2P to VQs: bit 0 is mapped to VQID 6. bit 1 i…
46501 …RC_NOSNOOP_E5 (0x1<<1) // Nosnoop attribut…
46502 …SWRQ2_REG_TGSRC_PCI_ATTR_TGSRC_NOSNOOP_E5_SHIFT 1
46506 …RC_NOSNOOP_E5 (0x1<<1) // Nosnoop attribut…
46507 …SWRQ2_REG_RGSRC_PCI_ATTR_RGSRC_NOSNOOP_E5_SHIFT 1
46511 …_NOSNOOP_E5 (0x1<<1) // Nosnoop attribut…
46512 …SWRQ2_REG_PRMS_PCI_ATTR_PRMS_NOSNOOP_E5_SHIFT 1
46513 … // Page size in L2P table for tgsrc module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
46514 … // Page size in L2P table for RGSRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
46519 … 0x240d14UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr…
46520 … 0x240d18UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr…
46521 … 0x240d1cUL //Access:R DataWidth:0x8 // Debug only: eop counter per wr…
46522 … 0x240d20UL //Access:R DataWidth:0xe // Debug only: byte counter per w…
46523 … 0x240d24UL //Access:R DataWidth:0xe // Debug only: byte counter per w…
46524 … 0x240d28UL //Access:R DataWidth:0xe // Debug only: byte counter per w…
46552 …5 // Internal lookup table for logical to physical address translation. Re-instantiated in E4 du…
46559 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
46560 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
46561 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
46562 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
46565 … 0x280060UL //Access:RW DataWidth:0x6 // Debug only: Reserved bits for …
46569 …ERFLOW (0x1<<1) // Overflow in pbf …
46570 …SWRQ_REG_INT_STS_PBF_FIFO_OVERFLOW_SHIFT 1
46614 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
46616 … (0x1<<1) // This bit masks, when set, the Interrupt …
46617 …SWRQ_REG_INT_MASK_PBF_FIFO_OVERFLOW_SHIFT 1
46618 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
46620 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
46622 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
46624 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
46626 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
46628 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
46630 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
46632 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
46634 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
46636 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
46638 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
46640 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
46642 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
46644 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
46646 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
46648 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
46650 … (0x1<<18) // This bit masks, when set, the Interrupt bit: P…
46652 … (0x1<<19) // This bit masks, when set, the Interrupt bit: P…
46654 … (0x1<<20) // This bit masks, when set, the Interrupt bit: P…
46656 … (0x1<<21) // This bit masks, when set, the Interrupt bit: P…
46658 … (0x1<<22) // This bit masks, when set, the Interrupt bit: P…
46663 …_OVERFLOW (0x1<<1) // Overflow in pbf …
46664 …SWRQ_REG_INT_STS_WR_PBF_FIFO_OVERFLOW_SHIFT 1
46710 …O_OVERFLOW (0x1<<1) // Overflow in pbf …
46711 …SWRQ_REG_INT_STS_CLR_PBF_FIFO_OVERFLOW_SHIFT 1
46755 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
46772 …bit indicates if full is asserted towards the client. The clients order is according to the increm…
46773 …bit indicates if full was asserted since reset towards the client. The clients order is according …
46775 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
46776 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
46777 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
46778 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
46783 … 0x29a0c8UL //Access:RW DataWidth:0x6 // Debug only: Reserved bits for …
46790 …ERFLOW (0x1<<1) // Overflow in src …
46791 …SWWR_REG_INT_STS_SRC_FIFO_OVERFLOW_SHIFT 1
46827 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
46829 … (0x1<<1) // This bit masks, when set, the Interrupt …
46830 …SWWR_REG_INT_MASK_SRC_FIFO_OVERFLOW_SHIFT 1
46831 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
46833 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
46835 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
46837 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
46839 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
46841 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
46843 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
46845 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
46847 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
46849 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
46851 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
46853 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
46855 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
46857 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
46859 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
46861 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
46863 … (0x1<<18) // This bit masks, when set, the Interrupt bit: P…
46868 …_OVERFLOW (0x1<<1) // Overflow in src …
46869 …SWWR_REG_INT_STS_WR_SRC_FIFO_OVERFLOW_SHIFT 1
46907 …O_OVERFLOW (0x1<<1) // Overflow in src …
46908 …SWWR_REG_INT_STS_CLR_SRC_FIFO_OVERFLOW_SHIFT 1
46944 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
46948 …- client ID. [7:5] - (sum1[5:3] + 1) or (sum1[5:4] + 1) according to the definition in the spec. […
46955 … 0x29b064UL //Access:RW DataWidth:0x6 // Debug only: Reserved bits for …
46956 …0x29b068UL //Access:RW DataWidth:0x7 // If Number of entries in the PRM-secondary internal fi…
46957 … 0x29b06cUL //Access:R DataWidth:0x7 // Current internal PRM-secondary fill level …
46958 … 0x29b070UL //Access:R DataWidth:0x7 // Maximum internal PRM-secondary fill level …
46962 …ERROR (0x1<<1) // Indicates that t…
46963 …SWWR2_REG_INT_STS_PGLUE_EOP_ERROR_SHIFT 1
46996 …he last read request from the glue block; but the number of valid 128-bit or 64-bit words in the m…
47005 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
47007 … (0x1<<1) // This bit masks, when set, the Interrupt …
47008 …SWWR2_REG_INT_MASK_PGLUE_EOP_ERROR_SHIFT 1
47009 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
47011 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
47013 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
47015 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
47017 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
47019 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
47021 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
47023 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
47025 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
47027 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
47029 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
47031 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
47033 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
47035 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
47037 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
47039 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
47041 … (0x1<<18) // This bit masks, when set, the Interrupt bit: P…
47043 … (0x1<<19) // This bit masks, when set, the Interrupt bit: P…
47045 … (0x1<<20) // This bit masks, when set, the Interrupt bit: P…
47047 … (0x1<<21) // This bit masks, when set, the Interrupt bit: P…
47052 …OP_ERROR (0x1<<1) // Indicates that t…
47053 …SWWR2_REG_INT_STS_WR_PGLUE_EOP_ERROR_SHIFT 1
47086 …he last read request from the glue block; but the number of valid 128-bit or 64-bit words in the m…
47097 …EOP_ERROR (0x1<<1) // Indicates that t…
47098 …SWWR2_REG_INT_STS_CLR_PGLUE_EOP_ERROR_SHIFT 1
47131 …he last read request from the glue block; but the number of valid 128-bit or 64-bit words in the m…
47140 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47143 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47145 … (0x1<<1) // This bit masks, when set, the Parity bi…
47146 …SWWR2_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_E5_SHIFT 1
47147 … (0x1<<1) // This bit masks, when set, the Parity bi…
47148 …SWWR2_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT 1
47149 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47151 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47153 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47155 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47157 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47159 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47161 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47163 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47165 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47167 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47169 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47171 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47173 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47175 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47177 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47179 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47181 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47183 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47185 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47187 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47189 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47191 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47193 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47195 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47197 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47199 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47201 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47203 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47205 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47207 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47209 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47211 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47213 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47215 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47217 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47219 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47221 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47223 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47225 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47227 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47229 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47231 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47233 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47235 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47237 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47239 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47241 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47243 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47245 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47247 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47249 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47251 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47253 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47255 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47257 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47259 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47261 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47263 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47266 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47268 … (0x1<<1) // This bit masks, when set, the Parity bi…
47269 …SWWR2_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_2_E5_SHIFT 1
47270 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47272 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47274 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47276 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47278 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47280 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47282 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47284 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47286 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47288 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47290 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47292 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47294 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47296 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47298 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47300 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47302 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47304 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47306 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47308 … (0x1<<1) // This bit masks, when set, the Parity bi…
47309 …SWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_3_BB_K2_SHIFT 1
47310 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47312 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47314 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47316 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47318 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47320 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47322 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47324 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47326 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47328 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47330 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47332 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47334 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47336 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47338 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47340 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47342 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47344 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47346 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47348 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47350 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47352 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47354 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47356 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47358 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47360 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47362 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47364 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47366 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47368 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47370 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47372 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47374 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47376 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47378 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47380 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47382 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47384 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47386 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47388 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47391 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47393 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47395 … (0x1<<1) // This bit masks, when set, the Parity bi…
47396 …SWWR2_REG_PRTY_MASK_H_2_MEM006_I_MEM_PRTY_6_E5_SHIFT 1
47397 … (0x1<<1) // This bit masks, when set, the Parity bi…
47398 …SWWR2_REG_PRTY_MASK_H_2_MEM006_I_MEM_PRTY_7_BB_K2_SHIFT 1
47399 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47401 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47403 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47405 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47407 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47409 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47411 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47413 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47415 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47417 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47419 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47421 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47423 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47425 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47427 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47429 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47431 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47433 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47435 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47437 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47439 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47441 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47443 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47445 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47447 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47449 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47451 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47453 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47455 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47457 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47459 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47461 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47463 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47465 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47467 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47469 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47471 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47473 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47475 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47477 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47479 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47481 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47483 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47485 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47487 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47489 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47491 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47493 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47495 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47497 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47499 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47501 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47503 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47505 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47507 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47509 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47511 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47513 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47516 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47518 … (0x1<<1) // This bit masks, when set, the Parity bi…
47519 …SWWR2_REG_PRTY_MASK_H_3_MEM019_I_MEM_PRTY_0_E5_SHIFT 1
47520 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47522 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47524 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47526 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47528 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47530 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47532 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47534 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47536 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47538 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47540 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47542 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47544 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47546 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47548 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47550 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47552 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47554 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47556 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47558 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47560 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47562 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47564 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47566 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47568 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47570 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47572 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47574 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47576 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47578 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47580 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47582 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47584 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47586 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47588 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47590 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47592 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47594 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47596 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47598 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47600 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47602 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47604 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47606 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47608 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47610 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47612 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47614 … (0x1<<1) // This bit masks, when set, the Parity bi…
47615 …SWWR2_REG_PRTY_MASK_H_3_MEM015_I_MEM_PRTY_1_BB_K2_SHIFT 1
47616 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47619 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47621 … (0x1<<1) // This bit masks, when set, the Parity bi…
47622 …SWWR2_REG_PRTY_MASK_H_4_MEM013_I_MEM_PRTY_6_E5_SHIFT 1
47623 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47625 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47627 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47629 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47631 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47633 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47635 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47637 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47639 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47641 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47643 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47645 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47646 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47647 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47652 …EM009_I_ECC_EN_E5 (0x1<<1) // Enable ECC for m…
47653 …SWWR2_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN_E5_SHIFT 1
47658 …TY_E5 (0x1<<0) // Set parity only for memory ecc inst…
47660 …_I_ECC_PRTY_E5 (0x1<<1) // Set parity only for memory…
47661 …SWWR2_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY_E5_SHIFT 1
47662 …ONLY_0_BB_K2 (0x1<<0) // Set parity only for memory ecc inst…
47668 …ECTED_0_MEM009_I_ECC_CORRECT_E5 (0x1<<1) // Record if a corr…
47669 …SWWR2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT_E5_SHIFT 1
47675 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
47676 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
47677 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
47678 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
47683 … 0x29c0a0UL //Access:RW DataWidth:0xa // Debug only: Reserved bits for …
47684 … 0x29c0a4UL //Access:R DataWidth:0x12 // Each bit indicates if full i…
47685 … 0x29c0a8UL //Access:R DataWidth:0x12 // Each bit indicates if full w…
47689 … (0x1<<1) // An error in one …
47690 …SWRD_REG_INT_STS_POP_ERROR_SHIFT 1
47694 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
47696 … (0x1<<1) // This bit masks, when set, the Interrupt …
47697 …SWRD_REG_INT_MASK_POP_ERROR_SHIFT 1
47698 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
47703 …R (0x1<<1) // An error in one …
47704 …SWRD_REG_INT_STS_WR_POP_ERROR_SHIFT 1
47710 …OR (0x1<<1) // An error in one …
47711 …SWRD_REG_INT_STS_CLR_POP_ERROR_SHIFT 1
47715 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47717 … 0x29d000UL //Access:RW DataWidth:0x1 // Driver should write 1 to this register in …
47718 …s initialization is done. Driver should check this register is 1 some time after writing 1 to star…
47719 …only and read only: Each entry provides the first sub request ID in 3 VQs. SR ID of 0x1ff is NULL …
47721 … 0x29d060UL //Access:RW DataWidth:0x12 // Debug only: '1' indicates that e…
47723 …uld override the data in case of an error. Duplicated 4 times to create 64 bit data. Can be deadde…
47725 …1 indicates to override the data to the client in case of an error and use the error pattern. 0 in…
47727 …only when override_data_when_error is 1. 1 indicates to override the data to the client in case of…
47729 …uest with error on receive side: [15:0] - Echo ID. [28:16] - sub-request length minus 1. [29] - fi…
47730 …ils of first request with error on receive side: [4:0] - VQ ID. [9:5] - client ID. [10] - valid - …
47732 … 0x29d074UL //Access:RW DataWidth:0x4 // Debug only: The arbiter delay.…
47733 … 0x29d078UL //Access:RW DataWidth:0x1 // 1' indicates that the …
47734 … 0x29d07cUL //Access:R DataWidth:0x1 // Debug only: Indication if deli…
47735 … 0x29d080UL //Access:R DataWidth:0x1 // Debug only: Indication if deli…
47736 … 0x29d084UL //Access:RW DataWidth:0x14 // Debug only: Reserved bits for …
47737 …only and read only: Each entry provides the first sub request ID in 3 VQs. SR ID of 0x1ff is NULL …
47747 … 0x29d0e0UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' …
47748 … 0x29d0e4UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' …
47749 … 0x29d0e8UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' …
47750 … 0x29d0ecUL //Access:R DataWidth:0x1 // Debug only: The 'almost full' …
47751 … 0x29d0f0UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' …
47752 … 0x29d0f4UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' …
47753 … 0x29d0f8UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' …
47754 … 0x29d0fcUL //Access:R DataWidth:0x1 // Debug only: The 'almost full' …
47755 … 0x29d100UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' …
47756 … 0x29d104UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' …
47757 … 0x29d108UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' …
47758 … 0x29d10cUL //Access:R DataWidth:0x1 // Debug only: The 'almost full' …
47759 … 0x29d110UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' …
47760 … 0x29d114UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' …
47761 … 0x29d118UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' …
47762 … 0x29d11cUL //Access:R DataWidth:0x1 // Debug only: The 'almost full' …
47763 …:0x5 // Debug only: If more than this Number of entries are used in the clock synchronization F…
47764 … // Debug only: If less or equal than this Number of entries are used in the clock synchronizatio…
47765 …x5 // Debug only: If more than this Number of entries are used in the CDU clock synchronization…
47766 …// Debug only: If less or equal than this Number of entries are used in the CDU clock synchronizat…
47767 …x7 // Debug only: If more than this Number of entries are used in the PBF clock synchronization…
47768 …// Debug only: If less or equal than this Number of entries are used in the PBF clock synchronizat…
47769 …x3 // Debug only: If more than this Number of entries are used in the PRM clock synchronization…
47770 … // Debug only: If less or equal than this Number of entries are used in the clock synchronizatio…
47771 …bit indicates if 'almost full' was asserted since reset from the FIFO towards the delivery module.…
47772 … 0x29d144UL //Access:R DataWidth:0x20 // Per-client maximum sync F…
47773 … 0x29d148UL //Access:R DataWidth:0x20 // Per-client maximum sync F…
47774 … 0x29d14cUL //Access:R DataWidth:0x20 // Per-client maximum sync F…
47775 … 0x29d150UL //Access:R DataWidth:0x20 // Per-client maximum sync F…
47777 … 0x29d158UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' …
47778 … 0x29d15cUL //Access:R DataWidth:0x1 // Debug only: The 'almost full' …
47779 … 0x29d160UL //Access:R DataWidth:0x8 // Per-client maximum sync F…
47783 …ROR (0x1<<1) // An error in the …
47784 …SWRD2_REG_INT_STS_SR_FIFO_ERROR_SHIFT 1
47792 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
47794 … (0x1<<1) // This bit masks, when set, the Interrupt …
47795 …SWRD2_REG_INT_MASK_SR_FIFO_ERROR_SHIFT 1
47796 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
47798 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
47800 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
47805 …_ERROR (0x1<<1) // An error in the …
47806 …SWRD2_REG_INT_STS_WR_SR_FIFO_ERROR_SHIFT 1
47816 …O_ERROR (0x1<<1) // An error in the …
47817 …SWRD2_REG_INT_STS_CLR_SR_FIFO_ERROR_SHIFT 1
47825 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47828 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47830 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47832 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47834 … (0x1<<1) // This bit masks, when set, the Parity bi…
47835 …SWRD2_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_E5_SHIFT 1
47836 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47838 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47840 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47842 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47844 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47846 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47848 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47850 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47852 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47854 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47856 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47858 … (0x1<<1) // This bit masks, when set, the Parity bi…
47859 …SWRD2_REG_PRTY_MASK_H_0_MEM018_I_ECC_RF_INT_BB_K2_SHIFT 1
47860 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47862 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47864 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47866 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47868 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47870 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47872 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47874 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47876 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47878 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47880 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47882 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47884 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47886 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47888 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47890 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47892 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47894 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47896 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47898 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47900 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47902 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47904 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47906 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47908 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47910 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47912 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47914 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47916 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47918 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47920 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47922 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47924 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47926 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47928 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47930 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47932 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47934 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47936 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47938 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47940 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47942 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47944 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47946 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47948 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47951 … (0x1<<1) // This bit masks, when set, the Parity bi…
47952 …SWRD2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_BB_K2_SHIFT 1
47953 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47955 … (0x1<<1) // This bit masks, when set, the Parity bi…
47956 …SWRD2_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_E5_SHIFT 1
47957 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47959 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47961 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47963 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47965 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47967 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47968 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47969 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47970 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47971 …[1].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an …
47972 …[1].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an …
47973 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47974 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47975 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47976 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47977 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47978 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47979 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47980 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47982 … (0x1<<3) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc …
47988 … (0x1<<1) // Enable ECC for memory ecc instance pswrd.TETRIS_3…
47989 …SWRD2_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN_E5_SHIFT 1
47996 … (0x1<<3) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc …
48012 … (0x1<<1) // Enable ECC for memory ecc instance pswrd.TETRIS_3…
48013 …SWRD2_REG_MEM_ECC_ENABLE_0_MEM018_I_ECC_EN_BB_K2_SHIFT 1
48025 … (0x1<<3) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_…
48027 …TY_E5 (0x1<<0) // Set parity only for memory ecc inst…
48029 …TY_BB_K2 (0x1<<4) // Set parity only for memory ecc inst…
48031 … (0x1<<1) // Set parity only for memory ecc instance pswrd.TETRI…
48032 …SWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY_E5_SHIFT 1
48033 …TY_BB_K2 (0x1<<5) // Set parity only for memory ecc inst…
48035 …TY_E5 (0x1<<2) // Set parity only for memory ecc inst…
48037 …TY_BB_K2 (0x1<<6) // Set parity only for memory ecc inst…
48039 … (0x1<<3) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_…
48041 …TY_BB_K2 (0x1<<7) // Set parity only for memory ecc inst…
48043 …TY_E5 (0x1<<4) // Set parity only for memory ecc inst…
48045 …TY_BB_K2 (0x1<<8) // Set parity only for memory ecc inst…
48047 …TY_E5 (0x1<<5) // Set parity only for memory ecc inst…
48049 …TY_E5 (0x1<<6) // Set parity only for memory ecc inst…
48051 …TY_E5 (0x1<<7) // Set parity only for memory ecc inst…
48053 …TY_E5 (0x1<<8) // Set parity only for memory ecc inst…
48055 … (0x1<<1) // Set parity only for memory ecc instance pswrd.TETRI…
48056 …SWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM018_I_ECC_PRTY_BB_K2_SHIFT 1
48057 …TY_E5 (0x1<<9) // Set parity only for memory ecc inst…
48059 …Y_E5 (0x1<<10) // Set parity only for memory ecc inst…
48061 …TY_BB_K2 (0x1<<0) // Set parity only for memory ecc inst…
48063 …TY_BB_K2 (0x1<<2) // Set parity only for memory ecc inst…
48065 …TY_BB_K2 (0x1<<9) // Set parity only for memory ecc inst…
48068 …a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc …
48074 … (0x1<<1) // Record if a correctable error occurred on memory ecc instance …
48075 …SWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT_E5_SHIFT 1
48082 …a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc …
48098 … (0x1<<1) // Record if a correctable error occurred on memory ecc instance …
48099 …SWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM018_I_ECC_CORRECT_BB_K2_SHIFT 1
48112 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
48113 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
48114 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
48115 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
48120 … 0x29d460UL //Access:RW DataWidth:0x1 // When '1'; inputs to the PSWR…
48121 …Access:RW DataWidth:0x9 // Debug only: Total number of available PCI read sub-requests. Must …
48122 … 0x29d468UL //Access:RW DataWidth:0xa // Debug only: Total number of av…
48123 …bit. When reset all ATC logic is disabled within the PSWRD. 'ATC entry ID' interface from PSWRQ is…
48124 … 0 - The delivery port continues delivering the next PBF request only if the second delivery port …
48142 … 0x29e040UL //Access:R DataWidth:0x7 // Debug only: Number of used ent…
48143 … 0x29e044UL //Access:R DataWidth:0x7 // Debug only: Number of used ent…
48144 … 0x29e048UL //Access:R DataWidth:0x7 // Debug only: Maximum number of …
48145 … 0x29e04cUL //Access:R DataWidth:0x7 // Debug only: Maximum number of …
48146 … 0x29e050UL //Access:RW DataWidth:0x4 // Debug only: If more than this …
48147 … 0x29e054UL //Access:RW DataWidth:0x5 // Debug only: Reserved bits for …
48149 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
48150 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
48151 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
48152 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
48160 …R_FIFO_ERR (0x1<<1) // An error in the …
48161 …SWHST2_REG_INT_STS_HST_HEADER_FIFO_ERR_SHIFT 1
48169 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
48171 … (0x1<<1) // This bit masks, when set, the Interrupt …
48172 …SWHST2_REG_INT_MASK_HST_HEADER_FIFO_ERR_SHIFT 1
48173 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
48175 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
48177 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
48182 …ADER_FIFO_ERR (0x1<<1) // An error in the …
48183 …SWHST2_REG_INT_STS_WR_HST_HEADER_FIFO_ERR_SHIFT 1
48193 …EADER_FIFO_ERR (0x1<<1) // An error in the …
48194 …SWHST2_REG_INT_STS_CLR_HST_HEADER_FIFO_ERR_SHIFT 1
48202 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
48205 …t sequence. Driver should check the value of this register is 1 some time after it wrote 1 to zone…
48206 … 0x2a0040UL //Access:RW DataWidth:0x1 // When 1; new internal writes…
48207 … 0x2a0044UL //Access:RW DataWidth:0x1 // When 1; doorbells are disca…
48208 … 0x2a0048UL //Access:RW DataWidth:0x1 // When 1; p2m are discarded a…
48209 …9 // Debug only: A bit mask for all PSWHST internal write clients. '1' means this PSWHST is dis…
48210 …050UL //Access:R DataWidth:0x1 // Debug only: '1' means this PSWHST is discarding doorbells.…
48211 …2a0054UL //Access:R DataWidth:0x1 // Debug only: '1' means this PSWHST is discarding p2m. Th…
48212 …only: A bit per arbiter-engine indicating if the engine is idle. Idle means the engine is not send…
48213 …- pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 P…
48214 … 0x2a0060UL //Access:R DataWidth:0x1 // 1 - An error request is…
48216 …- RSV [25:18] - byte enable; [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM…
48217 … first incorrect access. the format is: [6:0] - length in DWs. The data is written only when the v…
48218 … 0x2a0070UL //Access:R DataWidth:0x1 // 1 - An incorrect access is logged. The valid b…
48220 … 0x2a0078UL //Access:R DataWidth:0x1 // 1- permission violation data is logged. The vali…
48225 …3 // Number of available credits for source in internal write interface: [1:0] usdm; [3:2] xsdm;…
48226 … that consumed more than its allowed credits. the format is: [3:0] - client (0 TSDM; 1 MSDM; 2 USD…
48227 … 0x2a0094UL //Access:R DataWidth:0x1 // 1 - A source credit violation is logged. The vali…
48231 …/ Number of available credits for destination in internal write interface. [1:0] usdm; [3:2] xsdm;…
48233 … 0x2a00acUL //Access:R DataWidth:0x1 // 1 - PSWHST is in drain …
48234 … 0x2a00b0UL //Access:W DataWidth:0x1 // Writing 1 to this register ind…
48235 …- length in DWs; [25:18] - byte enable; [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - cli…
48236 … 0x2a00b8UL //Access:R DataWidth:0x1 // 1 - An hst timeout data is logged. The valid b…
48238 …interface. PSWHST issues an attention if more credits are consumed. Added in BB-B0 due to pipeline.
48240 … 0x2a00c8UL //Access:RW DataWidth:0x1 // When 1; host requests have …
48242 … 0x2a00d0UL //Access:RW DataWidth:0xa // Debug only: Reserved bits for …
48254 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
48255 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
48256 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
48257 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
48262 …only: Each entry contains a bit mask for PSWHST source arbiter clients. '1' means this client is w…
48267 … (0x1<<1) // An error in write source FIFO 1.
48268 …SWHST_REG_INT_STS_HST_SRC_FIFO1_ERR_SHIFT 1
48302 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
48304 … (0x1<<1) // This bit masks, when set, the Interrupt …
48305 …SWHST_REG_INT_MASK_HST_SRC_FIFO1_ERR_SHIFT 1
48306 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
48308 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
48310 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
48312 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
48314 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
48316 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
48318 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
48320 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
48322 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
48324 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
48326 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
48328 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
48330 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
48332 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
48334 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
48336 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
48341 … (0x1<<1) // An error in write source FIFO 1.
48342 …SWHST_REG_INT_STS_WR_HST_SRC_FIFO1_ERR_SHIFT 1
48378 … (0x1<<1) // An error in write source FIFO 1.
48379 …SWHST_REG_INT_STS_CLR_HST_SRC_FIFO1_ERR_SHIFT 1
48413 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
48416 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
48418 … (0x1<<1) // This bit masks, when set, the Parity bi…
48419 …SWHST_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT 1
48420 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
48422 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
48424 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
48426 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
48428 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
48430 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
48432 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
48434 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
48436 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
48438 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
48440 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
48442 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
48444 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
48446 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
48448 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
48451 …und interrupts memory. E4 entry structure: [15:0] - CompParams. [23:16] - EventID. [24] - T. [28:2…
48457 …1 to this register signals the PGLUE block to start initializing inbound interrupt memories for PF…
48458 …e sure the corresponding bit is 1 some time after writing to start_init_inb_int_mem. Bit 0 is for …
48459 … 0x2a8008UL //Access:W DataWidth:0x1 // Writing 1 to this register sig…
48460 …0x1 // PTT and GTT initialization is done. MCP should make sure this bit is 1 some time after w…
48461 … 0x2a8010UL //Access:W DataWidth:0x1 // Writing 1 to this register sig…
48462 …ake sure the corresponding bit is 1 some time after writing to start_init_zone_a. Bit 0 is for pat…
48466 …_RCV_BEHAVIOR (0x1<<1) // Target RW or com…
48467 …GLUE_B_REG_INT_STS_INCORRECT_RCV_BEHAVIOR_SHIFT 1
48470 …h of 2DWs and address not QW aligned; window is GRC and length is more than 1 DW. Details are stor…
48486 …ates Read/Write accesses to the admin window that have a length bigger than 1DW or first byte enab…
48490 … (0x1<<13) // Indicates an illegal address event - address smaller than…
48513 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
48515 … (0x1<<1) // This bit masks, when set, the Interrupt …
48516 …GLUE_B_REG_INT_MASK_INCORRECT_RCV_BEHAVIOR_SHIFT 1
48517 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
48519 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
48521 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
48523 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
48525 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
48527 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
48529 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
48531 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
48533 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
48535 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
48537 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
48539 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
48541 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
48543 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
48545 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
48547 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
48549 … (0x1<<18) // This bit masks, when set, the Interrupt bit: P…
48551 … (0x1<<19) // This bit masks, when set, the Interrupt bit: P…
48553 … (0x1<<20) // This bit masks, when set, the Interrupt bit: P…
48555 … (0x1<<21) // This bit masks, when set, the Interrupt bit: P…
48557 … (0x1<<22) // This bit masks, when set, the Interrupt bit: P…
48559 … (0x1<<23) // This bit masks, when set, the Interrupt bit: P…
48564 …ECT_RCV_BEHAVIOR (0x1<<1) // Target RW or com…
48565 …GLUE_B_REG_INT_STS_WR_INCORRECT_RCV_BEHAVIOR_SHIFT 1
48568 …h of 2DWs and address not QW aligned; window is GRC and length is more than 1 DW. Details are stor…
48584 …ates Read/Write accesses to the admin window that have a length bigger than 1DW or first byte enab…
48588 … (0x1<<13) // Indicates an illegal address event - address smaller than…
48613 …RECT_RCV_BEHAVIOR (0x1<<1) // Target RW or com…
48614 …GLUE_B_REG_INT_STS_CLR_INCORRECT_RCV_BEHAVIOR_SHIFT 1
48617 …h of 2DWs and address not QW aligned; window is GRC and length is more than 1 DW. Details are stor…
48633 …ates Read/Write accesses to the admin window that have a length bigger than 1DW or first byte enab…
48637 … (0x1<<13) // Indicates an illegal address event - address smaller than…
48660 … (0x1<<0) // This bit masks, when set, the Parity bit: PG…
48663 … (0x1<<0) // This bit masks, when set, the Parity bit: PG…
48665 … (0x1<<4) // This bit masks, when set, the Parity bit: PG…
48667 … (0x1<<1) // This bit masks, when set, the Parity bi…
48668 …GLUE_B_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_E5_SHIFT 1
48669 … (0x1<<2) // This bit masks, when set, the Parity bit: PG…
48671 … (0x1<<3) // This bit masks, when set, the Parity bit: PG…
48673 … (0x1<<5) // This bit masks, when set, the Parity bit: PG…
48675 … (0x1<<4) // This bit masks, when set, the Parity bit: PG…
48677 … (0x1<<5) // This bit masks, when set, the Parity bit: PG…
48679 … (0x1<<6) // This bit masks, when set, the Parity bit: PG…
48681 … (0x1<<7) // This bit masks, when set, the Parity bit: PG…
48683 … (0x1<<8) // This bit masks, when set, the Parity bit: PG…
48685 … (0x1<<10) // This bit masks, when set, the Parity bit: PG…
48687 … (0x1<<9) // This bit masks, when set, the Parity bit: PG…
48689 … (0x1<<11) // This bit masks, when set, the Parity bit: PG…
48691 … (0x1<<10) // This bit masks, when set, the Parity bit: PG…
48693 … (0x1<<6) // This bit masks, when set, the Parity bit: PG…
48695 … (0x1<<11) // This bit masks, when set, the Parity bit: PG…
48697 … (0x1<<12) // This bit masks, when set, the Parity bit: PG…
48699 … (0x1<<13) // This bit masks, when set, the Parity bit: PG…
48701 … (0x1<<7) // This bit masks, when set, the Parity bit: PG…
48703 … (0x1<<14) // This bit masks, when set, the Parity bit: PG…
48705 … (0x1<<8) // This bit masks, when set, the Parity bit: PG…
48707 … (0x1<<15) // This bit masks, when set, the Parity bit: PG…
48709 … (0x1<<9) // This bit masks, when set, the Parity bit: PG…
48711 … (0x1<<16) // This bit masks, when set, the Parity bit: PG…
48713 … (0x1<<0) // This bit masks, when set, the Parity bit: PG…
48715 … (0x1<<17) // This bit masks, when set, the Parity bit: PG…
48717 … (0x1<<18) // This bit masks, when set, the Parity bit: PG…
48719 … (0x1<<19) // This bit masks, when set, the Parity bit: PG…
48721 … (0x1<<20) // This bit masks, when set, the Parity bit: PG…
48723 … (0x1<<21) // This bit masks, when set, the Parity bit: PG…
48725 … (0x1<<22) // This bit masks, when set, the Parity bit: PG…
48727 … (0x1<<1) // This bit masks, when set, the Parity bi…
48728 …GLUE_B_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_SHIFT 1
48729 … (0x1<<23) // This bit masks, when set, the Parity bit: PG…
48731 … (0x1<<12) // This bit masks, when set, the Parity bit: PG…
48733 … (0x1<<24) // This bit masks, when set, the Parity bit: PG…
48735 … (0x1<<13) // This bit masks, when set, the Parity bit: PG…
48737 … (0x1<<25) // This bit masks, when set, the Parity bit: PG…
48739 … (0x1<<14) // This bit masks, when set, the Parity bit: PG…
48741 … (0x1<<26) // This bit masks, when set, the Parity bit: PG…
48743 … (0x1<<15) // This bit masks, when set, the Parity bit: PG…
48745 … (0x1<<27) // This bit masks, when set, the Parity bit: PG…
48747 … (0x1<<16) // This bit masks, when set, the Parity bit: PG…
48749 … (0x1<<28) // This bit masks, when set, the Parity bit: PG…
48751 … (0x1<<17) // This bit masks, when set, the Parity bit: PG…
48753 … (0x1<<29) // This bit masks, when set, the Parity bit: PG…
48755 … (0x1<<18) // This bit masks, when set, the Parity bit: PG…
48757 … (0x1<<30) // This bit masks, when set, the Parity bit: PG…
48759 … (0x1<<19) // This bit masks, when set, the Parity bit: PG…
48761 … (0x1<<20) // This bit masks, when set, the Parity bit: PG…
48763 … (0x1<<21) // This bit masks, when set, the Parity bit: PG…
48766 … (0x1<<0) // This bit masks, when set, the Parity bit: PG…
48768 … (0x1<<1) // This bit masks, when set, the Parity bi…
48769 …GLUE_B_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_7_K2_E5_SHIFT 1
48770 … (0x1<<2) // This bit masks, when set, the Parity bit: PG…
48775 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
48776 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
48777 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
48778 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
48783 …only: Reserved bits for ECO. Bit 0 - for Atomic Op / MRD handling of NPH credits. 0 - Can send bot…
48784 … 0x2a8464UL //Access:RW DataWidth:0x20 // Debug only: Reserved bits for …
48785 … 0x2a8468UL //Access:RW DataWidth:0x4 // Debug only: If more than this …
48787 … (0x1<<0) // 0 - Debug bus is not output to RBCN_e0. 1 - …
48789 … (0x1<<1) // 0 - Debug bus is not output to RBCN_e1. …
48790 …GLUE_B_REG_DBGBUS_PATH_SELECT_DBGBUS_PATH_SELECT_E1_SHIFT 1
48792 …GL_TXR_RELAX (0x1<<0) // Debug only.
48794 …GL_TXW_RELAX (0x1<<1) // Debug only.
48795 …GLUE_B_REG_PGL_DEBUG_PGL_TXW_RELAX_SHIFT 1
48796 …GL_DISABLE (0x1<<2) // Debug only.
48798 … 0x2a8474UL //Access:R DataWidth:0x6 // Debug only.
48800 … (0xf<<0) // Pcie core debug mux select 1. this field controls…
48804 …E (0x1<<8) // This bit forces a parity err…
48806 … (0x1<<9) // This bit give strict priority to read over write on the P…
48809 …dth:0x2 // Bit 0: This bit indicates that a write request was blocked because of bus_master_en …
48810 …idth:0x2 // Bit 0: This bit indicates that a read request was blocked because of bus_master_en …
48811 … 0x2a8488UL //Access:R DataWidth:0x4 // Debug only: Occupancy level in…
48812 … 0x2a848cUL //Access:R DataWidth:0x5 // Debug only: Maximal occupancy …
48813 … 0x2a8490UL //Access:R DataWidth:0x4 // Debug only: Maximal occupancy …
48814 … 0x2a8494UL //Access:R DataWidth:0x5 // Debug only: Write pointer in P…
48815 … 0x2a8498UL //Access:R DataWidth:0x5 // Debug only: Driver read pointe…
48816 … 0x2a849cUL //Access:R DataWidth:0x5 // Debug only: Filler read pointe…
48817 … 0x2a84a0UL //Access:R DataWidth:0x4 // Debug only: Write pointer in P…
48818 … 0x2a84a4UL //Access:R DataWidth:0x4 // Debug only: Driver read pointe…
48819 … 0x2a84a8UL //Access:R DataWidth:0x9 // Debug only: Maximal number of …
48820 …bit indicates a type of legacy error that was received in user RX interface since last reset. Note…
48821 … 0x2a84b0UL //Access:RW DataWidth:0x4 // Debug only: If more than this …
48822 … 0x2a84b4UL //Access:RW DataWidth:0x1 // Debug only: When 1, PCIe dbgsyn cl…
48824 …only. Used to disable an E2 optimization of having less dead cycles between adjacent write request…
48826 …_TWO_PENDING_REQUESTS (0x1<<1) // Debug only. Used to disa…
48827 …GLUE_B_REG_DISABLE_HIGHER_BW_DISABLE_TWO_PENDING_REQUESTS_SHIFT 1
48828 …(0x1<<2) // Debug only. Used to disable an E2 optimization of sending two pending write requests f…
48835 … // Debug only: 0 - PCIe checksum is generated towards PCIe core. 1 - PCIe checksum is not genera…
48836 … 0x2a84d4UL //Access:RW DataWidth:0x20 // A bit per VQ that indicat…
48839 …:0x5 // Pseudo VF target mode configuration that controls the size of each pseudo-VF in the BAR.
48841 … to accesss DORQ via BAR0: 0-disable access; 1-enable access if BAR0 size is 128K; 2-enable acces…
48842 … 0x2a84ecUL //Access:RW DataWidth:0x9 // VSC fields: bit 0 - enable VSC; bits 1-8 - VSC re…
48846 … (0x1<<7) // Debug only: disable inputs to …
48852 … 0x2a8524UL //Access:RW DataWidth:0x2 // Debug only: If more than this …
48853 … 0x2a8528UL //Access:RW DataWidth:0x5 // Debug only: If more than this …
48854 … 0x2a852cUL //Access:RW DataWidth:0x5 // Debug only: If more than this …
48855 … 0x2a8530UL //Access:RW DataWidth:0x5 // Debug only: If more than this …
48856 … 0x2a8560UL //Access:R DataWidth:0x9 // Debug only.
48857 … 0x2a8564UL //Access:R DataWidth:0x15 // Debug only.
48858 …-PF region. Addresses 0x0 - 0x5c: 12 per-PF PF windows. Each PF window contains two 32-bit values.…
48860 …region. 0x0 - 0x3c8 (0x200 - 0x5c8) - 243 global windows. Each entry is the 12-bit window offset.…
48862 …ister on which config space A attention is generated. Note that this register is in 128-byte units.
48863 …s starting in address cfg_space_a_address generates an attention. If bit N is set - a CSSNOOP cycl…
48864 …ister on which config space B attention is generated. Note that this register is in 128-byte units.
48865 …s starting in address cfg_space_b_address generates an attention. If bit N is set - a CSSNOOP cycl…
48866 …ion dirty bits. Each bit indicates that the corresponding PF generates config space A attention. S…
48867 …1 to a bit in this register in order to clear the corresponding bit in cfg_space_a_request registe…
48868 …ion dirty bits. Each bit indicates that the corresponding PF generates config space B attention. S…
48869 …1 to a bit in this register in order to clear the corresponding bit in cfg_space_b_request registe…
48870 …ts for VFs 0 to 31. Each bit indicates that the FLR register of the corresponding VF was set. Set …
48871 …s for VFs 32 to 63. Each bit indicates that the FLR register of the corresponding VF was set. Set …
48872 …s for VFs 64 to 95. Each bit indicates that the FLR register of the corresponding VF was set. Set …
48873 … for VFs 96 to 127. Each bit indicates that the FLR register of the corresponding VF was set. Set …
48874 …for VFs 128 to 159. Each bit indicates that the FLR register of the corresponding VF was set. Set …
48875 …for VFs 160 to 191. Each bit indicates that the FLR register of the corresponding VF was set. Set …
48876 …for VFs 192 to 223. Each bit indicates that the FLR register of the corresponding VF was set. Set …
48877 …for VFs 224 to 255. Each bit indicates that the FLR register of the corresponding VF was set. Set …
48878 …y bits for all PFs. Each bit indicates that the FLR register of the corresponding PF was set. Set …
48879 …rty bits clear for VFs 0 to 31. MCP writes 1 to a bit in this register in order to clear the corre…
48880 …ty bits clear for VFs 32 to 63. MCP writes 1 to a bit in this register in order to clear the corre…
48881 …ty bits clear for VFs 64 to 95. MCP writes 1 to a bit in this register in order to clear the corre…
48882 …y bits clear for VFs 96 to 127. MCP writes 1 to a bit in this register in order to clear the corre…
48883 … bits clear for VFs 128 to 159. MCP writes 1 to a bit in this register in order to clear the corre…
48884 … bits clear for VFs 160 to 191. MCP writes 1 to a bit in this register in order to clear the corre…
48885 … bits clear for VFs 192 to 223. MCP writes 1 to a bit in this register in order to clear the corre…
48886 … bits clear for VFs 224 to 255. MCP writes 1 to a bit in this register in order to clear the corre…
48887 … dirty bits clear for all PFs. MCP writes 1 to a bit in this register in order to clear the corre…
48889 …FLR_REQUEST (0x1<<0) // Debug only: When 1 flr request is …
48891 …BLE_SRIOV_DISABLED_REQUEST (0x1<<1) // Debug only: When 1 SR-IOV disb…
48892 …GLUE_B_REG_DISABLE_FLR_SRIOV_DISABLED_DISABLE_SRIOV_DISABLED_REQUEST_SHIFT 1
48893 …. Each bit indicates that the VF enable register of the corresponding PF is written to 0 and was p…
48894 …led attention dirty bits clear. MCP writes 1 to a bit in this register in order to clear the corre…
48895 …/Access:R DataWidth:0x20 // Shadow BME register for VFs 0 to 31. Each bit indicates if the co…
48896 …Access:R DataWidth:0x20 // Shadow BME register for VFs 32 to 63. Each bit indicates if the co…
48897 …Access:R DataWidth:0x20 // Shadow BME register for VFs 64 to 95. Each bit indicates if the co…
48898 …ccess:R DataWidth:0x20 // Shadow BME register for VFs 96 to 127. Each bit indicates if the co…
48899 …cess:R DataWidth:0x20 // Shadow BME register for VFs 128 to 159. Each bit indicates if the co…
48900 …cess:R DataWidth:0x20 // Shadow BME register for VFs 160 to 191. Each bit indicates if the co…
48901 …cess:R DataWidth:0x20 // Shadow BME register for VFs 192 to 223. Each bit indicates if the co…
48902 …cess:R DataWidth:0x20 // Shadow BME register for VFs 224 to 255. Each bit indicates if the co…
48903 …UL //Access:R DataWidth:0x10 // Shadow BME register for all PFs. Each bit indicates if the co…
48904 …1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_…
48905 …1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_…
48906 …1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_…
48907 …1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_…
48908 …1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_…
48909 …1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_…
48910 …1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_…
48911 …1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_…
48912 …only - Shadow bits clear for PFs 0 to 31. MCP writes 1 to a bit in this register in order to rese…
48913 …:R DataWidth:0x20 // Shadow ats_enable register for VFs 0 to 31. Each bit indicates if ATS fo…
48914 …R DataWidth:0x20 // Shadow ats_enable register for VFs 32 to 63. Each bit indicates if ATS fo…
48915 …R DataWidth:0x20 // Shadow ats_enable register for VFs 64 to 95. Each bit indicates if ATS fo…
48916 … DataWidth:0x20 // Shadow ats_enable register for VFs 96 to 127. Each bit indicates if ATS fo…
48917 … DataWidth:0x20 // Shadow ats_enable register for VFs 128 to 159. Each bit indicates if ATS fo…
48918 … DataWidth:0x20 // Shadow ats_enable register for VFs 160 to 191. Each bit indicates if ATS fo…
48919 … DataWidth:0x20 // Shadow ats_enable register for VFs 192 to 223. Each bit indicates if ATS fo…
48920 … DataWidth:0x20 // Shadow ats_enable register for VFs 224 to 255. Each bit indicates if ATS fo…
48921 …cess:R DataWidth:0x10 // Shadow ats_enable register for all PFs. Each bit indicates if ATS fo…
48922 … DataWidth:0x10 // Shadow vf_enable register for all PFs. Each bit indicates if SR-IOV for the …
48923 … 0x2aa0e4UL //Access:R DataWidth:0x5 // Read only. Shadow ATS_STU reg…
48924 …5. [15:0] : Each bit indicates if IDO_REQ_ENABLE bit for the corresponding PF is set. [31:16] : Ea…
48925 …only: PGLUE automatically clears ATC enable for a function if a TCPL arrived for that function wit…
48926 …bit indicates an incorrect behavior in user RX interface. Bit 0 - Reserved. Bit 1 - Reserved. Bit …
48927 …to 31. Each bit indicates that there was a completion with uncorrectable error for the correspond…
48928 …to 63. Each bit indicates that there was a completion with uncorrectable error for the correspond…
48929 …to 95. Each bit indicates that there was a completion with uncorrectable error for the correspond…
48930 …o 127. Each bit indicates that there was a completion with uncorrectable error for the correspond…
48931 …o 159. Each bit indicates that there was a completion with uncorrectable error for the correspond…
48932 …o 191. Each bit indicates that there was a completion with uncorrectable error for the correspond…
48933 …o 223. Each bit indicates that there was a completion with uncorrectable error for the correspond…
48934 …o 255. Each bit indicates that there was a completion with uncorrectable error for the correspond…
48935 … to 7. Each bit indicates that there was a completion with uncorrectable error for the correspond…
48936 …1 to a bit in this register in order to clear the corresponding bit in was_error_vf_31_0 register.…
48937 …1 to a bit in this register in order to clear the corresponding bit in was_error_vf_63_32 register…
48938 …1 to a bit in this register in order to clear the corresponding bit in was_error_vf_95_64 register…
48939 …1 to a bit in this register in order to clear the corresponding bit in was_error_vf_127_96 registe…
48940 …1 to a bit in this register in order to clear the corresponding bit in was_error_vf_159_128 regist…
48941 …1 to a bit in this register in order to clear the corresponding bit in was_error_vf_191_160 regist…
48942 …1 to a bit in this register in order to clear the corresponding bit in was_error_vf_223_192 regist…
48943 …1 to a bit in this register in order to clear the corresponding bit in was_error_vf_255_224 regist…
48944 …1 to a bit in this register in order to clear the corresponding bit in flr_request_pf_31_0 registe…
48945 …- PFID. [4] - VF_VALID. [12:5] - VFID. [14:13] - Error Code - 0 - Indicates Completion Timeout of …
48946 …- PFID. [4] - VF_VALID. [12:5] - VFID. [14:13] - Error Code - 0 - Indicates Completion Timeout of …
48949 …ot submitted due to error. [4:0] VQID. [17:5] - Length in bytes. [19] - VF_VALID. [23:20] - PFID. …
48950 …- Error type - [21] - Indicates was_error was set; [22] - Indicates BME was cleared; [23] - Indica…
48953 …VQID. [5] TREQ. 1 - Indicates the request is a Translation Request. [18:6] - Length in bytes. [19]…
48954 …- Error type - [21] - Indicates was_error was set; [22] - Indicates BME was cleared; [23] - Indica…
48955 …- PFID. [11:4] - VFID. [12] - VF_VALID. [17:13] - ITAG Index. [21:18] - Error type - [18] - Indic…
48956 …68UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-VF for master and tar…
48957 …6cUL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for master transac…
48958 …70UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for target write t…
48959 …74UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for target read tr…
48968 …pfid_enable registers for target flow. Bits [15:0] - internal_pfid_enable_target_write; Bits [31:1…
48969 … global view of internal_pfid_enable registers for master flow. Bits [15:0] - internal_pfid_enable…
49000 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49001 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49002 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49003 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49004 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49005 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49006 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49007 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49008 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49009 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49010 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49011 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49012 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49013 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49014 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49015 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49016 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49017 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49018 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49019 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49020 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49021 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49022 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49023 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49024 … 0x2aa318UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49025 … 0x2aa31cUL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49026 … 0x2aa320UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49027 … 0x2aa324UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49028 … 0x2aa328UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49029 … 0x2aa32cUL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49030 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49031 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49032 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49033 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49034 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49035 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49036 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49037 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49038 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49039 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49040 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49041 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49042 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49043 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49044 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49045 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49046 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49047 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49048 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49049 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49050 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49051 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49052 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49053 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49054 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49055 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49056 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49057 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49058 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49059 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49060 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49061 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49062 …R0. [12:0] Address in DWs (bits [14:2] of byte address). [14:13] BAR. [22:15] VFID. [26:23] - PFID.
49063 …- Length in DWs. [6] valid - indicates if there was a request with length violation since the las…
49064 …ermission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write. [23:16] VFID. [27:24] - PFID. [28…
49065 …1 to each bit in this register clears a corresponding error details register and enables logging n…
49066 … 0x2aa3c0UL //Access:RW DataWidth:0x20 // Each bit when set indicates that IDO bit tow…
49067 … 0x2aa3c4UL //Access:RW DataWidth:0x1 // Bit 0 - when set indicates that IDO bit t…
49068 … 0x2aa3c8UL //Access:RW DataWidth:0x1 // Bit 0 - when set indicates that IDO bit t…
49069 …/Access:RW DataWidth:0x1 // 1 - Do not discard IGU master transactions for PF when the corres…
49070 …- Accesses to the first 8KB of IGU in BAR0 (MSIX table and PBA) are not allowed. When this value i…
49071 …pletion is considered erroneous. [3:0] - PFID. [4] - VF_VALID. [12:5] - VFID. [17:13] - OTB EntryI…
49072 …- Unsupported Request or Completer Abort on User RX Interface. 1 - Reception of a poisoned TLP on …
49073 …ccess:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset;…
49074 …ccess:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset;…
49075 …only: 0 - Enable the fix for CQ45220. If a Function receives a Translation Completion with a Trans…
49076 …ccess:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset;…
49077 …ccess:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset;…
49094 … lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end…
49096 … lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end…
49098 … lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end…
49100 … lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end…
49102 … lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end…
49104 … lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end…
49106 … lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end…
49108 … lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end…
49110 …bit in this read-only register reflects the value of the corresponding 'PF trusted' config bit on …
49113 …1 - Indicates the request is a Translation Request. [9:6] - PFID. [10] - VF_VALID. [18:11] - VFID.…
49114 …1' and with either address not DW aligned or length not a multiple of DWs. 0 - PGLUE will submit t…
49115 …1DW or first byte enable != 0xf . [9:0] Address in DWs (bits [11:2] of byte address). [13:10] BE f…
49116 …- original PFID. [7:4] Pretend PFID. [15:8] Pretend VFID. [16] Pretend vf_valid. [20:17] Pretend r…
49118 …2aa560UL //Access:RW DataWidth:0x1 // 0 - Work with external BAR0 mechanism as defined in E4 …
49125 …57cUL //Access:RW DataWidth:0x1 // FID channel enable configuration per-VF. Controls Target …
49126 …l is enabled for that SDM. One bit per SDM. Bit 0 - TSDM. Bit 1 - MSDM. Bit 2 - USDM. Bit 3 - XSDM…
49127 …3 // Window size for VF to PF channel. 0 - NA; 1 - 8B; 2 - 16B; 3 - 32B; 4 - 64B; 5 - 128B; 6 -…
49130 … (0x1<<0) // Decision bit for PF master requests when BME is cleared: 0 - b…
49132 … (0x1<<1) // Decision bit for PF master requests when fid_enable is cle…
49133 …GLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_PF_FID_ENABLE_SHIFT 1
49134 … (0x1<<2) // Decision bit for PF master requests when was_error is set: 0 - …
49136 … (0x1<<3) // Decision bit for VF master requests when BME is cleared: 0 - b…
49138 … (0x1<<4) // Decision bit for VF master requests when fid_enable is cleared: 0…
49140 … (0x1<<5) // Decision bit for VF master requests when was_error is set: 0 - …
49143 …hen BME is cleared: 0 - Always set (and log error details); 1 - never set attention; 2 - set atten…
49145 …enabled is cleared: 0 - Always set (and log error details); 1 - never set attention; 2 - set atten…
49147 …n was_error is set: 0 - Always set (and log error details); 1 - never set attention; 2 - set atten…
49149 …hen BME is cleared: 0 - Always set (and log error details); 1 - never set attention; 2 - set atten…
49151 …enabled is cleared: 0 - Always set (and log error details); 1 - never set attention; 2 - set atten…
49153 …n was_error is set: 0 - Always set (and log error details); 1 - never set attention; 2 - set atten…
49155 …en this bit is set and attntion setting configuration is 2 any block or discard event for that fun…
49156 …en this bit is set and attntion setting configuration is 2 any block or discard event for that fun…
49157 … 0x2aa800UL //Access:WB_R DataWidth:0xfb // Debug only and read only: Each entry …
49159 … 0x2aac00UL //Access:WB_R DataWidth:0xae // Debug only and read only: Each entry …
49161 … 0x2aae00UL //Access:R DataWidth:0x5 // Debug only: Occupancy level in…
49162 …ss:RW DataWidth:0x1 // A value of '1' instructs PGLUE to use the client ID value in the 'tag'…
49163 …8UL //Access:RW DataWidth:0x1 // This field is an enable bit for 'detection of out-of-range r…
49165 … of ) the minimal legal address value. It is used in the 'detection of out-of-range requests' debu…
49167 … of ) the maximal legal address value. It is used in the 'detection of out-of-range requests' debu…
49171 …th illegal address. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20]…
49172 …- address was smaller than minimal_address_log; 1 - address was bigger than maximal_address_log. …
49175 …th TPH information. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20]…
49176 …nt ID. [6:5] PH. [14:7] Steering Tag. [15] - write_n_read: 0 - read; 1 - write. [16] - last SR. […
49177 …x1 // 0 - never pad write sub-requests with zeros. 1 - Pad write sub-requests with zeros and al…
49178 …/Access:RW DataWidth:0x3 // Cache line size for padding. 0 - 32B. 1 - 64B. 2 - 128B. 3 - 256B.
49179 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49180 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49181 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49182 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49183 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49184 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49185 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49186 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49188 …ut writing it from config space generates Kernel warning. For these cases only it should be writte…
49189 …G_PCIER_CONFIG_2) and configure to this register. Decoding: 0 disabled; 1 64K; 2 128K; up to 15 1G.
49190 …1 64K; 2 128K; up to 15 1G. When using resizable BAR, the driver should read the value from BAR_SI…
49191 …PCIER_REG_VF_BAR_REG) and configure to this register. Decoding: 0 disabled; 1 4K; 2 8K; up to 15 6…
49192 …that was genertaed due to bus number change detected by PCIe IP. MCP writes 1 to this register in …
49196 …t error indication. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20]…
49197 …[15:0] Request ID. [20:16] client ID. [21] - write_n_read: 0 - read; 1 - write. [22] - last SR. […
49198 … DataWidth:0x10 // Atomic Op requester enable register for all PFs. Each bit indicates if Atomic…
49199 …M attention dirty bits. Bit 0 is for engine 0 and bit 1 for engine 1. Set by PXP. Reset by MCP wri…
49200 …y bits clear. Bit 0 is for engine 0 and bit 1 for engine 1. MCP writes 1 to a bit in this register…
49201 … DataWidth:0x10 // MPS attention dirty bit. Set by PXP. Reset by MCP writing 1 to the corresp…
49202 …h:0x10 // MPS attention dirty bit clear. MCP writes 1 to a bit in this register in order to clea…
49203 … DataWidth:0x10 // VPD request attention dirty bits for all PFs. Each bit indicates that the …
49204 …bit corresponds to a PF in the path. A value of 0 indicates the power state of this PF is not take…
49208 … 0x2aaeacUL //Access:RW DataWidth:0x1 // Value of 1 indicates that was_e…
49209 … 0x2aaeb0UL //Access:RW DataWidth:0x1 // Chicken bit to disable app_xfer…
49210 …E_REG_PCIER_REG_VF_BAR_REG) and configure to this register. Decoding: 0 2K; 1 4K; 2 8K; up to 15 6…
49211 …E_REG_PCIER_REG_VF_BAR_REG) and configure to this register. Decoding: 0 2k; 1 4K; 2 8K; up to 15 6…
49220 … 0x2aaedcUL //Access:RW DataWidth:0x1 // enable drop packet when TD is 1
49222 …ataWidth:0x1 // Disable master read back 2 back transition IT's checken bit for perfomance impr…
49233 … 0x2aaf10UL //Access:R DataWidth:0x10 // pm_dstate 47-032
49234 …er if check tc on error = 0 Then we will not check TC If check tc on error =1. we need check if TC…
49235 … 0x2aaf60UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 31-0
49236 … 0x2aaf64UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 63 -32
49237 … 0x2aaf68UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 95 - 64
49238 … 0x2aaf6cUL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 127 - 96
49239 … 0x2aaf70UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 159-128
49243 …20 // Indicates there was an error in MCTP BIt 21-30 Message code Bit 7-22 Vender ID Bit 3-6 …
49244 …aWidth:0x20 // Indicates there was an error in MCTP Bit 21-30 Length Bit 5-20 PCIE REQ ID Bit 0…
49256 …0x2aafb4UL //Access:RW DataWidth:0x1 // 0 - Don't discard target request with unknown header …
49257 …cess:RW DataWidth:0x1 // 0 - Don't compare the function received in the completion to the ori…
49258 …dth:0x1 // 0 - Enable b2b pop from sync fifos in pgl_pci_core_rx. 1 - Disable b2b pop from sync…
49259 … 0x2aafc0UL //Access:RW DataWidth:0x1 // 0 - Don't discard master request during FLR 1 …
49260 … DataWidth:0x4 // 0 - TXCPL sync fifo push overflow 1 - TXR sync fifo push overflow 2 - TXW hea…
49261 … // 0 - RX target read and config sync fifo pop underflow 1 - RX header sync fifo pop underflow…
49262 …x2aafccUL //Access:R DataWidth:0x12 // 8:0 - RX target read and config sync fifo pop status …
49263 …2aafd0UL //Access:R DataWidth:0x1c // RX data sync fifo pop status (7 bit per each 128b insta…
49267 …_CONFIG_CONN_MEM_SELF_INIT_START (0x1<<1) // Reset the config…
49268 …M_REG_MEMORY_SELF_INIT_START_CONFIG_CONN_MEM_SELF_INIT_START_SHIFT 1
49273 …Width:0x1 // When set, the self init for the context memory is done. TBD - need to change to re…
49300 …A_FIFO_OV (0x1<<1) // PXP READ DATA FI…
49301 …M_REG_INT_STS_0_PXP_READ_DATA_FIFO_OV_SHIFT 1
49350 … (0x1<<26) // INIT command and the logical client valid bit is asserted.
49363 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
49365 … (0x1<<1) // This bit masks, when set, the Interrupt …
49366 …M_REG_INT_MASK_0_PXP_READ_DATA_FIFO_OV_SHIFT 1
49367 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
49369 … (0x1<<3) // This bit masks, when set, the Interrupt bit: T…
49371 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
49373 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
49375 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
49377 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
49379 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
49381 … (0x1<<9) // This bit masks, when set, the Interrupt bit: T…
49383 … (0x1<<10) // This bit masks, when set, the Interrupt bit: T…
49385 … (0x1<<11) // This bit masks, when set, the Interrupt bit: T…
49387 … (0x1<<12) // This bit masks, when set, the Interrupt bit: T…
49389 … (0x1<<13) // This bit masks, when set, the Interrupt bit: T…
49391 … (0x1<<14) // This bit masks, when set, the Interrupt bit: T…
49393 … (0x1<<15) // This bit masks, when set, the Interrupt bit: T…
49395 … (0x1<<16) // This bit masks, when set, the Interrupt bit: T…
49397 … (0x1<<17) // This bit masks, when set, the Interrupt bit: T…
49399 … (0x1<<18) // This bit masks, when set, the Interrupt bit: T…
49401 … (0x1<<19) // This bit masks, when set, the Interrupt bit: T…
49403 … (0x1<<20) // This bit masks, when set, the Interrupt bit: T…
49405 … (0x1<<21) // This bit masks, when set, the Interrupt bit: T…
49407 … (0x1<<22) // This bit masks, when set, the Interrupt bit: T…
49409 … (0x1<<23) // This bit masks, when set, the Interrupt bit: T…
49411 … (0x1<<24) // This bit masks, when set, the Interrupt bit: T…
49413 … (0x1<<25) // This bit masks, when set, the Interrupt bit: T…
49415 … (0x1<<26) // This bit masks, when set, the Interrupt bit: T…
49417 … (0x1<<27) // This bit masks, when set, the Interrupt bit: T…
49419 … (0x1<<28) // This bit masks, when set, the Interrupt bit: T…
49421 … (0x1<<29) // This bit masks, when set, the Interrupt bit: T…
49423 … (0x1<<30) // This bit masks, when set, the Interrupt bit: T…
49425 … (0x1<<31) // This bit masks, when set, the Interrupt bit: T…
49430 …DATA_FIFO_OV (0x1<<1) // PXP READ DATA FI…
49431 …M_REG_INT_STS_WR_0_PXP_READ_DATA_FIFO_OV_SHIFT 1
49480 … (0x1<<26) // INIT command and the logical client valid bit is asserted.
49495 …_DATA_FIFO_OV (0x1<<1) // PXP READ DATA FI…
49496 …M_REG_INT_STS_CLR_0_PXP_READ_DATA_FIFO_OV_SHIFT 1
49545 … (0x1<<26) // INIT command and the logical client valid bit is asserted.
49560 …LIDERR_CONN (0x1<<1) // Connections Load…
49561 …M_REG_INT_STS_1_CLOAD_RES_VALIDERR_CONN_SHIFT 1
49562 … (0x1<<2) // Context Read with Last indication de-asserted.
49564 … (0x1<<3) // Context Write with Last indication de-asserted.
49581 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
49583 … (0x1<<1) // This bit masks, when set, the Interrupt …
49584 …M_REG_INT_MASK_1_CLOAD_RES_VALIDERR_CONN_SHIFT 1
49585 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
49587 … (0x1<<3) // This bit masks, when set, the Interrupt bit: T…
49589 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
49591 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
49593 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
49595 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
49597 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
49599 … (0x1<<9) // This bit masks, when set, the Interrupt bit: T…
49601 … (0x1<<10) // This bit masks, when set, the Interrupt bit: T…
49606 …_VALIDERR_CONN (0x1<<1) // Connections Load…
49607 …M_REG_INT_STS_WR_1_CLOAD_RES_VALIDERR_CONN_SHIFT 1
49608 … (0x1<<2) // Context Read with Last indication de-asserted.
49610 … (0x1<<3) // Context Write with Last indication de-asserted.
49629 …S_VALIDERR_CONN (0x1<<1) // Connections Load…
49630 …M_REG_INT_STS_CLR_1_CLOAD_RES_VALIDERR_CONN_SHIFT 1
49631 … (0x1<<2) // Context Read with Last indication de-asserted.
49633 … (0x1<<3) // Context Write with Last indication de-asserted.
49650 … (0x1<<0) // This bit masks, when set, the Parity bit: TM…
49652 … (0x1<<9) // This bit masks, when set, the Parity bit: TM…
49654 … (0x1<<1) // This bit masks, when set, the Parity bi…
49655 …M_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5_SHIFT 1
49656 … (0x1<<11) // This bit masks, when set, the Parity bit: TM…
49658 … (0x1<<2) // This bit masks, when set, the Parity bit: TM…
49660 … (0x1<<4) // This bit masks, when set, the Parity bit: TM…
49662 … (0x1<<3) // This bit masks, when set, the Parity bit: TM…
49664 … (0x1<<12) // This bit masks, when set, the Parity bit: TM…
49666 … (0x1<<4) // This bit masks, when set, the Parity bit: TM…
49668 … (0x1<<13) // This bit masks, when set, the Parity bit: TM…
49670 … (0x1<<5) // This bit masks, when set, the Parity bit: TM…
49672 … (0x1<<6) // This bit masks, when set, the Parity bit: TM…
49674 … (0x1<<7) // This bit masks, when set, the Parity bit: TM…
49676 … (0x1<<5) // This bit masks, when set, the Parity bit: TM…
49678 … (0x1<<8) // This bit masks, when set, the Parity bit: TM…
49680 … (0x1<<10) // This bit masks, when set, the Parity bit: TM…
49682 … (0x1<<9) // This bit masks, when set, the Parity bit: TM…
49684 … (0x1<<8) // This bit masks, when set, the Parity bit: TM…
49686 … (0x1<<10) // This bit masks, when set, the Parity bit: TM…
49688 … (0x1<<15) // This bit masks, when set, the Parity bit: TM…
49690 … (0x1<<11) // This bit masks, when set, the Parity bit: TM…
49692 … (0x1<<16) // This bit masks, when set, the Parity bit: TM…
49694 … (0x1<<12) // This bit masks, when set, the Parity bit: TM…
49696 … (0x1<<13) // This bit masks, when set, the Parity bit: TM…
49698 … (0x1<<6) // This bit masks, when set, the Parity bit: TM…
49700 … (0x1<<14) // This bit masks, when set, the Parity bit: TM…
49702 … (0x1<<0) // This bit masks, when set, the Parity bit: TM…
49704 … (0x1<<1) // This bit masks, when set, the Parity bi…
49705 …M_REG_PRTY_MASK_H_0_MEM012_I_ECC_1_RF_INT_BB_K2_SHIFT 1
49706 … (0x1<<2) // This bit masks, when set, the Parity bit: TM…
49708 … (0x1<<3) // This bit masks, when set, the Parity bit: TM…
49710 … (0x1<<14) // This bit masks, when set, the Parity bit: TM…
49717 …2_I_ECC_1_EN_BB_K2 (0x1<<1) // Enable ECC for m…
49718 …M_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_1_EN_BB_K2_SHIFT 1
49722 …_0_E5 (0x1<<0) // Set parity only for memory ecc inst…
49724 …_BB_K2 (0x1<<0) // Set parity only for memory ecc inst…
49726 …CC_1_PRTY_BB_K2 (0x1<<1) // Set parity only for memory…
49727 …M_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_1_PRTY_BB_K2_SHIFT 1
49728 …B_K2 (0x1<<2) // Set parity only for memory ecc inst…
49735 …D_0_MEM012_I_ECC_1_CORRECT_BB_K2 (0x1<<1) // Record if a corr…
49736 …M_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_1_CORRECT_BB_K2_SHIFT 1
49742 … // Almost full threshold for the CFC LOAD COMMAND FIFO, which its size is 16 rows. For Debug only.
49743 …:0x4 // Almost full threshold for the CLIENT OUT FIFO, which its size is 4 rows. For Debug only.
49744 …3 // Almost full threshold for the CLIENT IN PBF FIFO, which its size is 4 rows. For Debug only.
49745 …3 // Almost full threshold for the CLIENT IN XCM FIFO, which its size is 4 rows. For Debug only.
49746 …3 // Almost full threshold for the CLIENT IN TCM FIFO, which its size is 4 rows. For Debug only.
49747 …3 // Almost full threshold for the CLIENT IN UCM FIFO, which its size is 4 rows. For Debug only.
49748 …// Almost full threshold for the EXPIRATION COMMAND FIFO, which its size is 8 rows. For Debug only.
49749 … // Almost full threshold for the CFC LOAD ECHO FIFO, which its size is 16 rows. For Debug only.
49750 …0x4 // Almost full threshold for the AC COMMAND FIFO, which its size is 12 rows. For Debug only.
49751 …le the VF functions for the connections. This configuration is applicable only to scan operation. …
49752 …able the PF functions for the connections. This configuration is applicable only to scan opeartion.
49753 …/ Enable the VF functions for the tasks. This configuration is applicable only to scan operation. …
49754 …s. This configuration is applicable only to scan opeartion. Bit 0: segment 0, bit 1: segment 1, bi…
49769 … the pci outstanding read requests, generated by the scan engine. The applicable values are 1 to 4.
49770 …x2 // Number of timers per connection group: 00 - 128 timers, 01 - 64 timers, 10 - 32 timers, 1…
49771 …idth:0x2 // Number of timers per task group: 00 - 128 timers, 01 - 64 timers, 10 - 32 timers, 1…
49772 …- the pre scan feature is disabled, i.e. every scan pulse all the groups are scanned. 01 - each gr…
49773 …- the pre scan feature is disabled, i.e. every scan pulse all the groups are scanned. 01 - each gr…
49774 …en set, the pre scan memory is bypassed. This configuration is applicable only if PreScanRange reg…
49776 …lock in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49777 …lock in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49778 …ckss in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49779 …eld for writes; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49780 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49781 …1, per each connection type (16 types), configuration of the applicable client out interface that …
49782 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49783 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49784 …1, per each task type (8 types), configuration of the applicable client out interface that the exp…
49785 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49786 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49787 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49788 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49789 …1, per each connection type (16 types), configuration of the threshold on the nearest expiration f…
49790 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49791 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49792 …1, per each task type (8 types), configuration of the threshold on the nearest expiration for send…
49793 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49795 … 0x2c04e8UL //Access:RW DataWidth:0x19 // A threshold value, 1 , for connections, w…
49798 … 0x2c04f4UL //Access:RW DataWidth:0x19 // A threshold value, 1 , for tasks which is…
49800 … if the PF connection is active, ie if it is during the scan process. When =1, the PF connection i…
49801 …ring the scan process. Bit 0 is for segment 0, bit 1 is for segment 1, bit 2 is for segment 2 and …
49802 … if the VF connection is active, ie if it is during the scan process. When =1, the VF connection i…
49803 …icates if the VF task is active, ie if it is during the scan process. When =1, the VF task is acti…
49804 … // Indicates if the block is during the connections scan process. When =1, the block is during…
49805 …th:0x1 // Indicates if the block is during the tasks scan process. When =1, the block is during…
49806 …dicates if the block is during the tasks or connections scan process. When =1, the block is during…
49854 …Bit [0]: if = 1, the following error is enabled: STOP_ALL_TIMERS command and the logical client i…
49855 …UL //Access:RW DataWidth:0x1 // If enabled, if the error took place, only a command with erro…
49856 …ataWidth:0x10 // If debug_0_fid_en is enabled, if the error took place, only a command with erro…
49857 …UL //Access:RW DataWidth:0x1 // If enabled, if the error took place, only a command with erro…
49858 …only a command with error for the source identical to this regsiter is kept in the debug_0 registe…
49859 …idth:0x1 // When asserted, = 1, indicates that the debug_0 registers contain valid data. Assert…
49863 …- SET TIMER, 1 - CLEAR TIMER, 2 - STOP ALL TIMERS, 3 - INIT, 4 - FORCE CLEAR TIMER, 5 - reserved,…
49866 …s:R DataWidth:0x1 // The Leader Type field for the errored command: 0 - connection, 1 - task.
49867 …r the errored command. The source: 0 - PBF, 1 -TCM, 2- UCM, 3 - XCM, 4 - expiration, 5 - reserved,…
49868 …Bit 0: logical client 0 valid bit, Bit 1: logical client 0 active bit, Bit 2: logical client 1 val…
49869 …Bit [0]: if = 1, the following error happened: STOP_ALL_TIMERS command and the logical client is …
49870 …idth:0x1 // When asserted, = 1, indicates that the debug_1 registers contain valid data. Assert…
49872 …-0: LCID, Bit 9: scan type (0 - connection, 1 - task), Bits 12-10: type (3 LSbits), Bit 13: Load E…
49873 …idth:0x1 // When asserted, = 1, indicates that the debug_2 registers contain valid data. Assert…
49874 …last indication de-asserted fields: Bits 8-0: LCID, Bit 9: Type (0 - connection, 1 - task), Bit 10…
49875 …idth:0x1 // When asserted, = 1, indicates that the debug_3 registers contain valid data. Assert…
49876 …ion de-asserted fields: Bits 8-0: LCID, Bit 9: Type (0 - connection, 1 - task), Bit 11-10: Qward V…
49877 …-0: cmd_handler. Bit 3: reserved. Bits 7-4: writ…
49878 …idth:0x1 // When asserted, = 1, indicates that the debug_4 registers contain valid data. Assert…
49879 … Bits 8-0: function # (0-239 VFs, 240 and above PFs / segments) . Bit 9: type (0 - connecti…
49881 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
49882 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
49883 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
49884 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
49889 …1 for VF1, row 2 for VF 2, etc. Rows 240 to 255 are for the PFs: row 240 for PF 0, row 193 for PF …
49893 …1 for VF1, row 2 for VF 2, etc. Rows 240 to 303 are for the PFs segments: row 240 for PF 0 segment…
49897 …r connections, the last 512 rows contain the scan rate fields for tasks. TBD - describe the fields.
49906 … (0x1ff<<1) // This field is only relevant …
49907 …CFC_REG_INIT_REG_LL_INIT_LAST_LCID_SHIFT 1
49908 … (0x1<<10) // When set link list ram will be initialized - all LCIDs will be lo…
49912 … (0x1<<12) // Setting this bit causes the TID Lock RAM to be initialized. This cannot be set du…
49921 … (0x1<<1) // Interrupt indica…
49922 …CFC_REG_INT_STS_0_EXE_ERROR_SHIFT 1
49924 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
49926 … (0x1<<1) // This bit masks, when set, the Interrupt …
49927 …CFC_REG_INT_MASK_0_EXE_ERROR_SHIFT 1
49931 …OR (0x1<<1) // Interrupt indica…
49932 …CFC_REG_INT_STS_WR_0_EXE_ERROR_SHIFT 1
49936 …ROR (0x1<<1) // Interrupt indica…
49937 …CFC_REG_INT_STS_CLR_0_EXE_ERROR_SHIFT 1
49939 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
49941 … (0x1<<1) // This bit masks, when set, the Parity bi…
49942 …CFC_REG_PRTY_MASK_H_0_MEM003_I_ECC2_RF_INT_E5_SHIFT 1
49943 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
49945 … (0x1<<2) // This bit masks, when set, the Parity bit: TC…
49947 … (0x1<<1) // This bit masks, when set, the Parity bi…
49948 …CFC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT 1
49949 … (0x1<<3) // This bit masks, when set, the Parity bit: TC…
49954 …003_I_ECC2_EN_E5 (0x1<<1) // Enable ECC for m…
49955 …CFC_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC2_EN_E5_SHIFT 1
49957 …Y_E5 (0x1<<0) // Set parity only for memory ecc inst…
49959 …_ECC2_PRTY_E5 (0x1<<1) // Set parity only for memory…
49960 …CFC_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC2_PRTY_E5_SHIFT 1
49964 …TED_0_MEM003_I_ECC2_CORRECT_E5 (0x1<<1) // Record if a corr…
49965 …CFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC2_CORRECT_E5_SHIFT 1
49981 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
49982 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
49983 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
49984 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
49989 …0x8 // Eco reserved. bit0: Chicken bit for CQ73536 fix. When '0' takes into account LCIDs in t…
49990 … when the CFC detects an internal error it will set one of these bits. the bit description can be …
49991 …ataWidth:0x11 // Masking for error logging. if a bit in this field is set then the corresponding…
49993 …-- CFC Controller ID [20:16] -- CFC Client ID [15:08] -- Requested Regions [04:00] -- Error ID Not…
49994 … DataWidth:0x20 // When the CFC detects an internal error it updates these fields. [31:00] -- CID
49995 …CFC detects an internal error it updates these fields. [24:16] -- Request LCID [08:00] -- Active L…
49996 …an internal error it updates these fields. [23:16] -- Increment Value [15:12] -- Type Field [08:00…
50000 …EQ_ARB (0x1<<1) // When set load co…
50001 …CFC_REG_ARBITERS_REG_SP_LC_REQ_ARB_SHIFT 1
50010 …Width:0x3 // This field allows changing the priorities of the weighted-round-robin arbiter whic…
50014 … (0x1<<0) // This bit disables the inputs…
50016 … (0x1<<1) // This bit disables the o…
50017 …CFC_REG_DEBUG0_DISABLE_OUTPUTS_SHIFT 1
50018 …ER_ZERO (0xff<<2) // Debug only.
50020 … (0xf<<10) // This register is not used in BB-B0. Reduced width to 1 bit to keep…
50022 …OLD (0x7<<14) // Debug only.
50024 …SHOLD (0x7<<17) // Debug only.
50026 …HOLD (0x7<<20) // Debug only.
50029 …RESHOLD (0xf<<0) // Debug only.
50031 …C (0x1<<4) // Debug only.
50033 …AC (0x1<<5) // Debug only.
50035 … (0x3<<6) // Debug only.
50037 …OM_REQ (0x1<<8) // Debug only.
50039 …EL_STATE (0x1<<9) // Debug only.
50041 … (0x1<<10) // Debug only.
50043 …T_CLR (0x1<<11) // Debug only.
50045 …EL_DIS (0x1<<12) // Debug only.
50048 …or DORQ Client on Virtual Functions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mas…
50049 …or DORQ Client on Virtual Functions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mas…
50050 …or DORQ Client on Virtual Functions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mas…
50055 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
50057 … (0x1<<1) // This bit masks, when set, the Parity bi…
50058 …CFC_REG_PRTY_MASK_SCAM_PAR_ERR_SHIFT 1
50059 … (0x1<<2) // This bit masks, when set, the Parity bit: TC…
50061 … (0x1<<3) // This bit masks, when set, the Parity bit: TC…
50063 … (0x1<<4) // This bit masks, when set, the Parity bit: TC…
50065 … (0x1<<5) // This bit masks, when set, the Parity bit: TC…
50078 … 0x2d0700UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cance…
50079 … 0x2d0704UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cance…
50080 …s:RW DataWidth:0x1 // This bit when clear will cause a CFC execution error (weak_enable will …
50081 …s:RW DataWidth:0x1 // This bit when clear will cause a CFC execution error (weak_enable will …
50086 … (0x1<<10) // This field is not used in BB-B0. When set, this configuration bit wi…
50092 … (0x1<<9) // When set to 1 the search string ca…
50094 … (0x1<<10) // When set to 1 the cid cam is disab…
50096 … (0x1<<11) // New Load On Error. if this bit is set and there is…
50098 … (0x1<<12) // When set to 1 the string cam hit p…
50100 … (0x1<<13) // When set to 1 the string cam miss …
50102 … (0x1<<14) // When set to 1 the cid cam hit pari…
50104 … (0x1<<15) // When set to 1 the cid cam miss par…
50112 …L //Access:RW DataWidth:0x7 // Set the initial credit for the CDU write-back interface if les…
50113 … Array of indirect registers defines the forced load regions per type. Applicable only in the TCFC.
50125 … //Access:RW DataWidth:0x9 // This is the LCID Threshold for LC CLient 1 (XYLD). When the num…
50139 …bit corresponds to one of the state machines [2:0]. Writing the bits to 1'b1 will restart the Time…
50141 … (0x1<<0) // This is the Enable bit for the LCID Limiti…
50143 … (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #0. The Waveform wi…
50144 …CFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_POLARITY_SHIFT 1
50150 … (0x1<<0) // This is the Enable bit for the LCID Limiting Waveform Generator …
50152 … (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #1. The Waveform wi…
50153 …CFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_POLARITY_SHIFT 1
50154 … DataWidth:0xe // This is the list of LC Clients that will be affected by Waveform Generator #1.
50155 …9 // This is the Threshold value of active LCIDs that triggers masking by Waveform Generator #1.
50156 … DataWidth:0x10 // This is the count of cycles that Waveform Generator #1 will output a ZERO v…
50157 … DataWidth:0x10 // This is the count of cycles that Waveform Generator #1 will output a ONE va…
50159 … (0x1<<0) // This is the Enable bit for the LCID Limiti…
50161 … (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #2. The Waveform wi…
50162 …CFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_POLARITY_SHIFT 1
50167 …bit in this register matches the corresponding String Type. Bit[0] = TCP Bit[1] = UDP Bit[2] …
50171 …NABLE_L2_CACHING (0x1<<1) // When set, the St…
50172 …CFC_REG_SCAM_CACHE_ENABLES_ENABLE_L2_CACHING_SHIFT 1
50173 …nd Writes to the CID CAM. Setting a bit to 0 will ignore that bit in a search. Setting a bit to 0 …
50174 … 0x2d0a0cUL //Access:RW DataWidth:0x1 // When this bit is set writing to t…
50185 … 0x2d0a38UL //Access:RW DataWidth:0x1 // When this bit is set writing to t…
50186 … 0x2d0a3cUL //Access:R DataWidth:0xa // {HIT;LCID}. HIT - if set then previous…
50187 …- tid is not included in hash calculation (like in A0). 1 - tid is included in hash calculation by…
50188 …- vlan is not included in hash calculation (like in A0). 1 - vlan is included in hash calculation …
50192 … 0x2d0b0cUL //Access:R DataWidth:0x20 // Provides read-only access to the CID …
50196 … 0x2d0b1cUL //Access:R DataWidth:0x20 // Provides read-only access to the STRI…
50207 … 0x2db000UL //Access:WB DataWidth:0x21 // CID cam access (Valid - 32;31:0 - Data).
50213 … 0x2dd000UL //Access:RW DataWidth:0x7 // State select vector for VF/PF LCID state counter 1 .
50215 … 0x2dd008UL //Access:R DataWidth:0x9 // VF port to VF/PF LCID state counter 1 .
50216 … 0x2dd00cUL //Access:R DataWidth:0x9 // PF port to VF/PF LCID state counter 1 .
50222 … (0x1ff<<1) // This field is only relevant …
50223 …CFC_REG_INIT_REG_LL_INIT_LAST_LCID_SHIFT 1
50224 … (0x1<<10) // When set link list ram will be initialized - all LCIDs will be lo…
50228 … (0x1<<12) // Setting this bit causes the TID Lock RAM to be initialized. This cannot be set du…
50233 … 0x2e0010UL //Access:R DataWidth:0x1 // This bit does not exist for CCFC and will always rea…
50237 … (0x1<<1) // Interrupt indica…
50238 …CFC_REG_INT_STS_0_EXE_ERROR_SHIFT 1
50240 … (0x1<<0) // This bit masks, when set, the Interrupt bit: C…
50242 … (0x1<<1) // This bit masks, when set, the Interrupt …
50243 …CFC_REG_INT_MASK_0_EXE_ERROR_SHIFT 1
50247 …OR (0x1<<1) // Interrupt indica…
50248 …CFC_REG_INT_STS_WR_0_EXE_ERROR_SHIFT 1
50252 …ROR (0x1<<1) // Interrupt indica…
50253 …CFC_REG_INT_STS_CLR_0_EXE_ERROR_SHIFT 1
50255 … (0x1<<0) // This bit masks, when set, the Parity bit: CC…
50257 … (0x1<<1) // This bit masks, when set, the Parity bi…
50258 …CFC_REG_PRTY_MASK_H_0_MEM005_I_ECC2_RF_INT_E5_SHIFT 1
50259 … (0x1<<0) // This bit masks, when set, the Parity bit: CC…
50261 … (0x1<<2) // This bit masks, when set, the Parity bit: CC…
50263 … (0x1<<3) // This bit masks, when set, the Parity bit: CC…
50265 … (0x1<<4) // This bit masks, when set, the Parity bit: CC…
50267 … (0x1<<5) // This bit masks, when set, the Parity bit: CC…
50269 … (0x1<<1) // This bit masks, when set, the Parity bi…
50270 …CFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT 1
50274 …005_I_ECC2_EN_E5 (0x1<<1) // Enable ECC for m…
50275 …CFC_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC2_EN_E5_SHIFT 1
50285 …Y_E5 (0x1<<0) // Set parity only for memory ecc inst…
50287 …_ECC2_PRTY_E5 (0x1<<1) // Set parity only for memory…
50288 …CFC_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC2_PRTY_E5_SHIFT 1
50289 …_E5 (0x1<<2) // Set parity only for memory ecc inst…
50291 …_E5 (0x1<<3) // Set parity only for memory ecc inst…
50293 …_E5 (0x1<<4) // Set parity only for memory ecc inst…
50295 …LY_0_BB_K2 (0x1<<0) // Set parity only for memory ecc inst…
50300 …TED_0_MEM005_I_ECC2_CORRECT_E5 (0x1<<1) // Record if a corr…
50301 …CFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC2_CORRECT_E5_SHIFT 1
50324 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
50325 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
50326 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
50327 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
50332 …0x8 // Eco reserved. bit0: Chicken bit for CQ73536 fix. When '0' takes into account LCIDs in t…
50333 … when the CFC detects an internal error it will set one of these bits. the bit description can be …
50334 …ataWidth:0x11 // Masking for error logging. if a bit in this field is set then the corresponding…
50336 …-- CFC Controller ID [20:16] -- CFC Client ID [15:08] -- Requested Regions [04:00] -- Error ID Not…
50337 … DataWidth:0x20 // When the CFC detects an internal error it updates these fields. [31:00] -- CID
50338 …CFC detects an internal error it updates these fields. [24:16] -- Request LCID [08:00] -- Active L…
50339 …an internal error it updates these fields. [23:16] -- Increment Value [15:12] -- Type Field [08:00…
50343 …EQ_ARB (0x1<<1) // When set load co…
50344 …CFC_REG_ARBITERS_REG_SP_LC_REQ_ARB_SHIFT 1
50353 …Width:0x3 // This field allows changing the priorities of the weighted-round-robin arbiter whic…
50357 … (0x1<<0) // This bit disables the inputs…
50359 … (0x1<<1) // This bit disables the o…
50360 …CFC_REG_DEBUG0_DISABLE_OUTPUTS_SHIFT 1
50361 …ER_ZERO (0xff<<2) // Debug only.
50363 … (0xf<<10) // This register is not used in BB-B0. Reduced width to 1 bit to keep…
50365 …OLD (0x7<<14) // Debug only.
50367 …SHOLD (0x7<<17) // Debug only.
50369 …HOLD (0x7<<20) // Debug only.
50372 …RESHOLD (0xf<<0) // Debug only.
50374 …C (0x1<<4) // Debug only.
50376 …AC (0x1<<5) // Debug only.
50378 … (0x3<<6) // Debug only.
50380 …OM_REQ (0x1<<8) // Debug only.
50382 …EL_STATE (0x1<<9) // Debug only.
50384 … (0x1<<10) // Debug only.
50386 …T_CLR (0x1<<11) // Debug only.
50388 …EL_DIS (0x1<<12) // Debug only.
50391 …or DORQ Client on Virtual Functions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mas…
50392 …or DORQ Client on Virtual Functions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mas…
50393 …or DORQ Client on Virtual Functions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mas…
50398 … (0x1<<0) // This bit masks, when set, the Parity bit: CC…
50400 … (0x1<<1) // This bit masks, when set, the Parity bi…
50401 …CFC_REG_PRTY_MASK_SCAM_PAR_ERR_SHIFT 1
50402 … (0x1<<2) // This bit masks, when set, the Parity bit: CC…
50404 … (0x1<<3) // This bit masks, when set, the Parity bit: CC…
50406 … (0x1<<4) // This bit masks, when set, the Parity bit: CC…
50408 … (0x1<<5) // This bit masks, when set, the Parity bit: CC…
50421 … 0x2e0700UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cance…
50422 … 0x2e0704UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cance…
50423 …s:RW DataWidth:0x1 // This bit when clear will cause a CFC execution error (weak_enable will …
50424 …s:RW DataWidth:0x1 // This bit when clear will cause a CFC execution error (weak_enable will …
50429 … (0x1<<10) // This field is not used in BB-B0. When set, this configuration bit wi…
50435 … (0x1<<9) // When set to 1 the search string ca…
50437 … (0x1<<10) // When set to 1 the cid cam is disab…
50439 … (0x1<<11) // New Load On Error. if this bit is set and there is…
50441 … (0x1<<12) // When set to 1 the string cam hit p…
50443 … (0x1<<13) // When set to 1 the string cam miss …
50445 … (0x1<<14) // When set to 1 the cid cam hit pari…
50447 … (0x1<<15) // When set to 1 the cid cam miss par…
50455 …L //Access:RW DataWidth:0x7 // Set the initial credit for the CDU write-back interface if les…
50456 … Array of indirect registers defines the forced load regions per type. Applicable only in the TCFC.
50468 … //Access:RW DataWidth:0x9 // This is the LCID Threshold for LC CLient 1 (XYLD). When the num…
50482 …bit corresponds to one of the state machines [2:0]. Writing the bits to 1'b1 will restart the Time…
50484 … (0x1<<0) // This is the Enable bit for the LCID Limiti…
50486 … (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #0. The Waveform wi…
50487 …CFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_POLARITY_SHIFT 1
50493 … (0x1<<0) // This is the Enable bit for the LCID Limiting Waveform Generator …
50495 … (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #1. The Waveform wi…
50496 …CFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_POLARITY_SHIFT 1
50497 … DataWidth:0xe // This is the list of LC Clients that will be affected by Waveform Generator #1.
50498 …9 // This is the Threshold value of active LCIDs that triggers masking by Waveform Generator #1.
50499 … DataWidth:0x10 // This is the count of cycles that Waveform Generator #1 will output a ZERO v…
50500 … DataWidth:0x10 // This is the count of cycles that Waveform Generator #1 will output a ONE va…
50502 … (0x1<<0) // This is the Enable bit for the LCID Limiti…
50504 … (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #2. The Waveform wi…
50505 …CFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_POLARITY_SHIFT 1
50510 …bit in this register matches the corresponding String Type. Bit[0] = TCP Bit[1] = UDP Bit[2] …
50514 …NABLE_L2_CACHING (0x1<<1) // When set, the St…
50515 …CFC_REG_SCAM_CACHE_ENABLES_ENABLE_L2_CACHING_SHIFT 1
50516 …nd Writes to the CID CAM. Setting a bit to 0 will ignore that bit in a search. Setting a bit to 0 …
50517 … 0x2e0a0cUL //Access:RW DataWidth:0x1 // When this bit is set writing to t…
50528 … 0x2e0a38UL //Access:RW DataWidth:0x1 // When this bit is set writing to t…
50529 … 0x2e0a3cUL //Access:R DataWidth:0xa // {HIT;LCID}. HIT - if set then previous…
50530 …- tid is not included in hash calculation (like in A0). 1 - tid is included in hash calculation by…
50531 …- vlan is not included in hash calculation (like in A0). 1 - vlan is included in hash calculation …
50535 … 0x2e0b0cUL //Access:R DataWidth:0x20 // Provides read-only access to the CID …
50539 … 0x2e0b1cUL //Access:R DataWidth:0x20 // Provides read-only access to the STRI…
50550 … 0x2eb000UL //Access:WB DataWidth:0x21 // CID cam access (Valid - 32;31:0 - Data).
50557 … 0x2ed000UL //Access:RW DataWidth:0x7 // State select vector for VF/PF LCID state counter 1 .
50559 … 0x2ed008UL //Access:R DataWidth:0x9 // VF port to VF/PF LCID state counter 1 .
50560 … 0x2ed00cUL //Access:R DataWidth:0x9 // PF port to VF/PF LCID state counter 1 .
50566 … (0x1<<1) // Over flow occurs…
50567 …M_REG_INT_STS_OVF_ERR_TX_SHIFT 1
50609 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Q…
50611 … (0x1<<1) // This bit masks, when set, the Interrupt …
50612 …M_REG_INT_MASK_OVF_ERR_TX_SHIFT 1
50613 … (0x1<<2) // This bit masks, when set, the Interrupt bit: Q…
50615 … (0x1<<3) // This bit masks, when set, the Interrupt bit: Q…
50617 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Q…
50619 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Q…
50621 … (0x1<<6) // This bit masks, when set, the Interrupt bit: Q…
50623 … (0x1<<7) // This bit masks, when set, the Interrupt bit: Q…
50625 … (0x1<<8) // This bit masks, when set, the Interrupt bit: Q…
50627 … (0x1<<9) // This bit masks, when set, the Interrupt bit: Q…
50629 … (0x1<<10) // This bit masks, when set, the Interrupt bit: Q…
50631 … (0x1<<11) // This bit masks, when set, the Interrupt bit: Q…
50633 … (0x1<<12) // This bit masks, when set, the Interrupt bit: Q…
50635 … (0x1<<13) // This bit masks, when set, the Interrupt bit: Q…
50637 … (0x1<<14) // This bit masks, when set, the Interrupt bit: Q…
50639 … (0x1<<15) // This bit masks, when set, the Interrupt bit: Q…
50641 … (0x1<<16) // This bit masks, when set, the Interrupt bit: Q…
50643 … (0x1<<17) // This bit masks, when set, the Interrupt bit: Q…
50645 … (0x1<<18) // This bit masks, when set, the Interrupt bit: Q…
50647 … (0x1<<19) // This bit masks, when set, the Interrupt bit: Q…
50649 … (0x1<<20) // This bit masks, when set, the Interrupt bit: Q…
50651 … (0x1<<21) // This bit masks, when set, the Interrupt bit: Q…
50656 … (0x1<<1) // Over flow occurs…
50657 …M_REG_INT_STS_WR_OVF_ERR_TX_SHIFT 1
50701 … (0x1<<1) // Over flow occurs…
50702 …M_REG_INT_STS_CLR_OVF_ERR_TX_SHIFT 1
50744 … (0x1<<0) // This bit masks, when set, the Parity bit: QM…
50746 … (0x1<<1) // This bit masks, when set, the Parity bi…
50747 …M_REG_PRTY_MASK_UCM_WRC_FIFO_SHIFT 1
50748 … (0x1<<2) // This bit masks, when set, the Parity bit: QM…
50750 … (0x1<<3) // This bit masks, when set, the Parity bit: QM…
50752 … (0x1<<4) // This bit masks, when set, the Parity bit: QM…
50754 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
50756 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
50758 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
50760 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
50762 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
50764 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
50767 … (0x1<<0) // This bit masks, when set, the Parity bit: QM…
50769 … (0x1<<1) // This bit masks, when set, the Parity bi…
50770 …M_REG_PRTY_MASK_H_0_MEM004_I_ECC_1_RF_INT_E5_SHIFT 1
50771 … (0x1<<2) // This bit masks, when set, the Parity bit: QM…
50773 … (0x1<<3) // This bit masks, when set, the Parity bit: QM…
50775 … (0x1<<4) // This bit masks, when set, the Parity bit: QM…
50777 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
50779 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
50781 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
50783 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
50785 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
50787 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
50789 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
50791 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
50793 … (0x1<<11) // This bit masks, when set, the Parity bit: QM…
50795 … (0x1<<12) // This bit masks, when set, the Parity bit: QM…
50797 … (0x1<<13) // This bit masks, when set, the Parity bit: QM…
50799 … (0x1<<11) // This bit masks, when set, the Parity bit: QM…
50801 … (0x1<<14) // This bit masks, when set, the Parity bit: QM…
50803 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
50805 … (0x1<<15) // This bit masks, when set, the Parity bit: QM…
50807 … (0x1<<16) // This bit masks, when set, the Parity bit: QM…
50809 … (0x1<<17) // This bit masks, when set, the Parity bit: QM…
50811 … (0x1<<18) // This bit masks, when set, the Parity bit: QM…
50813 … (0x1<<19) // This bit masks, when set, the Parity bit: QM…
50815 … (0x1<<20) // This bit masks, when set, the Parity bit: QM…
50817 … (0x1<<21) // This bit masks, when set, the Parity bit: QM…
50819 … (0x1<<13) // This bit masks, when set, the Parity bit: QM…
50821 … (0x1<<22) // This bit masks, when set, the Parity bit: QM…
50823 … (0x1<<15) // This bit masks, when set, the Parity bit: QM…
50825 … (0x1<<23) // This bit masks, when set, the Parity bit: QM…
50827 … (0x1<<24) // This bit masks, when set, the Parity bit: QM…
50829 … (0x1<<14) // This bit masks, when set, the Parity bit: QM…
50831 … (0x1<<25) // This bit masks, when set, the Parity bit: QM…
50833 … (0x1<<12) // This bit masks, when set, the Parity bit: QM…
50835 … (0x1<<26) // This bit masks, when set, the Parity bit: QM…
50837 … (0x1<<16) // This bit masks, when set, the Parity bit: QM…
50839 … (0x1<<27) // This bit masks, when set, the Parity bit: QM…
50841 … (0x1<<19) // This bit masks, when set, the Parity bit: QM…
50843 … (0x1<<28) // This bit masks, when set, the Parity bit: QM…
50845 … (0x1<<21) // This bit masks, when set, the Parity bit: QM…
50847 … (0x1<<29) // This bit masks, when set, the Parity bit: QM…
50849 … (0x1<<17) // This bit masks, when set, the Parity bit: QM…
50851 … (0x1<<30) // This bit masks, when set, the Parity bit: QM…
50853 … (0x1<<0) // This bit masks, when set, the Parity bit: QM…
50855 … (0x1<<1) // This bit masks, when set, the Parity bi…
50856 …M_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_BB_K2_SHIFT 1
50857 … (0x1<<2) // This bit masks, when set, the Parity bit: QM…
50859 … (0x1<<3) // This bit masks, when set, the Parity bit: QM…
50861 … (0x1<<4) // This bit masks, when set, the Parity bit: QM…
50863 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
50865 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
50867 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
50869 … (0x1<<18) // This bit masks, when set, the Parity bit: QM…
50871 … (0x1<<20) // This bit masks, when set, the Parity bit: QM…
50873 … (0x1<<22) // This bit masks, when set, the Parity bit: QM…
50875 … (0x1<<23) // This bit masks, when set, the Parity bit: QM…
50877 … (0x1<<24) // This bit masks, when set, the Parity bit: QM…
50879 … (0x1<<25) // This bit masks, when set, the Parity bit: QM…
50881 … (0x1<<26) // This bit masks, when set, the Parity bit: QM…
50883 … (0x1<<27) // This bit masks, when set, the Parity bit: QM…
50885 … (0x1<<28) // This bit masks, when set, the Parity bit: QM…
50887 … (0x1<<29) // This bit masks, when set, the Parity bit: QM…
50889 … (0x1<<30) // This bit masks, when set, the Parity bit: QM…
50892 … (0x1<<0) // This bit masks, when set, the Parity bit: QM…
50894 … (0x1<<1) // This bit masks, when set, the Parity bi…
50895 …M_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY_E5_SHIFT 1
50896 … (0x1<<2) // This bit masks, when set, the Parity bit: QM…
50898 … (0x1<<13) // This bit masks, when set, the Parity bit: QM…
50900 … (0x1<<3) // This bit masks, when set, the Parity bit: QM…
50902 … (0x1<<14) // This bit masks, when set, the Parity bit: QM…
50904 … (0x1<<4) // This bit masks, when set, the Parity bit: QM…
50906 … (0x1<<21) // This bit masks, when set, the Parity bit: QM…
50908 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
50910 … (0x1<<20) // This bit masks, when set, the Parity bit: QM…
50912 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
50914 … (0x1<<19) // This bit masks, when set, the Parity bit: QM…
50916 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
50918 … (0x1<<18) // This bit masks, when set, the Parity bit: QM…
50920 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
50922 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
50924 … (0x1<<4) // This bit masks, when set, the Parity bit: QM…
50926 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
50928 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
50930 … (0x1<<11) // This bit masks, when set, the Parity bit: QM…
50932 … (0x1<<2) // This bit masks, when set, the Parity bit: QM…
50934 … (0x1<<12) // This bit masks, when set, the Parity bit: QM…
50936 … (0x1<<0) // This bit masks, when set, the Parity bit: QM…
50938 … (0x1<<13) // This bit masks, when set, the Parity bit: QM…
50940 … (0x1<<14) // This bit masks, when set, the Parity bit: QM…
50942 … (0x1<<1) // This bit masks, when set, the Parity bi…
50943 …M_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_BB_K2_SHIFT 1
50944 … (0x1<<15) // This bit masks, when set, the Parity bit: QM…
50946 … (0x1<<16) // This bit masks, when set, the Parity bit: QM…
50948 … (0x1<<17) // This bit masks, when set, the Parity bit: QM…
50950 … (0x1<<18) // This bit masks, when set, the Parity bit: QM…
50952 … (0x1<<19) // This bit masks, when set, the Parity bit: QM…
50954 … (0x1<<20) // This bit masks, when set, the Parity bit: QM…
50956 … (0x1<<21) // This bit masks, when set, the Parity bit: QM…
50958 … (0x1<<22) // This bit masks, when set, the Parity bit: QM…
50960 … (0x1<<23) // This bit masks, when set, the Parity bit: QM…
50962 … (0x1<<24) // This bit masks, when set, the Parity bit: QM…
50964 … (0x1<<25) // This bit masks, when set, the Parity bit: QM…
50966 … (0x1<<26) // This bit masks, when set, the Parity bit: QM…
50968 … (0x1<<12) // This bit masks, when set, the Parity bit: QM…
50970 … (0x1<<27) // This bit masks, when set, the Parity bit: QM…
50972 … (0x1<<15) // This bit masks, when set, the Parity bit: QM…
50974 … (0x1<<28) // This bit masks, when set, the Parity bit: QM…
50976 … (0x1<<29) // This bit masks, when set, the Parity bit: QM…
50978 … (0x1<<30) // This bit masks, when set, the Parity bit: QM…
50980 … (0x1<<3) // This bit masks, when set, the Parity bit: QM…
50982 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
50984 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
50986 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
50988 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
50990 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
50992 … (0x1<<11) // This bit masks, when set, the Parity bit: QM…
50994 … (0x1<<16) // This bit masks, when set, the Parity bit: QM…
50996 … (0x1<<17) // This bit masks, when set, the Parity bit: QM…
50998 … (0x1<<22) // This bit masks, when set, the Parity bit: QM…
51000 … (0x1<<23) // This bit masks, when set, the Parity bit: QM…
51002 … (0x1<<24) // This bit masks, when set, the Parity bit: QM…
51004 … (0x1<<25) // This bit masks, when set, the Parity bit: QM…
51006 … (0x1<<26) // This bit masks, when set, the Parity bit: QM…
51008 … (0x1<<27) // This bit masks, when set, the Parity bit: QM…
51010 … (0x1<<28) // This bit masks, when set, the Parity bit: QM…
51012 … (0x1<<29) // This bit masks, when set, the Parity bit: QM…
51014 … (0x1<<30) // This bit masks, when set, the Parity bit: QM…
51017 … (0x1<<0) // This bit masks, when set, the Parity bit: QM…
51019 … (0x1<<1) // This bit masks, when set, the Parity bi…
51020 …M_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_1_E5_SHIFT 1
51021 … (0x1<<2) // This bit masks, when set, the Parity bit: QM…
51023 … (0x1<<3) // This bit masks, when set, the Parity bit: QM…
51025 … (0x1<<4) // This bit masks, when set, the Parity bit: QM…
51027 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
51029 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
51031 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
51033 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
51035 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
51037 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
51039 … (0x1<<11) // This bit masks, when set, the Parity bit: QM…
51041 … (0x1<<12) // This bit masks, when set, the Parity bit: QM…
51043 … (0x1<<13) // This bit masks, when set, the Parity bit: QM…
51045 … (0x1<<14) // This bit masks, when set, the Parity bit: QM…
51047 … (0x1<<15) // This bit masks, when set, the Parity bit: QM…
51049 … (0x1<<16) // This bit masks, when set, the Parity bit: QM…
51051 … (0x1<<17) // This bit masks, when set, the Parity bit: QM…
51053 … (0x1<<0) // This bit masks, when set, the Parity bit: QM…
51055 … (0x1<<1) // This bit masks, when set, the Parity bi…
51056 …M_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_4_BB_K2_SHIFT 1
51057 … (0x1<<2) // This bit masks, when set, the Parity bit: QM…
51059 … (0x1<<3) // This bit masks, when set, the Parity bit: QM…
51061 … (0x1<<4) // This bit masks, when set, the Parity bit: QM…
51063 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
51065 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
51067 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
51069 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
51071 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
51073 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
51075 … (0x1<<11) // This bit masks, when set, the Parity bit: QM…
51077 … (0x1<<12) // This bit masks, when set, the Parity bit: QM…
51079 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
51081 … (0x1<<13) // This bit masks, when set, the Parity bit: QM…
51083 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
51085 … (0x1<<14) // This bit masks, when set, the Parity bit: QM…
51087 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
51089 … (0x1<<15) // This bit masks, when set, the Parity bit: QM…
51091 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
51093 … (0x1<<16) // This bit masks, when set, the Parity bit: QM…
51095 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
51097 … (0x1<<17) // This bit masks, when set, the Parity bit: QM…
51099 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
51101 … (0x1<<18) // This bit masks, when set, the Parity bit: QM…
51106 …4_I_ECC_1_EN_E5 (0x1<<1) // Enable ECC for m…
51107 …M_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_1_EN_E5_SHIFT 1
51116 …6_I_ECC_1_EN_BB_K2 (0x1<<1) // Enable ECC for m…
51117 …M_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN_BB_K2_SHIFT 1
51125 …_E5 (0x1<<0) // Set parity only for memory ecc inst…
51127 …CC_1_PRTY_E5 (0x1<<1) // Set parity only for memory…
51128 …M_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_1_PRTY_E5_SHIFT 1
51129 …_E5 (0x1<<2) // Set parity only for memory ecc inst…
51131 …_E5 (0x1<<3) // Set parity only for memory ecc inst…
51133 …5 (0x1<<4) // Set parity only for memory ecc inst…
51135 …_BB_K2 (0x1<<0) // Set parity only for memory ecc inst…
51137 …CC_1_PRTY_BB_K2 (0x1<<1) // Set parity only for memory…
51138 …M_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY_BB_K2_SHIFT 1
51139 …_BB_K2 (0x1<<2) // Set parity only for memory ecc inst…
51141 …_BB_K2 (0x1<<3) // Set parity only for memory ecc inst…
51143 …B_K2 (0x1<<4) // Set parity only for memory ecc inst…
51148 …D_0_MEM004_I_ECC_1_CORRECT_E5 (0x1<<1) // Record if a corr…
51149 …M_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_1_CORRECT_E5_SHIFT 1
51158 …D_0_MEM006_I_ECC_1_CORRECT_BB_K2 (0x1<<1) // Record if a corr…
51159 …M_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT_BB_K2_SHIFT 1
51167 …ccess:R DataWidth:0x8 // drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51168 …ccess:R DataWidth:0x8 // drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51169 …ccess:R DataWidth:0x8 // drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51170 …ccess:R DataWidth:0x8 // drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51171 …ccess:R DataWidth:0x8 // drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51172 …ccess:R DataWidth:0x8 // drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51173 …idth:0x5 // Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51174 …idth:0x5 // Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51175 …idth:0x5 // Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51176 …idth:0x5 // Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51177 …idth:0x5 // Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51178 …idth:0x5 // Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51179 …0x2f0430UL //Access:RW DataWidth:0x6 // Enable the write client. Bit: 0 = M; 1 = U; 2 = T; 3 …
51180 …1 which dictates the size of the queues which belong to the function for TX queues. There are 2 di…
51181 …1 which dictates the size of the queues which belong to the function for TX queues. There are 2 di…
51182 …1 which dictates the size of the queues which belong to the function for Other queues. There is si…
51183 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51184 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51185 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51186 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51187 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51188 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51189 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51190 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51191 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51192 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51193 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51194 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51195 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51196 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51197 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51198 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51199 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51200 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51201 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51202 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51203 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51204 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51205 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51206 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51207 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51208 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51209 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51210 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51211 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51212 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51213 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51214 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51215 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51216 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51217 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51218 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51219 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51220 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51221 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51222 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51223 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51224 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51225 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51226 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51227 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51228 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51229 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51230 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51231 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51232 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51233 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51234 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51235 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51236 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51237 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51238 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51239 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51240 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51241 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51242 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51243 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51244 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51245 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51246 … PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 fo…
51254 …es 63-0; The mapping is as follow: ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[…
51257 … BigRamTxData (for wr cmd only); (c) writing the cmd type BigRamTxCmd; (d) accessing the rd data B…
51258 … BigRamTxData (for wr cmd only); (c) writing the cmd type BigRamTxCmd; (d) accessing the rd data B…
51260 …- rd; 1 - wr) sent towards of the TX bigRam. Accessing the BigRam should be implemented as follows…
51261 …mOtherData (for wr cmd only); (c) writing the cmd type BigRamOtherCmd; (d) accessing the rd data B…
51262 …mOtherData (for wr cmd only); (c) writing the cmd type BigRamOtherCmd; (d) accessing the rd data B…
51264 …- rd; 1 - wr) sent towards of the Other bigRam. Accessing the BigRam should be implemented as foll…
51265 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51266 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51267 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51268 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51269 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51270 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51271 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51272 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51273 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51274 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51275 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51276 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51277 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51278 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51279 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51280 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51281 …// Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Q…
51282 …// Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Q…
51283 …// Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Q…
51284 …// Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Q…
51285 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51286 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51287 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51288 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51289 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51290 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51291 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51292 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51293 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51294 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51295 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51296 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51297 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51298 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51299 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51300 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51301 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51302 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51303 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51304 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51305 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51306 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51307 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51308 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51309 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51310 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51311 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51312 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51313 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51314 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51315 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51316 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51317 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51318 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51319 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51320 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51321 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51322 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51323 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51324 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51325 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51326 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51327 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51328 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51329 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51330 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51331 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51332 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51333 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51334 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51335 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51336 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51337 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51338 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51339 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51340 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51341 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51342 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51343 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51344 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51345 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51346 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51347 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51348 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51349 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51350 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51351 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51352 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51353 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51354 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51355 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51356 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51357 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51358 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51359 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51360 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51361 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51362 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51363 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51364 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51367 …-b0: rd first bank in page; b3: reserved (zero); b6-b4: wr first bank in page; b7: reserved (zero)…
51368 …al STU within the PXP (there is STU per PF). 0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
51369 …H field used in the PCI request. Per PF value. bits: 8-0 TPH Steering Tag Index; 12-9 reserved; 14…
51375 …- VOQs [0..31] VoqCrdLineFull_msb - VOQs [32..35] Some VOQs are "not used" depending on the…
51376 … smaller or equal to the matched Voq line credit (relevant only for VOQs that are being used - or …
51377 …- VOQs [0..31]. VoqCrdByteFull_msb - VOQs [32..35]. Some VOQs are "not used" depending on t…
51378 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51379 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51380 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51381 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51382 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51383 …bit). AFullQmBypThrLineVoqMask (This one) - VOQs [0..31]. AFullQmBypThrLineVoqMask_msb - VO…
51388 …bit per credit resource for the qm bypass. 1 - resource is required to be more than the almost ful…
51391 …ost full threshold for the opportunistic credit flow operation. reset value: -1 x TaskByteCrdCost_3
51392 …ost full threshold for the opportunistic credit flow operation. reset value: -1 x TaskByteCrdCost_4
51395 …bit per credit resource for the opportunistic credit. 1 - resource is required to be more than the…
51398 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51399 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51400 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51401 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51402 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51403 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51404 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51405 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51406 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51407 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51408 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51409 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51410 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51411 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51412 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51413 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51414 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51415 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51416 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51417 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51418 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51419 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51420 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51421 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51422 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51423 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51424 …-s that belong to TxPqMap[WrrWeightGrpRng]==2'b01. NOTE: weight update is allowed only to queues w…
51425 …-s that belong to TxPqMap[WrrWeightGrpRng]==2'b11. NOTE: weight update is allowed only to queues w…
51436 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51437 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51438 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51439 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51440 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51441 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51442 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51443 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51444 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51445 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51446 …bit per CM interface. If this bit is 0 then this interface is masked. i: 0 - MCM sec; 1 - MCM pri…
51447 …bit vector per CM interface which indicates which one of the Other queues are tied to the matched …
51450 …the SdmCmdReady bit (i.e. SdmCmdReady=1). (b) Write SdmCmdAddr, SdmCmdDataLsb and SdmCmdDataMsb (c…
51451 …the SdmCmdReady bit (i.e. SdmCmdReady=1). (b) Write SdmCmdAddr, SdmCmdDataLsb and SdmCmdDataMsb (c…
51452 …the SdmCmdReady bit (i.e. SdmCmdReady=1). (b) Write SdmCmdAddr, SdmCmdDataLsb and SdmCmdDataMsb (c…
51453 …the SdmCmdReady bit (i.e. SdmCmdReady=1). (b) Write SdmCmdAddr, SdmCmdDataLsb and SdmCmdDataMsb (c…
51454 …n the SdmCmdReady bit (i.e. SdmCmdReady=1). (b) Write SdmCmdAddr, SdmCmdDataLsb and SdmCmdDataMsb …
51455 … DataWidth:0x18 // The number of tasks queued for each Other queue. Should be read only access.
51462 …cess:R DataWidth:0x1 // The status of the Other PQ-s: bit0 - PQ paused. Should be read only …
51465 … 0x2f2c00UL //Access:RW DataWidth:0x1 // Initialization bit command.
51466 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51467 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51468 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51469 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51470 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51471 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51472 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51473 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51474 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51475 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51476 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51477 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51478 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51479 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51480 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51481 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51482 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51483 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51484 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51485 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51486 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51487 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51488 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51489 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51490 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51491 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51492 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51493 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51494 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51495 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51496 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51497 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51498 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51499 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51500 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51501 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51502 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51503 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51504 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51505 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51506 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51507 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51508 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51509 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51510 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51511 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51512 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51513 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51514 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51515 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51516 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51517 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51518 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51519 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51520 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51521 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51522 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51523 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51524 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51525 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51526 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51527 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51528 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51529 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51530 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51531 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51532 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51533 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51534 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51535 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51536 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51537 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51538 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51539 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51540 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51541 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51542 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51543 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51544 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51545 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51550 …//Access:RW DataWidth:0x8 // Debug only: For dbgmux usage (debug data that goes from QM to th…
51551 …//Access:RW DataWidth:0x4 // Debug only: For dbgmux usage (debug data that goes from QM to th…
51552 …//Access:RW DataWidth:0x2 // Debug only: For dbgmux usage (debug data that goes from QM to th…
51553 …//Access:RW DataWidth:0x4 // Debug only: For dbgmux usage (debug data that goes from QM to th…
51554 …//Access:RW DataWidth:0x4 // Debug only: For dbgmux usage (debug data that goes from QM to th…
51555 …//Access:R DataWidth:0x20 // Debug only: For dbgmux usage (debug data that goes from QM to th…
51556 …//Access:R DataWidth:0x20 // Debug only: For dbgmux usage (debug data that goes from QM to th…
51557 …//Access:R DataWidth:0x4 // Debug only: For dbgmux usage (debug data that goes from QM to th…
51558 …//Access:R DataWidth:0x4 // Debug only: For dbgmux usage (debug data that goes from QM to th…
51560 … DataWidth:0x1 // Selects between the Mem Array (0) and the Mask Array (1) when accessing the …
51561 …r. The driver can clear this bit (through RBC) based on the functional flows (e.g. FLR). It is als…
51562 … 0x2f2ea4UL //Access:RW DataWidth:0x1 // PF enable vector. Bit per PF. If set the …
51563 … 0x2f2ea8UL //Access:RW DataWidth:0x1 // VF enable vector. Bit per VF. If set the …
51571 …ut period in 25Mhz clock cycles for the global. VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Gl…
51572 …out period in 25Mhz clock cycles for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Gl…
51573 … for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. Upon init should be set with value of …
51574 …od counter in 25Mhz clock cycles for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Gl…
51575 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51576 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51577 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51578 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51579 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51580 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51581 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51582 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51585 … the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of…
51587 …only access in non-init mode. In init mode should be written with the same value of RlGlblUpperBou…
51590 …2f4c04UL //Access:RW DataWidth:0x9 // number of active RL counters (between 1 to QM_NUM_OF_RL)
51591 …1 - force cam search and update sts_rlglbl_pq_blocked vector even when the rlglblcrd did not chang…
51592 …r)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: clie…
51593 …r)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: clie…
51594 …o). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: clie…
51595 …e bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_Rl…
51596 …ataWidth:0x20 // The RL timeout period in 25Mhz clock cycles for the PF RL-s. NOTE: ck25 domain.…
51597 …:0x20 // The RL timeout period counter in 25Mhz clock cycles for the PF RL-s. Upon init should b…
51601 … the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of…
51604 …only access in non-init mode. In init mode should be written with the same value of RlPfUpperBound…
51608 …- VOQs [0..31]. RlPfVoqEnable_msb - VOQs [32..35]. Some VOQs are "not used" depending on th…
51609 …ter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: clie…
51610 …ter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: clie…
51611 …ero). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: clie…
51612 …ype bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_…
51616 … the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of…
51619 …- VOQ0..VOQ15. WfqPfCrd_msb - VOQ16..VOQ35. Should be read only access in non-init mode. In init m…
51624 …- error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id; b15-b12…
51625 …- error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id; b15-b12…
51626 …- error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id; b15-b12…
51627 …pe bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_W…
51629 … 1 - force cam search and update sts_wfqvp_pq_blocked vector even when the wfqvpcrd did not change…
51630 …- error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (s…
51631 …- error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (s…
51632 …- error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (s…
51633 …pe bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_W…
51634 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51635 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51636 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51637 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51638 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51639 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51640 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51641 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51642 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51643 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51644 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51645 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51646 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51647 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51648 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51649 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51650 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51651 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51652 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51653 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51654 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51655 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51656 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51657 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51659 …-idle state, trying to start new TX arbitration depends on the GO mode as follows: 0 - start new T…
51660 …xa // The number of cycles between 2 adjacent TX arbitrations. Valid only when Tx_Arb_Go_Mode==1
51662 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51663 …ue. b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51664 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51665 …o). b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51666 …bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_VoqL…
51667 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51668 …ue. b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51669 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51670 …o). b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51671 …bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_VoqB…
51678 …1, the enabled mems (Mem_Init_Mask_0/1) will be initialized with value of Mem_Init_Value_0/1. NOTE…
51680 …ed. when reset the mem in not initiazlied. There is mask bit per mem, the following are mems 31-0:…
51681 …ed. when reset the mem in not initiazlied. There is mask bit per mem, the following are mems 63-32…
51682 …n reset the mem in initialized with all zeroes. There is bit per mem, the following are mems 31-0:…
51683 …n reset the mem in initialized with all zeroes. There is bit per mem, the following are mems 63-32…
51684 … the mem is currently being initialized. There is status bit per mem, the following are mems 31-0:…
51685 … the mem is currently being initialized. There is status bit per mem, the following are mems 63-32…
51689 … 0x2f5da8UL //Access:R DataWidth:0x16 // Provides read-only access to the BIST…
51693 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51694 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51695 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51696 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51697 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51698 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51699 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51700 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51701 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51702 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51703 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51704 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51705 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51706 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51707 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51708 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51709 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51710 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51711 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51712 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51713 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51714 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51715 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51716 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51717 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51718 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51719 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51720 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51721 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51722 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51723 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51724 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51725 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51726 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51727 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51728 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51729 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51730 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51731 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51732 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51733 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51734 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51735 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51736 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51737 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51738 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51739 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51740 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51741 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51742 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51743 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51744 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51745 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51746 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51747 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51748 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51749 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51750 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51751 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51752 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51753 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51754 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51755 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51756 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51757 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51758 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51759 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51760 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51761 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51762 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51763 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51764 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51765 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51766 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51767 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51768 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51769 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51770 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51771 …0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51772 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51773 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51774 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51775 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51776 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51777 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51778 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51779 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51780 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51781 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51782 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51783 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51784 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51785 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51786 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51787 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51788 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51789 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51790 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51791 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51792 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51793 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51794 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51795 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51796 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51797 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51798 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51799 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51800 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51801 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51802 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51803 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51804 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51805 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51806 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51807 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51808 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51809 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51810 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51811 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51812 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51813 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51814 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51815 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51816 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51817 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51818 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51819 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51820 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51821 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51822 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51823 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51824 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51825 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51826 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51827 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51828 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51829 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51830 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51831 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51832 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51833 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51834 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51835 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51836 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51837 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51838 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51839 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51840 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51841 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51842 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51843 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51844 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51845 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51846 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51847 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51848 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51849 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51850 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51851 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51852 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51853 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51854 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51855 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51856 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51857 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51858 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51859 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51860 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51861 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51862 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51863 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51864 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51865 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51866 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51867 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51868 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51869 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51870 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51871 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51872 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51873 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51874 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51875 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51876 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51877 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51878 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51879 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51880 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51881 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51882 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51883 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51884 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51885 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51886 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51887 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51888 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51889 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51890 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51891 …ity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4…
51892 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51893 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51894 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51895 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51896 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51897 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51898 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51899 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51900 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51901 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51902 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51903 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51904 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51905 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51906 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51907 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51908 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51909 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51910 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51911 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51912 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51913 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51914 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51915 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51916 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51917 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51918 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51919 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51920 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51921 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51922 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51923 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51924 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51925 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51926 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51927 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51928 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51929 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51930 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51931 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51932 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnT…
51933 …:RW DataWidth:0x18 // The number of tasks queued for each TX queue. Should be read only access.
51936 …atus of the TX PQ-s: bit0 - PQ global VP/QCN RL block; bit1 - PQ active; bit2 - PQ paused; bit3 - …
51939 …1) Mem Array: Maps between TX PQ and its resources as follows: bit 0 - PQ valid; bits 8:1 -…
51945 … the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of…
51948 …only access in non-init mode. In init mode should be written with the same value of WfqVpUpperBoun…
51951 …1) Mem Array: Maps between VP WFQ counter and its resources as follows: bit 5:0 - Voq id; bit …
51954 …s 447-0; The mapping is as follow: ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[…
51957 …only access in non-init mode. In init mode should be written with the same value of WfqPfUpperBoun…
51958 …only access in non-init mode. In init mode should be written with the same value of WfqPfUpperBoun…
51961 …bit vector per CM interface which indicates which one of the Other queues are tied to the matched …
51962 …bit vector per CM interface which indicates which one of the Other queues are tied to the matched …
51964 …idth:0x10 // The actual line credit for each VOQ. Should be read only access in non-init mode. I…
51965 …only access in non-init mode. In init mode should be written with the same value of voqinitcrdline…
51969 …it and maximum line credit for each VOQ. The max allowed init value is 2^15-1-2^9. Granularity of …
51970 …-1-2^9. Granularity of 16B. Some VOQs are "not used" depending on the port_mode. Namely : port_mo…
51974 …idth:0x18 // The actual byte credit for each VOQ. Should be read only access in non-init mode. I…
51975 …only access in non-init mode. In init mode should be written with the same value of voqinitcrdbyte…
51979 …0x18 // The init and maximum byte credit for each VOQ. The max allowed init value is 2^23-1-2^16.
51980 …-1-2^16. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port devi…
51984 …bit). AFullQmBypThrLineVoqMask - VOQs [0..31]. AFullQmBypThrLineVoqMask_msb (This o…
51985 …- VOQs [0..31]. RlPfVoqEnable_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending o…
51986 …- VOQs [0..31]. VoqCrdLineFull_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending …
51987 …- VOQs [0..31]. VoqCrdByteFull_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending …
51989 …dth:0x1 // If set and DIF block found error; the DIF block will be stuck - hard reset is needed.
51992 … the configured number of cycles the dirty_l1 register will be set. Configuring 0 is the same as 1.
51993 …ess:R DataWidth:0x1 // Indicates that there is a pending L1 WB. Set only if this is the case…
51998 … 0x300070UL //Access:R DataWidth:0x1 // Debug: 1 = fifo is empty.
51999 … 0x300074UL //Access:R DataWidth:0x1 // Debug: 1 = fifo is empty.
52000 … 0x300078UL //Access:R DataWidth:0x1 // Debug: 1 = fifo is empty.
52001 …8 // If bit i is set; the data in the debug_error_info address[5:3] = i is valid. By writing 1 …
52004 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52005 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52007 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52008 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52010 …4] set_err_with_eop ; [3] host_guard_is_crc ; [2] initial_ref_tag_valid; [1] err_in_io,[0] parti…
52013 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52014 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52016 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52017 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52019 …4] set_err_with_eop ; [3] host_guard_is_crc ; [2] initial_ref_tag_valid; [1] err_in_io,[0] parti…
52020 … 0x3000c8UL //Access:R DataWidth:0x1 // Debug: one bit for each protocol ID. 1 = fifo…
52021 … 0x3000ccUL //Access:R DataWidth:0x1 // DEBUG: 0 - no credit; 1 - there is cred…
52022 … 0x3000d0UL //Access:R DataWidth:0x1 // DEBUG: 0 - no message pending; 1 - message …
52023 …00d4UL //Access:R DataWidth:0x17 // DEBUG: configuration fatal error. [1:0] host interface; […
52030 …R (0x1<<1) // DIX data is miss…
52031 …DIF_REG_INT_STS_FATAL_DIX_ERR_SHIFT 1
52042 … (0x1<<7) // end of burst arrived with end of interval and only partial DIF data ar…
52047 … (0x1<<0) // This bit masks, when set, the Interrupt bit: R…
52049 … (0x1<<1) // This bit masks, when set, the Interrupt …
52050 …DIF_REG_INT_MASK_FATAL_DIX_ERR_SHIFT 1
52051 … (0x1<<2) // This bit masks, when set, the Interrupt bit: R…
52053 … (0x1<<3) // This bit masks, when set, the Interrupt bit: R…
52055 … (0x1<<4) // This bit masks, when set, the Interrupt bit: R…
52057 … (0x1<<5) // This bit masks, when set, the Interrupt bit: R…
52059 … (0x1<<6) // This bit masks, when set, the Interrupt bit: R…
52061 … (0x1<<7) // This bit masks, when set, the Interrupt bit: R…
52063 … (0x1<<8) // This bit masks, when set, the Interrupt bit: R…
52068 …_ERR (0x1<<1) // DIX data is miss…
52069 …DIF_REG_INT_STS_WR_FATAL_DIX_ERR_SHIFT 1
52080 … (0x1<<7) // end of burst arrived with end of interval and only partial DIF data ar…
52087 …X_ERR (0x1<<1) // DIX data is miss…
52088 …DIF_REG_INT_STS_CLR_FATAL_DIX_ERR_SHIFT 1
52099 … (0x1<<7) // end of burst arrived with end of interval and only partial DIF data ar…
52104 … (0x1<<1) // This bit masks, when set, the Parity bi…
52105 …DIF_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT 1
52106 …Only the first errors in the IO will be logged. In bits [5:3] of the address represent the error n…
52109 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
52110 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
52111 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
52112 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
52117 …Only 320b are valid. Data order:Field name-Initial reference tag Address offset-0 bits [31:0]; Fie…
52118 …bit). The partition per task context is as follows: In TDIF - Has 8 QWORDs per task allocated (All…
52122 …dth:0x1 // If set and DIF block found error; the DIF block will be stuck - hard reset is needed.
52123 … DataWidth:0x1 // mask bit for the following case: host interface = DIF end of burst arrived w…
52126 … the configured number of cycles the dirty_l1 register will be set. Configuring 0 is the same as 1.
52127 …ess:R DataWidth:0x1 // Indicates that there is a pending L1 WB. Set only if this is the case…
52132 … 0x310070UL //Access:R DataWidth:0x1 // Debug: 1 = fifo is empty.
52133 … 0x310074UL //Access:R DataWidth:0x1 // Debug: 1 = fifo is empty.
52134 … 0x310078UL //Access:R DataWidth:0x1 // Debug: 1 = fifo is empty.
52135 …8 // If bit i is set; the data in the debug_error_info address[5:3] = i is valid. By writing 1 …
52138 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52139 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52141 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52142 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52144 …4] set_err_with_eop ; [3] host_guard_is_crc ; [2] initial_ref_tag_valid; [1] err_in_io,[0] parti…
52147 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52148 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52150 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52151 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52153 …4] set_err_with_eop ; [3] host_guard_is_crc ; [2] initial_ref_tag_valid; [1] err_in_io,[0] parti…
52154 … 0x3100c8UL //Access:R DataWidth:0x10 // Debug: one bit for each protocol ID. 1 = fifo…
52155 … 0x3100ccUL //Access:R DataWidth:0x1 // DEBUG: 0 - no credit; 1 - there is cred…
52156 … 0x3100d0UL //Access:R DataWidth:0x1 // DEBUG: 0 - no message pending; 1 - message …
52157 …00d4UL //Access:R DataWidth:0x17 // DEBUG: configuration fatal error. [1:0] host interface; […
52158 … 0x3100d8UL //Access:R DataWidth:0x1b // [3:0] - error type ([0] Write overflow. [1] Re…
52161 …Access:RW DataWidth:0x20 // Number of interval with error arrived to the DIF for protocol ID 1.
52180 …R (0x1<<1) // DIX data is miss…
52181 …DIF_REG_INT_STS_FATAL_DIX_ERR_SHIFT 1
52192 … (0x1<<7) // end of burst arrived with end of interval and only partial DIF data ar…
52197 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
52199 … (0x1<<1) // This bit masks, when set, the Interrupt …
52200 …DIF_REG_INT_MASK_FATAL_DIX_ERR_SHIFT 1
52201 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
52203 … (0x1<<3) // This bit masks, when set, the Interrupt bit: T…
52205 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
52207 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
52209 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
52211 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
52213 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
52218 …_ERR (0x1<<1) // DIX data is miss…
52219 …DIF_REG_INT_STS_WR_FATAL_DIX_ERR_SHIFT 1
52230 … (0x1<<7) // end of burst arrived with end of interval and only partial DIF data ar…
52237 …X_ERR (0x1<<1) // DIX data is miss…
52238 …DIF_REG_INT_STS_CLR_FATAL_DIX_ERR_SHIFT 1
52249 … (0x1<<7) // end of burst arrived with end of interval and only partial DIF data ar…
52254 … (0x1<<1) // This bit masks, when set, the Parity bi…
52255 …DIF_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT 1
52257 … (0x1<<0) // This bit masks, when set, the Parity bit: TD…
52259 … (0x1<<1) // This bit masks, when set, the Parity bi…
52260 …DIF_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_SHIFT 1
52261 … (0x1<<2) // This bit masks, when set, the Parity bit: TD…
52263 … (0x1<<3) // This bit masks, when set, the Parity bit: TD…
52265 … (0x1<<4) // This bit masks, when set, the Parity bit: TD…
52267 … (0x1<<5) // This bit masks, when set, the Parity bit: TD…
52269 … (0x1<<6) // This bit masks, when set, the Parity bit: TD…
52271 … (0x1<<7) // This bit masks, when set, the Parity bit: TD…
52273 … (0x1<<8) // This bit masks, when set, the Parity bit: TD…
52275 … (0x1<<9) // This bit masks, when set, the Parity bit: TD…
52277 … (0x1<<10) // This bit masks, when set, the Parity bit: TD…
52279 … (0x1<<10) // This bit masks, when set, the Parity bit: TD…
52281 … (0x1<<11) // This bit masks, when set, the Parity bit: TD…
52286 …009_I_ECC_EN (0x1<<1) // Enable ECC for m…
52287 …DIF_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN_SHIFT 1
52293 … (0x1<<0) // Set parity only for memory ecc inst…
52295 …_ECC_PRTY (0x1<<1) // Set parity only for memory…
52296 …DIF_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY_SHIFT 1
52297 … (0x1<<2) // Set parity only for memory ecc inst…
52299 … (0x1<<3) // Set parity only for memory ecc inst…
52304 …TED_0_MEM009_I_ECC_CORRECT (0x1<<1) // Record if a corr…
52305 …DIF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT_SHIFT 1
52311 …Only the first errors in the IO will be logged. In bits [5:3] of the address represent the error n…
52314 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
52315 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
52316 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
52317 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
52322 …bit). The partition per task context is as follows: In TDIF - Has 8 QWORDs per task allocated (All…
52326 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
52327 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
52328 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
52329 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
52338 … (0x1<<0) // This bit masks, when set, the Interrupt bit: R…
52348 … (0x1<<0) // This bit masks, when set, the Parity bit: RG…
52350 … (0x1<<1) // This bit masks, when set, the Parity bi…
52351 …GSRC_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_E5_SHIFT 1
52355 …M001_I_ECC_EN_E5 (0x1<<1) // Enable ECC for m…
52356 …GSRC_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_E5_SHIFT 1
52358 …Y_E5 (0x1<<0) // Set parity only for memory ecc inst…
52360 …I_ECC_PRTY_E5 (0x1<<1) // Set parity only for memory…
52361 …GSRC_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_E5_SHIFT 1
52365 …CTED_0_MEM001_I_ECC_CORRECT_E5 (0x1<<1) // Record if a corr…
52366 …GSRC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_E5_SHIFT 1
52373 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_…
52374 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_…
52389 …- SRC cmd result in no match; [1] - DEL cmd result in no match; [2] - CHG cmd result in no match; …
52396 … 0x320478UL //Access:RC DataWidth:0x20 // Number of SRC commands which hit with HOP=1
52400 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
52401 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
52402 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
52403 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
52412 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
52422 … (0x1<<0) // This bit masks, when set, the Parity bit: TG…
52424 … (0x1<<1) // This bit masks, when set, the Parity bi…
52425 …GSRC_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_E5_SHIFT 1
52429 …M001_I_ECC_EN_E5 (0x1<<1) // Enable ECC for m…
52430 …GSRC_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_E5_SHIFT 1
52432 …Y_E5 (0x1<<0) // Set parity only for memory ecc inst…
52434 …I_ECC_PRTY_E5 (0x1<<1) // Set parity only for memory…
52435 …GSRC_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_E5_SHIFT 1
52439 …CTED_0_MEM001_I_ECC_CORRECT_E5 (0x1<<1) // Record if a corr…
52440 …GSRC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_E5_SHIFT 1
52447 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_…
52448 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_…
52463 …- SRC cmd result in no match; [1] - DEL cmd result in no match; [2] - CHG cmd result in no match; …
52470 … 0x322478UL //Access:RC DataWidth:0x20 // Number of SRC commands which hit with HOP=1
52473 … // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en re…
52474 … // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en re…
52475 …bit should be set when initialization of all BRTB registers and memories is finished. BRTB will fi…
52479 …_ERROR (0x1<<1) // Read packet clie…
52480 …RB_REG_INT_STS_0_RC_PKT0_RLS_ERROR_SHIFT 1
52485 … (0x1<<4) // Read packet client PRM error when SOP bit is set in the packe…
52495 … (0x1<<9) // Read packet client MSDM error when SOP bit is set in the packe…
52505 … (0x1<<14) // Read packet client TSDM error when SOP bit is set in the packe…
52515 … (0x1<<19) // Read packet client parser error when SOP bit is set in the packe…
52525 …/ Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have…
52527 … (0x1<<25) // Warning! Check this bit connection for E4 A…
52529 … (0x1<<26) // Warning! Check this bit connection for E4 A…
52539 …r for MAC port 0 RX_INT::/RX_INT/d in Comments. When unified_shared_area is 1, then the error appl…
52542 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
52544 … (0x1<<1) // This bit masks, when set, the Interrupt …
52545 …RB_REG_INT_MASK_0_RC_PKT0_RLS_ERROR_SHIFT 1
52546 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
52548 … (0x1<<3) // This bit masks, when set, the Interrupt bit: B…
52550 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
52552 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
52554 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
52556 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
52558 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
52560 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
52562 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
52564 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
52566 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
52568 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
52570 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
52572 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
52574 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
52576 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
52578 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
52580 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
52582 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
52584 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
52586 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
52588 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
52590 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
52592 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
52594 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
52596 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
52598 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
52600 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
52602 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
52604 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
52609 …RLS_ERROR (0x1<<1) // Read packet clie…
52610 …RB_REG_INT_STS_WR_0_RC_PKT0_RLS_ERROR_SHIFT 1
52615 … (0x1<<4) // Read packet client PRM error when SOP bit is set in the packe…
52625 … (0x1<<9) // Read packet client MSDM error when SOP bit is set in the packe…
52635 … (0x1<<14) // Read packet client TSDM error when SOP bit is set in the packe…
52645 … (0x1<<19) // Read packet client parser error when SOP bit is set in the packe…
52655 …/ Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have…
52657 … (0x1<<25) // Warning! Check this bit connection for E4 A…
52659 … (0x1<<26) // Warning! Check this bit connection for E4 A…
52669 …r for MAC port 0 RX_INT::/RX_INT/d in Comments. When unified_shared_area is 1, then the error appl…
52674 …_RLS_ERROR (0x1<<1) // Read packet clie…
52675 …RB_REG_INT_STS_CLR_0_RC_PKT0_RLS_ERROR_SHIFT 1
52680 … (0x1<<4) // Read packet client PRM error when SOP bit is set in the packe…
52690 … (0x1<<9) // Read packet client MSDM error when SOP bit is set in the packe…
52700 … (0x1<<14) // Read packet client TSDM error when SOP bit is set in the packe…
52710 … (0x1<<19) // Read packet client parser error when SOP bit is set in the packe…
52720 …/ Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have…
52722 … (0x1<<25) // Warning! Check this bit connection for E4 A…
52724 … (0x1<<26) // Warning! Check this bit connection for E4 A…
52734 …r for MAC port 0 RX_INT::/RX_INT/d in Comments. When unified_shared_area is 1, then the error appl…
52737 …e shared area calculation error for MAC port 1 RX_INT::/RX_INT/d in Comments. When unified_shared_…
52739 …_ERROR (0x1<<1) // Calculations err…
52740 …RB_REG_INT_STS_1_LL_ARB_CALC_ERROR_SHIFT 1
52769 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in wr…
52771 … (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in wri…
52773 … (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in wri…
52775 … (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in wr…
52777 … (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in…
52779 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in…
52781 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in wr…
52783 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error…
52785 … (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error …
52787 … (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in…
52789 … (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in wr…
52791 … (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in writ…
52793 … (0x1<<30) // Warning! Check this bit connection for E4 A…
52795 … (0x1<<31) // Warning! Check this bit connection for E4 A…
52798 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
52800 … (0x1<<1) // This bit masks, when set, the Interrupt …
52801 …RB_REG_INT_MASK_1_LL_ARB_CALC_ERROR_SHIFT 1
52802 … (0x1<<3) // This bit masks, when set, the Interrupt bit: B…
52804 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
52806 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
52808 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
52810 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
52812 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
52814 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
52816 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
52818 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
52820 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
52822 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
52824 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
52826 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
52828 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
52830 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
52832 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
52834 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
52836 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
52838 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
52840 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
52842 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
52844 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
52846 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
52848 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
52850 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
52852 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
52854 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
52856 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
52859 …e shared area calculation error for MAC port 1 RX_INT::/RX_INT/d in Comments. When unified_shared_…
52861 …ALC_ERROR (0x1<<1) // Calculations err…
52862 …RB_REG_INT_STS_WR_1_LL_ARB_CALC_ERROR_SHIFT 1
52891 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in wr…
52893 … (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in wri…
52895 … (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in wri…
52897 … (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in wr…
52899 … (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in…
52901 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in…
52903 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in wr…
52905 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error…
52907 … (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error …
52909 … (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in…
52911 … (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in wr…
52913 … (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in writ…
52915 … (0x1<<30) // Warning! Check this bit connection for E4 A…
52917 … (0x1<<31) // Warning! Check this bit connection for E4 A…
52920 …e shared area calculation error for MAC port 1 RX_INT::/RX_INT/d in Comments. When unified_shared_…
52922 …CALC_ERROR (0x1<<1) // Calculations err…
52923 …RB_REG_INT_STS_CLR_1_LL_ARB_CALC_ERROR_SHIFT 1
52952 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in wr…
52954 … (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in wri…
52956 … (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in wri…
52958 … (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in wr…
52960 … (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in…
52962 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in…
52964 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in wr…
52966 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error…
52968 … (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error …
52970 … (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in…
52972 … (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in wr…
52974 … (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in writ…
52976 … (0x1<<30) // Warning! Check this bit connection for E4 A…
52978 … (0x1<<31) // Warning! Check this bit connection for E4 A…
52981 … (0x1<<0) // Warning! Check this bit connection for E4 A…
52983 … (0x1<<1) // Warning! Check this bit connec…
52984 …RB_REG_INT_STS_2_WC2_SOP_FIFO_ERROR_SHIFT 1
52985 … (0x1<<2) // Warning! Check this bit connection for E4 A…
52987 … (0x1<<3) // Warning! Check this bit connection for E4 A…
52989 … (0x1<<4) // Warning! Check this bit connection for E4 A…
52991 … (0x1<<5) // Warning! Check this bit connection for E4 A…
52993 … (0x1<<6) // Warning! Check this bit connection for E4 A…
52995 … (0x1<<7) // Warning! Check this bit connection for E4 A…
52997 … (0x1<<8) // Warning! Check this bit connection for E4 A…
52999 … (0x1<<9) // Warning! Check this bit connection for E4 A…
53001 … (0x1<<10) // Warning! Check this bit connection for E4 A…
53003 … (0x1<<11) // Warning! Check this bit connection for E4 A…
53005 … (0x1<<12) // Warning! Check this bit connection for E4 A…
53007 … (0x1<<13) // Warning! Check this bit connection for E4 A…
53009 … (0x1<<14) // Warning! Check this bit connection for E4 A…
53011 … (0x1<<15) // Warning! Check this bit connection for E4 A…
53013 … (0x1<<16) // Warning! Check this bit connection for E4 A…
53015 … (0x1<<17) // Warning! Check this bit connection for E4 A…
53017 … (0x1<<18) // Warning! Check this bit connection for E4 A…
53019 … (0x1<<19) // Warning! Check this bit connection for E4 A…
53021 … (0x1<<20) // Warning! Check this bit connection for E4 A…
53023 … (0x1<<21) // Warning! Check this bit connection for E4 A…
53025 … (0x1<<22) // Warning! Check this bit connection for E4 A…
53027 … (0x1<<23) // Warning! Check this bit connection for E4 A…
53029 … (0x1<<24) // Warning! Check this bit connection for E4 A…
53031 … (0x1<<25) // Warning! Check this bit connection for E4 A…
53033 … (0x1<<26) // Warning! Check this bit connection for E4 A…
53035 … (0x1<<27) // Warning! Check this bit connection for E4 A…
53038 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
53040 … (0x1<<1) // This bit masks, when set, the Interrupt …
53041 …RB_REG_INT_MASK_2_WC2_SOP_FIFO_ERROR_SHIFT 1
53042 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
53044 … (0x1<<3) // This bit masks, when set, the Interrupt bit: B…
53046 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
53048 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
53050 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
53052 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
53054 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
53056 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
53058 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
53060 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
53062 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
53064 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
53066 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
53068 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
53070 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
53072 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
53074 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
53076 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
53078 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
53080 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
53082 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
53084 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
53086 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
53088 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
53090 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
53092 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
53095 … (0x1<<0) // Warning! Check this bit connection for E4 A…
53097 … (0x1<<1) // Warning! Check this bit connec…
53098 …RB_REG_INT_STS_WR_2_WC2_SOP_FIFO_ERROR_SHIFT 1
53099 … (0x1<<2) // Warning! Check this bit connection for E4 A…
53101 … (0x1<<3) // Warning! Check this bit connection for E4 A…
53103 … (0x1<<4) // Warning! Check this bit connection for E4 A…
53105 … (0x1<<5) // Warning! Check this bit connection for E4 A…
53107 … (0x1<<6) // Warning! Check this bit connection for E4 A…
53109 … (0x1<<7) // Warning! Check this bit connection for E4 A…
53111 … (0x1<<8) // Warning! Check this bit connection for E4 A…
53113 … (0x1<<9) // Warning! Check this bit connection for E4 A…
53115 … (0x1<<10) // Warning! Check this bit connection for E4 A…
53117 … (0x1<<11) // Warning! Check this bit connection for E4 A…
53119 … (0x1<<12) // Warning! Check this bit connection for E4 A…
53121 … (0x1<<13) // Warning! Check this bit connection for E4 A…
53123 … (0x1<<14) // Warning! Check this bit connection for E4 A…
53125 … (0x1<<15) // Warning! Check this bit connection for E4 A…
53127 … (0x1<<16) // Warning! Check this bit connection for E4 A…
53129 … (0x1<<17) // Warning! Check this bit connection for E4 A…
53131 … (0x1<<18) // Warning! Check this bit connection for E4 A…
53133 … (0x1<<19) // Warning! Check this bit connection for E4 A…
53135 … (0x1<<20) // Warning! Check this bit connection for E4 A…
53137 … (0x1<<21) // Warning! Check this bit connection for E4 A…
53139 … (0x1<<22) // Warning! Check this bit connection for E4 A…
53141 … (0x1<<23) // Warning! Check this bit connection for E4 A…
53143 … (0x1<<24) // Warning! Check this bit connection for E4 A…
53145 … (0x1<<25) // Warning! Check this bit connection for E4 A…
53147 … (0x1<<26) // Warning! Check this bit connection for E4 A…
53149 … (0x1<<27) // Warning! Check this bit connection for E4 A…
53152 … (0x1<<0) // Warning! Check this bit connection for E4 A…
53154 … (0x1<<1) // Warning! Check this bit connec…
53155 …RB_REG_INT_STS_CLR_2_WC2_SOP_FIFO_ERROR_SHIFT 1
53156 … (0x1<<2) // Warning! Check this bit connection for E4 A…
53158 … (0x1<<3) // Warning! Check this bit connection for E4 A…
53160 … (0x1<<4) // Warning! Check this bit connection for E4 A…
53162 … (0x1<<5) // Warning! Check this bit connection for E4 A…
53164 … (0x1<<6) // Warning! Check this bit connection for E4 A…
53166 … (0x1<<7) // Warning! Check this bit connection for E4 A…
53168 … (0x1<<8) // Warning! Check this bit connection for E4 A…
53170 … (0x1<<9) // Warning! Check this bit connection for E4 A…
53172 … (0x1<<10) // Warning! Check this bit connection for E4 A…
53174 … (0x1<<11) // Warning! Check this bit connection for E4 A…
53176 … (0x1<<12) // Warning! Check this bit connection for E4 A…
53178 … (0x1<<13) // Warning! Check this bit connection for E4 A…
53180 … (0x1<<14) // Warning! Check this bit connection for E4 A…
53182 … (0x1<<15) // Warning! Check this bit connection for E4 A…
53184 … (0x1<<16) // Warning! Check this bit connection for E4 A…
53186 … (0x1<<17) // Warning! Check this bit connection for E4 A…
53188 … (0x1<<18) // Warning! Check this bit connection for E4 A…
53190 … (0x1<<19) // Warning! Check this bit connection for E4 A…
53192 … (0x1<<20) // Warning! Check this bit connection for E4 A…
53194 … (0x1<<21) // Warning! Check this bit connection for E4 A…
53196 … (0x1<<22) // Warning! Check this bit connection for E4 A…
53198 … (0x1<<23) // Warning! Check this bit connection for E4 A…
53200 … (0x1<<24) // Warning! Check this bit connection for E4 A…
53202 … (0x1<<25) // Warning! Check this bit connection for E4 A…
53204 … (0x1<<26) // Warning! Check this bit connection for E4 A…
53206 … (0x1<<27) // Warning! Check this bit connection for E4 A…
53209 …E_FIFO_ERROR (0x1<<1) // Read packet clie…
53210 …RB_REG_INT_STS_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT 1
53272 … (0x1<<1) // This bit masks, when set, the Interrupt …
53273 …RB_REG_INT_MASK_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT 1
53274 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
53276 … (0x1<<3) // This bit masks, when set, the Interrupt bit: B…
53278 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
53280 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
53282 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
53284 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
53286 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
53288 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
53290 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
53292 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
53294 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
53296 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
53298 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
53300 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
53302 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
53304 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
53306 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
53308 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
53310 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
53312 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
53314 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
53316 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
53318 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
53320 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
53322 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
53324 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
53326 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
53328 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
53330 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
53332 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
53335 …SIDE_FIFO_ERROR (0x1<<1) // Read packet clie…
53336 …RB_REG_INT_STS_WR_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT 1
53398 …_SIDE_FIFO_ERROR (0x1<<1) // Read packet clie…
53399 …RB_REG_INT_STS_CLR_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT 1
53463 …_FIFO_ERROR (0x1<<1) // Read SOP client …
53464 …RB_REG_INT_STS_4_RC_SOP_STRT_FIFO_ERROR_SHIFT 1
53473 … (0x1<<6) // Read EOP client 1 request FIFO error R…
53495 … (0x1<<22) // Read packet client parser error when SOP bit is set in the packe…
53516 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
53518 … (0x1<<1) // This bit masks, when set, the Interrupt …
53519 …RB_REG_INT_MASK_4_RC_SOP_STRT_FIFO_ERROR_SHIFT 1
53520 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
53522 … (0x1<<3) // This bit masks, when set, the Interrupt bit: B…
53524 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
53526 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
53528 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
53530 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
53532 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
53534 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
53536 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
53538 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
53540 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
53542 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
53544 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
53546 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
53548 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
53550 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
53552 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
53554 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
53556 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
53558 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
53560 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
53562 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
53564 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
53566 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
53568 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
53573 …TRT_FIFO_ERROR (0x1<<1) // Read SOP client …
53574 …RB_REG_INT_STS_WR_4_RC_SOP_STRT_FIFO_ERROR_SHIFT 1
53583 … (0x1<<6) // Read EOP client 1 request FIFO error R…
53605 … (0x1<<22) // Read packet client parser error when SOP bit is set in the packe…
53628 …STRT_FIFO_ERROR (0x1<<1) // Read SOP client …
53629 …RB_REG_INT_STS_CLR_4_RC_SOP_STRT_FIFO_ERROR_SHIFT 1
53638 … (0x1<<6) // Read EOP client 1 request FIFO error R…
53660 … (0x1<<22) // Read packet client parser error when SOP bit is set in the packe…
53684 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
53695 … (0x1<<23) // Warning! Check this bit connection for E4 A…
53697 … (0x1<<24) // Warning! Check this bit connection for E4 A…
53699 … (0x1<<25) // Warning! Check this bit connection for E4 A…
53701 … (0x1<<26) // Warning! Check this bit connection for E4 A…
53703 … (0x1<<29) // Warning! Check this bit connection for E4 A…
53705 … (0x1<<30) // Warning! Check this bit connection for E4 A…
53707 … (0x1<<31) // Warning! Check this bit connection for E4 A…
53710 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
53712 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
53714 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
53716 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
53718 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
53720 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
53722 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
53724 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
53729 … (0x1<<23) // Warning! Check this bit connection for E4 A…
53731 … (0x1<<24) // Warning! Check this bit connection for E4 A…
53733 … (0x1<<25) // Warning! Check this bit connection for E4 A…
53735 … (0x1<<26) // Warning! Check this bit connection for E4 A…
53737 … (0x1<<29) // Warning! Check this bit connection for E4 A…
53739 … (0x1<<30) // Warning! Check this bit connection for E4 A…
53741 … (0x1<<31) // Warning! Check this bit connection for E4 A…
53746 … (0x1<<23) // Warning! Check this bit connection for E4 A…
53748 … (0x1<<24) // Warning! Check this bit connection for E4 A…
53750 … (0x1<<25) // Warning! Check this bit connection for E4 A…
53752 … (0x1<<26) // Warning! Check this bit connection for E4 A…
53754 … (0x1<<29) // Warning! Check this bit connection for E4 A…
53756 … (0x1<<30) // Warning! Check this bit connection for E4 A…
53758 … (0x1<<31) // Warning! Check this bit connection for E4 A…
53761 … (0x1<<0) // Warning! Check this bit connection for E4 A…
53763 … (0x1<<1) // Warning! Check this bit connec…
53764 …RB_REG_INT_STS_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT 1
53765 … (0x1<<2) // Warning! Check this bit connection for E4 A…
53767 … (0x1<<3) // Warning! Check this bit connection for E4 A…
53769 … (0x1<<4) // Warning! Check this bit connection for E4 A…
53771 … (0x1<<5) // Warning! Check this bit connection for E4 A…
53773 … (0x1<<6) // Warning! Check this bit connection for E4 A…
53775 … (0x1<<7) // Warning! Check this bit connection for E4 A…
53777 … (0x1<<8) // Warning! Check this bit connection for E4 A…
53779 … (0x1<<9) // Warning! Check this bit connection for E4 A…
53781 … (0x1<<10) // Warning! Check this bit connection for E4 A…
53783 … (0x1<<11) // Warning! Check this bit connection for E4 A…
53785 … (0x1<<12) // Warning! Check this bit connection for E4 A…
53787 … (0x1<<13) // Warning! Check this bit connection for E4 A…
53789 … (0x1<<14) // Warning! Check this bit connection for E4 A…
53791 … (0x1<<15) // Warning! Check this bit connection for E4 A…
53793 … (0x1<<16) // Warning! Check this bit connection for E4 A…
53795 … (0x1<<17) // Warning! Check this bit connection for E4 A…
53797 … (0x1<<18) // Warning! Check this bit connection for E4 A…
53801 … (0x1<<20) // Warning! Check this bit connection for E4 A…
53803 … (0x1<<21) // Warning! Check this bit connection for E4 A…
53805 … (0x1<<22) // Warning! Check this bit connection for E4 A…
53807 … (0x1<<23) // Warning! Check this bit connection for E4 A…
53809 … (0x1<<24) // Warning! Check this bit connection for E4 A…
53811 … (0x1<<25) // Warning! Check this bit connection for E4 A…
53813 … (0x1<<26) // Warning! Check this bit connection for E4 A…
53815 … (0x1<<27) // Warning! Check this bit connection for E4 A…
53817 … (0x1<<28) // Warning! Check this bit connection for E4 A…
53819 … (0x1<<29) // Warning! Check this bit connection for E4 A…
53821 … (0x1<<30) // Warning! Check this bit connection for E4 A…
53823 … (0x1<<31) // Warning! Check this bit connection for E4 A…
53826 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
53828 … (0x1<<1) // This bit masks, when set, the Interrupt …
53829 …RB_REG_INT_MASK_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT 1
53830 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
53832 … (0x1<<3) // This bit masks, when set, the Interrupt bit: B…
53834 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
53836 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
53838 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
53840 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
53842 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
53844 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
53846 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
53848 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
53850 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
53852 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
53854 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
53856 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
53858 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
53860 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
53862 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
53864 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
53866 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
53868 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
53870 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
53872 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
53874 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
53876 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
53878 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
53880 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
53882 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
53884 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
53886 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
53888 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
53891 … (0x1<<0) // Warning! Check this bit connection for E4 A…
53893 …ROR (0x1<<1) // Warning! Check this bit connec…
53894 …RB_REG_INT_STS_WR_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT 1
53895 … (0x1<<2) // Warning! Check this bit connection for E4 A…
53897 … (0x1<<3) // Warning! Check this bit connection for E4 A…
53899 … (0x1<<4) // Warning! Check this bit connection for E4 A…
53901 … (0x1<<5) // Warning! Check this bit connection for E4 A…
53903 … (0x1<<6) // Warning! Check this bit connection for E4 A…
53905 … (0x1<<7) // Warning! Check this bit connection for E4 A…
53907 … (0x1<<8) // Warning! Check this bit connection for E4 A…
53909 … (0x1<<9) // Warning! Check this bit connection for E4 A…
53911 … (0x1<<10) // Warning! Check this bit connection for E4 A…
53913 … (0x1<<11) // Warning! Check this bit connection for E4 A…
53915 … (0x1<<12) // Warning! Check this bit connection for E4 A…
53917 … (0x1<<13) // Warning! Check this bit connection for E4 A…
53919 … (0x1<<14) // Warning! Check this bit connection for E4 A…
53921 … (0x1<<15) // Warning! Check this bit connection for E4 A…
53923 … (0x1<<16) // Warning! Check this bit connection for E4 A…
53925 … (0x1<<17) // Warning! Check this bit connection for E4 A…
53927 … (0x1<<18) // Warning! Check this bit connection for E4 A…
53931 … (0x1<<20) // Warning! Check this bit connection for E4 A…
53933 … (0x1<<21) // Warning! Check this bit connection for E4 A…
53935 … (0x1<<22) // Warning! Check this bit connection for E4 A…
53937 … (0x1<<23) // Warning! Check this bit connection for E4 A…
53939 … (0x1<<24) // Warning! Check this bit connection for E4 A…
53941 … (0x1<<25) // Warning! Check this bit connection for E4 A…
53943 … (0x1<<26) // Warning! Check this bit connection for E4 A…
53945 … (0x1<<27) // Warning! Check this bit connection for E4 A…
53947 … (0x1<<28) // Warning! Check this bit connection for E4 A…
53949 … (0x1<<29) // Warning! Check this bit connection for E4 A…
53951 … (0x1<<30) // Warning! Check this bit connection for E4 A…
53953 … (0x1<<31) // Warning! Check this bit connection for E4 A…
53956 … (0x1<<0) // Warning! Check this bit connection for E4 A…
53958 …RROR (0x1<<1) // Warning! Check this bit connec…
53959 …RB_REG_INT_STS_CLR_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT 1
53960 … (0x1<<2) // Warning! Check this bit connection for E4 A…
53962 … (0x1<<3) // Warning! Check this bit connection for E4 A…
53964 … (0x1<<4) // Warning! Check this bit connection for E4 A…
53966 … (0x1<<5) // Warning! Check this bit connection for E4 A…
53968 … (0x1<<6) // Warning! Check this bit connection for E4 A…
53970 … (0x1<<7) // Warning! Check this bit connection for E4 A…
53972 … (0x1<<8) // Warning! Check this bit connection for E4 A…
53974 … (0x1<<9) // Warning! Check this bit connection for E4 A…
53976 … (0x1<<10) // Warning! Check this bit connection for E4 A…
53978 … (0x1<<11) // Warning! Check this bit connection for E4 A…
53980 … (0x1<<12) // Warning! Check this bit connection for E4 A…
53982 … (0x1<<13) // Warning! Check this bit connection for E4 A…
53984 … (0x1<<14) // Warning! Check this bit connection for E4 A…
53986 … (0x1<<15) // Warning! Check this bit connection for E4 A…
53988 … (0x1<<16) // Warning! Check this bit connection for E4 A…
53990 … (0x1<<17) // Warning! Check this bit connection for E4 A…
53992 … (0x1<<18) // Warning! Check this bit connection for E4 A…
53996 … (0x1<<20) // Warning! Check this bit connection for E4 A…
53998 … (0x1<<21) // Warning! Check this bit connection for E4 A…
54000 … (0x1<<22) // Warning! Check this bit connection for E4 A…
54002 … (0x1<<23) // Warning! Check this bit connection for E4 A…
54004 … (0x1<<24) // Warning! Check this bit connection for E4 A…
54006 … (0x1<<25) // Warning! Check this bit connection for E4 A…
54008 … (0x1<<26) // Warning! Check this bit connection for E4 A…
54010 … (0x1<<27) // Warning! Check this bit connection for E4 A…
54012 … (0x1<<28) // Warning! Check this bit connection for E4 A…
54014 … (0x1<<29) // Warning! Check this bit connection for E4 A…
54016 … (0x1<<30) // Warning! Check this bit connection for E4 A…
54018 … (0x1<<31) // Warning! Check this bit connection for E4 A…
54021 … (0x1<<0) // Warning! Check this bit connection for E4 A…
54023 … (0x1<<1) // Warning! Check this bit connec…
54024 …RB_REG_INT_STS_8_WC6_LL_REQ_FIFO_ERROR_SHIFT 1
54025 … (0x1<<2) // Warning! Check this bit connection for E4 A…
54027 … (0x1<<3) // Warning! Check this bit connection for E4 A…
54029 … (0x1<<4) // Warning! Check this bit connection for E4 A…
54031 … (0x1<<5) // Warning! Check this bit connection for E4 A…
54033 … (0x1<<6) // Warning! Check this bit connection for E4 A…
54035 … (0x1<<7) // Warning! Check this bit connection for E4 A…
54037 … (0x1<<8) // Warning! Check this bit connection for E4 A…
54039 … (0x1<<9) // Warning! Check this bit connection for E4 A…
54041 … (0x1<<10) // Warning! Check this bit connection for E4 A…
54043 … (0x1<<11) // Warning! Check this bit connection for E4 A…
54045 … (0x1<<12) // Warning! Check this bit connection for E4 A…
54047 … (0x1<<13) // Warning! Check this bit connection for E4 A…
54049 … (0x1<<14) // Warning! Check this bit connection for E4 A…
54051 … (0x1<<15) // Warning! Check this bit connection for E4 A…
54053 … (0x1<<16) // Warning! Check this bit connection for E4 A…
54056 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
54058 … (0x1<<1) // This bit masks, when set, the Interrupt …
54059 …RB_REG_INT_MASK_8_WC6_LL_REQ_FIFO_ERROR_SHIFT 1
54060 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
54062 … (0x1<<3) // This bit masks, when set, the Interrupt bit: B…
54064 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
54066 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
54068 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
54070 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
54072 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
54074 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
54076 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
54078 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
54080 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
54082 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
54084 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
54086 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
54088 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
54091 … (0x1<<0) // Warning! Check this bit connection for E4 A…
54093 … (0x1<<1) // Warning! Check this bit connec…
54094 …RB_REG_INT_STS_WR_8_WC6_LL_REQ_FIFO_ERROR_SHIFT 1
54095 … (0x1<<2) // Warning! Check this bit connection for E4 A…
54097 … (0x1<<3) // Warning! Check this bit connection for E4 A…
54099 … (0x1<<4) // Warning! Check this bit connection for E4 A…
54101 … (0x1<<5) // Warning! Check this bit connection for E4 A…
54103 … (0x1<<6) // Warning! Check this bit connection for E4 A…
54105 … (0x1<<7) // Warning! Check this bit connection for E4 A…
54107 … (0x1<<8) // Warning! Check this bit connection for E4 A…
54109 … (0x1<<9) // Warning! Check this bit connection for E4 A…
54111 … (0x1<<10) // Warning! Check this bit connection for E4 A…
54113 … (0x1<<11) // Warning! Check this bit connection for E4 A…
54115 … (0x1<<12) // Warning! Check this bit connection for E4 A…
54117 … (0x1<<13) // Warning! Check this bit connection for E4 A…
54119 … (0x1<<14) // Warning! Check this bit connection for E4 A…
54121 … (0x1<<15) // Warning! Check this bit connection for E4 A…
54123 … (0x1<<16) // Warning! Check this bit connection for E4 A…
54126 … (0x1<<0) // Warning! Check this bit connection for E4 A…
54128 … (0x1<<1) // Warning! Check this bit connec…
54129 …RB_REG_INT_STS_CLR_8_WC6_LL_REQ_FIFO_ERROR_SHIFT 1
54130 … (0x1<<2) // Warning! Check this bit connection for E4 A…
54132 … (0x1<<3) // Warning! Check this bit connection for E4 A…
54134 … (0x1<<4) // Warning! Check this bit connection for E4 A…
54136 … (0x1<<5) // Warning! Check this bit connection for E4 A…
54138 … (0x1<<6) // Warning! Check this bit connection for E4 A…
54140 … (0x1<<7) // Warning! Check this bit connection for E4 A…
54142 … (0x1<<8) // Warning! Check this bit connection for E4 A…
54144 … (0x1<<9) // Warning! Check this bit connection for E4 A…
54146 … (0x1<<10) // Warning! Check this bit connection for E4 A…
54148 … (0x1<<11) // Warning! Check this bit connection for E4 A…
54150 … (0x1<<12) // Warning! Check this bit connection for E4 A…
54152 … (0x1<<13) // Warning! Check this bit connection for E4 A…
54154 … (0x1<<14) // Warning! Check this bit connection for E4 A…
54156 … (0x1<<15) // Warning! Check this bit connection for E4 A…
54158 … (0x1<<16) // Warning! Check this bit connection for E4 A…
54161 … (0x1<<0) // Warning! Check this bit connection for E4 A…
54164 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
54167 … (0x1<<0) // Warning! Check this bit connection for E4 A…
54170 … (0x1<<0) // Warning! Check this bit connection for E4 A…
54173 …_SYNC_FIFO_PUSH_ERROR (0x1<<1) // SOP input SYNC F…
54174 …RB_REG_INT_STS_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT 1
54210 … (0x1<<1) // This bit masks, when set, the Interrupt …
54211 …RB_REG_INT_MASK_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT 1
54212 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
54214 … (0x1<<3) // This bit masks, when set, the Interrupt bit: B…
54216 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
54218 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
54220 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
54222 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
54224 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
54226 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
54228 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
54230 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
54232 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
54234 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
54236 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
54238 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
54240 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
54242 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
54244 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
54247 …INP_SYNC_FIFO_PUSH_ERROR (0x1<<1) // SOP input SYNC F…
54248 …RB_REG_INT_STS_WR_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT 1
54284 …_INP_SYNC_FIFO_PUSH_ERROR (0x1<<1) // SOP input SYNC F…
54285 …RB_REG_INT_STS_CLR_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT 1
54325 …ee shared area calculation error for MAC port 2 When unified_shared_area is 1 this error can be ig…
54327 …ee shared area calculation error for MAC port 3 When unified_shared_area is 1 this error can be ig…
54329 … (0x1<<14) // Warning! Check this bit connection for E4 A…
54331 … (0x1<<15) // Warning! Check this bit connection for E4 A…
54333 … (0x1<<16) // Warning! Check this bit connection for E4 A…
54335 … (0x1<<17) // Warning! Check this bit connection for E4 A…
54338 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
54340 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
54342 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
54344 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
54346 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
54348 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
54350 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
54352 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
54359 …ee shared area calculation error for MAC port 2 When unified_shared_area is 1 this error can be ig…
54361 …ee shared area calculation error for MAC port 3 When unified_shared_area is 1 this error can be ig…
54363 … (0x1<<14) // Warning! Check this bit connection for E4 A…
54365 … (0x1<<15) // Warning! Check this bit connection for E4 A…
54367 … (0x1<<16) // Warning! Check this bit connection for E4 A…
54369 … (0x1<<17) // Warning! Check this bit connection for E4 A…
54376 …ee shared area calculation error for MAC port 2 When unified_shared_area is 1 this error can be ig…
54378 …ee shared area calculation error for MAC port 3 When unified_shared_area is 1 this error can be ig…
54380 … (0x1<<14) // Warning! Check this bit connection for E4 A…
54382 … (0x1<<15) // Warning! Check this bit connection for E4 A…
54384 … (0x1<<16) // Warning! Check this bit connection for E4 A…
54386 … (0x1<<17) // Warning! Check this bit connection for E4 A…
54389 … (0x1<<0) // This bit masks, when set, the Parity bit: BR…
54391 … (0x1<<1) // This bit masks, when set, the Parity bi…
54392 …RB_REG_PRTY_MASK_LL_BANK1_MEM_PRTY_SHIFT 1
54393 … (0x1<<2) // This bit masks, when set, the Parity bit: BR…
54395 … (0x1<<3) // This bit masks, when set, the Parity bit: BR…
54397 … (0x1<<4) // This bit masks, when set, the Parity bit: BR…
54400 … (0x1<<0) // This bit masks, when set, the Parity bit: BR…
54402 … (0x1<<1) // This bit masks, when set, the Parity bi…
54403 …RB_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_SHIFT 1
54404 … (0x1<<2) // This bit masks, when set, the Parity bit: BR…
54406 … (0x1<<3) // This bit masks, when set, the Parity bit: BR…
54408 … (0x1<<4) // This bit masks, when set, the Parity bit: BR…
54410 … (0x1<<5) // This bit masks, when set, the Parity bit: BR…
54412 … (0x1<<6) // This bit masks, when set, the Parity bit: BR…
54414 … (0x1<<7) // This bit masks, when set, the Parity bit: BR…
54416 … (0x1<<8) // This bit masks, when set, the Parity bit: BR…
54418 … (0x1<<9) // This bit masks, when set, the Parity bit: BR…
54420 … (0x1<<10) // This bit masks, when set, the Parity bit: BR…
54422 … (0x1<<11) // This bit masks, when set, the Parity bit: BR…
54424 … (0x1<<12) // This bit masks, when set, the Parity bit: BR…
54426 … (0x1<<13) // This bit masks, when set, the Parity bit: BR…
54428 … (0x1<<14) // This bit masks, when set, the Parity bit: BR…
54430 … (0x1<<15) // This bit masks, when set, the Parity bit: BR…
54432 … (0x1<<16) // This bit masks, when set, the Parity bit: BR…
54434 … (0x1<<17) // This bit masks, when set, the Parity bit: BR…
54436 … (0x1<<18) // This bit masks, when set, the Parity bit: BR…
54438 … (0x1<<19) // This bit masks, when set, the Parity bit: BR…
54440 … (0x1<<20) // This bit masks, when set, the Parity bit: BR…
54442 … (0x1<<21) // This bit masks, when set, the Parity bit: BR…
54444 … (0x1<<22) // This bit masks, when set, the Parity bit: BR…
54446 … (0x1<<23) // This bit masks, when set, the Parity bit: BR…
54448 … (0x1<<29) // This bit masks, when set, the Parity bit: BR…
54450 … (0x1<<24) // This bit masks, when set, the Parity bit: BR…
54452 … (0x1<<28) // This bit masks, when set, the Parity bit: BR…
54454 … (0x1<<25) // This bit masks, when set, the Parity bit: BR…
54456 … (0x1<<20) // This bit masks, when set, the Parity bit: BR…
54458 … (0x1<<26) // This bit masks, when set, the Parity bit: BR…
54460 … (0x1<<21) // This bit masks, when set, the Parity bit: BR…
54462 … (0x1<<27) // This bit masks, when set, the Parity bit: BR…
54464 … (0x1<<22) // This bit masks, when set, the Parity bit: BR…
54466 … (0x1<<28) // This bit masks, when set, the Parity bit: BR…
54468 … (0x1<<23) // This bit masks, when set, the Parity bit: BR…
54470 … (0x1<<29) // This bit masks, when set, the Parity bit: BR…
54472 … (0x1<<24) // This bit masks, when set, the Parity bit: BR…
54474 … (0x1<<30) // This bit masks, when set, the Parity bit: BR…
54476 … (0x1<<16) // This bit masks, when set, the Parity bit: BR…
54478 … (0x1<<17) // This bit masks, when set, the Parity bit: BR…
54480 … (0x1<<17) // This bit masks, when set, the Parity bit: BR…
54482 … (0x1<<18) // This bit masks, when set, the Parity bit: BR…
54484 … (0x1<<16) // This bit masks, when set, the Parity bit: BR…
54486 … (0x1<<19) // This bit masks, when set, the Parity bit: BR…
54488 … (0x1<<20) // This bit masks, when set, the Parity bit: BR…
54490 … (0x1<<21) // This bit masks, when set, the Parity bit: BR…
54492 … (0x1<<22) // This bit masks, when set, the Parity bit: BR…
54494 … (0x1<<23) // This bit masks, when set, the Parity bit: BR…
54496 … (0x1<<24) // This bit masks, when set, the Parity bit: BR…
54498 … (0x1<<25) // This bit masks, when set, the Parity bit: BR…
54500 … (0x1<<26) // This bit masks, when set, the Parity bit: BR…
54502 … (0x1<<27) // This bit masks, when set, the Parity bit: BR…
54504 … (0x1<<30) // This bit masks, when set, the Parity bit: BR…
54506 … (0x1<<18) // This bit masks, when set, the Parity bit: BR…
54508 … (0x1<<19) // This bit masks, when set, the Parity bit: BR…
54510 … (0x1<<25) // This bit masks, when set, the Parity bit: BR…
54512 … (0x1<<26) // This bit masks, when set, the Parity bit: BR…
54514 … (0x1<<27) // This bit masks, when set, the Parity bit: BR…
54516 … (0x1<<28) // This bit masks, when set, the Parity bit: BR…
54518 … (0x1<<29) // This bit masks, when set, the Parity bit: BR…
54520 … (0x1<<30) // This bit masks, when set, the Parity bit: BR…
54523 … (0x1<<10) // This bit masks, when set, the Parity bit: BR…
54525 … (0x1<<0) // This bit masks, when set, the Parity bit: BR…
54527 … (0x1<<1) // This bit masks, when set, the Parity bi…
54528 …RB_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_E5_SHIFT 1
54529 … (0x1<<2) // This bit masks, when set, the Parity bit: BR…
54531 … (0x1<<3) // This bit masks, when set, the Parity bit: BR…
54533 … (0x1<<4) // This bit masks, when set, the Parity bit: BR…
54535 … (0x1<<5) // This bit masks, when set, the Parity bit: BR…
54537 … (0x1<<6) // This bit masks, when set, the Parity bit: BR…
54539 … (0x1<<7) // This bit masks, when set, the Parity bit: BR…
54541 … (0x1<<8) // This bit masks, when set, the Parity bit: BR…
54543 … (0x1<<9) // This bit masks, when set, the Parity bit: BR…
54545 … (0x1<<10) // This bit masks, when set, the Parity bit: BR…
54547 … (0x1<<11) // This bit masks, when set, the Parity bit: BR…
54549 … (0x1<<12) // This bit masks, when set, the Parity bit: BR…
54551 … (0x1<<13) // This bit masks, when set, the Parity bit: BR…
54553 … (0x1<<14) // This bit masks, when set, the Parity bit: BR…
54555 … (0x1<<15) // This bit masks, when set, the Parity bit: BR…
54557 … (0x1<<11) // This bit masks, when set, the Parity bit: BR…
54559 … (0x1<<16) // This bit masks, when set, the Parity bit: BR…
54561 … (0x1<<3) // This bit masks, when set, the Parity bit: BR…
54563 … (0x1<<17) // This bit masks, when set, the Parity bit: BR…
54565 … (0x1<<4) // This bit masks, when set, the Parity bit: BR…
54567 … (0x1<<18) // This bit masks, when set, the Parity bit: BR…
54569 … (0x1<<17) // This bit masks, when set, the Parity bit: BR…
54571 … (0x1<<19) // This bit masks, when set, the Parity bit: BR…
54573 … (0x1<<28) // This bit masks, when set, the Parity bit: BR…
54575 … (0x1<<20) // This bit masks, when set, the Parity bit: BR…
54577 … (0x1<<13) // This bit masks, when set, the Parity bit: BR…
54579 … (0x1<<21) // This bit masks, when set, the Parity bit: BR…
54581 … (0x1<<0) // This bit masks, when set, the Parity bit: BR…
54583 … (0x1<<22) // This bit masks, when set, the Parity bit: BR…
54585 … (0x1<<1) // This bit masks, when set, the Parity bi…
54586 …RB_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_BB_SHIFT 1
54587 … (0x1<<23) // This bit masks, when set, the Parity bit: BR…
54589 … (0x1<<8) // This bit masks, when set, the Parity bit: BR…
54591 … (0x1<<14) // This bit masks, when set, the Parity bit: BR…
54593 … (0x1<<24) // This bit masks, when set, the Parity bit: BR…
54595 … (0x1<<7) // This bit masks, when set, the Parity bit: BR…
54597 … (0x1<<13) // This bit masks, when set, the Parity bit: BR…
54599 … (0x1<<25) // This bit masks, when set, the Parity bit: BR…
54601 … (0x1<<2) // This bit masks, when set, the Parity bit: BR…
54603 … (0x1<<26) // This bit masks, when set, the Parity bit: BR…
54605 … (0x1<<3) // This bit masks, when set, the Parity bit: BR…
54607 … (0x1<<29) // This bit masks, when set, the Parity bit: BR…
54609 … (0x1<<27) // This bit masks, when set, the Parity bit: BR…
54611 … (0x1<<6) // This bit masks, when set, the Parity bit: BR…
54613 … (0x1<<12) // This bit masks, when set, the Parity bit: BR…
54615 … (0x1<<28) // This bit masks, when set, the Parity bit: BR…
54617 … (0x1<<9) // This bit masks, when set, the Parity bit: BR…
54619 … (0x1<<21) // This bit masks, when set, the Parity bit: BR…
54621 … (0x1<<29) // This bit masks, when set, the Parity bit: BR…
54623 … (0x1<<10) // This bit masks, when set, the Parity bit: BR…
54625 … (0x1<<22) // This bit masks, when set, the Parity bit: BR…
54627 … (0x1<<30) // This bit masks, when set, the Parity bit: BR…
54629 … (0x1<<0) // This bit masks, when set, the Parity bit: BR…
54631 … (0x1<<1) // This bit masks, when set, the Parity bi…
54632 …RB_REG_PRTY_MASK_H_1_MEM067_I_MEM_PRTY_K2_SHIFT 1
54633 … (0x1<<2) // This bit masks, when set, the Parity bit: BR…
54635 … (0x1<<5) // This bit masks, when set, the Parity bit: BR…
54637 … (0x1<<6) // This bit masks, when set, the Parity bit: BR…
54639 … (0x1<<7) // This bit masks, when set, the Parity bit: BR…
54641 … (0x1<<8) // This bit masks, when set, the Parity bit: BR…
54643 … (0x1<<9) // This bit masks, when set, the Parity bit: BR…
54645 … (0x1<<4) // This bit masks, when set, the Parity bit: BR…
54647 … (0x1<<15) // This bit masks, when set, the Parity bit: BR…
54649 … (0x1<<16) // This bit masks, when set, the Parity bit: BR…
54651 … (0x1<<5) // This bit masks, when set, the Parity bit: BR…
54653 … (0x1<<18) // This bit masks, when set, the Parity bit: BR…
54655 … (0x1<<19) // This bit masks, when set, the Parity bit: BR…
54657 … (0x1<<20) // This bit masks, when set, the Parity bit: BR…
54659 … (0x1<<11) // This bit masks, when set, the Parity bit: BR…
54661 … (0x1<<23) // This bit masks, when set, the Parity bit: BR…
54663 … (0x1<<12) // This bit masks, when set, the Parity bit: BR…
54665 … (0x1<<24) // This bit masks, when set, the Parity bit: BR…
54667 … (0x1<<25) // This bit masks, when set, the Parity bit: BR…
54669 … (0x1<<26) // This bit masks, when set, the Parity bit: BR…
54671 … (0x1<<27) // This bit masks, when set, the Parity bit: BR…
54673 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54675 … (0x1<<0) // This bit masks, when set, the Parity bit: BR…
54677 …1].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of ea…
54678 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54679 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54685 … (0x1<<1) // Enable ECC for memory ecc instance brb.BB_BANK_K…
54686 …RB_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_EN_SHIFT 1
54719 … (0x1<<18) // Enable ECC for memory ecc instance brb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i…
54721 … (0x1<<19) // Enable ECC for memory ecc instance brb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i…
54731 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54735 … (0x1<<0) // Set parity only for memory ecc inst…
54737 … (0x1<<1) // Set parity only for memory ecc instance brb.BB_BANK…
54738 …RB_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_PRTY_SHIFT 1
54739 … (0x1<<2) // Set parity only for memory ecc inst…
54741 … (0x1<<3) // Set parity only for memory ecc inst…
54743 … (0x1<<4) // Set parity only for memory ecc inst…
54745 … (0x1<<5) // Set parity only for memory ecc inst…
54747 … (0x1<<6) // Set parity only for memory ecc inst…
54749 … (0x1<<7) // Set parity only for memory ecc inst…
54751 … (0x1<<8) // Set parity only for memory ecc inst…
54753 … (0x1<<9) // Set parity only for memory ecc inst…
54755 … (0x1<<10) // Set parity only for memory ecc inst…
54757 … (0x1<<11) // Set parity only for memory ecc inst…
54759 … (0x1<<12) // Set parity only for memory ecc inst…
54761 … (0x1<<13) // Set parity only for memory ecc inst…
54763 … (0x1<<14) // Set parity only for memory ecc inst…
54765 … (0x1<<15) // Set parity only for memory ecc inst…
54767 …E5 (0x1<<16) // Set parity only for memory ecc inst…
54769 …E5 (0x1<<17) // Set parity only for memory ecc inst…
54771 … (0x1<<18) // Set parity only for memory ecc instance brb.LL_BANK_K2_GEN_…
54773 … (0x1<<19) // Set parity only for memory ecc instance brb.LL_BANK_K2_GEN_…
54775 …E5 (0x1<<20) // Set parity only for memory ecc inst…
54777 …E5 (0x1<<21) // Set parity only for memory ecc inst…
54779 …E5 (0x1<<22) // Set parity only for memory ecc inst…
54781 …E5 (0x1<<23) // Set parity only for memory ecc inst…
54783 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54789 … (0x1<<1) // Record if a correctable error occurred on memory ecc instance …
54790 …RB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_CORRECT_SHIFT 1
54823 … a correctable error occurred on memory ecc instance brb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i…
54825 … a correctable error occurred on memory ecc instance brb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i…
54835 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54839 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54840 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54841 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54842 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54843 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54844 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54845 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54846 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54847 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54848 … to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_…
54849 …04UL //Access:RW DataWidth:0xa // Number of valid bytes in header in 16-bytes resolution. Aft…
54857 … 0x340844UL //Access:RW DataWidth:0x5 // There is bit for each PACKET read client. When bit …
54858 …- SUM(tc_guarantied) Reset value is right for 128B block size only. It should be twice smaller for…
54861 …only. It should be twice smaller for 256B block size. When unified_shared_area is 1, then the thre…
54864 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
54865 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
54866 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
54867 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
54868 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
54869 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
54870 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
54871 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
54872 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
54873 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
54874 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
54875 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
54876 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
54877 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
54878 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
54879 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
54880 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
54881 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
54882 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
54883 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
54884 …on for each TC in each main port.Reset value is right for 128B block size only. It should be twice…
54885 …on for each TC in each main port.Reset value is right for 128B block size only. It should be twice…
54886 …on for each TC in each main port.Reset value is right for 128B block size only. It should be twice…
54887 …on for each TC in each main port.Reset value is right for 128B block size only. It should be twice…
54888 …on for each TC in each main port.Reset value is right for 128B block size only. It should be twice…
54889 …on for each TC in each main port.Reset value is right for 128B block size only. It should be twice…
54890 …on for each TC in each main port.Reset value is right for 128B block size only. It should be twice…
54891 …on for each TC in each main port.Reset value is right for 128B block size only. It should be twice…
54892 …on for each TC in each main port.Reset value is right for 128B block size only. It should be twice…
54893 …on for each TC in each main port.Reset value is right for 128B block size only. It should be twice…
54894 …on for each TC in each main port.Reset value is right for 128B block size only. It should be twice…
54895 …on for each TC in each main port.Reset value is right for 128B block size only. It should be twice…
54896 …on for each TC in each main port.Reset value is right for 128B block size only. It should be twice…
54897 …on for each TC in each main port.Reset value is right for 128B block size only. It should be twice…
54898 …on for each TC in each main port.Reset value is right for 128B block size only. It should be twice…
54899 …on for each TC in each main port.Reset value is right for 128B block size only. It should be twice…
54900 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
54901 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
54902 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
54903 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
54904 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
54905 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
54906 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
54907 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
54908 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
54909 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
54910 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
54911 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
54912 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
54913 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
54914 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
54915 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
54916 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
54917 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
54918 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
54919 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
54920 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54921 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54922 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54923 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54924 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54925 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54926 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54927 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54928 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54929 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54930 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54931 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54932 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54933 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54934 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54935 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54936 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54937 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54938 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54939 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54940 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54941 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54942 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54943 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54944 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54945 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54946 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54947 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54948 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54949 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54950 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54951 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54952 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54953 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54954 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54955 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54956 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54957 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54958 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54959 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54960 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54961 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54962 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54963 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54964 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54965 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54966 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54967 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54968 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54969 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54970 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54971 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54972 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54973 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54974 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54975 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54976 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54977 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54978 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54979 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54980 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54981 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54982 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54983 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54984 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54985 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54986 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54987 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54988 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54989 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54990 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54991 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54992 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
54993 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
54994 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
54995 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
54996 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
54997 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
54998 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
54999 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55000 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55001 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55002 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55003 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55004 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55005 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55006 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55007 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55008 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55009 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55010 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55011 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55012 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55013 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55014 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55015 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55016 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55017 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55018 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55019 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55020 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55021 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55022 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55023 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55024 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55025 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55026 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55027 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55028 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55029 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55030 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55031 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55032 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55033 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55034 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55035 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55036 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55037 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55038 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55039 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55040 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55041 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55042 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55043 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55044 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55045 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55046 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55047 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55048 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55049 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55050 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55051 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55052 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55053 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55054 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55055 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55056 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55057 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55058 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55059 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55060 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55061 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55062 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55063 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55065 …DataWidth:0x1 // If 1 then interrupt will be asserted when number of allocated blocks in TC bi…
55066 …H/13/g in Data Width::/EMPTY_EN/d in Existance. When unified_shared_area is 1, then the threshold …
55067 …low which EMPTY[1] is asserted for this MAC port::s/BLK_WDTH/13/g in Data Width::/EMPTY_EN/d in Ex…
55070 …bit for each PACKET read client. Bit 0 suits to client 0 and so on. If bit is set then packet will…
55072 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
55074 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
55076 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
55078 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
55080 … priority then selection between them is done with RR. Possible values are 1-3. Priority 7 is high…
55082 …bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then packet wil…
55083 …bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then highest pr…
55084 …is is priority for SOP read client to Big RAM arbiter. Possible values are 1-3. Priority 3 is high…
55085 …s is priority for EOP read client to BIG RAM arbiters. Possible values are 0-7. Priority 7 is high…
55086 …cket request of write client group to Big RAM arbiter. Possible values are 1-3. Priority 3 is high…
55087 …ll be done with round robin. Only one group with multiple clients of identical priority is support…
55098 …H/13/g in Data Width::/EMPTY_EN/d in Existance. When unified_shared_area is 1, then the free block…
55099 …er management block when number of packets of appropriate TC is bigger than 1::s/COS_NUM/9/g in Da…
55100 …er management block when number of packets of appropriate TC is bigger than 1::s/COS_NUM/9/g in Da…
55101 …er management block when number of packets of appropriate TC is bigger than 1::s/COS_NUM/9/g in Da…
55102 …er management block when number of packets of appropriate TC is bigger than 1::s/COS_NUM/9/g in Da…
55103 … 0x340ec4UL //Access:RW DataWidth:0x4 // Debug only: If more than this …
55107 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
55108 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
55109 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
55110 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
55116 …bit per each read client interface: B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser. When bit is set then …
55118 …0) // There is bit per each EOP read client interface: B0 - IF0, B1- IF1. When bit is set then app…
55120 … (0x1<<14) // There is bit per SOP read client interface. When bit is set then appropriate int…
55122 …bit per write client interface: B0 - NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - …
55125 …bit per each read client interface: B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser. When bit is set then …
55127 …10) // There is bit per each EOP read client interface: B0 - IF0, B1- IF1. When bit is set then ap…
55129 … (0x1<<14) // There is bit per SOP read client interface. When bit is set then appropriate int…
55131 …bit for all pause interfaces per each MAC port. When bit is set then pause interface is enabled. W…
55133 …bit for empty interfaces per each MAC port. When bit is set then empty interface is enabled. When …
55135 …bit for packet avalable interfaces. When bit is set then packet avalable interface is enabled. Whe…
55137 …bit for stop parsing interfaces. When bit is set then stop parsing interface is enabled. When bit …
55139 …bit for power management interfaces. When bit is set then power management interface is enabled. …
55141 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55142 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55143 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55144 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55145 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55146 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55147 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55148 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55149 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55150 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55151 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55152 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55153 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55154 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55155 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55156 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55159 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55160 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55161 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55162 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55163 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55164 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55165 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55166 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55167 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55168 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55169 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
55170 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
55171 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
55172 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
55173 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
55174 …4 // Debug register. Empty status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
55175 …x4 // Debug register. Full status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
55176 … register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr_fifo; B3:0-queue…
55177 … input FIFO for EOP client 0[0]; empty status of input FIFO for EOP client 1[1]::s/SHARE_GRP_CNT/2…
55178 …f input FIFO for EOP client 0[0]; full status of input FIFO for EOP client 1[1]::s/SHARE_GRP_CNT/2…
55179 …us of input FIFO for EOP client 0[2:0]; status of input FIFO for EOP client 1[6:3]::s/RC_EOP_STAT_…
55183 …g in Array Size::/EMPTY_EN/d in Existance. When unified_shared_area is 1 this only the first index…
55184 …g in Array Size::/EMPTY_EN/d in Existance. When unified_shared_area is 1 this only the first index…
55185 …g in Array Size::/EMPTY_EN/d in Existance. When unified_shared_area is 1 this only the first index…
55186 …g in Array Size::/EMPTY_EN/d in Existance. When unified_shared_area is 1 this only the first index…
55222 …/ Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Ar…
55223 …/ Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Ar…
55224 …/ Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Ar…
55225 …/ Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Ar…
55226 …/ Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Ar…
55227 …/ Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Ar…
55228 …/ Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Ar…
55229 …/ Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Ar…
55230 …/ Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Ar…
55241 …room areas. When unified_shared_area is 1, then the value applies to the common area for all MAC p…
55242 …room areas. When unified_shared_area is 1, then the value applies to the common area for all MAC p…
55243 …room areas. When unified_shared_area is 1, then the value applies to the common area for all MAC p…
55244 …room areas. When unified_shared_area is 1, then the value applies to the common area for all MAC p…
55269 … // Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g …
55270 … // Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g …
55271 … // Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g …
55272 … // Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g …
55273 … // Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g …
55274 … // Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g …
55275 … // Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g …
55276 … // Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g …
55291 …ter for each queue of each write client. It contains: b31 - valid; b30:16 - queue size; b15:0 - qu…
55294 …acket client interface: 0-PRM; 1-MSDM ; 2-TSDM; 3-TMLD; 4-PRS. Message spelling (MSB->LSB): rest_s…
55296 …ister for each read packet client interface: 0-PRM; 1-MSDM ; 2-TSDM; 3-TMLD; 4-PRS. Message spelli…
55298 …-port per-TC counters. In BigBear, entries 0-7 are port 0 (main 0) TCs 0-7. Entries 8-16 are port …
55301 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55303 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55305 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55307 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55309 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55311 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55313 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55315 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55321 …344000UL //Access:RW DataWidth:0x8 // This is a bitmap per WC which is 1 for WC with high pri…
55322 …344004UL //Access:RW DataWidth:0x1 // This is a bitmap per WC which is 1 for WC with high pri…
55323 …ccess:RW DataWidth:0x1 // When this bit is set, then the shared area is common for all ports.…
55326 … 0x344014UL //Access:RW DataWidth:0x10 // Bit enable per each main TC. When the bit …
55327 … 0x344018UL //Access:RW DataWidth:0x14 // Bit enable per each LB TC. When the bit i…
55328 … 0x34401cUL //Access:RW DataWidth:0x10 // Bit enable per each main TC. When the bit …
55329 … 0x344020UL //Access:RW DataWidth:0x14 // Bit enable per each LB TC. When the bit i…
55330 …Access:RW DataWidth:0xe // Link list dual port memory that contains per-block descriptor::s/B…
55331 …Access:RW DataWidth:0xf // Link list dual port memory that contains per-block descriptor::s/B…
55335 …c0000UL //Access:RW DataWidth:0x4 // Each bit indicates if the current queue ahs a strict pri…
55351 …c0048UL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 1
55356 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 1
55365 …dth:0x20 // Logging in case of minicache failure.bits 31:0 CID Valid only if bit 13 in ld_cid_mi…
55366 …dth:0x20 // Logging in case of minicache failure.bits 31:0 TID Valid only if bit 13 in ld_tid_mi…
55367 … // Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_c…
55368 … // Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_t…
55369 …th:0x4 // Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags com…
55370 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55371 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55372 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55373 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55374 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55375 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55376 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55377 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55378 …0x4c00b4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55379 …0x4c00b8UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55380 …0x4c00bcUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55381 …0x4c00c0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55383 …:0x8 // Logging register for segment message error: bits 3:0 - header len; bits 7:4 - number of…
55384 … DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 31:0 of the seg…
55385 … DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 63:32 of the se…
55386 … DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 95:64 of the se…
55392 …bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message wi…
55393 …//Access:R DataWidth:0x20 // Logging register for long message error: bit 0:3 Segment message…
55399 … (0x1<<1) // There is a probl…
55400 …YLD_REG_INT_STS_LD_HDR_ERR_SHIFT 1
55401 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55403 … (0x1<<3) // Mini cache error - meaning that A load …
55405 … (0x1<<4) // Mini cache error - meaning that A load …
55410 … (0x1<<0) // This bit masks, when set, the Interrupt bit: X…
55412 … (0x1<<1) // This bit masks, when set, the Interrupt …
55413 …YLD_REG_INT_MASK_LD_HDR_ERR_SHIFT 1
55414 … (0x1<<2) // This bit masks, when set, the Interrupt bit: X…
55416 … (0x1<<3) // This bit masks, when set, the Interrupt bit: X…
55418 … (0x1<<4) // This bit masks, when set, the Interrupt bit: X…
55420 … (0x1<<5) // This bit masks, when set, the Interrupt bit: X…
55425 …R (0x1<<1) // There is a probl…
55426 …YLD_REG_INT_STS_WR_LD_HDR_ERR_SHIFT 1
55427 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55429 … (0x1<<3) // Mini cache error - meaning that A load …
55431 … (0x1<<4) // Mini cache error - meaning that A load …
55438 …RR (0x1<<1) // There is a probl…
55439 …YLD_REG_INT_STS_CLR_LD_HDR_ERR_SHIFT 1
55440 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55442 … (0x1<<3) // Mini cache error - meaning that A load …
55444 … (0x1<<4) // Mini cache error - meaning that A load …
55449 … (0x1<<0) // This bit masks, when set, the Parity bit: XY…
55451 … (0x1<<1) // This bit masks, when set, the Parity bi…
55452 …YLD_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_E5_SHIFT 1
55453 … (0x1<<2) // This bit masks, when set, the Parity bit: XY…
55455 … (0x1<<3) // This bit masks, when set, the Parity bit: XY…
55457 … (0x1<<4) // This bit masks, when set, the Parity bit: XY…
55459 … (0x1<<5) // This bit masks, when set, the Parity bit: XY…
55461 … (0x1<<7) // This bit masks, when set, the Parity bit: XY…
55463 … (0x1<<6) // This bit masks, when set, the Parity bit: XY…
55465 … (0x1<<7) // This bit masks, when set, the Parity bit: XY…
55467 … (0x1<<8) // This bit masks, when set, the Parity bit: XY…
55469 … (0x1<<6) // This bit masks, when set, the Parity bit: XY…
55471 … (0x1<<9) // This bit masks, when set, the Parity bit: XY…
55473 … (0x1<<10) // This bit masks, when set, the Parity bit: XY…
55475 … (0x1<<5) // This bit masks, when set, the Parity bit: XY…
55477 … (0x1<<11) // This bit masks, when set, the Parity bit: XY…
55479 … (0x1<<4) // This bit masks, when set, the Parity bit: XY…
55481 … (0x1<<12) // This bit masks, when set, the Parity bit: XY…
55483 … (0x1<<8) // This bit masks, when set, the Parity bit: XY…
55485 … (0x1<<13) // This bit masks, when set, the Parity bit: XY…
55487 … (0x1<<14) // This bit masks, when set, the Parity bit: XY…
55489 … (0x1<<0) // This bit masks, when set, the Parity bit: XY…
55491 … (0x1<<1) // This bit masks, when set, the Parity bi…
55492 …YLD_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_BB_K2_SHIFT 1
55496 …012_I_ECC_EN_E5 (0x1<<1) // Enable ECC for m…
55497 …YLD_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN_E5_SHIFT 1
55500 …006_I_ECC_EN_BB_K2 (0x1<<1) // Enable ECC for m…
55501 …YLD_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN_BB_K2_SHIFT 1
55503 …_E5 (0x1<<0) // Set parity only for memory ecc inst…
55505 …_ECC_PRTY_E5 (0x1<<1) // Set parity only for memory…
55506 …YLD_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY_E5_SHIFT 1
55507 …_BB_K2 (0x1<<0) // Set parity only for memory ecc inst…
55509 …_ECC_PRTY_BB_K2 (0x1<<1) // Set parity only for memory…
55510 …YLD_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY_BB_K2_SHIFT 1
55514 …TED_0_MEM012_I_ECC_CORRECT_E5 (0x1<<1) // Record if a corr…
55515 …YLD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT_E5_SHIFT 1
55518 …TED_0_MEM006_I_ECC_CORRECT_BB_K2 (0x1<<1) // Record if a corr…
55519 …YLD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT_BB_K2_SHIFT 1
55521 … 0x4c0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
55523 … 0x4c0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
55528 …NORE_CM_AGG_MSG_E5 (0x1<<1) // indicates not to…
55529 …YLD_REG_L2MA_AGGR_CONFIG1_IGNORE_CM_AGG_MSG_E5_SHIFT 1
55530 … (0x1<<2) // defines that only back-to-back aggregatio…
55549 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
55551 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
55553 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
55555 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
55558 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
55560 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
55562 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
55564 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
55567 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
55569 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
55571 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
55573 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
55576 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
55578 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
55580 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
55582 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
55618 … 0x4c0924UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55619 … 0x4c0928UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55620 … 0x4c092cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55621 … 0x4c0930UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55622 … 0x4c0934UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55623 … 0x4c0938UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55624 … 0x4c093cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55625 … 0x4c0940UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55626 … 0x4c0944UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
55627 … 0x4c0948UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
55628 … 0x4c094cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
55629 … 0x4c0950UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
55630 … 0x4c0954UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
55631 … 0x4c0958UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
55632 … 0x4c095cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
55633 … 0x4c0960UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
55634 … 0x4c0964UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55635 … 0x4c0968UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55636 … 0x4c096cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55637 … 0x4c0970UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55638 … 0x4c0974UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55639 … 0x4c0978UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55640 … 0x4c097cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55641 … 0x4c0980UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55642 … 0x4c0984UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55643 … 0x4c0988UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55644 … 0x4c098cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55645 … 0x4c0990UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55646 … 0x4c0994UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55647 … 0x4c0998UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55648 … 0x4c099cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55649 … 0x4c09a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55651 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
55653 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
55655 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
55657 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
55660 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
55662 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
55664 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
55666 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
55669 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
55671 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
55673 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
55675 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
55678 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
55680 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
55682 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
55684 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
55723 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
55725 … (0x1<<1) // indication if to include the flow-ID in the stream…
55726 …YLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1_E5_SHIFT 1
55727 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
55729 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
55731 … (0x1f<<4) // offset of the flow-ID, in 32b units, fro…
55733 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
55735 … (0x1f<<14) // offset of the flow-ID, in 32b units, fro…
55737 … (0x1f<<19) // offset of the flow-ID, in 32b units, fro…
55742 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 1.
55751 … (0xf<<4) // the maximal number of children in a specific aggregation. for set 1.
55758 … (0xff<<0) // The value by which to increment the event-ID in case of success…
55760 …xff<<8) // The value by which to increment the event-ID in case of successful aggregation. for set…
55762 … (0xff<<16) // The value by which to increment the event-ID in case of success…
55764 … (0xff<<24) // The value by which to increment the event-ID in case of success…
55766 … 0x4c09d4UL //Access:RW DataWidth:0xc // maximum loader size in 256 bit words
55767 …Width:0x2 // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_st…
55768 …Width:0x2 // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_st…
55769 … //Access:RW DataWidth:0x2 // The weight of queue 1 at the WRR arbiteration, in case its bit …
55770 … //Access:RW DataWidth:0x2 // The weight of queue 1 at the WRR arbiteration, in case its bit …
55771 …Width:0x2 // The weight of queue 2 at the WRR arbiteration, in case its bit is reset at scbd_st…
55772 …Width:0x2 // The weight of queue 3 at the WRR arbiteration, in case its bit is reset at scbd_st…
55774 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
55775 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
55776 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
55777 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
55786 …c8000UL //Access:RW DataWidth:0x4 // Each bit indicates if the current queue ahs a strict pri…
55787 …Width:0x2 // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_st…
55788 … //Access:RW DataWidth:0x2 // The weight of queue 1 at the WRR arbiteration, in case its bit …
55800 …c8038UL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 1
55805 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 1
55811 …dth:0x20 // Logging in case of minicache failure.bits 31:0 CID Valid only if bit 13 in ld_cid_mi…
55812 …dth:0x20 // Logging in case of minicache failure.bits 31:0 TID Valid only if bit 13 in ld_tid_mi…
55813 … // Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_c…
55814 … // Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_t…
55815 …th:0x4 // Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags com…
55816 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55817 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55818 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55819 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55820 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55821 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55822 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55823 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55824 …0x4c8098UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55825 …0x4c809cUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55826 …0x4c80a0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55827 …0x4c80a4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55832 …bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message wi…
55833 …//Access:R DataWidth:0x20 // Logging register for long message error: bit 0:3 Segment message…
55839 …B_K2 (0x1<<1) // There is a probl…
55840 …ULD_REG_INT_STS_LD_HDR_ERR_BB_K2_SHIFT 1
55841 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55843 … (0x1<<3) // Mini cache error - meaning that A load …
55845 … (0x1<<4) // Mini cache error - meaning that A load …
55850 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Y…
55852 … (0x1<<1) // This bit masks, when set, the Interrupt …
55853 …ULD_REG_INT_MASK_LD_HDR_ERR_BB_K2_SHIFT 1
55854 … (0x1<<2) // This bit masks, when set, the Interrupt bit: Y…
55856 … (0x1<<3) // This bit masks, when set, the Interrupt bit: Y…
55858 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Y…
55860 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Y…
55865 …R_BB_K2 (0x1<<1) // There is a probl…
55866 …ULD_REG_INT_STS_WR_LD_HDR_ERR_BB_K2_SHIFT 1
55867 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55869 … (0x1<<3) // Mini cache error - meaning that A load …
55871 … (0x1<<4) // Mini cache error - meaning that A load …
55878 …RR_BB_K2 (0x1<<1) // There is a probl…
55879 …ULD_REG_INT_STS_CLR_LD_HDR_ERR_BB_K2_SHIFT 1
55880 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55882 … (0x1<<3) // Mini cache error - meaning that A load …
55884 … (0x1<<4) // Mini cache error - meaning that A load …
55889 … (0x1<<0) // This bit masks, when set, the Parity bit: YU…
55891 … (0x1<<1) // This bit masks, when set, the Parity bi…
55892 …ULD_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT 1
55893 … (0x1<<2) // This bit masks, when set, the Parity bit: YU…
55895 … (0x1<<3) // This bit masks, when set, the Parity bit: YU…
55897 … (0x1<<4) // This bit masks, when set, the Parity bit: YU…
55899 … (0x1<<5) // This bit masks, when set, the Parity bit: YU…
55902 … 0x4c8400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
55904 … 0x4c8800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
55907 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
55908 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
55909 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
55910 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
55919 …d0000UL //Access:RW DataWidth:0x4 // Each bit indicates if the current queue ahs a strict pri…
55925 …the BRB read response buffer. The slot size would be the BRB-response-buffer-size/number-of-slots.…
55928 …data returning from the BRB is swapped. meaning that bytes 0-3 is swapped with bytes 4-7 in …
55929 …30UL //Access:RW DataWidth:0x3 // Max credit number for the BRB request-resonse interface::/M…
55934 …d0044UL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 1
55939 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 1
55947 …dth:0x20 // Logging in case of minicache failure.bits 31:0 CID Valid only if bit 13 in ld_cid_mi…
55948 …dth:0x20 // Logging in case of minicache failure.bits 31:0 TID Valid only if bit 13 in ld_tid_mi…
55949 … // Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_c…
55950 … // Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_t…
55951 …th:0x4 // Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags com…
55952 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55953 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55954 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55955 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55956 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55957 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55958 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55959 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55960 …0x4d00acUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55961 …0x4d00b0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55962 …0x4d00b4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55963 …0x4d00b8UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55968 …bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message wi…
55969 …//Access:R DataWidth:0x20 // Logging register for long message error: bit 0:3 Segment message…
55975 … (0x1<<1) // There is a probl…
55976 …MLD_REG_INT_STS_LD_HDR_ERR_SHIFT 1
55977 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55979 … (0x1<<3) // Mini cache error - meaning that A load …
55981 … (0x1<<4) // Mini cache error - meaning that A load …
55986 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
55988 … (0x1<<1) // This bit masks, when set, the Interrupt …
55989 …MLD_REG_INT_MASK_LD_HDR_ERR_SHIFT 1
55990 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
55992 … (0x1<<3) // This bit masks, when set, the Interrupt bit: T…
55994 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
55996 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
56001 …R (0x1<<1) // There is a probl…
56002 …MLD_REG_INT_STS_WR_LD_HDR_ERR_SHIFT 1
56003 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56005 … (0x1<<3) // Mini cache error - meaning that A load …
56007 … (0x1<<4) // Mini cache error - meaning that A load …
56014 …RR (0x1<<1) // There is a probl…
56015 …MLD_REG_INT_STS_CLR_LD_HDR_ERR_SHIFT 1
56016 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56018 … (0x1<<3) // Mini cache error - meaning that A load …
56020 … (0x1<<4) // Mini cache error - meaning that A load …
56025 … (0x1<<0) // This bit masks, when set, the Parity bit: TM…
56027 … (0x1<<1) // This bit masks, when set, the Parity bi…
56028 …MLD_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_SHIFT 1
56029 … (0x1<<2) // This bit masks, when set, the Parity bit: TM…
56031 … (0x1<<3) // This bit masks, when set, the Parity bit: TM…
56033 … (0x1<<4) // This bit masks, when set, the Parity bit: TM…
56035 … (0x1<<5) // This bit masks, when set, the Parity bit: TM…
56037 … (0x1<<4) // This bit masks, when set, the Parity bit: TM…
56039 … (0x1<<6) // This bit masks, when set, the Parity bit: TM…
56041 … (0x1<<7) // This bit masks, when set, the Parity bit: TM…
56043 … (0x1<<6) // This bit masks, when set, the Parity bit: TM…
56045 … (0x1<<8) // This bit masks, when set, the Parity bit: TM…
56047 … (0x1<<9) // This bit masks, when set, the Parity bit: TM…
56049 … (0x1<<10) // This bit masks, when set, the Parity bit: TM…
56051 … (0x1<<11) // This bit masks, when set, the Parity bit: TM…
56053 … (0x1<<12) // This bit masks, when set, the Parity bit: TM…
56055 … (0x1<<5) // This bit masks, when set, the Parity bit: TM…
56057 … (0x1<<13) // This bit masks, when set, the Parity bit: TM…
56059 … (0x1<<0) // This bit masks, when set, the Parity bit: TM…
56064 …002_I_ECC_EN (0x1<<1) // Enable ECC for m…
56065 …MLD_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_SHIFT 1
56069 …_E5 (0x1<<0) // Set parity only for memory ecc inst…
56071 …_ECC_PRTY (0x1<<1) // Set parity only for memory…
56072 …MLD_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_SHIFT 1
56073 …_BB_K2 (0x1<<0) // Set parity only for memory ecc inst…
56078 …TED_0_MEM002_I_ECC_CORRECT (0x1<<1) // Record if a corr…
56079 …MLD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_SHIFT 1
56083 … 0x4d0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
56085 … 0x4d0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
56090 …NORE_CM_AGG_MSG_E5 (0x1<<1) // indicates not to…
56091 …MLD_REG_L2MA_AGGR_CONFIG1_IGNORE_CM_AGG_MSG_E5_SHIFT 1
56092 … (0x1<<2) // defines that only back-to-back aggregatio…
56111 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
56113 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
56115 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
56117 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
56120 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
56122 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
56124 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
56126 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
56129 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
56131 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
56133 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
56135 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
56138 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
56140 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
56142 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
56144 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
56180 … 0x4d0924UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56181 … 0x4d0928UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56182 … 0x4d092cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56183 … 0x4d0930UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56184 … 0x4d0934UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56185 … 0x4d0938UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56186 … 0x4d093cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56187 … 0x4d0940UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56188 … 0x4d0944UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
56189 … 0x4d0948UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
56190 … 0x4d094cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
56191 … 0x4d0950UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
56192 … 0x4d0954UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
56193 … 0x4d0958UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
56194 … 0x4d095cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
56195 … 0x4d0960UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
56196 … 0x4d0964UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56197 … 0x4d0968UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56198 … 0x4d096cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56199 … 0x4d0970UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56200 … 0x4d0974UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56201 … 0x4d0978UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56202 … 0x4d097cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56203 … 0x4d0980UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56204 … 0x4d0984UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56205 … 0x4d0988UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56206 … 0x4d098cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56207 … 0x4d0990UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56208 … 0x4d0994UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56209 … 0x4d0998UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56210 … 0x4d099cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56211 … 0x4d09a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56213 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
56215 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
56217 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
56219 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
56222 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
56224 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
56226 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
56228 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
56231 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
56233 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
56235 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
56237 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
56240 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
56242 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
56244 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
56246 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
56285 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
56287 … (0x1<<1) // indication if to include the flow-ID in the stream…
56288 …MLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1_E5_SHIFT 1
56289 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
56291 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
56293 … (0x1f<<4) // offset of the flow-ID, in 32b units, fro…
56295 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
56297 … (0x1f<<14) // offset of the flow-ID, in 32b units, fro…
56299 … (0x1f<<19) // offset of the flow-ID, in 32b units, fro…
56304 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 1.
56313 … (0xf<<4) // the maximal number of children in a specific aggregation. for set 1.
56320 … (0xff<<0) // The value by which to increment the event-ID in case of success…
56322 …xff<<8) // The value by which to increment the event-ID in case of successful aggregation. for set…
56324 … (0xff<<16) // The value by which to increment the event-ID in case of success…
56326 … (0xff<<24) // The value by which to increment the event-ID in case of success…
56328 … 0x4d09d4UL //Access:RW DataWidth:0xc // maximum loader size in 256 bit words
56329 …Width:0x2 // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_st…
56330 …Width:0x2 // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_st…
56331 … //Access:RW DataWidth:0x2 // The weight of queue 1 at the WRR arbiteration, in case its bit …
56332 … //Access:RW DataWidth:0x2 // The weight of queue 1 at the WRR arbiteration, in case its bit …
56333 …Width:0x2 // The weight of queue 2 at the WRR arbiteration, in case its bit is reset at scbd_st…
56334 …Width:0x2 // The weight of queue 3 at the WRR arbiteration, in case its bit is reset at scbd_st…
56336 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
56337 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
56338 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
56339 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
56348 …e0000UL //Access:RW DataWidth:0x4 // Each bit indicates if the current queue ahs a strict pri…
56349 …Width:0x2 // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_st…
56350 … //Access:RW DataWidth:0x2 // The weight of queue 1 at the WRR arbiteration, in case its bit …
56351 …Width:0x2 // The weight of queue 2 at the WRR arbiteration, in case its bit is reset at scbd_st…
56352 …Width:0x2 // The weight of queue 3 at the WRR arbiteration, in case its bit is reset at scbd_st…
56353 … 0x4e0014UL //Access:RW DataWidth:0x4 // Log 2 of the BD size in bytes - 2:BD size is 4bytes;…
56355 …0x4e001cUL //Access:RW DataWidth:0x4 // Log 2 of the SGE size in bytes - 2:SGE size is 4bytes…
56371 …e005cUL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 1
56376 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 1
56387 …dth:0x20 // Logging in case of minicache failure.bits 31:0 CID Valid only if bit 13 in ld_cid_mi…
56388 …dth:0x20 // Logging in case of minicache failure.bits 31:0 TID Valid only if bit 13 in ld_tid_mi…
56389 … // Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_c…
56390 … // Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_t…
56391 …th:0x4 // Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags com…
56392 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56393 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56394 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56395 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56396 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56397 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56398 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56399 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56400 …0x4e00d0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56401 …0x4e00d4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56402 …0x4e00d8UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56403 …0x4e00dcUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56408 …bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message wi…
56409 …//Access:R DataWidth:0x20 // Logging register for long message error: bit 0:3 Segment message…
56415 … (0x1<<1) // There is a probl…
56416 …ULD_REG_INT_STS_LD_HDR_ERR_SHIFT 1
56417 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56419 … (0x1<<3) // Mini cache error - meaning that A load …
56421 … (0x1<<4) // Mini cache error - meaning that A load …
56426 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
56428 … (0x1<<1) // This bit masks, when set, the Interrupt …
56429 …ULD_REG_INT_MASK_LD_HDR_ERR_SHIFT 1
56430 … (0x1<<2) // This bit masks, when set, the Interrupt bit: M…
56432 … (0x1<<3) // This bit masks, when set, the Interrupt bit: M…
56434 … (0x1<<4) // This bit masks, when set, the Interrupt bit: M…
56436 … (0x1<<5) // This bit masks, when set, the Interrupt bit: M…
56441 …R (0x1<<1) // There is a probl…
56442 …ULD_REG_INT_STS_WR_LD_HDR_ERR_SHIFT 1
56443 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56445 … (0x1<<3) // Mini cache error - meaning that A load …
56447 … (0x1<<4) // Mini cache error - meaning that A load …
56454 …RR (0x1<<1) // There is a probl…
56455 …ULD_REG_INT_STS_CLR_LD_HDR_ERR_SHIFT 1
56456 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56458 … (0x1<<3) // Mini cache error - meaning that A load …
56460 … (0x1<<4) // Mini cache error - meaning that A load …
56465 … (0x1<<0) // This bit masks, when set, the Parity bit: MU…
56467 … (0x1<<1) // This bit masks, when set, the Parity bi…
56468 …ULD_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_SHIFT 1
56469 … (0x1<<2) // This bit masks, when set, the Parity bit: MU…
56471 … (0x1<<3) // This bit masks, when set, the Parity bit: MU…
56473 … (0x1<<4) // This bit masks, when set, the Parity bit: MU…
56475 … (0x1<<5) // This bit masks, when set, the Parity bit: MU…
56477 … (0x1<<6) // This bit masks, when set, the Parity bit: MU…
56479 … (0x1<<7) // This bit masks, when set, the Parity bit: MU…
56481 … (0x1<<9) // This bit masks, when set, the Parity bit: MU…
56483 … (0x1<<8) // This bit masks, when set, the Parity bit: MU…
56485 … (0x1<<9) // This bit masks, when set, the Parity bit: MU…
56487 … (0x1<<8) // This bit masks, when set, the Parity bit: MU…
56489 … (0x1<<10) // This bit masks, when set, the Parity bit: MU…
56491 … (0x1<<11) // This bit masks, when set, the Parity bit: MU…
56493 … (0x1<<7) // This bit masks, when set, the Parity bit: MU…
56495 … (0x1<<12) // This bit masks, when set, the Parity bit: MU…
56497 … (0x1<<6) // This bit masks, when set, the Parity bit: MU…
56499 … (0x1<<13) // This bit masks, when set, the Parity bit: MU…
56501 … (0x1<<14) // This bit masks, when set, the Parity bit: MU…
56503 … (0x1<<15) // This bit masks, when set, the Parity bit: MU…
56505 … (0x1<<0) // This bit masks, when set, the Parity bit: MU…
56507 … (0x1<<2) // This bit masks, when set, the Parity bit: MU…
56509 … (0x1<<3) // This bit masks, when set, the Parity bit: MU…
56514 …001_I_ECC_EN (0x1<<1) // Enable ECC for m…
56515 …ULD_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_SHIFT 1
56527 …_E5 (0x1<<0) // Set parity only for memory ecc inst…
56529 …_ECC_PRTY (0x1<<1) // Set parity only for memory…
56530 …ULD_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_SHIFT 1
56531 …_E5 (0x1<<2) // Set parity only for memory ecc inst…
56533 …_E5 (0x1<<3) // Set parity only for memory ecc inst…
56535 …_BB_K2 (0x1<<0) // Set parity only for memory ecc inst…
56537 …_BB_K2 (0x1<<2) // Set parity only for memory ecc inst…
56539 …_BB_K2 (0x1<<3) // Set parity only for memory ecc inst…
56544 …TED_0_MEM001_I_ECC_CORRECT (0x1<<1) // Record if a corr…
56545 …ULD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_SHIFT 1
56557 … 0x4e0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
56559 … 0x4e0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
56561 … 0x4e0c00UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue2 - Debug access::/TMLD_…
56563 … 0x4e1000UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue3 - Debug access::/TMLD_…
56568 …NORE_CM_AGG_MSG_E5 (0x1<<1) // indicates not to…
56569 …ULD_REG_L2MA_AGGR_CONFIG1_IGNORE_CM_AGG_MSG_E5_SHIFT 1
56570 … (0x1<<2) // defines that only back-to-back aggregatio…
56589 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
56591 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
56593 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
56595 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
56598 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
56600 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
56602 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
56604 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
56607 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
56609 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
56611 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
56613 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
56616 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
56618 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
56620 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
56622 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
56658 … 0x4e1424UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56659 … 0x4e1428UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56660 … 0x4e142cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56661 … 0x4e1430UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56662 … 0x4e1434UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56663 … 0x4e1438UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56664 … 0x4e143cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56665 … 0x4e1440UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56666 … 0x4e1444UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
56667 … 0x4e1448UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
56668 … 0x4e144cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
56669 … 0x4e1450UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
56670 … 0x4e1454UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
56671 … 0x4e1458UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
56672 … 0x4e145cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
56673 … 0x4e1460UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
56674 … 0x4e1464UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56675 … 0x4e1468UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56676 … 0x4e146cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56677 … 0x4e1470UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56678 … 0x4e1474UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56679 … 0x4e1478UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56680 … 0x4e147cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56681 … 0x4e1480UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56682 … 0x4e1484UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56683 … 0x4e1488UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56684 … 0x4e148cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56685 … 0x4e1490UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56686 … 0x4e1494UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56687 … 0x4e1498UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56688 … 0x4e149cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56689 … 0x4e14a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56691 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
56693 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
56695 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
56697 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
56700 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
56702 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
56704 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
56706 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
56709 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
56711 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
56713 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
56715 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
56718 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
56720 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
56722 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
56724 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
56763 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
56765 … (0x1<<1) // indication if to include the flow-ID in the stream…
56766 …ULD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1_E5_SHIFT 1
56767 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
56769 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
56771 … (0x1f<<4) // offset of the flow-ID, in 32b units, fro…
56773 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
56775 … (0x1f<<14) // offset of the flow-ID, in 32b units, fro…
56777 … (0x1f<<19) // offset of the flow-ID, in 32b units, fro…
56782 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 1.
56791 … (0xf<<4) // the maximal number of children in a specific aggregation. for set 1.
56798 … (0xff<<0) // The value by which to increment the event-ID in case of success…
56800 …xff<<8) // The value by which to increment the event-ID in case of successful aggregation. for set…
56802 … (0xff<<16) // The value by which to increment the event-ID in case of success…
56804 … (0xff<<24) // The value by which to increment the event-ID in case of success…
56806 … 0x4e14d4UL //Access:RW DataWidth:0xc // maximum loader size in 256 bit words
56809 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
56810 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
56811 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
56812 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
56819 …- Fields order[Link page]: [180] Next address valid; [179:178] Endianity bits; [177] No snoop flag…
56823 …- Fields order[Link page]: [180] Next address valid; [179:178] Endianity bits; [177] No snoop flag…
56832 …ERROR (0x1<<1) // FIFO error in de…
56833 …IG_REG_INT_STS_0_DEBUG_FIFO_ERROR_SHIFT 1
56859 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
56861 … (0x1<<1) // This bit masks, when set, the Interrupt …
56862 …IG_REG_INT_MASK_0_DEBUG_FIFO_ERROR_SHIFT 1
56863 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
56865 … (0x1<<3) // This bit masks, when set, the Interrupt bit: N…
56867 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
56869 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
56871 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
56873 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
56875 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
56877 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
56879 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
56881 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
56883 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
56885 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
56890 …FO_ERROR (0x1<<1) // FIFO error in de…
56891 …IG_REG_INT_STS_WR_0_DEBUG_FIFO_ERROR_SHIFT 1
56919 …IFO_ERROR (0x1<<1) // FIFO error in de…
56920 …IG_REG_INT_STS_CLR_0_DEBUG_FIFO_ERROR_SHIFT 1
56948 …ROR (0x1<<1) // Error in the TX …
56949 …IG_REG_INT_STS_1_TX_SOPQ1_ERROR_SHIFT 1
57011 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
57013 … (0x1<<1) // This bit masks, when set, the Interrupt …
57014 …IG_REG_INT_MASK_1_TX_SOPQ1_ERROR_SHIFT 1
57015 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
57017 … (0x1<<3) // This bit masks, when set, the Interrupt bit: N…
57019 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
57021 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
57023 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
57025 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
57027 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
57029 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
57031 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
57033 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
57035 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
57037 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
57039 … (0x1<<14) // This bit masks, when set, the Interrupt bit: N…
57041 … (0x1<<15) // This bit masks, when set, the Interrupt bit: N…
57043 … (0x1<<16) // This bit masks, when set, the Interrupt bit: N…
57045 … (0x1<<17) // This bit masks, when set, the Interrupt bit: N…
57047 … (0x1<<18) // This bit masks, when set, the Interrupt bit: N…
57049 … (0x1<<19) // This bit masks, when set, the Interrupt bit: N…
57051 … (0x1<<20) // This bit masks, when set, the Interrupt bit: N…
57053 … (0x1<<21) // This bit masks, when set, the Interrupt bit: N…
57055 … (0x1<<22) // This bit masks, when set, the Interrupt bit: N…
57057 … (0x1<<23) // This bit masks, when set, the Interrupt bit: N…
57059 … (0x1<<24) // This bit masks, when set, the Interrupt bit: N…
57061 … (0x1<<25) // This bit masks, when set, the Interrupt bit: N…
57063 … (0x1<<26) // This bit masks, when set, the Interrupt bit: N…
57065 … (0x1<<27) // This bit masks, when set, the Interrupt bit: N…
57067 … (0x1<<28) // This bit masks, when set, the Interrupt bit: N…
57069 … (0x1<<29) // This bit masks, when set, the Interrupt bit: N…
57071 … (0x1<<30) // This bit masks, when set, the Interrupt bit: N…
57073 … (0x1<<31) // This bit masks, when set, the Interrupt bit: N…
57078 …_ERROR (0x1<<1) // Error in the TX …
57079 …IG_REG_INT_STS_WR_1_TX_SOPQ1_ERROR_SHIFT 1
57143 …1_ERROR (0x1<<1) // Error in the TX …
57144 …IG_REG_INT_STS_CLR_1_TX_SOPQ1_ERROR_SHIFT 1
57206 … (0x1<<0) // Error in the pure-loopback SOPQ.
57208 …FO_ERROR (0x1<<1) // Error in RX MAC …
57209 …IG_REG_INT_STS_2_P0_RX_MACFIFO_ERROR_SHIFT 1
57251 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
57253 … (0x1<<1) // This bit masks, when set, the Interrupt …
57254 …IG_REG_INT_MASK_2_P0_RX_MACFIFO_ERROR_SHIFT 1
57255 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
57257 … (0x1<<3) // This bit masks, when set, the Interrupt bit: N…
57259 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
57261 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
57263 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
57265 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
57267 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
57269 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
57271 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
57273 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
57275 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
57277 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
57279 … (0x1<<14) // This bit masks, when set, the Interrupt bit: N…
57281 … (0x1<<15) // This bit masks, when set, the Interrupt bit: N…
57283 … (0x1<<16) // This bit masks, when set, the Interrupt bit: N…
57285 … (0x1<<17) // This bit masks, when set, the Interrupt bit: N…
57287 … (0x1<<18) // This bit masks, when set, the Interrupt bit: N…
57289 … (0x1<<19) // This bit masks, when set, the Interrupt bit: N…
57291 … (0x1<<20) // This bit masks, when set, the Interrupt bit: N…
57293 … (0x1<<21) // This bit masks, when set, the Interrupt bit: N…
57296 … (0x1<<0) // Error in the pure-loopback SOPQ.
57298 …CFIFO_ERROR (0x1<<1) // Error in RX MAC …
57299 …IG_REG_INT_STS_WR_2_P0_RX_MACFIFO_ERROR_SHIFT 1
57341 … (0x1<<0) // Error in the pure-loopback SOPQ.
57343 …ACFIFO_ERROR (0x1<<1) // Error in RX MAC …
57344 …IG_REG_INT_STS_CLR_2_P0_RX_MACFIFO_ERROR_SHIFT 1
57388 …E_TOO_LONG_INT (0x1<<1) // Triggered by TC …
57389 …IG_REG_INT_STS_3_P0_TC0_PAUSE_TOO_LONG_INT_SHIFT 1
57423 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
57425 … (0x1<<1) // This bit masks, when set, the Interrupt …
57426 …IG_REG_INT_MASK_3_P0_TC0_PAUSE_TOO_LONG_INT_SHIFT 1
57427 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
57429 … (0x1<<3) // This bit masks, when set, the Interrupt bit: N…
57431 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
57433 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
57435 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
57437 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
57439 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
57441 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
57443 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
57445 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
57447 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
57449 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
57451 … (0x1<<14) // This bit masks, when set, the Interrupt bit: N…
57453 … (0x1<<15) // This bit masks, when set, the Interrupt bit: N…
57455 … (0x1<<16) // This bit masks, when set, the Interrupt bit: N…
57457 … (0x1<<17) // This bit masks, when set, the Interrupt bit: N…
57462 …AUSE_TOO_LONG_INT (0x1<<1) // Triggered by TC …
57463 …IG_REG_INT_STS_WR_3_P0_TC0_PAUSE_TOO_LONG_INT_SHIFT 1
57499 …PAUSE_TOO_LONG_INT (0x1<<1) // Triggered by TC …
57500 …IG_REG_INT_STS_CLR_3_P0_TC0_PAUSE_TOO_LONG_INT_SHIFT 1
57534 … (0x1<<0) // Error in the pure-loopback SOPQ.
57536 …FO_ERROR (0x1<<1) // Error in RX MAC …
57537 …IG_REG_INT_STS_4_P1_RX_MACFIFO_ERROR_SHIFT 1
57579 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
57581 … (0x1<<1) // This bit masks, when set, the Interrupt …
57582 …IG_REG_INT_MASK_4_P1_RX_MACFIFO_ERROR_SHIFT 1
57583 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
57585 … (0x1<<3) // This bit masks, when set, the Interrupt bit: N…
57587 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
57589 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
57591 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
57593 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
57595 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
57597 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
57599 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
57601 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
57603 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
57605 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
57607 … (0x1<<14) // This bit masks, when set, the Interrupt bit: N…
57609 … (0x1<<15) // This bit masks, when set, the Interrupt bit: N…
57611 … (0x1<<16) // This bit masks, when set, the Interrupt bit: N…
57613 … (0x1<<17) // This bit masks, when set, the Interrupt bit: N…
57615 … (0x1<<18) // This bit masks, when set, the Interrupt bit: N…
57617 … (0x1<<19) // This bit masks, when set, the Interrupt bit: N…
57619 … (0x1<<20) // This bit masks, when set, the Interrupt bit: N…
57621 … (0x1<<21) // This bit masks, when set, the Interrupt bit: N…
57624 … (0x1<<0) // Error in the pure-loopback SOPQ.
57626 …CFIFO_ERROR (0x1<<1) // Error in RX MAC …
57627 …IG_REG_INT_STS_WR_4_P1_RX_MACFIFO_ERROR_SHIFT 1
57669 … (0x1<<0) // Error in the pure-loopback SOPQ.
57671 …ACFIFO_ERROR (0x1<<1) // Error in RX MAC …
57672 …IG_REG_INT_STS_CLR_4_P1_RX_MACFIFO_ERROR_SHIFT 1
57716 …E_TOO_LONG_INT (0x1<<1) // Triggered by TC …
57717 …IG_REG_INT_STS_5_P1_TC0_PAUSE_TOO_LONG_INT_SHIFT 1
57751 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
57753 … (0x1<<1) // This bit masks, when set, the Interrupt …
57754 …IG_REG_INT_MASK_5_P1_TC0_PAUSE_TOO_LONG_INT_SHIFT 1
57755 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
57757 … (0x1<<3) // This bit masks, when set, the Interrupt bit: N…
57759 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
57761 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
57763 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
57765 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
57767 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
57769 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
57771 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
57773 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
57775 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
57777 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
57779 … (0x1<<14) // This bit masks, when set, the Interrupt bit: N…
57781 … (0x1<<15) // This bit masks, when set, the Interrupt bit: N…
57783 … (0x1<<16) // This bit masks, when set, the Interrupt bit: N…
57785 … (0x1<<17) // This bit masks, when set, the Interrupt bit: N…
57790 …AUSE_TOO_LONG_INT (0x1<<1) // Triggered by TC …
57791 …IG_REG_INT_STS_WR_5_P1_TC0_PAUSE_TOO_LONG_INT_SHIFT 1
57827 …PAUSE_TOO_LONG_INT (0x1<<1) // Triggered by TC …
57828 …IG_REG_INT_STS_CLR_5_P1_TC0_PAUSE_TOO_LONG_INT_SHIFT 1
57862 … (0x1<<0) // Error in the pure-loopback SOPQ.
57864 …FO_ERROR_K2_E5 (0x1<<1) // Error in RX MAC …
57865 …IG_REG_INT_STS_6_P2_RX_MACFIFO_ERROR_K2_E5_SHIFT 1
57907 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
57909 … (0x1<<1) // This bit masks, when set, the Interrupt …
57910 …IG_REG_INT_MASK_6_P2_RX_MACFIFO_ERROR_K2_E5_SHIFT 1
57911 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
57913 … (0x1<<3) // This bit masks, when set, the Interrupt bit: N…
57915 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
57917 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
57919 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
57921 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
57923 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
57925 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
57927 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
57929 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
57931 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
57933 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
57935 … (0x1<<14) // This bit masks, when set, the Interrupt bit: N…
57937 … (0x1<<15) // This bit masks, when set, the Interrupt bit: N…
57939 … (0x1<<16) // This bit masks, when set, the Interrupt bit: N…
57941 … (0x1<<17) // This bit masks, when set, the Interrupt bit: N…
57943 … (0x1<<18) // This bit masks, when set, the Interrupt bit: N…
57945 … (0x1<<19) // This bit masks, when set, the Interrupt bit: N…
57947 … (0x1<<20) // This bit masks, when set, the Interrupt bit: N…
57949 … (0x1<<21) // This bit masks, when set, the Interrupt bit: N…
57952 …_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
57954 …CFIFO_ERROR_K2_E5 (0x1<<1) // Error in RX MAC …
57955 …IG_REG_INT_STS_WR_6_P2_RX_MACFIFO_ERROR_K2_E5_SHIFT 1
57997 …2_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
57999 …ACFIFO_ERROR_K2_E5 (0x1<<1) // Error in RX MAC …
58000 …IG_REG_INT_STS_CLR_6_P2_RX_MACFIFO_ERROR_K2_E5_SHIFT 1
58044 …E_TOO_LONG_INT_K2_E5 (0x1<<1) // Triggered by TC …
58045 …IG_REG_INT_STS_7_P2_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 1
58079 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
58081 … (0x1<<1) // This bit masks, when set, the Interrupt …
58082 …IG_REG_INT_MASK_7_P2_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 1
58083 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
58085 … (0x1<<3) // This bit masks, when set, the Interrupt bit: N…
58087 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
58089 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
58091 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
58093 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
58095 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
58097 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
58099 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
58101 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
58103 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
58105 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
58107 … (0x1<<14) // This bit masks, when set, the Interrupt bit: N…
58109 … (0x1<<15) // This bit masks, when set, the Interrupt bit: N…
58111 … (0x1<<16) // This bit masks, when set, the Interrupt bit: N…
58113 … (0x1<<17) // This bit masks, when set, the Interrupt bit: N…
58118 …AUSE_TOO_LONG_INT_K2_E5 (0x1<<1) // Triggered by TC …
58119 …IG_REG_INT_STS_WR_7_P2_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 1
58155 …PAUSE_TOO_LONG_INT_K2_E5 (0x1<<1) // Triggered by TC …
58156 …IG_REG_INT_STS_CLR_7_P2_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 1
58190 … (0x1<<0) // Error in the pure-loopback SOPQ.
58192 …FO_ERROR_K2_E5 (0x1<<1) // Error in RX MAC …
58193 …IG_REG_INT_STS_8_P3_RX_MACFIFO_ERROR_K2_E5_SHIFT 1
58235 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
58237 … (0x1<<1) // This bit masks, when set, the Interrupt …
58238 …IG_REG_INT_MASK_8_P3_RX_MACFIFO_ERROR_K2_E5_SHIFT 1
58239 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
58241 … (0x1<<3) // This bit masks, when set, the Interrupt bit: N…
58243 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
58245 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
58247 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
58249 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
58251 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
58253 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
58255 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
58257 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
58259 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
58261 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
58263 … (0x1<<14) // This bit masks, when set, the Interrupt bit: N…
58265 … (0x1<<15) // This bit masks, when set, the Interrupt bit: N…
58267 … (0x1<<16) // This bit masks, when set, the Interrupt bit: N…
58269 … (0x1<<17) // This bit masks, when set, the Interrupt bit: N…
58271 … (0x1<<18) // This bit masks, when set, the Interrupt bit: N…
58273 … (0x1<<19) // This bit masks, when set, the Interrupt bit: N…
58275 … (0x1<<20) // This bit masks, when set, the Interrupt bit: N…
58277 … (0x1<<21) // This bit masks, when set, the Interrupt bit: N…
58280 …_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
58282 …CFIFO_ERROR_K2_E5 (0x1<<1) // Error in RX MAC …
58283 …IG_REG_INT_STS_WR_8_P3_RX_MACFIFO_ERROR_K2_E5_SHIFT 1
58325 …2_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
58327 …ACFIFO_ERROR_K2_E5 (0x1<<1) // Error in RX MAC …
58328 …IG_REG_INT_STS_CLR_8_P3_RX_MACFIFO_ERROR_K2_E5_SHIFT 1
58372 …E_TOO_LONG_INT_K2_E5 (0x1<<1) // Triggered by TC …
58373 …IG_REG_INT_STS_9_P3_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 1
58407 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
58409 … (0x1<<1) // This bit masks, when set, the Interrupt …
58410 …IG_REG_INT_MASK_9_P3_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 1
58411 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
58413 … (0x1<<3) // This bit masks, when set, the Interrupt bit: N…
58415 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
58417 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
58419 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
58421 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
58423 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
58425 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
58427 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
58429 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
58431 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
58433 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
58435 … (0x1<<14) // This bit masks, when set, the Interrupt bit: N…
58437 … (0x1<<15) // This bit masks, when set, the Interrupt bit: N…
58439 … (0x1<<16) // This bit masks, when set, the Interrupt bit: N…
58441 … (0x1<<17) // This bit masks, when set, the Interrupt bit: N…
58446 …AUSE_TOO_LONG_INT_K2_E5 (0x1<<1) // Triggered by TC …
58447 …IG_REG_INT_STS_WR_9_P3_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 1
58483 …PAUSE_TOO_LONG_INT_K2_E5 (0x1<<1) // Triggered by TC …
58484 …IG_REG_INT_STS_CLR_9_P3_TC0_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 1
58519 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
58524 …ERROR_E5 (0x1<<1) // Error in the TX …
58525 …IG_REG_INT_STS_10_TX_SOPQ17_ERROR_E5_SHIFT 1
58555 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
58557 … (0x1<<1) // This bit masks, when set, the Interrupt …
58558 …IG_REG_INT_MASK_10_TX_SOPQ17_ERROR_E5_SHIFT 1
58559 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
58561 … (0x1<<3) // This bit masks, when set, the Interrupt bit: N…
58563 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
58565 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
58567 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
58569 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
58571 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
58573 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
58575 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
58577 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
58579 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
58581 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
58583 … (0x1<<14) // This bit masks, when set, the Interrupt bit: N…
58585 … (0x1<<15) // This bit masks, when set, the Interrupt bit: N…
58590 …17_ERROR_E5 (0x1<<1) // Error in the TX …
58591 …IG_REG_INT_STS_WR_10_TX_SOPQ17_ERROR_E5_SHIFT 1
58623 …Q17_ERROR_E5 (0x1<<1) // Error in the TX …
58624 …IG_REG_INT_STS_CLR_10_TX_SOPQ17_ERROR_E5_SHIFT 1
58654 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
58656 … (0x1<<1) // This bit masks, when set, the Parity bi…
58657 …IG_REG_PRTY_MASK_H_0_MEM115_I_MEM_PRTY_E5_SHIFT 1
58658 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
58660 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
58662 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
58664 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
58666 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
58668 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
58670 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
58672 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
58674 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
58676 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
58678 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
58680 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
58682 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
58684 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
58686 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
58688 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
58690 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
58692 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
58694 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
58696 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
58698 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
58700 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
58702 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
58704 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
58706 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
58708 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
58710 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
58712 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
58714 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
58716 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
58718 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
58720 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
58722 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
58724 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
58726 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
58728 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
58730 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
58732 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
58734 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
58736 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
58738 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
58740 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
58742 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
58744 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
58746 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
58748 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
58750 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
58752 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
58754 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
58756 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
58758 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
58760 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
58762 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
58764 … (0x1<<1) // This bit masks, when set, the Parity bi…
58765 …IG_REG_PRTY_MASK_H_0_MEM103_I_MEM_PRTY_K2_SHIFT 1
58766 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
58768 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
58770 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
58772 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
58774 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
58776 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
58778 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
58780 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
58782 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
58784 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
58786 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
58788 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
58790 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
58792 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
58794 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
58796 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
58798 … (0x1<<1) // This bit masks, when set, the Parity bi…
58799 …IG_REG_PRTY_MASK_H_0_MEM052_I_MEM_PRTY_BB_SHIFT 1
58800 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
58802 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
58804 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
58806 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
58808 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
58810 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
58812 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
58814 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
58816 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
58818 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
58820 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
58822 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
58824 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
58826 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
58828 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
58830 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
58832 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
58834 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
58836 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
58838 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
58841 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
58843 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
58845 … (0x1<<1) // This bit masks, when set, the Parity bi…
58846 …IG_REG_PRTY_MASK_H_1_MEM073_I_MEM_PRTY_E5_SHIFT 1
58847 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
58849 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
58851 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
58853 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
58855 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
58857 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
58859 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
58861 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
58863 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
58865 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
58867 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
58869 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
58871 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
58873 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
58875 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
58877 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
58879 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
58881 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
58883 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
58885 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
58887 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
58889 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
58891 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
58893 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
58895 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
58897 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
58899 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
58901 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
58903 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
58905 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
58907 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
58909 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
58911 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
58913 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
58915 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
58917 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
58919 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
58921 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
58923 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
58925 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
58927 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
58929 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
58931 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
58933 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
58935 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
58937 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
58939 … (0x1<<1) // This bit masks, when set, the Parity bi…
58940 …IG_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_K2_SHIFT 1
58941 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
58943 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
58945 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
58947 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
58949 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
58951 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
58953 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
58955 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
58957 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
58959 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
58961 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
58963 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
58965 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
58967 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
58969 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
58971 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
58973 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
58975 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
58977 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
58979 … (0x1<<1) // This bit masks, when set, the Parity bi…
58980 …IG_REG_PRTY_MASK_H_1_MEM085_I_MEM_PRTY_BB_SHIFT 1
58981 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
58983 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
58985 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
58987 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
58989 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
58991 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
58993 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
58995 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
58997 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
58999 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
59001 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
59003 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
59005 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
59007 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
59009 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
59011 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
59013 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
59015 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
59017 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
59019 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
59021 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
59023 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
59025 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
59028 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
59030 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
59032 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
59034 … (0x1<<1) // This bit masks, when set, the Parity bi…
59035 …IG_REG_PRTY_MASK_H_2_MEM104_I_MEM_PRTY_E5_SHIFT 1
59036 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
59038 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
59040 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
59042 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
59044 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
59046 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
59048 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
59050 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
59052 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
59054 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
59056 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
59058 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
59060 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
59062 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
59064 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
59066 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
59068 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
59070 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
59072 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
59074 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
59076 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
59078 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
59080 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
59082 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
59084 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
59086 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
59088 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
59090 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
59092 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
59094 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
59096 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
59098 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
59100 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
59102 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
59104 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
59106 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
59108 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
59110 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
59112 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
59114 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
59116 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
59118 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
59120 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
59122 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
59124 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
59126 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
59128 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
59130 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
59132 … (0x1<<1) // This bit masks, when set, the Parity bi…
59133 …IG_REG_PRTY_MASK_H_2_MEM097_I_MEM_PRTY_K2_SHIFT 1
59134 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
59136 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
59138 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
59140 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
59142 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
59144 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
59146 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
59148 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
59150 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
59152 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
59154 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
59156 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
59158 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
59160 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
59162 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
59164 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
59166 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
59168 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
59170 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
59172 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
59174 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
59176 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
59178 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
59180 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
59182 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
59184 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
59186 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
59188 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
59190 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
59192 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
59194 … (0x1<<1) // This bit masks, when set, the Parity bi…
59195 …IG_REG_PRTY_MASK_H_2_MEM046_I_MEM_PRTY_BB_SHIFT 1
59196 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
59198 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
59200 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
59202 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
59204 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
59206 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
59208 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
59210 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
59212 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
59215 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
59217 … (0x1<<1) // This bit masks, when set, the Parity bi…
59218 …IG_REG_PRTY_MASK_H_3_MEM095_I_MEM_PRTY_E5_SHIFT 1
59219 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
59221 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
59223 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
59225 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
59227 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
59229 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
59231 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
59233 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
59235 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
59237 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
59239 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
59241 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
59243 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
59245 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
59247 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
59249 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
59251 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
59253 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
59255 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
59257 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
59259 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
59261 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
59263 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
59265 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
59267 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
59269 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
59271 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
59273 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
59275 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
59277 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
59279 … (0x1<<1) // This bit masks, when set, the Parity bi…
59280 …IG_REG_PRTY_MASK_H_3_MEM012_I_MEM_PRTY_K2_SHIFT 1
59281 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
59283 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
59285 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
59287 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
59289 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
59291 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
59293 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
59295 … (0x1<<1) // This bit masks, when set, the Parity bi…
59296 …IG_REG_PRTY_MASK_H_3_MEM024_I_MEM_PRTY_BB_SHIFT 1
59297 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
59299 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
59301 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
59303 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
59305 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
59307 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
59309 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
59311 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
59313 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
59315 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
59317 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
59319 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
59321 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
59324 …0x1 // Close-gate function disable bit: 0 - egress drain mode is enabled when close-gate input…
59326 …0808UL //Access:RW DataWidth:0x10 // The Ethernet type value for L2 tag 1. The reset value is…
59331 …W DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Vali…
59332 …W DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Vali…
59333 …W DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Vali…
59334 …W DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Vali…
59335 …W DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Vali…
59336 …W DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Vali…
59338 …bit for choosing between XSTORM and YSTORM for forwarding RX packets. 0 is for XSTORM; 1 is for Y…
59339 …get the current credit count on the interface. This configuration should be static during run-time.
59343 … (0x1<<8) // T-bit to be used in CM he…
59349 …-PF drop and per-VPORT drop packets or forward the packet to the destination with the error bit se…
59350 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59351 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59352 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59353 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59354 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59355 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59356 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59357 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59358 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59359 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59360 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59361 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59362 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59363 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59364 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59365 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59366 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59367 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59368 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59369 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59370 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59371 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59372 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59373 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59374 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59375 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59376 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59377 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59378 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59379 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59380 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59381 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59382 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59383 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59384 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59385 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59386 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59387 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59388 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59389 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59390 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59391 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59392 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59393 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59394 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59395 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59396 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59397 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59398 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59399 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59400 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59401 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59402 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59403 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59404 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59405 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59406 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59407 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59408 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59409 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59410 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59411 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59412 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59413 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59414 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59415 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59416 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59417 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59418 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59419 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59420 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59421 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59422 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59423 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59424 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59425 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59426 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59427 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59428 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59429 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59430 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59431 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59432 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59433 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59434 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59435 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59436 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59437 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59438 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59439 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59440 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59441 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59442 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59443 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59444 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59445 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59446 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59447 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59448 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59449 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59450 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59451 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59452 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59453 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59454 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59455 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59456 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59457 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59458 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59459 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59460 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59461 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59462 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59463 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59464 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59465 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59466 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59467 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59468 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59469 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59470 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59471 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59472 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59473 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59474 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59475 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59476 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59477 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59478 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59479 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59480 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59481 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59482 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59483 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59484 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59485 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59486 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59487 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59488 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59489 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59490 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59491 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59492 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59493 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59494 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59495 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59496 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59497 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59498 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59499 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59500 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59501 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59502 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59503 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59504 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59505 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59506 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59507 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59508 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59509 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59510 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59511 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59512 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59513 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59514 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59515 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59516 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59517 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59518 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59519 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59520 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59521 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59522 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59523 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59524 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59525 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59526 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59527 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59528 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59529 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59530 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59531 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59532 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59533 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59534 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59535 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59536 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59537 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59538 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59539 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59540 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59541 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59542 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59543 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59544 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59545 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59546 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59547 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59548 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59549 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59550 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59551 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59552 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59553 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59554 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59555 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59556 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59557 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
59558 …ess:RW DataWidth:0x1 // Per-PF drop configuration to be used for main and LB traffic of all p…
59561 …0cUL //Access:R DataWidth:0x18 // TX SOP descriptor queue empty status - for main traffic que…
59562 …c10UL //Access:R DataWidth:0x18 // TX SOP descriptor queue full status - for main traffic que…
59563 … DataWidth:0x40 // Addresses for TimeSync related registers in the timesync generator sub-module.
59567 …1 // Output enable for the STORM interface. This configuration should be static during run-time.
59580 …UL //Access:RW DataWidth:0x4 // Size of the proprietary header, in 32-bit words, that is pres…
59581 …s, whichever that is smaller. Values different from the default value are only for debug purposes …
59582 …//Access:RW DataWidth:0x1 // Packet has Ethernet FCS field. Set this bit to indicate that th…
59586 …Bit-map indicating which L2 hdrs may appear after the basic Ethernet header. Bit 0-tag0 (outer ta…
59587 … 0x50101cUL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59588 … 0x501020UL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59589 … 0x501024UL //Access:RW DataWidth:0x8 // Bit-map indicating which L2 hdrs may appear after L…
59590 … 0x501028UL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59591 … 0x50102cUL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59592 … 0x501030UL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59593 … 0x501034UL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59594 …Bit-map indicating which L2 hdrs may appear after the basic Ethernet header. Bit 0-tag0 (outer ta…
59595 … 0x50103cUL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59596 … 0x501040UL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59597 … 0x501044UL //Access:RW DataWidth:0x8 // Bit-map indicating which L2 hdrs may appear after L…
59598 … 0x501048UL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59599 … 0x50104cUL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59600 … 0x501050UL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59601 … 0x501054UL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59603 … (0x1<<0) // Enable bit for Ethernet-over-GRE (L2 GRE…
59605 … (0x1<<1) // Enable bit for IP-over-GRE (IP…
59606 …IG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1
59607 … (0x1<<2) // Enable bit for VXLAN encapsula…
59612 … 0x501068UL //Access:RW DataWidth:0x10 // FCOE Ethertype - default is 0x8906.
59617 … 0x50107cUL //Access:RW DataWidth:0x8 // IPv4 protocol field for ICMPv4 - defaults to 0x01.
59618 … 0x501080UL //Access:RW DataWidth:0x8 // IPv6 next header field for ICMPv6 - defaults to 0x3A.
59620 … 0x501088UL //Access:RW DataWidth:0x20 // Destination MAC address 1; The LLH will look f…
59621 … 0x50108cUL //Access:RW DataWidth:0x10 // Destination MAC address 1; The LLH will look f…
59635 … 0x5010c4UL //Access:RW DataWidth:0xc // Inner VLAN ID 1 used in NCSI filteri…
59639 …0x20 // Destination IP address 1;The LLH will look for this address in all incoming packets. In …
59640 …0x20 // Destination IP address 1;The LLH will look for this address in all incoming packets. In …
59641 …0x20 // Destination IP address 1;The LLH will look for this address in all incoming packets. In …
59642 …0x20 // Destination IP address 1;The LLH will look for this address in all incoming packets. In …
59643 …dress 2;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
59644 …dress 2;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
59645 …dress 2;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
59646 …dress 2;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
59647 …dress 3;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
59648 …dress 3;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
59649 …dress 3;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
59650 …dress 3;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.
59651 …s:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_0: 0 - IPv6; 1-IPv4.
59652 …s:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_1: 0 - IPv6; 1-IPv4.
59653 …s:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_2: 0 - IPv6; 1-IPv4.
59654 … 0x501110UL //Access:RW DataWidth:0x10 // Destination TCP address 1. The LLH will look f…
59657 … 0x50111cUL //Access:RW DataWidth:0x10 // Destination UDP address 1 The LLH will look fo…
59661 … (0x1<<0) // Mask bit for forwarding broadcast (MAC destination address…
59663 … (0x1<<1) // Mask bit for forwarding multicast (MAC destination …
59664 …IG_REG_RX_LLH_NCSI_MCP_MASK_ALLMLCST_SHIFT 1
59667 … (0x1<<3) // Mask bit for forwarding IPv6…
59669 … (0x1<<4) // Mask bit for forwarding unic…
59671 … (0x1<<5) // Mask bit for forwarding pack…
59673 … (0x1<<6) // Mask bit for forwarding pack…
59675 … (0x1<<7) // Mask bit for forwarding pack…
59677 … (0x1<<8) // Mask bit for forwarding pack…
59679 … (0x1<<9) // Mask bit for forwarding pack…
59681 … (0x1<<10) // Mask bit for forwarding pack…
59683 … (0x1<<11) // Mask bit for forwarding pack…
59685 … (0x1<<12) // Mask bit for forwarding pack…
59687 … (0x1<<13) // Mask bit for forwarding pack…
59689 … (0x1<<14) // Mask bit for forwarding pack…
59691 … (0x1<<15) // Mask bit for forwarding pack…
59693 … (0x1<<16) // Mask bit for forwarding pack…
59695 … (0x1<<17) // Mask bit for forwarding pack…
59697 … (0x1<<18) // Mask bit for forwarding pack…
59699 … (0x1<<19) // Mask bit for forwarding pack…
59705 … (0x1<<22) // Mask bit for forwarding pack…
59707 … (0x1<<23) // Mask bit for forwarding pack…
59709 … (0x1<<24) // Mask bit for forwarding pack…
59711 … (0x1<<25) // Mask bit for forwarding pack…
59713 … (0x1<<26) // Mask bit for forwarding pack…
59719 … (0x1<<29) // Mask bit for forwarding ICMP…
59721 … (0x1<<30) // Mask bit for forwarding ICMP…
59723 … (0x1<<31) // Mask bit for forwarding ICMP…
59726 … (0x1<<0) // Mask bit for forwarding pack…
59728 …ONE (0x1<<1) // Mask bit for forwarding…
59729 …IG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_NONE_SHIFT 1
59730 … (0x1<<2) // Mask bit for forwarding pack…
59732 … (0x1<<3) // Mask bit for forwarding pack…
59734 … (0x1<<4) // Mask bit for forwarding pack…
59737 … (0x1<<0) // Mask bit for forwarding pack…
59739 …NE (0x1<<1) // Mask bit for forwarding…
59740 …IG_REG_RX_LLH_NCSI_MCP_MASK_OTAG_NONE_SHIFT 1
59741 … (0x1<<2) // Mask bit for forwarding pack…
59743 … (0x1<<3) // Mask bit for forwarding pack…
59745 … (0x1<<4) // Mask bit for forwarding pack…
59748 … (0x1<<0) // Mask bit for forwarding pack…
59750 … (0x1<<1) // Mask bit for forwarding…
59751 …IG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV4_SHIFT 1
59752 … (0x1<<2) // Mask bit for forwarding IPv6…
59754 … (0x1<<3) // Mask bit for forwarding ICMP…
59756 … (0x1<<4) // Mask bit for forwarding ICMP…
59758 … (0x1<<5) // Mask bit for forwarding ICMP…
59760 … 0x501138UL //Access:RW DataWidth:0x1 // Enable bit for forwarding pack…
59761 …s:RW DataWidth:0x1 // Enable bit for forwarding packets for each PF to MCP in multifunction m…
59763 … (0x1<<0) // Mask bit for not forwarding broadcast (MAC destination addre…
59765 … (0x1<<1) // Mask bit for not forwarding multicast (MAC destinatio…
59766 …IG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ALLMLCST_SHIFT 1
59769 …MLCST (0x1<<3) // Mask bit for not forwarding …
59771 … (0x1<<4) // Mask bit for not forwarding …
59773 … (0x1<<5) // Mask bit for not forwarding …
59775 … (0x1<<6) // Mask bit for not forwarding …
59777 … (0x1<<7) // Mask bit for not forwarding …
59779 … (0x1<<8) // Mask bit for not forwarding …
59781 … (0x1<<9) // Mask bit for not forwarding …
59783 … (0x1<<10) // Mask bit for not forwarding …
59785 …YPE0 (0x1<<11) // Mask bit for not forwarding …
59787 …YPE1 (0x1<<12) // Mask bit for not forwarding …
59789 … (0x1<<13) // Mask bit for not forwarding …
59791 … (0x1<<14) // Mask bit for not forwarding …
59793 … (0x1<<15) // Mask bit for not forwarding …
59795 … (0x1<<16) // Mask bit for not forwarding …
59797 … (0x1<<17) // Mask bit for not forwarding …
59799 … (0x1<<18) // Mask bit for not forwarding …
59801 … (0x1<<19) // Mask bit for not forwarding …
59807 … (0x1<<22) // Mask bit for not forwarding …
59809 … (0x1<<23) // Mask bit for not forwarding …
59811 … (0x1<<24) // Mask bit for not forwarding …
59813 … (0x1<<25) // Mask bit for not forwarding …
59815 …_DST (0x1<<26) // Mask bit for not forwarding …
59821 …_NA (0x1<<29) // Mask bit for not forwarding …
59823 …_RA (0x1<<30) // Mask bit for not forwarding …
59825 … (0x1<<31) // Mask bit for not forwarding …
59828 …_ANY (0x1<<0) // Mask bit for not forwarding …
59830 …IVLAN_NONE (0x1<<1) // Mask bit for not forwar…
59831 …IG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_NONE_SHIFT 1
59832 …_ID0 (0x1<<2) // Mask bit for not forwarding …
59834 …_ID1 (0x1<<3) // Mask bit for not forwarding …
59836 …_ID2 (0x1<<4) // Mask bit for not forwarding …
59839 …ANY (0x1<<0) // Mask bit for not forwarding …
59841 …OTAG_NONE (0x1<<1) // Mask bit for not forwar…
59842 …IG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG_NONE_SHIFT 1
59843 … (0x1<<2) // Mask bit for not forwarding …
59845 … (0x1<<3) // Mask bit for not forwarding …
59847 …PF (0x1<<4) // Mask bit for not forwarding …
59850 … (0x1<<0) // Mask bit for not forwarding …
59852 …ICMPV4 (0x1<<1) // Mask bit for not forwar…
59853 …IG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV4_SHIFT 1
59854 …6 (0x1<<2) // Mask bit for not forwarding …
59856 …4_ER (0x1<<3) // Mask bit for not forwarding …
59858 …6_ER (0x1<<4) // Mask bit for not forwarding …
59860 …6_NS (0x1<<5) // Mask bit for not forwarding …
59862 … 0x501150UL //Access:RW DataWidth:0x1 // Enable bit for not forwarding …
59863 … DataWidth:0x1 // Enable bit for not forwarding packets for the PF to the host in multifuncti…
59885 … (0x1<<0) // L2 filter rule enable. Set this bit to enable this rule.
59887 …E0_ADDR_EN (0x1<<1) // L2 filter addres…
59888 …IG_REG_RX_LLH_L2FILT_MCP_RULE0_ADDR_EN_SHIFT 1
59889 … broadcast address of all 1's for comparison. A value of 7 selects the MAC address range 01-80-C2…
59902 …E1_ADDR_EN (0x1<<1) // See definition f…
59903 …IG_REG_RX_LLH_L2FILT_MCP_RULE1_ADDR_EN_SHIFT 1
59917 …E2_ADDR_EN (0x1<<1) // See definition f…
59918 …IG_REG_RX_LLH_L2FILT_MCP_RULE2_ADDR_EN_SHIFT 1
59932 …E3_ADDR_EN (0x1<<1) // See definition f…
59933 …IG_REG_RX_LLH_L2FILT_MCP_RULE3_ADDR_EN_SHIFT 1
59947 …E4_ADDR_EN (0x1<<1) // See definition f…
59948 …IG_REG_RX_LLH_L2FILT_MCP_RULE4_ADDR_EN_SHIFT 1
59962 …E5_ADDR_EN (0x1<<1) // See definition f…
59963 …IG_REG_RX_LLH_L2FILT_MCP_RULE5_ADDR_EN_SHIFT 1
59977 …E6_ADDR_EN (0x1<<1) // See definition f…
59978 …IG_REG_RX_LLH_L2FILT_MCP_RULE6_ADDR_EN_SHIFT 1
59992 …E7_ADDR_EN (0x1<<1) // See definition f…
59993 …IG_REG_RX_LLH_L2FILT_MCP_RULE7_ADDR_EN_SHIFT 1
60005 …1<<0) // L2 filter (for not forwarding to the host) rule enable. Set this bit to enable this rule.
60007 …FWD_RULE0_ADDR_EN (0x1<<1) // L2 filter (for n…
60008 …IG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_ADDR_EN_SHIFT 1
60009 …e broadcast address of all 1's for comparison. A value of 7 selects the MAC address range 01-80-C2…
60022 …FWD_RULE1_ADDR_EN (0x1<<1) // See definition f…
60023 …IG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_ADDR_EN_SHIFT 1
60037 …FWD_RULE2_ADDR_EN (0x1<<1) // See definition f…
60038 …IG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_ADDR_EN_SHIFT 1
60052 …FWD_RULE3_ADDR_EN (0x1<<1) // See definition f…
60053 …IG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_ADDR_EN_SHIFT 1
60067 …FWD_RULE4_ADDR_EN (0x1<<1) // See definition f…
60068 …IG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_ADDR_EN_SHIFT 1
60082 …FWD_RULE5_ADDR_EN (0x1<<1) // See definition f…
60083 …IG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_ADDR_EN_SHIFT 1
60097 …FWD_RULE6_ADDR_EN (0x1<<1) // See definition f…
60098 …IG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_ADDR_EN_SHIFT 1
60112 …FWD_RULE7_ADDR_EN (0x1<<1) // See definition f…
60113 …IG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_ADDR_EN_SHIFT 1
60124 …ataWidth:0x1 // Disable bit for forwarding packets to the host for this port. No packet is for…
60125 …:RW DataWidth:0x1 // Disable bit for forwarding packets to the host. No packet is forwarded …
60126 …e bit for forwarding packets that failed PF classification to the host. No packet with classifica…
60127 …-PF disable bit for forwarding packets to the host. Packets are not forwarded to BRB for PFs that …
60133 … (0x1<<0) // Mask bit for filtering packe…
60135 … (0x1<<1) // Mask bit for filtering …
60136 …IG_REG_RX_LLH_STORM_MASK_ETHERTYPE1_SHIFT 1
60137 … (0x1<<2) // Mask bit for filtering packe…
60139 … (0x1<<3) // Mask bit for filtering packe…
60147 …Bit 0 - message FIFO empty. Bit 1 - descriptor FIFO empty. Bit 2 - message FIFO has more than 32 e…
60148 …-to-send data remaining below which ETS arbiter for the LB path should start selecting the next pa…
60149 …//Access:RW DataWidth:0x1 // Packet has Ethernet FCS field. Set this bit to indicate that th…
60150 …ataWidth:0x1 // Zero-padding enable for LB packets. Set this bit to enable the padding of shor…
60152 …T_EN (0x1<<0) // Enable bit for the BRB interfa…
60154 … (0x3<<1) // Select between byte, cycle, and packet level of fairness for the BRB interface …
60155 …IG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_BASE_TYPE_SHIFT 1
60156 …or the BRB interface rate limiter - in term of 25MHz clock cycles. Note that this register shoul…
60157 …W DataWidth:0x20 // Increment VALUE for the BRB interface rate limiter - in term of bytes, cy…
60158 … DataWidth:0x20 // Upper bound VALUE for the BRB interface rate limiter - in term of bytes, cy…
60161 … (0x1<<0) // Enable bit for the per-TC rate limite…
60163 … (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rat…
60164 …IG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_BASE_TYPE_0_SHIFT 1
60166 … (0x1<<0) // Enable bit for the per-TC rate limite…
60168 … (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rat…
60169 …IG_REG_LB_TCRATELIMIT_CTRL_1_LB_TCRATELIMIT_BASE_TYPE_1_SHIFT 1
60171 … (0x1<<0) // Enable bit for the per-TC rate limite…
60173 … (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rat…
60174 …IG_REG_LB_TCRATELIMIT_CTRL_2_LB_TCRATELIMIT_BASE_TYPE_2_SHIFT 1
60176 … (0x1<<0) // Enable bit for the per-TC rate limite…
60178 … (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rat…
60179 …IG_REG_LB_TCRATELIMIT_CTRL_3_LB_TCRATELIMIT_BASE_TYPE_3_SHIFT 1
60181 … (0x1<<0) // Enable bit for the per-TC rate limite…
60183 … (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rat…
60184 …IG_REG_LB_TCRATELIMIT_CTRL_4_LB_TCRATELIMIT_BASE_TYPE_4_SHIFT 1
60186 … (0x1<<0) // Enable bit for the per-TC rate limite…
60188 … (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rat…
60189 …IG_REG_LB_TCRATELIMIT_CTRL_5_LB_TCRATELIMIT_BASE_TYPE_5_SHIFT 1
60191 … (0x1<<0) // Enable bit for the per-TC rate limite…
60193 … (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rat…
60194 …IG_REG_LB_TCRATELIMIT_CTRL_6_LB_TCRATELIMIT_BASE_TYPE_6_SHIFT 1
60196 … (0x1<<0) // Enable bit for the per-TC rate limite…
60198 … (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rat…
60199 …IG_REG_LB_TCRATELIMIT_CTRL_7_LB_TCRATELIMIT_BASE_TYPE_7_SHIFT 1
60200 …crement PERIOD for the per-TC rate limiter - in term of 25MHz clock cycles. Note that this regis…
60201 …crement PERIOD for the per-TC rate limiter - in term of 25MHz clock cycles. Note that this regis…
60202 …crement PERIOD for the per-TC rate limiter - in term of 25MHz clock cycles. Note that this regis…
60203 …crement PERIOD for the per-TC rate limiter - in term of 25MHz clock cycles. Note that this regis…
60204 …crement PERIOD for the per-TC rate limiter - in term of 25MHz clock cycles. Note that this regis…
60205 …crement PERIOD for the per-TC rate limiter - in term of 25MHz clock cycles. Note that this regis…
60206 …crement PERIOD for the per-TC rate limiter - in term of 25MHz clock cycles. Note that this regis…
60207 …crement PERIOD for the per-TC rate limiter - in term of 25MHz clock cycles. Note that this regis…
60208 …560UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60209 …564UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60210 …568UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60211 …56cUL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60212 …570UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60213 …574UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60214 …578UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60215 …57cUL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60216 …0UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60217 …4UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60218 …8UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60219 …cUL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60220 …0UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60221 …4UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60222 …8UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60223 …cUL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60232 …lient): 0-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6…
60233 …lient): 0-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6…
60234 …-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the …
60235 …g IDs: 0-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6…
60237 …-robin arbiter stays on the winning input instead of moving to the next one. Bit 0 is for the mai…
60239 … 0x5015e0UL //Access:RW DataWidth:0x1 // Enable bit for the pseudo-random arbit…
60241 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 1 is allowed to reach.
60251 …idth:0x20 // Specify the weight (in bytes) to be added to credit register 1 when it is time to i…
60260 …501634UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
60261 …R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter credit register 1.
60262 …50163cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
60263 …501640UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
60264 …501644UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
60265 …501648UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
60266 …50164cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
60267 …501650UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
60268 …501654UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
60269 …501658UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
60270 …:RW DataWidth:0x1 // Disable bit for forwarding packets to the host. No packet is forwarded …
60271 …e bit for forwarding packets that failed PF classification to the host. No packet with classifica…
60272 …-PF disable bit for forwarding packets to the host. Packets are not forwarded to BRB for PFs that …
60289 …r TimeSync feature. Bit 0 enables TimeSync on RX side. Bit 1 enables V1 frame format in timesync…
60290 …r TimeSync feature. Bit 0 enables TimeSync on TX side. Bit 1 enables V1 frame format in timesync…
60291 … 0x501908UL //Access:RW DataWidth:0x1 // Set to 1 to enable PTP packet…
60292 … 0x50190cUL //Access:RW DataWidth:0x1 // Set to 1 to enable PTP packet…
60293 …-specified packet timestamp mode. NIG will capture the timestamp value of the packet that SW indi…
60294 … 0x501914UL //Access:RW DataWidth:0x10 // MAC Ethertype 1 for PTP packet detec…
60295 …estination address 0 is fixed at 0x011B_1900_0000. MAC destination address 1 is fixed at 0x0180_C…
60296 …estination address 0 is fixed at 0x011B_1900_0000. MAC destination address 1 is fixed at 0x0180_C…
60297 …bit to 1 to mask out the particular parameter. 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0…
60298 …bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . 1-{IPv4 DA 0; UDP DP 1} . 2…
60299 …bit to 1 to mask out the particular parameter. 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0…
60300 …bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . 1-{IPv4 DA 0; UDP DP 1} . 2…
60301 …1-deep FIFOs for the host. Bits [15:0] return the sequence ID of the packet. Bit 16 indicates th…
60302 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for the ho…
60303 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for the ho…
60304 … 1-deep FIFOs for MCP. Bits [15:0] return the sequence ID of the packet. Bit 16 indicates the va…
60305 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. …
60306 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. …
60307 …1-deep FIFOs for TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16 indicates th…
60308 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFO for the TX …
60309 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFO for the TX …
60310 …-bit time for the 64-bit timestamp value. Error occurs when bits [31:30] of the MAC timestamp val…
60311 …-bit time for the 64-bit timestamp value. Error occurs when bits [31:30] of the MAC timestamp val…
60312 …bit to perform PF classification before sending the packet to the BRB and performing WOL detection…
60313 …ode. 0: no classification. 1: classification based on tag/VLAN/MAC matching. 2: classification b…
60314 …-stage classification mode; value of 0: AND the hit vectors; value of 1: OR the hit vectors; value…
60315 …-port value to be used when protocol-based classification fails. This is the per-port per-PF ID (…
60316 …-port value to be used when outer-tag/inner VLAN/MAC classification fails. This is the per-port …
60317 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60318 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60319 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60320 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60321 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60322 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60323 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60324 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60325 …-bit field immediately following the Ethertype to be used for each of the outer tag value bit. The…
60326 …23:18] of this register specify the index for bit 7. Bits [5:0] of this register specify the inde…
60327 …3:18] of this register specify the index for bit 11. Bits [5:0] of this register specify the inde…
60328 …3:18] of this register specify the index for bit 15. Bits [5:0] of this register specify the inde…
60329 …:RW DataWidth:0x10 // Outer tag value mask. Set a bit to 0 to mask out the corresponding bit …
60330 …-port per-PF register. This register selects the classification type for the tag/VLAN/MAC mode. …
60331 … 0x5019b0UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60333 …9c0UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function select b…
60335 …-port per-PF register. Per-function outer tag/inner VLAN configuration for PF classification. Th…
60337 …1 // This is a per-port per-PF register. Per-function no outer tag/inner VLAN configuration fo…
60338 …er-port per-PF register. Per-function MAC addresses to be matched with for MAC-address-based clas…
60340 … 0x501a80UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60342 …-port per-PF register. Per-function mode select bit to indicate whether the filter is to be used …
60344 …-port per-PF register. Per-function select bits for the different protocol types to be evaluated …
60346 …b40UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function select b…
60348 …e. 0 selects connection-based classification. 1 selects the PF-based classification. This regist…
60349 …-tuple search for TCP packets. Set this bit to use the TCP 4-tuple (TCP source and destination po…
60350 …-tuple search for UDP packets. Set this bit to use the UDP 4-tuple (UDP source and destination po…
60351 …ed to hash the data string in connection-based engine classification. This register is used only …
60352 …-entry Engine ID lookup table, with 1 bit per entry. Set the bit to 1 to have packets associated …
60354 …bit select. This configuration selects one of the 24-bit destination QP bits to be used as the en…
60355 …-global-PF engine ID to be used in PF-based engine classification. Set the bit to 1 to have packe…
60356 …ss:RW DataWidth:0x3 // Flow control mode. 0 - disable; 1 - PFC; 2 - LLFC; 3 - PPP; 4 - PAUSE…
60357 … 0x501ba4UL //Access:RW DataWidth:0x20 // Eight 4-bit configurations for specifying which TC (…
60359 …priority information. Valid values are 2-5 for selecting one of the L2 tags 2-5. This field is e…
60361 …Bit offset in the outer tag starting from which to extract the 3-bit packet priority information. …
60363 …Bit offset in the selected tag starting from which to extract the 3-bit packet priority informatio…
60365 …bit per TC and the same configuration is applicable to both RX and LB interfaces to the BRB of the…
60366 … There is one bit per TC and the same configuration is applicable to both RX and LB interfaces to …
60367 …s:RW DataWidth:0x8 // Per-TC flow control enable for received XOFF requests to pause transmit…
60368 …L //Access:RW DataWidth:0x8 // Per-TC flow control enable for XOFF messages sent to the MAC. …
60369 …cess:RW DataWidth:0x9 // Per-TC flow control enable for received XOFF requests to pause LB qu…
60370 …W DataWidth:0x1 // Enable bit for the no-drop-hdr-ind field of the LB-only-header. When set,…
60371 …-drop of LB packets with the no-drop-hdr-ind bit set due to per-TC full backpressure from the BRB.…
60372 …cifies the number of 256-bit cycles, starting from the SOP cycle, of the packet not to be dropped …
60373 … // Flow control priorities used for each TC. This register is bit-mapped with one bit for each …
60374 … // Flow control priorities used for each TC. This register is bit-mapped with one bit for each …
60375 … // Flow control priorities used for each TC. This register is bit-mapped with one bit for each …
60376 … // Flow control priorities used for each TC. This register is bit-mapped with one bit for each …
60377 … // Flow control priorities used for each TC. This register is bit-mapped with one bit for each …
60378 … // Flow control priorities used for each TC. This register is bit-mapped with one bit for each …
60379 … // Flow control priorities used for each TC. This register is bit-mapped with one bit for each …
60380 … // Flow control priorities used for each TC. This register is bit-mapped with one bit for each …
60381 …Bit-map indicating which received SAFC/PFC priorities to map to the TC. A priority is mapped to t…
60382 … Bit-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC wh…
60383 … Bit-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC wh…
60384 … Bit-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC wh…
60385 …Bit-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC whe…
60386 …Bit-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC whe…
60387 …Bit-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC whe…
60388 …Bit-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC whe…
60391 …of cycles that the TX path is PAUSEd before an interrupt is asserted. This is used for PAUSE only.
60392 …of cycles that the TX path is PAUSEd before an interrupt is asserted. This is used for PAUSE only.
60393 …enable. Set this bit to enable drain mode. Drain mode starts immediately upon assertion and stops…
60394 …affic. Set this bit to enable drain mode. Drain mode starts immediately upon assertion and stops…
60395 …Bit 0 is for TC0 flow. Bit 7 is for TC7 flow. When enabled -- draining of the corrresponding TC …
60396 …Bit 0 is for TC0 flow. Bit 8 is for TC8 flow. When enabled -- draining of the corrresponding TC …
60406 … 0x501c50UL //Access:RW DataWidth:0x1 // Set this bit to clear the curren…
60435 …rrors, and filtering. Note that statistics for packets with 32B or less are in stat_*1cyc_pkt_drop.
60436 … // Statistics for the number of single-cycle packets dropped. This is an RF generated RC statist…
60454 …dropped due to buffer full. This is an RF generated RC statistics register - reading this registe…
60455 …uncated due to buffer full. This is an RF generated RC statistics register - reading this registe…
60496 …rrors, and filtering. Note that statistics for packets with 32B or less are in stat_*1cyc_pkt_drop.
60497 … // Statistics for the number of single-cycle packets dropped. This is an RF generated RC statist…
60498 …ll of the TX packets dropped, due to the drop bit, the per-PF drop, the per-VPORT drop, and the M…
60499 …// Statistic register for the number of TX packets that have the per-PF drop or per-VPORT drop con…
60500 … all of the LB packets dropped, due to the drop bit, the per-PF drop, the per-VPORT drop, and the…
60501 …-PF drop or per-VPORT drop configuration set while the no-drop-hdr-ind in the packet is cleared. T…
60568 …ets from BMB to be forwarded to the host that got truncated due to BRB LB per-TC full backpressure.
60569 …ckets from BMB to be forwarded to the host that got dropped due to BRB LB per-TC full backpressure.
60570 … 0x501f08UL //Access:RW DataWidth:0x1 // Zero-padding enable for TX packets. Set this bi…
60574 … (0xff<<1) // TC enable for EDPM. There is one bit…
60575 …IG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN_SHIFT 1
60576 …-to-transmit data remaining below which ETS arbiter for the transmit path should start selecting …
60580 …TELIMIT_EN (0x1<<0) // Enable bit for the global rate…
60582 … (0x3<<1) // Select between byte, cycle, and packet level of fairness for the global rat…
60583 …IG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_BASE_TYPE_SHIFT 1
60584 …PERIOD for the global rate limiter - in term of 25MHz clock cycles. Note that this register shoul…
60585 …Access:RW DataWidth:0x20 // Increment VALUE for the global rate limiter - in term of bytes, cy…
60586 …cess:RW DataWidth:0x20 // Upper bound VALUE for the global rate limiter - in term of bytes, cy…
60589 …-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic from other port; 4-TC0 traffi…
60590 …-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic from other port; 4-TC0 traffi…
60591 …-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the …
60592 …-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic from other port; 4-TC0 traffi…
60594 …-robin arbiter stays on the winning input instead of moving to the next one. Bit 0 is for the mai…
60596 … 0x501f50UL //Access:RW DataWidth:0x1 // Enable bit for the pseudo-random arbit…
60597 … 0x501f54UL //Access:RW DataWidth:0x1 // Set this bit to disable debug tr…
60599 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 1 is allowed to reach.
60611 …idth:0x20 // Specify the weight (in bytes) to be added to credit register 1 when it is time to i…
60622 …501fb8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60623 …R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter credit register 1.
60624 …501fc0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60625 …501fc4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60626 …501fc8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60627 …501fccUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60628 …501fd0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60629 …501fd4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60630 …501fd8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60631 …501fdcUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60632 …501fe0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60633 …501fe4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60635 … (0x1<<0) // Mask bit for forwarding broadcast (MAC destination address…
60637 … (0x1<<1) // Mask bit for forwarding multicast (MAC destination …
60638 …IG_REG_TX_LLH_NCSI_MCP_MASK_ALLMLCST_SHIFT 1
60641 … (0x1<<3) // Mask bit for forwarding IPv6…
60643 … (0x1<<4) // Mask bit for forwarding unic…
60645 … (0x1<<5) // Mask bit for forwarding pack…
60647 … (0x1<<6) // Mask bit for forwarding pack…
60649 … (0x1<<7) // Mask bit for forwarding pack…
60651 … (0x1<<8) // Mask bit for forwarding pack…
60653 … (0x1<<9) // Mask bit for forwarding pack…
60655 … (0x1<<10) // Mask bit for forwarding pack…
60657 … (0x1<<11) // Mask bit for forwarding pack…
60659 … (0x1<<12) // Mask bit for forwarding pack…
60661 … (0x1<<13) // Mask bit for forwarding pack…
60663 … (0x1<<14) // Mask bit for forwarding pack…
60665 … (0x1<<15) // Mask bit for forwarding pack…
60667 … (0x1<<16) // Mask bit for forwarding pack…
60669 … (0x1<<17) // Mask bit for forwarding pack…
60671 … (0x1<<18) // Mask bit for forwarding pack…
60673 … (0x1<<19) // Mask bit for forwarding pack…
60679 … (0x1<<22) // Mask bit for forwarding pack…
60681 … (0x1<<23) // Mask bit for forwarding pack…
60683 … (0x1<<24) // Mask bit for forwarding pack…
60685 … (0x1<<25) // Mask bit for forwarding pack…
60687 … (0x1<<26) // Mask bit for forwarding pack…
60693 … (0x1<<29) // Mask bit for forwarding ICMP…
60695 … (0x1<<30) // Mask bit for forwarding ICMP…
60697 … (0x1<<31) // Mask bit for forwarding ICMP…
60700 … (0x1<<0) // Mask bit for forwarding pack…
60702 …ONE (0x1<<1) // Mask bit for forwarding…
60703 …IG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_NONE_SHIFT 1
60704 … (0x1<<2) // Mask bit for forwarding pack…
60706 … (0x1<<3) // Mask bit for forwarding pack…
60708 … (0x1<<4) // Mask bit for forwarding pack…
60711 … (0x1<<0) // Mask bit for not forwarding broadcast (MAC destination addre…
60713 … (0x1<<1) // Mask bit for not forwarding multicast (MAC destinatio…
60714 …IG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ALLMLCST_SHIFT 1
60717 …_MLCST (0x1<<3) // Mask bit for not forwarding …
60719 …T (0x1<<4) // Mask bit for not forwarding …
60721 … (0x1<<5) // Mask bit for not forwarding …
60723 … (0x1<<6) // Mask bit for not forwarding …
60725 … (0x1<<7) // Mask bit for not forwarding …
60727 … (0x1<<8) // Mask bit for not forwarding …
60729 … (0x1<<9) // Mask bit for not forwarding …
60731 … (0x1<<10) // Mask bit for not forwarding …
60733 …TYPE0 (0x1<<11) // Mask bit for not forwarding …
60735 …TYPE1 (0x1<<12) // Mask bit for not forwarding …
60737 … (0x1<<13) // Mask bit for not forwarding …
60739 … (0x1<<14) // Mask bit for not forwarding …
60741 … (0x1<<15) // Mask bit for not forwarding …
60743 … (0x1<<16) // Mask bit for not forwarding …
60745 … (0x1<<17) // Mask bit for not forwarding …
60747 … (0x1<<18) // Mask bit for not forwarding …
60749 … (0x1<<19) // Mask bit for not forwarding …
60755 … (0x1<<22) // Mask bit for not forwarding …
60757 … (0x1<<23) // Mask bit for not forwarding …
60759 … (0x1<<24) // Mask bit for not forwarding …
60761 … (0x1<<25) // Mask bit for not forwarding …
60763 …U_DST (0x1<<26) // Mask bit for not forwarding …
60769 …6_NA (0x1<<29) // Mask bit for not forwarding …
60771 …6_RA (0x1<<30) // Mask bit for not forwarding …
60773 …6 (0x1<<31) // Mask bit for not forwarding …
60776 … (0x1<<0) // Mask bit for forwarding broadcast (MAC destination address…
60778 … (0x1<<1) // Mask bit for forwarding multicast (MAC destination …
60779 …IG_REG_TX_LLH_NCSI_NTWK_MASK_ALLMLCST_SHIFT 1
60782 … (0x1<<3) // Mask bit for forwarding IPv6…
60784 … (0x1<<4) // Mask bit for forwarding unic…
60786 … (0x1<<5) // Mask bit for forwarding pack…
60788 … (0x1<<6) // Mask bit for forwarding pack…
60790 … (0x1<<7) // Mask bit for forwarding pack…
60792 … (0x1<<8) // Mask bit for forwarding pack…
60794 … (0x1<<9) // Mask bit for forwarding pack…
60796 … (0x1<<10) // Mask bit for forwarding pack…
60798 … (0x1<<11) // Mask bit for forwarding pack…
60800 … (0x1<<12) // Mask bit for forwarding pack…
60802 … (0x1<<13) // Mask bit for forwarding pack…
60804 … (0x1<<14) // Mask bit for forwarding pack…
60806 … (0x1<<15) // Mask bit for forwarding pack…
60808 … (0x1<<16) // Mask bit for forwarding pack…
60810 … (0x1<<17) // Mask bit for forwarding pack…
60812 … (0x1<<18) // Mask bit for forwarding pack…
60814 … (0x1<<19) // Mask bit for forwarding pack…
60820 … (0x1<<22) // Mask bit for forwarding pack…
60822 … (0x1<<23) // Mask bit for forwarding pack…
60824 … (0x1<<24) // Mask bit for forwarding pack…
60826 … (0x1<<25) // Mask bit for forwarding pack…
60828 … (0x1<<26) // Mask bit for forwarding pack…
60834 … (0x1<<29) // Mask bit for forwarding ICMP…
60836 … (0x1<<30) // Mask bit for forwarding ICMP…
60838 … (0x1<<31) // Mask bit for forwarding ICMP…
60841 … (0x1<<0) // Mask bit for forwarding pack…
60843 …NONE (0x1<<1) // Mask bit for forwarding…
60844 …IG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_NONE_SHIFT 1
60845 … (0x1<<2) // Mask bit for forwarding pack…
60847 … (0x1<<3) // Mask bit for forwarding pack…
60849 … (0x1<<4) // Mask bit for forwarding pack…
60871 …ride for management packets. This field consists of {3-bit priority, 1-bit drop eligible, 12-bit …
60872 …ride for management packets. This field consists of {3-bit priority, 1-bit drop eligible, 12-bit …
60889 …n the BMC-to-host path to BRB. This is also used in the TX management path (when enabled by *tx_m…
60890 …e the use of TC to control the flow of TX management traffic. Set this bit to 1 to enable the use…
60891 …-to-MCP path enable. Set this bit to enable the routing of management packets from PBF interface …
60895 … 0x5020acUL //Access:RW DataWidth:0x6 // Almost-full threshold for BM…
60900 … 0x5020c0UL //Access:RW DataWidth:0x7 // Almost-full threshold for DO…
60903 …ission. This is applicalbe to packets longer than this many cycles. The valid values are 1 to 16.
60904 …- send debug traffic through port 0. 1 - send debug traffic through port 1. 2 - send debug traffi…
60906 …ssion. This is applicalbe to packets longer than this many cycles. The valid values are 1 to 128.
60907 … 0x5020dcUL //Access:RW DataWidth:0x8 // Almost-full threshold for de…
60910 …- the number of valid bytes in the last cycle (0=all bytes are valid); [261]eop - active on the la…
60913 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
60914 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
60915 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
60916 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
60922 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
60923 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
60924 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
60925 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
60927 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
60928 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
60929 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
60930 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
60932 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
60933 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
60934 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
60935 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
60937 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
60938 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
60939 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
60940 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
60942 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
60943 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
60944 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
60945 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
60947 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
60948 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
60949 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
60950 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
60953 …-port per-PF register. L2 tag removal configuration for ACPI. Bit mapped as follow: bit 0: 5 - L…
60954 … per-port per-PF register. Proprietary header removal configuration for ACPI. Set this bit to 1 …
60955 …taWidth:0x1 // Set this bit to enable ACPI pattern matching and TCP SYN matching in multi-funct…
60956 …ataWidth:0x1 // Set this bit to enable ACPI and TCP SYN matching even when the packet is forwar…
60957 … 0x508080UL //Access:WB DataWidth:0x100 // This is a per-port per-PF register. Byt…
60959 …Width:0x1 // This is a per-port per-PF register. When this bit is set ACPI packet recognition…
60960 … 0x508104UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60961 … 0x508108UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60962 …810cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC32C for pattern 1.
60963 … 0x508110UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60964 … 0x508114UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60965 … 0x508118UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60966 … 0x50811cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60967 … 0x508120UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60968 … 0x508124UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60969 … 0x508128UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60970 … 0x50812cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60971 … 0x508130UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60972 … 0x508134UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60973 … 0x508138UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60974 … 0x50813cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60975 … 0x508140UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60976 …:RW DataWidth:0x2 // This is a per-port per-PF register. Set bit 0 to enable wake on IPv4 TC…
60977 …-port per-PF register. Enable bits for fields to be compared if IPv6 is present in the packet. B…
60978 …-port per-PF register. Enable bits for fields to be compared if IPv4 is present in the packet. B…
60979 … 0x508150UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. IPv…
60980 … 0x508154UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. TCP…
60981 … 0x508158UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. IPv…
60982 … 0x50815cUL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. TCP…
60983 … 0x508160UL //Access:WB DataWidth:0x80 // This is a per-port per-PF register. IPv…
60985 … 0x508170UL //Access:WB DataWidth:0x80 // This is a per-port per-PF register. IPv…
60987 … 0x508180UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. IPv…
60988 … 0x508184UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. IPv…
60989 …idth:0x1 // This is a per-port per-PF register. When this bit is set Magic Packet recognition…
60990 … 0x508190UL //Access:WB DataWidth:0x30 // This is a per-port per-PF register. MAC…
60992 …/Access:RW DataWidth:0x1 // This is a per-port per-PF register. A low-to-high transition of …
60993 … 0x5081a0UL //Access:WB_R DataWidth:0x100 // Read-only data from the Wake…
60995 …- a low-to-high transition of this bit clears the wake_info, wake_pkt_len, and wake_details regist…
60996 …- all fields are sticky. Bits 15:0 - PF Vector: The bit-mapped vector indicating which of the gl…
60997 …length - the actual length of the 'wake' packet, in bytes. This register is sticky and is cleared …
60998 …- all fields are sticky. Bits 7:0 - ACPI MATCH: Per-function bit-mapped result from ACPI patte…
60999 …s:WB_R DataWidth:0x50 // Packet TimeSync information that is buffered in 1-deep FIFOs for the ho…
61001 …s:WB_R DataWidth:0x50 // Packet TimeSync information that is buffered in 1-deep FIFO for the TX …
61011 … classification mask bits bit 0: mask_dstMac bit 1: mask_srcMac bit 2: mask_dstIPv4 bit 3: mask_sr…
61012 … classification mask bits bit 0: mask_dstMac bit 1: mask_srcMac bit 2: mask_dstIPv4 bit 3: mask_sr…
61013 …ion rules bit 0: MAC address enable bit 1: IPV4 + UDP enable bit 2: Ethernet type enable bit 3: IP…
61014 …ion rules bit 0: MAC address enable bit 1: IPV4 + UDP enable bit 2: Ethernet type enable bit 3: IP…
61015 …aWidth:0x1 // This bit defines whether to add offset and jitter of the timestamp to the returne…
61017 …ich is sent to the port macro. 0: free running counter. [1..4]: synchronized counter for port [1..…
61018 …timer will be sent to SEMI/MCP 0: free running counter. [1..4]: synchronized counter for port [1..…
61019 …1: ETHERTYPE � insert timestamp if EtherType filter had a hit 2: UDP � insert timestamp to UDP pac…
61022 …RW DataWidth:0x5 // Global timestamp shift for the free running counter. Legal values are 0-16
61026 …1-deep FIFOs. Bits [15:0] return the sequence ID of the packet which is set by free running count…
61027 …ataWidth:0x40 // RX user protocol Packet information that is buffered in 1-deep FIFO. Timestamp …
61029 …ataWidth:0x30 // RX user protocol packet information that is buffered in 1-deep FIFO. Source add…
61031 …1-deep FIFOs. Bits [15:0] return the sequence ID of the packet which is set by free running count…
61032 …ataWidth:0x40 // TX user protocol Packet information that is buffered in 1-deep FIFO. Timestamp …
61034 …ataWidth:0x30 // RX user protocol packet information that is buffered in 1-deep FIFO. Destinatio…
61036 …0x5088a8UL //Access:RW DataWidth:0x20 // This register contains the 32 bit LSB of the configur…
61037 …0x5088acUL //Access:RW DataWidth:0x20 // This register contains the 32 bit MSB of the configur…
61038 …0x5088b0UL //Access:RW DataWidth:0x20 // This register contains the 32 bit LSB of the offset v…
61039 …0x5088b4UL //Access:RW DataWidth:0x20 // This register contains the 32 bit MSB of the offset v…
61040 …0x5088b8UL //Access:R DataWidth:0x20 // This register contains the 32 bit LSB of the free run…
61041 …0x5088bcUL //Access:R DataWidth:0x20 // This register contains the 32 bit MSB of the free run…
61042 …0x5088c0UL //Access:R DataWidth:0x20 // This register contains the 32 bit LSB of the synchron…
61043 …0x5088c4UL //Access:R DataWidth:0x20 // This register contains the 32 bit MSB of the synchron…
61044 …, high period and low period are all configurable, and when asserting this bit the PPS starts to t…
61049 …only when tsgen_rst_drift_cntr is 1. Bits 27:0 specify how many 16 nsec time quantas to wait befor…
61050 … 0x5088e0UL //Access:RW DataWidth:0x4 // Bits 3:0 are the active-low output enables fo…
61052 …FO data bytes occupancy is higher than this threshold nig_dorq_edpm_en is de-asserted. The value i…
61054 …bit 0 marks that packet should be duplicated to host and Storm when BTH opcode equals bth_hdr_flow…
61055 …cts engine ID in case that PF classification fails: 0: Use engine 0. 1: Use engine 1. 2/3: Use con…
61057 … packets: Bits [1:0] define decision for ROCE/RROCE packets. Bits [3:2] define decision for other …
61059 … // This field maps (ipv4_tos >> 2) 6 bits to 6 bits: bits 5:3 - priority bits 2:0 - TC This co…
61065 …-port register L2 tag removal configuration for ACPI. Bit mapped as follow: bit 0: 5 - L2 tags 0…
61066 …s a per-port register. Proprietary header removal configuration for ACPI. Set this bit to 1 to e…
61067 … 0x508b18UL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61068 … 0x508b1cUL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61069 … 0x508b20UL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61070 … 0x508b24UL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61071 … 0x508b28UL //Access:RW DataWidth:0x1 // This is a per-port register. Enabl…
61072 … 0x508b2cUL //Access:RW DataWidth:0x1 // This is a per-port register. Enable…
61073 … 0x508b30UL //Access:RW DataWidth:0x1 // This is a per-port register. Perfo…
61074 … 0x508b34UL //Access:RW DataWidth:0x10 // This is a per-port register. Next …
61075 … // This is a per-port register. Destination port value used to designate a NGE header following…
61076 …// This is a per-port register which defines mapping of TC from the received TC to the TC sent to …
61080 …I_MCP_MASK_IPV6_MLD (0x1<<0) // Mask bit for forwarding IPV6…
61082 …H_NCSI_MCP_MASK_IPV6_NEI_SOLICI (0x1<<1) // Mask bit for forwarding…
61083 …IG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_IPV6_NEI_SOLICI_SHIFT 1
61084 …I_MCP_MASK_DHCP_V6_SERVER (0x1<<2) // Mask bit for forwarding IPv6…
61086 …I_MCP_MASK_DHCP_V4_CLIENT (0x1<<3) // Mask bit for forwarding DCHP…
61088 …I_MCP_MASK_DHCP_V4_SERVER (0x1<<4) // Mask bit for forwarding DHCP…
61090 …I_MCP_MASK_MAC6_K2_E5 (0x1<<5) // Mask bit for forwarding pack…
61092 …I_MCP_MASK_MAC7_K2_E5 (0x1<<6) // Mask bit for forwarding pack…
61094 …I_MCP_MASK_DHCP_V6_CLI_E5 (0x1<<7) // Mask bit for forwarding IPv6…
61097 …I_MCP_MASK_IPV6_MLD (0x1<<0) // Mask bit for forwarding unic…
61099 …H_NCSI_MCP_MASK_IPV6_NEI_SOLICI (0x1<<1) // Mask bit for forwarding…
61100 …IG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_IPV6_NEI_SOLICI_SHIFT 1
61101 …I_MCP_MASK_DHCP_V6_SERVER (0x1<<2) // Mask bit for forwarding DHCP…
61103 …I_MCP_MASK_DHCP_V4_CLIENT (0x1<<3) // Mask bit for forwarding DHCP…
61105 …I_MCP_MASK_DHCP_V4_SERVER (0x1<<4) // Mask bit for forwarding DHCP…
61107 …I_MCP_MASK_DHCP_V6_CLI_E5 (0x1<<7) // Mask bit for forwarding DHCP…
61110 …LLH_NCSI_BRB_DNTFWD_MASK_IPV6_MLD (0x1<<0) // Mask bit for not forwarding …
61112 …2_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV6_NEI_SOLICI (0x1<<1) // Mask bit for not forwar…
61113 …IG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV6_NEI_SOLICI_SHIFT 1
61114 …LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V6_SERVER (0x1<<2) // Mask bit for not forwarding …
61116 …LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V4_CLIENT (0x1<<3) // Mask bit for not forwarding …
61118 …LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V4_SERVER (0x1<<4) // Mask bit for not forwarding …
61120 …LLH_NCSI_BRB_DNTFWD_MASK_MAC6_K2_E5 (0x1<<5) // Mask bit for not forwarding …
61122 …LLH_NCSI_BRB_DNTFWD_MASK_MAC7_K2_E5 (0x1<<6) // Mask bit for not forwarding …
61124 …LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V6_CLI_E5 (0x1<<7) // Mask bit for not forwarding …
61127 …_LLH_NCSI_NTWK_DNTFWD_MASK_IPV6_MLD (0x1<<0) // Mask bit for not forwarding …
61129 …_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV6_NEI_SOLICI (0x1<<1) // Mask bit for not forwar…
61130 …IG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV6_NEI_SOLICI_SHIFT 1
61131 …_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V6_SERVER (0x1<<2) // Mask bit for not forwarding …
61133 …_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V4_CLIENT (0x1<<3) // Mask bit for not forwarding …
61135 …_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V4_SERVER (0x1<<4) // Mask bit for not forwarding …
61137 …_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V6_CLI_E5 (0x1<<7) // Mask bit for not forwarding …
61140 …SI_NTWK_MASK_IPV6_MLD (0x1<<0) // Mask bit for forwarding IPv6…
61142 …LH_NCSI_NTWK_MASK_IPV6_NEI_SOLICI (0x1<<1) // Mask bit for forwarding…
61143 …IG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_IPV6_NEI_SOLICI_SHIFT 1
61144 …SI_NTWK_MASK_DHCP_V6_SERVER (0x1<<2) // Mask bit for forwarding DHCP…
61146 …SI_NTWK_MASK_DHCP_V4_CLIENT (0x1<<3) // Mask bit for forwarding DHCP…
61148 …SI_NTWK_MASK_DHCP_V4_SERVER (0x1<<4) // Mask bit for forwarding DHCP…
61150 …SI_NTWK_MASK_DHCP_V6_CLI_E5 (0x1<<7) // Mask bit for forwarding DHCP…
61152 …UL //Access:RW DataWidth:0x1 // This is a Global register. When this bit is enabled, instead…
61159 … 0x508b78UL //Access:RW DataWidth:0x1 // When this bit is set and there is…
61161 …This enables credit sharing with one of the BTB TCs. 0: DORQ. 1: MNG. 2: Debug. 3: N/A. 4-11: BTB …
61162 …This enables credit sharing with one of the BTB TCs. 0: DORQ. 1: MNG. 2: Debug. 3: N/A. 4-11: BTB …
61163 …t reisters. This enables credit sharing with one of the BTB TCs. 0: MNG. 1-8: BTB per TC. 9: B…
61164 … 0x508b8cUL //Access:RW DataWidth:0x1 // This bit inhibits sending mo…
61165 … 0x508b90UL //Access:RW DataWidth:0x1 // This bit inhibits sending mo…
61166 …Width:0x1 // When this bit is configured to 1, NIG trasmits ports 0 and 1 data in TDM manner. I…
61167 …Width:0x1 // When this bit is configured to 1, NIG trasmits ports 2 and 2 data in TDM manner. I…
61168 …o this register: Bit 0: resets the value of the free running counter. Bit 1: pauses the auto incre…
61174 …W DataWidth:0x1 // This register selects the polarity of TSIO signals. 1: active high. 0: act…
61182 … 0x509040UL //Access:RW DataWidth:0x1 // This bit enables time stamp …
61183 …s bit enables time stamp latching for one step PTP packets with RECORD_TIME_STAMP bit from BTB/PBF…
61184 …bit enables correction field update for one step PTP packets with RECORD_TIME_STAMP bit from BTB/P…
61185 …hich timer will be sent to PXP 0: free running counter. [1..4]: synchronized counter for port [1..…
61192 …h:0x1 // This bit selects whether to use the MPA CRC calculation on one fully contained PDU (le…
61193 …MAC addresses to be matched with for MAC-address-based classification. This register is also used…
61197 …ter is to be used for MAC-addresss based classification or protocol-based classification. Set thi…
61199 …-based classification mode: bit 0: compare the Ethertype; bit 1: compare the TCP source port; bit …
61205 …:0x20 // This field is a per NCSI filter rule setting. When configured to 1, it means that the p…
61206 …:0x8 // This field is a per NCSI filter rule setting. When configured to 1, it means that the p…
61207 …s:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all …
61209 … 0x50d800UL //Access:RW DataWidth:0x6 // Almost-full threshold for BM…
61220 …DataWidth:0x3 // compare the GRE version field to gre_version register if compare_gre_version=1.
61253 … // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en re…
61254 … // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en re…
61255 …bit should be set when initialization of all BRTB registers and memories is finished. BRTB will fi…
61259 …_ERROR (0x1<<1) // Read packet clie…
61260 …MB_REG_INT_STS_0_RC_PKT0_RLS_ERROR_SHIFT 1
61279 …/ Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have…
61281 … (0x1<<25) // Warning! Check this bit connection for E4 A…
61283 … (0x1<<26) // Warning! Check this bit connection for E4 A…
61287 …r for MAC port 0 RX_INT::/RX_INT/d in Comments. When unified_shared_area is 1, then the error appl…
61290 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
61292 … (0x1<<1) // This bit masks, when set, the Interrupt …
61293 …MB_REG_INT_MASK_0_RC_PKT0_RLS_ERROR_SHIFT 1
61294 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
61296 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
61298 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
61300 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
61302 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
61304 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
61306 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
61308 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
61310 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
61312 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
61314 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
61316 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
61318 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
61320 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
61325 …RLS_ERROR (0x1<<1) // Read packet clie…
61326 …MB_REG_INT_STS_WR_0_RC_PKT0_RLS_ERROR_SHIFT 1
61345 …/ Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have…
61347 … (0x1<<25) // Warning! Check this bit connection for E4 A…
61349 … (0x1<<26) // Warning! Check this bit connection for E4 A…
61353 …r for MAC port 0 RX_INT::/RX_INT/d in Comments. When unified_shared_area is 1, then the error appl…
61358 …_RLS_ERROR (0x1<<1) // Read packet clie…
61359 …MB_REG_INT_STS_CLR_0_RC_PKT0_RLS_ERROR_SHIFT 1
61378 …/ Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have…
61380 … (0x1<<25) // Warning! Check this bit connection for E4 A…
61382 … (0x1<<26) // Warning! Check this bit connection for E4 A…
61386 …r for MAC port 0 RX_INT::/RX_INT/d in Comments. When unified_shared_area is 1, then the error appl…
61389 …_ERROR (0x1<<1) // Calculations err…
61390 …MB_REG_INT_STS_1_LL_ARB_CALC_ERROR_SHIFT 1
61419 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in wr…
61421 … (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in wri…
61423 … (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in wr…
61425 … (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in…
61427 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in…
61429 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in wr…
61431 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error…
61433 … (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error …
61435 … (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in…
61437 … (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in wr…
61439 … (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in writ…
61441 … (0x1<<30) // Warning! Check this bit connection for E4 A…
61443 … (0x1<<31) // Warning! Check this bit connection for E4 A…
61446 … (0x1<<1) // This bit masks, when set, the Interrupt …
61447 …MB_REG_INT_MASK_1_LL_ARB_CALC_ERROR_SHIFT 1
61448 … (0x1<<3) // This bit masks, when set, the Interrupt bit: B…
61450 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
61452 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
61454 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
61456 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
61458 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
61460 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
61462 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
61464 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
61466 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
61468 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
61470 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
61472 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
61474 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
61476 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
61478 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
61480 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
61482 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
61484 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
61486 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
61488 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
61490 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
61492 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
61494 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
61496 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
61498 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
61500 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
61503 …ALC_ERROR (0x1<<1) // Calculations err…
61504 …MB_REG_INT_STS_WR_1_LL_ARB_CALC_ERROR_SHIFT 1
61533 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in wr…
61535 … (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in wri…
61537 … (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in wr…
61539 … (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in…
61541 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in…
61543 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in wr…
61545 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error…
61547 … (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error …
61549 … (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in…
61551 … (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in wr…
61553 … (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in writ…
61555 … (0x1<<30) // Warning! Check this bit connection for E4 A…
61557 … (0x1<<31) // Warning! Check this bit connection for E4 A…
61560 …CALC_ERROR (0x1<<1) // Calculations err…
61561 …MB_REG_INT_STS_CLR_1_LL_ARB_CALC_ERROR_SHIFT 1
61590 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in wr…
61592 … (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in wri…
61594 … (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in wr…
61596 … (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in…
61598 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in…
61600 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in wr…
61602 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error…
61604 … (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error …
61606 … (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in…
61608 … (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in wr…
61610 … (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in writ…
61612 … (0x1<<30) // Warning! Check this bit connection for E4 A…
61614 … (0x1<<31) // Warning! Check this bit connection for E4 A…
61617 … (0x1<<0) // Warning! Check this bit connection for E4 A…
61619 … (0x1<<1) // Warning! Check this bit connec…
61620 …MB_REG_INT_STS_2_WC2_SOP_FIFO_ERROR_SHIFT 1
61621 … (0x1<<3) // Warning! Check this bit connection for E4 A…
61623 … (0x1<<4) // Warning! Check this bit connection for E4 A…
61625 … (0x1<<5) // Warning! Check this bit connection for E4 A…
61627 … (0x1<<6) // Warning! Check this bit connection for E4 A…
61629 … (0x1<<7) // Warning! Check this bit connection for E4 A…
61631 … (0x1<<8) // Warning! Check this bit connection for E4 A…
61633 … (0x1<<9) // Warning! Check this bit connection for E4 A…
61635 … (0x1<<10) // Warning! Check this bit connection for E4 A…
61637 … (0x1<<11) // Warning! Check this bit connection for E4 A…
61639 … (0x1<<12) // Warning! Check this bit connection for E4 A…
61641 … (0x1<<13) // Warning! Check this bit connection for E4 A…
61643 … (0x1<<14) // Warning! Check this bit connection for E4 A…
61645 … (0x1<<15) // Warning! Check this bit connection for E4 A…
61647 … (0x1<<17) // Warning! Check this bit connection for E4 A…
61649 … (0x1<<18) // Warning! Check this bit connection for E4 A…
61651 … (0x1<<19) // Warning! Check this bit connection for E4 A…
61653 … (0x1<<20) // Warning! Check this bit connection for E4 A…
61655 … (0x1<<21) // Warning! Check this bit connection for E4 A…
61657 … (0x1<<22) // Warning! Check this bit connection for E4 A…
61659 … (0x1<<23) // Warning! Check this bit connection for E4 A…
61661 … (0x1<<24) // Warning! Check this bit connection for E4 A…
61663 … (0x1<<25) // Warning! Check this bit connection for E4 A…
61665 … (0x1<<26) // Warning! Check this bit connection for E4 A…
61667 … (0x1<<27) // Warning! Check this bit connection for E4 A…
61670 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
61672 … (0x1<<1) // This bit masks, when set, the Interrupt …
61673 …MB_REG_INT_MASK_2_WC2_SOP_FIFO_ERROR_SHIFT 1
61674 … (0x1<<3) // This bit masks, when set, the Interrupt bit: B…
61676 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
61678 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
61680 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
61682 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
61684 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
61686 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
61688 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
61690 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
61692 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
61694 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
61696 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
61698 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
61700 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
61702 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
61704 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
61706 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
61708 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
61710 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
61712 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
61714 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
61716 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
61718 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
61720 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
61723 … (0x1<<0) // Warning! Check this bit connection for E4 A…
61725 … (0x1<<1) // Warning! Check this bit connec…
61726 …MB_REG_INT_STS_WR_2_WC2_SOP_FIFO_ERROR_SHIFT 1
61727 … (0x1<<3) // Warning! Check this bit connection for E4 A…
61729 … (0x1<<4) // Warning! Check this bit connection for E4 A…
61731 … (0x1<<5) // Warning! Check this bit connection for E4 A…
61733 … (0x1<<6) // Warning! Check this bit connection for E4 A…
61735 … (0x1<<7) // Warning! Check this bit connection for E4 A…
61737 … (0x1<<8) // Warning! Check this bit connection for E4 A…
61739 … (0x1<<9) // Warning! Check this bit connection for E4 A…
61741 … (0x1<<10) // Warning! Check this bit connection for E4 A…
61743 … (0x1<<11) // Warning! Check this bit connection for E4 A…
61745 … (0x1<<12) // Warning! Check this bit connection for E4 A…
61747 … (0x1<<13) // Warning! Check this bit connection for E4 A…
61749 … (0x1<<14) // Warning! Check this bit connection for E4 A…
61751 … (0x1<<15) // Warning! Check this bit connection for E4 A…
61753 … (0x1<<17) // Warning! Check this bit connection for E4 A…
61755 … (0x1<<18) // Warning! Check this bit connection for E4 A…
61757 … (0x1<<19) // Warning! Check this bit connection for E4 A…
61759 … (0x1<<20) // Warning! Check this bit connection for E4 A…
61761 … (0x1<<21) // Warning! Check this bit connection for E4 A…
61763 … (0x1<<22) // Warning! Check this bit connection for E4 A…
61765 … (0x1<<23) // Warning! Check this bit connection for E4 A…
61767 … (0x1<<24) // Warning! Check this bit connection for E4 A…
61769 … (0x1<<25) // Warning! Check this bit connection for E4 A…
61771 … (0x1<<26) // Warning! Check this bit connection for E4 A…
61773 … (0x1<<27) // Warning! Check this bit connection for E4 A…
61776 … (0x1<<0) // Warning! Check this bit connection for E4 A…
61778 … (0x1<<1) // Warning! Check this bit connec…
61779 …MB_REG_INT_STS_CLR_2_WC2_SOP_FIFO_ERROR_SHIFT 1
61780 … (0x1<<3) // Warning! Check this bit connection for E4 A…
61782 … (0x1<<4) // Warning! Check this bit connection for E4 A…
61784 … (0x1<<5) // Warning! Check this bit connection for E4 A…
61786 … (0x1<<6) // Warning! Check this bit connection for E4 A…
61788 … (0x1<<7) // Warning! Check this bit connection for E4 A…
61790 … (0x1<<8) // Warning! Check this bit connection for E4 A…
61792 … (0x1<<9) // Warning! Check this bit connection for E4 A…
61794 … (0x1<<10) // Warning! Check this bit connection for E4 A…
61796 … (0x1<<11) // Warning! Check this bit connection for E4 A…
61798 … (0x1<<12) // Warning! Check this bit connection for E4 A…
61800 … (0x1<<13) // Warning! Check this bit connection for E4 A…
61802 … (0x1<<14) // Warning! Check this bit connection for E4 A…
61804 … (0x1<<15) // Warning! Check this bit connection for E4 A…
61806 … (0x1<<17) // Warning! Check this bit connection for E4 A…
61808 … (0x1<<18) // Warning! Check this bit connection for E4 A…
61810 … (0x1<<19) // Warning! Check this bit connection for E4 A…
61812 … (0x1<<20) // Warning! Check this bit connection for E4 A…
61814 … (0x1<<21) // Warning! Check this bit connection for E4 A…
61816 … (0x1<<22) // Warning! Check this bit connection for E4 A…
61818 … (0x1<<23) // Warning! Check this bit connection for E4 A…
61820 … (0x1<<24) // Warning! Check this bit connection for E4 A…
61822 … (0x1<<25) // Warning! Check this bit connection for E4 A…
61824 … (0x1<<26) // Warning! Check this bit connection for E4 A…
61826 … (0x1<<27) // Warning! Check this bit connection for E4 A…
61829 …E_FIFO_ERROR (0x1<<1) // Read packet clie…
61830 …MB_REG_INT_STS_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT 1
61892 … (0x1<<1) // This bit masks, when set, the Interrupt …
61893 …MB_REG_INT_MASK_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT 1
61894 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
61896 … (0x1<<3) // This bit masks, when set, the Interrupt bit: B…
61898 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
61900 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
61902 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
61904 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
61906 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
61908 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
61910 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
61912 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
61914 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
61916 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
61918 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
61920 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
61922 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
61924 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
61926 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
61928 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
61930 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
61932 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
61934 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
61936 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
61938 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
61940 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
61942 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
61944 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
61946 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
61948 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
61950 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
61952 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
61955 …SIDE_FIFO_ERROR (0x1<<1) // Read packet clie…
61956 …MB_REG_INT_STS_WR_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT 1
62018 …_SIDE_FIFO_ERROR (0x1<<1) // Read packet clie…
62019 …MB_REG_INT_STS_CLR_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT 1
62083 …_FIFO_ERROR (0x1<<1) // Read SOP client …
62084 …MB_REG_INT_STS_4_RC_SOP_STRT_FIFO_ERROR_SHIFT 1
62136 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
62138 … (0x1<<1) // This bit masks, when set, the Interrupt …
62139 …MB_REG_INT_MASK_4_RC_SOP_STRT_FIFO_ERROR_SHIFT 1
62140 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
62142 … (0x1<<3) // This bit masks, when set, the Interrupt bit: B…
62144 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
62146 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
62148 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
62150 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
62152 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
62154 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
62156 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
62158 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
62160 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
62162 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
62164 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
62166 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
62168 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
62170 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
62172 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
62174 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
62176 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
62178 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
62180 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
62182 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
62184 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
62186 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
62188 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
62193 …TRT_FIFO_ERROR (0x1<<1) // Read SOP client …
62194 …MB_REG_INT_STS_WR_4_RC_SOP_STRT_FIFO_ERROR_SHIFT 1
62248 …STRT_FIFO_ERROR (0x1<<1) // Read SOP client …
62249 …MB_REG_INT_STS_CLR_4_RC_SOP_STRT_FIFO_ERROR_SHIFT 1
62360 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
62362 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
62364 … (0x1<<3) // This bit masks, when set, the Interrupt bit: B…
62366 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
62368 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
62370 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
62372 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
62374 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
62376 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
62378 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
62380 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
62382 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
62384 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
62386 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
62388 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
62390 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
62392 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
62394 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
62396 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
62398 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
62400 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
62402 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
62404 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
62406 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
62408 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
62410 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
62412 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
62414 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
62416 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
62539 …_ERROR (0x1<<1) // Read packet clie…
62540 …MB_REG_INT_STS_6_RC_PKT8_RLS_ERROR_SHIFT 1
62579 … (0x1<<23) // Warning! Check this bit connection for E4 A…
62581 … (0x1<<24) // Warning! Check this bit connection for E4 A…
62583 … (0x1<<25) // Warning! Check this bit connection for E4 A…
62585 … (0x1<<26) // Warning! Check this bit connection for E4 A…
62587 … (0x1<<27) // Warning! Check this bit connection for E4 A…
62589 … (0x1<<28) // Warning! Check this bit connection for E4 A…
62591 … (0x1<<29) // Warning! Check this bit connection for E4 A…
62593 … (0x1<<30) // Warning! Check this bit connection for E4 A…
62595 … (0x1<<31) // Warning! Check this bit connection for E4 A…
62598 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
62600 … (0x1<<1) // This bit masks, when set, the Interrupt …
62601 …MB_REG_INT_MASK_6_RC_PKT8_RLS_ERROR_SHIFT 1
62602 … (0x1<<3) // This bit masks, when set, the Interrupt bit: B…
62604 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
62606 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
62608 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
62610 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
62612 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
62614 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
62616 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
62618 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
62620 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
62622 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
62624 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
62626 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
62628 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
62630 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
62632 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
62634 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
62636 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
62638 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
62640 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
62642 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
62644 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
62646 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
62648 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
62650 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
62652 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
62654 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
62656 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
62661 …RLS_ERROR (0x1<<1) // Read packet clie…
62662 …MB_REG_INT_STS_WR_6_RC_PKT8_RLS_ERROR_SHIFT 1
62701 … (0x1<<23) // Warning! Check this bit connection for E4 A…
62703 … (0x1<<24) // Warning! Check this bit connection for E4 A…
62705 … (0x1<<25) // Warning! Check this bit connection for E4 A…
62707 … (0x1<<26) // Warning! Check this bit connection for E4 A…
62709 … (0x1<<27) // Warning! Check this bit connection for E4 A…
62711 … (0x1<<28) // Warning! Check this bit connection for E4 A…
62713 … (0x1<<29) // Warning! Check this bit connection for E4 A…
62715 … (0x1<<30) // Warning! Check this bit connection for E4 A…
62717 … (0x1<<31) // Warning! Check this bit connection for E4 A…
62722 …_RLS_ERROR (0x1<<1) // Read packet clie…
62723 …MB_REG_INT_STS_CLR_6_RC_PKT8_RLS_ERROR_SHIFT 1
62762 … (0x1<<23) // Warning! Check this bit connection for E4 A…
62764 … (0x1<<24) // Warning! Check this bit connection for E4 A…
62766 … (0x1<<25) // Warning! Check this bit connection for E4 A…
62768 … (0x1<<26) // Warning! Check this bit connection for E4 A…
62770 … (0x1<<27) // Warning! Check this bit connection for E4 A…
62772 … (0x1<<28) // Warning! Check this bit connection for E4 A…
62774 … (0x1<<29) // Warning! Check this bit connection for E4 A…
62776 … (0x1<<30) // Warning! Check this bit connection for E4 A…
62778 … (0x1<<31) // Warning! Check this bit connection for E4 A…
62781 … (0x1<<0) // Warning! Check this bit connection for E4 A…
62783 … (0x1<<1) // Warning! Check this bit connec…
62784 …MB_REG_INT_STS_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT 1
62785 … (0x1<<2) // Warning! Check this bit connection for E4 A…
62787 … (0x1<<3) // Warning! Check this bit connection for E4 A…
62789 … (0x1<<4) // Warning! Check this bit connection for E4 A…
62791 … (0x1<<5) // Warning! Check this bit connection for E4 A…
62793 … (0x1<<6) // Warning! Check this bit connection for E4 A…
62795 … (0x1<<7) // Warning! Check this bit connection for E4 A…
62797 … (0x1<<8) // Warning! Check this bit connection for E4 A…
62799 … (0x1<<9) // Warning! Check this bit connection for E4 A…
62801 … (0x1<<10) // Warning! Check this bit connection for E4 A…
62803 … (0x1<<11) // Warning! Check this bit connection for E4 A…
62805 … (0x1<<12) // Warning! Check this bit connection for E4 A…
62807 … (0x1<<13) // Warning! Check this bit connection for E4 A…
62809 … (0x1<<14) // Warning! Check this bit connection for E4 A…
62811 … (0x1<<15) // Warning! Check this bit connection for E4 A…
62813 … (0x1<<16) // Warning! Check this bit connection for E4 A…
62815 … (0x1<<17) // Warning! Check this bit connection for E4 A…
62817 … (0x1<<18) // Warning! Check this bit connection for E4 A…
62821 … (0x1<<20) // Warning! Check this bit connection for E4 A…
62823 … (0x1<<21) // Warning! Check this bit connection for E4 A…
62825 … (0x1<<22) // Warning! Check this bit connection for E4 A…
62827 … (0x1<<23) // Warning! Check this bit connection for E4 A…
62829 … (0x1<<24) // Warning! Check this bit connection for E4 A…
62831 … (0x1<<25) // Warning! Check this bit connection for E4 A…
62833 … (0x1<<26) // Warning! Check this bit connection for E4 A…
62835 … (0x1<<27) // Warning! Check this bit connection for E4 A…
62837 … (0x1<<28) // Warning! Check this bit connection for E4 A…
62839 … (0x1<<29) // Warning! Check this bit connection for E4 A…
62841 … (0x1<<30) // Warning! Check this bit connection for E4 A…
62843 … (0x1<<31) // Warning! Check this bit connection for E4 A…
62846 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
62848 … (0x1<<1) // This bit masks, when set, the Interrupt …
62849 …MB_REG_INT_MASK_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT 1
62850 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
62852 … (0x1<<3) // This bit masks, when set, the Interrupt bit: B…
62854 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
62856 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
62858 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
62860 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
62862 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
62864 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
62866 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
62868 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
62870 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
62872 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
62874 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
62876 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
62878 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
62880 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
62882 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
62884 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
62886 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
62888 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
62890 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
62892 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
62894 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
62896 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
62898 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
62900 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
62902 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
62904 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
62906 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
62908 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
62911 … (0x1<<0) // Warning! Check this bit connection for E4 A…
62913 …ROR (0x1<<1) // Warning! Check this bit connec…
62914 …MB_REG_INT_STS_WR_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT 1
62915 … (0x1<<2) // Warning! Check this bit connection for E4 A…
62917 … (0x1<<3) // Warning! Check this bit connection for E4 A…
62919 … (0x1<<4) // Warning! Check this bit connection for E4 A…
62921 … (0x1<<5) // Warning! Check this bit connection for E4 A…
62923 … (0x1<<6) // Warning! Check this bit connection for E4 A…
62925 … (0x1<<7) // Warning! Check this bit connection for E4 A…
62927 … (0x1<<8) // Warning! Check this bit connection for E4 A…
62929 … (0x1<<9) // Warning! Check this bit connection for E4 A…
62931 … (0x1<<10) // Warning! Check this bit connection for E4 A…
62933 … (0x1<<11) // Warning! Check this bit connection for E4 A…
62935 … (0x1<<12) // Warning! Check this bit connection for E4 A…
62937 … (0x1<<13) // Warning! Check this bit connection for E4 A…
62939 … (0x1<<14) // Warning! Check this bit connection for E4 A…
62941 … (0x1<<15) // Warning! Check this bit connection for E4 A…
62943 … (0x1<<16) // Warning! Check this bit connection for E4 A…
62945 … (0x1<<17) // Warning! Check this bit connection for E4 A…
62947 … (0x1<<18) // Warning! Check this bit connection for E4 A…
62951 … (0x1<<20) // Warning! Check this bit connection for E4 A…
62953 … (0x1<<21) // Warning! Check this bit connection for E4 A…
62955 … (0x1<<22) // Warning! Check this bit connection for E4 A…
62957 … (0x1<<23) // Warning! Check this bit connection for E4 A…
62959 … (0x1<<24) // Warning! Check this bit connection for E4 A…
62961 … (0x1<<25) // Warning! Check this bit connection for E4 A…
62963 … (0x1<<26) // Warning! Check this bit connection for E4 A…
62965 … (0x1<<27) // Warning! Check this bit connection for E4 A…
62967 … (0x1<<28) // Warning! Check this bit connection for E4 A…
62969 … (0x1<<29) // Warning! Check this bit connection for E4 A…
62971 … (0x1<<30) // Warning! Check this bit connection for E4 A…
62973 … (0x1<<31) // Warning! Check this bit connection for E4 A…
62976 … (0x1<<0) // Warning! Check this bit connection for E4 A…
62978 …RROR (0x1<<1) // Warning! Check this bit connec…
62979 …MB_REG_INT_STS_CLR_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT 1
62980 … (0x1<<2) // Warning! Check this bit connection for E4 A…
62982 … (0x1<<3) // Warning! Check this bit connection for E4 A…
62984 … (0x1<<4) // Warning! Check this bit connection for E4 A…
62986 … (0x1<<5) // Warning! Check this bit connection for E4 A…
62988 … (0x1<<6) // Warning! Check this bit connection for E4 A…
62990 … (0x1<<7) // Warning! Check this bit connection for E4 A…
62992 … (0x1<<8) // Warning! Check this bit connection for E4 A…
62994 … (0x1<<9) // Warning! Check this bit connection for E4 A…
62996 … (0x1<<10) // Warning! Check this bit connection for E4 A…
62998 … (0x1<<11) // Warning! Check this bit connection for E4 A…
63000 … (0x1<<12) // Warning! Check this bit connection for E4 A…
63002 … (0x1<<13) // Warning! Check this bit connection for E4 A…
63004 … (0x1<<14) // Warning! Check this bit connection for E4 A…
63006 … (0x1<<15) // Warning! Check this bit connection for E4 A…
63008 … (0x1<<16) // Warning! Check this bit connection for E4 A…
63010 … (0x1<<17) // Warning! Check this bit connection for E4 A…
63012 … (0x1<<18) // Warning! Check this bit connection for E4 A…
63016 … (0x1<<20) // Warning! Check this bit connection for E4 A…
63018 … (0x1<<21) // Warning! Check this bit connection for E4 A…
63020 … (0x1<<22) // Warning! Check this bit connection for E4 A…
63022 … (0x1<<23) // Warning! Check this bit connection for E4 A…
63024 … (0x1<<24) // Warning! Check this bit connection for E4 A…
63026 … (0x1<<25) // Warning! Check this bit connection for E4 A…
63028 … (0x1<<26) // Warning! Check this bit connection for E4 A…
63030 … (0x1<<27) // Warning! Check this bit connection for E4 A…
63032 … (0x1<<28) // Warning! Check this bit connection for E4 A…
63034 … (0x1<<29) // Warning! Check this bit connection for E4 A…
63036 … (0x1<<30) // Warning! Check this bit connection for E4 A…
63038 … (0x1<<31) // Warning! Check this bit connection for E4 A…
63041 … (0x1<<0) // Warning! Check this bit connection for E4 A…
63043 … (0x1<<1) // Warning! Check this bit connec…
63044 …MB_REG_INT_STS_8_WC6_LL_REQ_FIFO_ERROR_SHIFT 1
63045 … (0x1<<2) // Warning! Check this bit connection for E4 A…
63047 … (0x1<<3) // Warning! Check this bit connection for E4 A…
63049 … (0x1<<4) // Warning! Check this bit connection for E4 A…
63051 … (0x1<<5) // Warning! Check this bit connection for E4 A…
63053 … (0x1<<6) // Warning! Check this bit connection for E4 A…
63055 … (0x1<<7) // Warning! Check this bit connection for E4 A…
63057 … (0x1<<8) // Warning! Check this bit connection for E4 A…
63059 … (0x1<<9) // Warning! Check this bit connection for E4 A…
63061 … (0x1<<10) // Warning! Check this bit connection for E4 A…
63063 … (0x1<<11) // Warning! Check this bit connection for E4 A…
63065 … (0x1<<12) // Warning! Check this bit connection for E4 A…
63067 … (0x1<<13) // Warning! Check this bit connection for E4 A…
63069 … (0x1<<14) // Warning! Check this bit connection for E4 A…
63071 … (0x1<<15) // Warning! Check this bit connection for E4 A…
63073 … (0x1<<16) // Warning! Check this bit connection for E4 A…
63075 … (0x1<<17) // Warning! Check this bit connection for E4 A…
63077 … (0x1<<18) // Warning! Check this bit connection for E4 A…
63079 … (0x1<<19) // Warning! Check this bit connection for E4 A…
63081 … (0x1<<20) // Warning! Check this bit connection for E4 A…
63083 … (0x1<<21) // Warning! Check this bit connection for E4 A…
63085 … (0x1<<22) // Warning! Check this bit connection for E4 A…
63087 … (0x1<<23) // Warning! Check this bit connection for E4 A…
63089 … (0x1<<24) // Warning! Check this bit connection for E4 A…
63091 … (0x1<<25) // Warning! Check this bit connection for E4 A…
63093 … (0x1<<26) // Warning! Check this bit connection for E4 A…
63095 … (0x1<<27) // Warning! Check this bit connection for E4 A…
63097 … (0x1<<28) // Warning! Check this bit connection for E4 A…
63099 … (0x1<<29) // Warning! Check this bit connection for E4 A…
63101 … (0x1<<30) // Warning! Check this bit connection for E4 A…
63103 … (0x1<<31) // Warning! Check this bit connection for E4 A…
63106 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
63108 … (0x1<<1) // This bit masks, when set, the Interrupt …
63109 …MB_REG_INT_MASK_8_WC6_LL_REQ_FIFO_ERROR_SHIFT 1
63110 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
63112 … (0x1<<3) // This bit masks, when set, the Interrupt bit: B…
63114 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
63116 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
63118 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
63120 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
63122 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
63124 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
63126 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
63128 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
63130 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
63132 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
63134 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
63136 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
63138 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
63140 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
63142 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
63144 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
63146 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
63148 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
63150 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
63152 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
63154 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
63156 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
63158 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
63160 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
63162 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
63164 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
63166 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
63168 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
63171 … (0x1<<0) // Warning! Check this bit connection for E4 A…
63173 … (0x1<<1) // Warning! Check this bit connec…
63174 …MB_REG_INT_STS_WR_8_WC6_LL_REQ_FIFO_ERROR_SHIFT 1
63175 … (0x1<<2) // Warning! Check this bit connection for E4 A…
63177 … (0x1<<3) // Warning! Check this bit connection for E4 A…
63179 … (0x1<<4) // Warning! Check this bit connection for E4 A…
63181 … (0x1<<5) // Warning! Check this bit connection for E4 A…
63183 … (0x1<<6) // Warning! Check this bit connection for E4 A…
63185 … (0x1<<7) // Warning! Check this bit connection for E4 A…
63187 … (0x1<<8) // Warning! Check this bit connection for E4 A…
63189 … (0x1<<9) // Warning! Check this bit connection for E4 A…
63191 … (0x1<<10) // Warning! Check this bit connection for E4 A…
63193 … (0x1<<11) // Warning! Check this bit connection for E4 A…
63195 … (0x1<<12) // Warning! Check this bit connection for E4 A…
63197 … (0x1<<13) // Warning! Check this bit connection for E4 A…
63199 … (0x1<<14) // Warning! Check this bit connection for E4 A…
63201 … (0x1<<15) // Warning! Check this bit connection for E4 A…
63203 … (0x1<<16) // Warning! Check this bit connection for E4 A…
63205 … (0x1<<17) // Warning! Check this bit connection for E4 A…
63207 … (0x1<<18) // Warning! Check this bit connection for E4 A…
63209 … (0x1<<19) // Warning! Check this bit connection for E4 A…
63211 … (0x1<<20) // Warning! Check this bit connection for E4 A…
63213 … (0x1<<21) // Warning! Check this bit connection for E4 A…
63215 … (0x1<<22) // Warning! Check this bit connection for E4 A…
63217 … (0x1<<23) // Warning! Check this bit connection for E4 A…
63219 … (0x1<<24) // Warning! Check this bit connection for E4 A…
63221 … (0x1<<25) // Warning! Check this bit connection for E4 A…
63223 … (0x1<<26) // Warning! Check this bit connection for E4 A…
63225 … (0x1<<27) // Warning! Check this bit connection for E4 A…
63227 … (0x1<<28) // Warning! Check this bit connection for E4 A…
63229 … (0x1<<29) // Warning! Check this bit connection for E4 A…
63231 … (0x1<<30) // Warning! Check this bit connection for E4 A…
63233 … (0x1<<31) // Warning! Check this bit connection for E4 A…
63236 … (0x1<<0) // Warning! Check this bit connection for E4 A…
63238 … (0x1<<1) // Warning! Check this bit connec…
63239 …MB_REG_INT_STS_CLR_8_WC6_LL_REQ_FIFO_ERROR_SHIFT 1
63240 … (0x1<<2) // Warning! Check this bit connection for E4 A…
63242 … (0x1<<3) // Warning! Check this bit connection for E4 A…
63244 … (0x1<<4) // Warning! Check this bit connection for E4 A…
63246 … (0x1<<5) // Warning! Check this bit connection for E4 A…
63248 … (0x1<<6) // Warning! Check this bit connection for E4 A…
63250 … (0x1<<7) // Warning! Check this bit connection for E4 A…
63252 … (0x1<<8) // Warning! Check this bit connection for E4 A…
63254 … (0x1<<9) // Warning! Check this bit connection for E4 A…
63256 … (0x1<<10) // Warning! Check this bit connection for E4 A…
63258 … (0x1<<11) // Warning! Check this bit connection for E4 A…
63260 … (0x1<<12) // Warning! Check this bit connection for E4 A…
63262 … (0x1<<13) // Warning! Check this bit connection for E4 A…
63264 … (0x1<<14) // Warning! Check this bit connection for E4 A…
63266 … (0x1<<15) // Warning! Check this bit connection for E4 A…
63268 … (0x1<<16) // Warning! Check this bit connection for E4 A…
63270 … (0x1<<17) // Warning! Check this bit connection for E4 A…
63272 … (0x1<<18) // Warning! Check this bit connection for E4 A…
63274 … (0x1<<19) // Warning! Check this bit connection for E4 A…
63276 … (0x1<<20) // Warning! Check this bit connection for E4 A…
63278 … (0x1<<21) // Warning! Check this bit connection for E4 A…
63280 … (0x1<<22) // Warning! Check this bit connection for E4 A…
63282 … (0x1<<23) // Warning! Check this bit connection for E4 A…
63284 … (0x1<<24) // Warning! Check this bit connection for E4 A…
63286 … (0x1<<25) // Warning! Check this bit connection for E4 A…
63288 … (0x1<<26) // Warning! Check this bit connection for E4 A…
63290 … (0x1<<27) // Warning! Check this bit connection for E4 A…
63292 … (0x1<<28) // Warning! Check this bit connection for E4 A…
63294 … (0x1<<29) // Warning! Check this bit connection for E4 A…
63296 … (0x1<<30) // Warning! Check this bit connection for E4 A…
63298 … (0x1<<31) // Warning! Check this bit connection for E4 A…
63301 … (0x1<<0) // Warning! Check this bit connection for E4 A…
63303 … (0x1<<1) // Warning! Check this bit connec…
63304 …MB_REG_INT_STS_9_WC9_FREE_POINT_FIFO_ERROR_SHIFT 1
63305 … (0x1<<2) // Warning! Check this bit connection for E4 A…
63307 … (0x1<<3) // Warning! Check this bit connection for E4 A…
63309 … (0x1<<4) // Warning! Check this bit connection for E4 A…
63311 … (0x1<<5) // Warning! Check this bit connection for E4 A…
63313 … (0x1<<6) // Warning! Check this bit connection for E4 A…
63315 … (0x1<<7) // Warning! Check this bit connection for E4 A…
63317 … (0x1<<8) // Warning! Check this bit connection for E4 A…
63319 … (0x1<<9) // Warning! Check this bit connection for E4 A…
63321 … (0x1<<10) // Warning! Check this bit connection for E4 A…
63376 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
63378 … (0x1<<1) // This bit masks, when set, the Interrupt …
63379 …MB_REG_INT_MASK_9_WC9_FREE_POINT_FIFO_ERROR_SHIFT 1
63380 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
63382 … (0x1<<3) // This bit masks, when set, the Interrupt bit: B…
63384 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
63386 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
63388 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
63390 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
63392 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
63394 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
63396 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
63398 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
63400 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
63402 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
63404 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
63406 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
63408 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
63410 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
63412 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
63414 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
63416 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
63418 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
63420 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
63422 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
63424 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
63426 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
63428 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
63430 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
63432 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
63434 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
63436 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
63438 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
63440 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
63442 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
63444 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
63446 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
63448 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
63451 … (0x1<<0) // Warning! Check this bit connection for E4 A…
63453 …ROR (0x1<<1) // Warning! Check this bit connec…
63454 …MB_REG_INT_STS_WR_9_WC9_FREE_POINT_FIFO_ERROR_SHIFT 1
63455 … (0x1<<2) // Warning! Check this bit connection for E4 A…
63457 … (0x1<<3) // Warning! Check this bit connection for E4 A…
63459 … (0x1<<4) // Warning! Check this bit connection for E4 A…
63461 … (0x1<<5) // Warning! Check this bit connection for E4 A…
63463 … (0x1<<6) // Warning! Check this bit connection for E4 A…
63465 … (0x1<<7) // Warning! Check this bit connection for E4 A…
63467 … (0x1<<8) // Warning! Check this bit connection for E4 A…
63469 … (0x1<<9) // Warning! Check this bit connection for E4 A…
63471 … (0x1<<10) // Warning! Check this bit connection for E4 A…
63526 … (0x1<<0) // Warning! Check this bit connection for E4 A…
63528 …RROR (0x1<<1) // Warning! Check this bit connec…
63529 …MB_REG_INT_STS_CLR_9_WC9_FREE_POINT_FIFO_ERROR_SHIFT 1
63530 … (0x1<<2) // Warning! Check this bit connection for E4 A…
63532 … (0x1<<3) // Warning! Check this bit connection for E4 A…
63534 … (0x1<<4) // Warning! Check this bit connection for E4 A…
63536 … (0x1<<5) // Warning! Check this bit connection for E4 A…
63538 … (0x1<<6) // Warning! Check this bit connection for E4 A…
63540 … (0x1<<7) // Warning! Check this bit connection for E4 A…
63542 … (0x1<<8) // Warning! Check this bit connection for E4 A…
63544 … (0x1<<9) // Warning! Check this bit connection for E4 A…
63546 … (0x1<<10) // Warning! Check this bit connection for E4 A…
63612 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
63614 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
63616 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
63618 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
63620 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
63645 … (0x1<<6) // Warning! Check this bit connection for E4 A…
63647 … (0x1<<7) // Warning! Check this bit connection for E4 A…
63656 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
63658 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
63660 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
63662 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
63664 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
63667 … (0x1<<6) // Warning! Check this bit connection for E4 A…
63669 … (0x1<<7) // Warning! Check this bit connection for E4 A…
63678 … (0x1<<6) // Warning! Check this bit connection for E4 A…
63680 … (0x1<<7) // Warning! Check this bit connection for E4 A…
63689 … (0x1<<0) // This bit masks, when set, the Parity bit: BM…
63691 … (0x1<<1) // This bit masks, when set, the Parity bi…
63692 …MB_REG_PRTY_MASK_LL_BANK1_MEM_PRTY_SHIFT 1
63693 … (0x1<<2) // This bit masks, when set, the Parity bit: BM…
63695 … (0x1<<3) // This bit masks, when set, the Parity bit: BM…
63697 … (0x1<<4) // This bit masks, when set, the Parity bit: BM…
63700 … (0x1<<0) // This bit masks, when set, the Parity bit: BM…
63702 … (0x1<<1) // This bit masks, when set, the Parity bi…
63703 …MB_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_SHIFT 1
63704 … (0x1<<2) // This bit masks, when set, the Parity bit: BM…
63706 … (0x1<<3) // This bit masks, when set, the Parity bit: BM…
63708 … (0x1<<4) // This bit masks, when set, the Parity bit: BM…
63710 … (0x1<<5) // This bit masks, when set, the Parity bit: BM…
63712 … (0x1<<6) // This bit masks, when set, the Parity bit: BM…
63714 … (0x1<<7) // This bit masks, when set, the Parity bit: BM…
63716 … (0x1<<8) // This bit masks, when set, the Parity bit: BM…
63718 … (0x1<<9) // This bit masks, when set, the Parity bit: BM…
63720 … (0x1<<10) // This bit masks, when set, the Parity bit: BM…
63722 … (0x1<<11) // This bit masks, when set, the Parity bit: BM…
63724 … (0x1<<12) // This bit masks, when set, the Parity bit: BM…
63726 … (0x1<<13) // This bit masks, when set, the Parity bit: BM…
63728 … (0x1<<14) // This bit masks, when set, the Parity bit: BM…
63730 … (0x1<<15) // This bit masks, when set, the Parity bit: BM…
63732 … (0x1<<16) // This bit masks, when set, the Parity bit: BM…
63734 … (0x1<<17) // This bit masks, when set, the Parity bit: BM…
63736 … (0x1<<18) // This bit masks, when set, the Parity bit: BM…
63738 … (0x1<<19) // This bit masks, when set, the Parity bit: BM…
63740 … (0x1<<20) // This bit masks, when set, the Parity bit: BM…
63742 … (0x1<<21) // This bit masks, when set, the Parity bit: BM…
63744 … (0x1<<22) // This bit masks, when set, the Parity bit: BM…
63746 … (0x1<<23) // This bit masks, when set, the Parity bit: BM…
63748 … (0x1<<24) // This bit masks, when set, the Parity bit: BM…
63750 … (0x1<<25) // This bit masks, when set, the Parity bit: BM…
63752 … (0x1<<26) // This bit masks, when set, the Parity bit: BM…
63754 … (0x1<<27) // This bit masks, when set, the Parity bit: BM…
63756 … (0x1<<28) // This bit masks, when set, the Parity bit: BM…
63758 … (0x1<<29) // This bit masks, when set, the Parity bit: BM…
63760 … (0x1<<30) // This bit masks, when set, the Parity bit: BM…
63762 … (0x1<<16) // This bit masks, when set, the Parity bit: BM…
63764 … (0x1<<17) // This bit masks, when set, the Parity bit: BM…
63766 … (0x1<<18) // This bit masks, when set, the Parity bit: BM…
63768 … (0x1<<19) // This bit masks, when set, the Parity bit: BM…
63770 … (0x1<<20) // This bit masks, when set, the Parity bit: BM…
63772 … (0x1<<21) // This bit masks, when set, the Parity bit: BM…
63774 … (0x1<<22) // This bit masks, when set, the Parity bit: BM…
63776 … (0x1<<23) // This bit masks, when set, the Parity bit: BM…
63778 … (0x1<<24) // This bit masks, when set, the Parity bit: BM…
63780 … (0x1<<25) // This bit masks, when set, the Parity bit: BM…
63782 … (0x1<<26) // This bit masks, when set, the Parity bit: BM…
63784 … (0x1<<27) // This bit masks, when set, the Parity bit: BM…
63786 … (0x1<<28) // This bit masks, when set, the Parity bit: BM…
63788 … (0x1<<29) // This bit masks, when set, the Parity bit: BM…
63790 … (0x1<<30) // This bit masks, when set, the Parity bit: BM…
63793 … (0x1<<11) // This bit masks, when set, the Parity bit: BM…
63795 … (0x1<<0) // This bit masks, when set, the Parity bit: BM…
63797 … (0x1<<12) // This bit masks, when set, the Parity bit: BM…
63799 … (0x1<<1) // This bit masks, when set, the Parity bi…
63800 …MB_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_E5_SHIFT 1
63801 … (0x1<<2) // This bit masks, when set, the Parity bit: BM…
63803 … (0x1<<3) // This bit masks, when set, the Parity bit: BM…
63805 … (0x1<<4) // This bit masks, when set, the Parity bit: BM…
63807 … (0x1<<5) // This bit masks, when set, the Parity bit: BM…
63809 … (0x1<<6) // This bit masks, when set, the Parity bit: BM…
63811 … (0x1<<7) // This bit masks, when set, the Parity bit: BM…
63813 … (0x1<<8) // This bit masks, when set, the Parity bit: BM…
63815 … (0x1<<9) // This bit masks, when set, the Parity bit: BM…
63817 … (0x1<<10) // This bit masks, when set, the Parity bit: BM…
63819 … (0x1<<11) // This bit masks, when set, the Parity bit: BM…
63821 … (0x1<<12) // This bit masks, when set, the Parity bit: BM…
63823 … (0x1<<13) // This bit masks, when set, the Parity bit: BM…
63825 … (0x1<<14) // This bit masks, when set, the Parity bit: BM…
63827 … (0x1<<0) // This bit masks, when set, the Parity bit: BM…
63829 … (0x1<<15) // This bit masks, when set, the Parity bit: BM…
63831 … (0x1<<1) // This bit masks, when set, the Parity bi…
63832 …MB_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_BB_K2_SHIFT 1
63833 … (0x1<<16) // This bit masks, when set, the Parity bit: BM…
63835 … (0x1<<17) // This bit masks, when set, the Parity bit: BM…
63837 … (0x1<<18) // This bit masks, when set, the Parity bit: BM…
63839 … (0x1<<19) // This bit masks, when set, the Parity bit: BM…
63841 … (0x1<<20) // This bit masks, when set, the Parity bit: BM…
63843 … (0x1<<13) // This bit masks, when set, the Parity bit: BM…
63845 … (0x1<<21) // This bit masks, when set, the Parity bit: BM…
63847 … (0x1<<14) // This bit masks, when set, the Parity bit: BM…
63849 … (0x1<<22) // This bit masks, when set, the Parity bit: BM…
63851 … (0x1<<2) // This bit masks, when set, the Parity bit: BM…
63853 … (0x1<<3) // This bit masks, when set, the Parity bit: BM…
63855 … (0x1<<4) // This bit masks, when set, the Parity bit: BM…
63857 … (0x1<<5) // This bit masks, when set, the Parity bit: BM…
63859 … (0x1<<6) // This bit masks, when set, the Parity bit: BM…
63861 … (0x1<<7) // This bit masks, when set, the Parity bit: BM…
63863 … (0x1<<8) // This bit masks, when set, the Parity bit: BM…
63865 … (0x1<<9) // This bit masks, when set, the Parity bit: BM…
63867 … (0x1<<10) // This bit masks, when set, the Parity bit: BM…
63869 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63870 …OR[1].i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an e…
63871 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63872 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63873 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63874 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63875 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63876 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63877 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63878 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63879 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63880 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63881 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63882 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63883 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63884 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63888 … (0x1<<1) // Enable ECC for memory ecc instance bmb.BB_BANK_…
63889 …MB_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_EN_SHIFT 1
63919 … (0x1<<0) // Set parity only for memory ecc inst…
63921 … (0x1<<1) // Set parity only for memory ecc instance bmb.BB_BA…
63922 …MB_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_PRTY_SHIFT 1
63923 … (0x1<<2) // Set parity only for memory ecc inst…
63925 … (0x1<<3) // Set parity only for memory ecc inst…
63927 … (0x1<<4) // Set parity only for memory ecc inst…
63929 … (0x1<<5) // Set parity only for memory ecc inst…
63931 … (0x1<<6) // Set parity only for memory ecc inst…
63933 … (0x1<<7) // Set parity only for memory ecc inst…
63935 … (0x1<<8) // Set parity only for memory ecc inst…
63937 … (0x1<<9) // Set parity only for memory ecc inst…
63939 … (0x1<<10) // Set parity only for memory ecc inst…
63941 … (0x1<<11) // Set parity only for memory ecc inst…
63943 … (0x1<<12) // Set parity only for memory ecc inst…
63945 … (0x1<<13) // Set parity only for memory ecc inst…
63947 … (0x1<<14) // Set parity only for memory ecc inst…
63949 … (0x1<<15) // Set parity only for memory ecc inst…
63954 … (0x1<<1) // Record if a correctable error occurred on memory ecc instanc…
63955 …MB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_CORRECT_SHIFT 1
63985 … to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_…
63986 …04UL //Access:RW DataWidth:0xa // Number of valid bytes in header in 16-bytes resolution. Aft…
63994 … 0x540844UL //Access:RW DataWidth:0x3 // There is bit for each PACKET read client. When bit …
63995 …- SUM(tc_guarantied) Reset value is right for 128B block size only. It should be twice smaller for…
63996 …only. It should be twice smaller for 256B block size. When unified_shared_area is 1, then the thre…
63997 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
63998 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
63999 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
64000 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
64001 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
64002 …aranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice…
64003 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
64004 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
64005 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
64006 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
64007 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
64008 …ion for each TC in each LB port. Reset value is right for 128B block size only. It should be twice…
64009 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
64010 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
64011 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
64012 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
64013 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
64014 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
64015 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
64016 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
64017 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
64018 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
64019 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
64020 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
64021 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
64022 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
64023 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
64024 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
64025 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
64026 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
64027 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64028 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64029 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64030 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64031 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64032 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64033 …bit for each PACKET read client. Bit 0 suits to client 0 and so on. If bit is set then packet will…
64035 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64037 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64039 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64041 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64043 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64045 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64047 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64049 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64051 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64053 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64055 …bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then packet wil…
64056 …bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then highest pr…
64057 …is is priority for SOP read client to Big RAM arbiter. Possible values are 1-3. Priority 3 is high…
64058 …cket request of write client group to Big RAM arbiter. Possible values are 1-3. Priority 3 is high…
64059 …ll be done with round robin. Only one group with multiple clients of identical priority is support…
64069 …er management block when number of packets of appropriate TC is bigger than 1::s/COS_NUM/9/g in Da…
64076 … 0x540a70UL //Access:RW DataWidth:0x4 // Debug only: If more than this …
64080 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
64081 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
64082 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
64083 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
64089 …bit per each read client interface: TBD. When bit is set then appropriate interface is enabled. Wh…
64091 … (0x1<<10) // There is bit per SOP read client interface. When bit is set then appropriate int…
64093 …bit per write client interface: B0 - NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - …
64096 …bit per each read client interface: TBD. When bit is set then appropriate interface is enabled. Wh…
64098 … (0x1<<10) // There is bit per SOP read client interface. When bit is set then appropriate int…
64100 …bit for all pause interfaces per each MAC port. When bit is set then pause interface is enabled. W…
64102 …bit for packet avalable interfaces. When bit is set then packet avalable interface is enabled. Whe…
64104 …bit for power management interfaces. When bit is set then power management interface is enabled. …
64106 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64107 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64108 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64109 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64110 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64111 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64112 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64113 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64114 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64115 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64128 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64129 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64130 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64131 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64132 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64133 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64134 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64135 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64136 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64137 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64138 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64139 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64140 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64141 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64142 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64143 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64144 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64145 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64146 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64147 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64148 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64149 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64150 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64151 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64152 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64153 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64154 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64155 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64156 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64157 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64158 …4 // Debug register. Empty status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
64159 …x4 // Debug register. Full status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
64160 … register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr_fifo; B3:0-queue…
64212 …ess:R DataWidth:0x1 // Debug register. This is empty status of SOP SYNC INP FIFO for client 1
64220 …ess:R DataWidth:0x1 // Debug register. This is empty status of SOP SYNC out FIFO for client 1
64247 …room areas. When unified_shared_area is 1, then the value applies to the common area for all MAC p…
64252 …ter for each queue of each write client. It contains: b31 - valid; b30:16 - queue size; b15:0 - qu…
64254 …erface: TBD. Message spelling (MSB->LSB): rest_size_error[0]; len_error[0]; 1st_error[0]; middle_e…
64257 …face: TBD. Message spelling (MSB->LSB): opaque[1:0]; rls_to_do[15:0]; queue_number[3:0]; packet_le…
64280 …Access:RW DataWidth:0xc // Link list dual port memory that contains per-block descriptor::s/B…
64282 …544000UL //Access:RW DataWidth:0xa // This is a bitmap per WC which is 1 for WC with high pri…
64283 …544004UL //Access:RW DataWidth:0x1 // This is a bitmap per WC which is 1 for WC with high pri…
64284 … DataWidth:0x1 // When this bit is enabled, then BMC is connected and BMB WC9/RC2 is connected…
64285 … 0x560000UL //Access:RW DataWidth:0x1 // Initiate the ATC array - reset all the valid …
64287 …taWidth:0x20 // Logging register for reuse miss on transpend entry [31:0] - TID of the problemat…
64288 …taWidth:0x1c // Logging register for reuse miss on transpend entry [27:0] - ATC page index of th…
64289 …gister for reuse miss on transpend entry [11:0] - Reuse count of the problematic lookuprequest [23…
64290 …ster for the case of invalidation halt (lkpres of invalidated range) [31:0] - TID of the problemat…
64291 …ster for the case of invalidation halt (lkpres of invalidated range) [27:0] - ATC page index of th…
64292 …ster for the case of invalidation halt (lkpres of invalidated range) [11:0] - Reuse count of the p…
64294 …s of the PXP read requests issued by the PTU logic. [0:8] - ST index; [10:9] - ST hint; [11] - ST …
64301 … 0x560078UL //Access:RW DataWidth:0x20 // TID of the invalidated range - register per PF.
64302 … 0x56007cUL //Access:RW DataWidth:0x20 // Bit mask for the invali…
64303 …Bit per PF.Indicates that the data in inv_tid and inv_tid_mask is valid and invalidation should ta…
64304 … 0x560084UL //Access:RW DataWidth:0x1 // Bit per PF. Indicates that the marked invalidation i…
64305 … 0x560088UL //Access:RW DataWidth:0x1 // Bit per PF. If set, the…
64306 … 0x56008cUL //Access:RW DataWidth:0x1 // When set - the block will halt …
64307 … 0x560090UL //Access:RW DataWidth:0x3 // Max credits of the PBF->PXP interface.
64308 … 0x560094UL //Access:RW DataWidth:0x3 // Max credits of the PRM->PXP interface.
64309 … 0x560098UL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64310 … 0x56009cUL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64311 … 0x5600a0UL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64320 …-asserted then low priority request will replace a high priority entry only if there are no low pr…
64326 … 0x5600dcUL //Access:RW DataWidth:0x1 // Chicken bit for the atc otb ove…
64328 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
64329 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
64330 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
64331 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
64339 … (0x1<<1) // TCPL arrives to an entry not in Trans-…
64340 …TU_REG_INT_STS_ATC_TCPL_TO_NOT_PEND_SHIFT 1
64354 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
64356 … (0x1<<1) // This bit masks, when set, the Interrupt …
64357 …TU_REG_INT_MASK_ATC_TCPL_TO_NOT_PEND_SHIFT 1
64358 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
64360 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
64362 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
64364 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
64366 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
64368 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
64373 … (0x1<<1) // TCPL arrives to an entry not in Trans-…
64374 …TU_REG_INT_STS_WR_ATC_TCPL_TO_NOT_PEND_SHIFT 1
64390 … (0x1<<1) // TCPL arrives to an entry not in Trans-…
64391 …TU_REG_INT_STS_CLR_ATC_TCPL_TO_NOT_PEND_SHIFT 1
64405 … (0x1<<0) // This bit masks, when set, the Parity bit: PT…
64407 … (0x1<<1) // This bit masks, when set, the Parity bi…
64408 …TU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5_SHIFT 1
64409 … (0x1<<3) // This bit masks, when set, the Parity bit: PT…
64411 … (0x1<<2) // This bit masks, when set, the Parity bit: PT…
64413 … (0x1<<4) // This bit masks, when set, the Parity bit: PT…
64415 … (0x1<<3) // This bit masks, when set, the Parity bit: PT…
64417 … (0x1<<5) // This bit masks, when set, the Parity bit: PT…
64419 … (0x1<<4) // This bit masks, when set, the Parity bit: PT…
64421 … (0x1<<6) // This bit masks, when set, the Parity bit: PT…
64423 … (0x1<<5) // This bit masks, when set, the Parity bit: PT…
64425 … (0x1<<7) // This bit masks, when set, the Parity bit: PT…
64427 … (0x1<<6) // This bit masks, when set, the Parity bit: PT…
64429 … (0x1<<17) // This bit masks, when set, the Parity bit: PT…
64431 … (0x1<<7) // This bit masks, when set, the Parity bit: PT…
64433 … (0x1<<8) // This bit masks, when set, the Parity bit: PT…
64435 … (0x1<<12) // This bit masks, when set, the Parity bit: PT…
64437 … (0x1<<9) // This bit masks, when set, the Parity bit: PT…
64439 … (0x1<<2) // This bit masks, when set, the Parity bit: PT…
64441 … (0x1<<10) // This bit masks, when set, the Parity bit: PT…
64443 … (0x1<<15) // This bit masks, when set, the Parity bit: PT…
64445 … (0x1<<11) // This bit masks, when set, the Parity bit: PT…
64447 … (0x1<<14) // This bit masks, when set, the Parity bit: PT…
64449 … (0x1<<12) // This bit masks, when set, the Parity bit: PT…
64451 … (0x1<<16) // This bit masks, when set, the Parity bit: PT…
64453 … (0x1<<13) // This bit masks, when set, the Parity bit: PT…
64455 … (0x1<<13) // This bit masks, when set, the Parity bit: PT…
64457 … (0x1<<14) // This bit masks, when set, the Parity bit: PT…
64459 … (0x1<<9) // This bit masks, when set, the Parity bit: PT…
64461 … (0x1<<15) // This bit masks, when set, the Parity bit: PT…
64463 … (0x1<<11) // This bit masks, when set, the Parity bit: PT…
64465 … (0x1<<16) // This bit masks, when set, the Parity bit: PT…
64467 … (0x1<<0) // This bit masks, when set, the Parity bit: PT…
64469 … (0x1<<1) // This bit masks, when set, the Parity bi…
64470 …TU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_K2_SHIFT 1
64471 … (0x1<<10) // This bit masks, when set, the Parity bit: PT…
64474 … 0x560214UL //Access:RW DataWidth:0x1 // Set parity only for memory ecc inst…
64477 …00UL //Access:RW DataWidth:0x2 // Defines the number of sets - 3 - 512 ;2- 256; 1- 128; 0- 64.
64478 … 0x560404UL //Access:RW DataWidth:0x1 // If set the ATC will use only one way per set.
64479 …ne FIFO full bit; RCPL FIFO full bit; TCPL FIFO full bit; IREQ full bit; PLKP FIFO full bit; MLKP …
64480 …IFO empty bit; RCPL FIFO empty bit; TCPL FIFO empty bit; IREQ empty bit; PLKP FIFO empty bit; MLKP…
64481 … 0x560410UL //Access:RW DataWidth:0x1 // WaitIfMiss configuration bit.
64482 … 0x560414UL //Access:RW DataWidth:0x1 // WaitTransPending cofiguration bit.
64483 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64484 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64485 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64486 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64487 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64488 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64489 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64490 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64491 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64492 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64493 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64494 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64498 …only: defines the IFIFO almost full threshold. Its size can't be bigger than the Ireq FIFO size. T…
64509 … 0x560480UL //Access:RW DataWidth:0x1 // CheckTags configuration bit - when set the avail…
64510 … 0x560484UL //Access:RW DataWidth:0x8 // TAG threshold - for the checkTags fe…
64522 … 0x5604b4UL //Access:RW DataWidth:0x1 // Disable bit for the scrubbing e…
64523 … 0x5604b8UL //Access:RC DataWidth:0x20 // Number of hits for Main-lookups in the ATC.
64525 … 0x5604c0UL //Access:RC DataWidth:0x20 // Number of treqs issued due to pre-lookup.
64568 … 0x56056cUL //Access:RW DataWidth:0x1 // Relevant only if hash_en is set. …
64569 …seperation for the different errors is: BME clear [0]; Unsupported request [1]; Completer abort/co…
64570 …seperation for the different errors is: BME clear [0]; Unsupported request [1]; Completer abort/co…
64571 …erroneous TCPL: [12:0] Func (VF_Valid;VFID;PFID);[13] U bit; [14] W bit; [15] R bit; [16] NS bit; …
64572 … //Access:R DataWidth:0x20 // Data belongs to an erroneous TCPL: [31:0]-bits [31:0] of the ad…
64573 … //Access:R DataWidth:0x14 // Data belongs to an erroneous TCPL: [19:0]-bits [51:32] of the a…
64578 … 0x560594UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 31-0.
64579 … 0x560598UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 63-32.
64580 … 0x56059cUL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 95-64.
64581 … 0x5605a0UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 127-96.
64582 … 0x5605a4UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 159-128.
64583 … 0x5605a8UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 191-160.
64584 … 0x5605acUL //Access:R DataWidth:0x10 // Indicates the end of FLI flow for PF 15-0.
64585 …b0UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VF bits 31-0 accordingly.
64586 …b4UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VFbits 63-32 accordingly.
64587 …8UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VF bits 95-64 accordingly.
64588 …cUL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VFbits 127-96 accordingly.
64589 …L //Access:RW DataWidth:0x20 // Clears the FLI done indication for VF bits 159-128 accordingly.
64590 …UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VFbits 191-160 accordingly.
64591 …c8UL //Access:RW DataWidth:0x10 // Clears the FLI done indication for PF bits 15-0 accordingly.
64592 … 0x5605ccUL //Access:RW DataWidth:0x4 // Debug only: If more than this …
64610 …605e4UL //Access:RW DataWidth:0x8 // Resource Type of the invalidated range - register per PF.
64611 … 0x5605e8UL //Access:RW DataWidth:0x8 // Bit mask for the invali…
64612 …er for the case of invalidation halt (lkpres of invalidated range) [7:0] - Resource type of the…
64614 …x8 // Logging register for reuse miss on transpend entry bits [35:28] - of the problematic r…
64615 …Width:0x8 // Logging register for reuse miss on transpend entry [7:0] - Resource type of the…
64617 … 0x560600UL //Access:RW DataWidth:0x20 // TID of the invalidated range - register per Strom.
64619 … 0x560620UL //Access:RW DataWidth:0x20 // Bit mask for the invali…
64621 … 0x560640UL //Access:RW DataWidth:0x8 // TID of the invalidated range - register per Storm.
64623 … 0x560660UL //Access:RW DataWidth:0x8 // Bit mask for the invali…
64625 …Bit per Storm. Indicates that the data in inv_tid and inv_tid_mask is valid and invalidation shoul…
64627 …0x5606a0UL //Access:RW DataWidth:0x1 // Bit per Storm. Indicates that the marked invalidation…
64629 … 0x5606c0UL //Access:RW DataWidth:0x1 // Bit per PF. If set, the…
64631 …x40 // Access the GPA table way 0; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:…
64633 …taWidth:0x40 // Access the GPA table way 1; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]…
64635 …x40 // Access the GPA table way 2; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:…
64639 …h:0x40 // Access the GPA table way3; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID-…
64641 …- {par - [51]; NS bit - [50]; W bit - [49]; R bit - [48]; U bit - [47]; Priority bit - [46]; PLRU …
64643 … // Access the GPA table way 0; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64645 …dth:0x58 // Access the GPA table way 1; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reus…
64647 … // Access the GPA table way 2; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64649 … // Access the GPA table way3; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64651 …- { Priority bit - [23]; PLRU - [22]; Err bit - [21]; invpend bit [20]; transpend bit - [19]; vali…
64658 … (0x1<<1) // Enables CDU Inputs -- Must be…
64659 …DU_REG_CONTROL0_ENABLE_INPUTS_SHIFT 1
64660 … (0x1<<2) // Enables CDU Outputs -- Must be set for nor…
64668 … (0x1<<6) // Masks all PCIE Errors for Load transactions. NOTE -- This is not connecte…
64673 …M_ERROR (0x1<<1) // Number of L1s wi…
64674 …DU_REG_INT_STS_CCFC_LD_L1_NUM_ERROR_SHIFT 1
64690 …1_NUM_ERROR (0x1<<1) // Number of L1s wi…
64691 …DU_REG_INT_STS_CLR_CCFC_LD_L1_NUM_ERROR_SHIFT 1
64707 …_NUM_ERROR (0x1<<1) // Number of L1s wi…
64708 …DU_REG_INT_STS_WR_CCFC_LD_L1_NUM_ERROR_SHIFT 1
64722 … (0x1<<0) // This bit masks, when set, the Interrupt bit: C…
64724 … (0x1<<1) // This bit masks, when set, the Interrupt …
64725 …DU_REG_INT_MASK_CCFC_LD_L1_NUM_ERROR_SHIFT 1
64726 … (0x1<<2) // This bit masks, when set, the Interrupt bit: C…
64728 … (0x1<<3) // This bit masks, when set, the Interrupt bit: C…
64730 … (0x1<<4) // This bit masks, when set, the Interrupt bit: C…
64732 … (0x1<<5) // This bit masks, when set, the Interrupt bit: C…
64734 … (0x1<<6) // This bit masks, when set, the Interrupt bit: C…
64736 … (0x1<<7) // This bit masks, when set, the Interrupt bit: C…
64739 … (0x1<<0) // This bit masks, when set, the Parity bit: CD…
64741 … (0x1<<4) // This bit masks, when set, the Parity bit: CD…
64743 … (0x1<<1) // This bit masks, when set, the Parity bi…
64744 …DU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_E5_SHIFT 1
64745 … (0x1<<2) // This bit masks, when set, the Parity bit: CD…
64747 … (0x1<<1) // This bit masks, when set, the Parity bi…
64748 …DU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT 1
64749 … (0x1<<3) // This bit masks, when set, the Parity bit: CD…
64751 … (0x1<<3) // This bit masks, when set, the Parity bit: CD…
64755 …n for Region0 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64757 …n for Region1 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64759 …n for Region2 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64761 …n for Region3 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64764 …n for Region4 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64766 …n for Region5 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64768 …n for Region6 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64770 …n for Region7 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64773 …n for Region0 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64775 …n for Region1 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64777 …n for Region2 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64779 …n for Region3 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64782 …n for Region4 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64784 …n for Region5 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64786 …n for Region6 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64788 …n for Region7 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64790 …rols the Full signal to PXP. This register must never be set higher than 8 -- doing so will result…
64791 …ories when past this limit. This register must never be set higher than 13 -- doing so will result…
64799 … (0x1<<16) // TPH Valid bit for CCFC PXP Reques…
64801 … (0x1<<17) // Relaxed ordering bit for CCFC PXP rd_req.
64803 … (0x1<<18) // Relaxed ordering bit for CCFC PXP wr_req.
64805 … (0x1<<19) // No snoop bit for CCFC PXP rd_req.
64807 … (0x1<<20) // No snoop bit for CCFC PXP wr_req.
64816 … (0x1<<16) // TPH Valid bit for TCFC PXP Reques…
64818 … (0x1<<17) // Relaxed ordering bit for TCFC working me…
64820 … (0x1<<18) // Relaxed ordering bit for TCFC init memor…
64822 … (0x1<<19) // Relaxed ordering bit for TCFC working me…
64824 … (0x1<<20) // No snoop bit for TCFC working me…
64826 … (0x1<<21) // No snoop bit for TCFC init memor…
64828 … (0x1<<22) // No snoop bit for TCFC working me…
64835 … (0x7fff<<1) // Reserved Bits.
64836 …DU_REG_DEBUG_RESERVED_1_SHIFT 1
64850 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
64851 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
64852 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
64853 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
64872 … (0xfff<<12) // Block waste within a page. this number equals to PageSize-NCIB*ContextSize.
64904 … L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*…
64910 … L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*…
64911 … L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*…
64921 …th:0x4 // Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags com…
64922 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64923 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64924 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64925 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64926 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64927 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64928 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64929 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64930 …0x5a0030UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64931 …0x5a0034UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64932 …0x5a0038UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64933 …0x5a003cUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64936 …bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message wi…
64937 …//Access:R DataWidth:0x20 // Logging register for long message error: bit 0:3 Segment message…
64943 …5 (0x1<<1) // There is a probl…
64944 …TLD_REG_INT_STS_LD_HDR_ERR_E5_SHIFT 1
64945 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
64947 … (0x1<<3) // Mini cache error - meaning that A load …
64949 … (0x1<<4) // Mini cache error - meaning that A load …
64954 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
64956 … (0x1<<1) // This bit masks, when set, the Interrupt …
64957 …TLD_REG_INT_MASK_LD_HDR_ERR_E5_SHIFT 1
64958 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
64960 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
64962 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
64964 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
64969 …R_E5 (0x1<<1) // There is a probl…
64970 …TLD_REG_INT_STS_WR_LD_HDR_ERR_E5_SHIFT 1
64971 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
64973 … (0x1<<3) // Mini cache error - meaning that A load …
64975 … (0x1<<4) // Mini cache error - meaning that A load …
64982 …RR_E5 (0x1<<1) // There is a probl…
64983 …TLD_REG_INT_STS_CLR_LD_HDR_ERR_E5_SHIFT 1
64984 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
64986 … (0x1<<3) // Mini cache error - meaning that A load …
64988 … (0x1<<4) // Mini cache error - meaning that A load …
64993 … (0x1<<0) // This bit masks, when set, the Parity bit: PT…
64995 … (0x1<<1) // This bit masks, when set, the Parity bi…
64996 …TLD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_E5_SHIFT 1
64997 … (0x1<<2) // This bit masks, when set, the Parity bit: PT…
64999 … (0x1<<3) // This bit masks, when set, the Parity bit: PT…
65001 … (0x1<<4) // This bit masks, when set, the Parity bit: PT…
65003 … (0x1<<5) // This bit masks, when set, the Parity bit: PT…
65005 … (0x1<<6) // This bit masks, when set, the Parity bit: PT…
65007 … (0x1<<7) // This bit masks, when set, the Parity bit: PT…
65010 … 0x5a0214UL //Access:RW DataWidth:0x1 // Set parity only for memory ecc inst…
65013 … 0x5a0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
65018 …NORE_CM_AGG_MSG_E5 (0x1<<1) // indicates not to…
65019 …TLD_REG_L2MA_AGGR_CONFIG1_IGNORE_CM_AGG_MSG_E5_SHIFT 1
65020 … (0x1<<2) // defines that only back-to-back aggregatio…
65039 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
65041 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
65043 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
65045 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
65048 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
65050 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
65052 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
65054 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
65057 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
65059 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
65061 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
65063 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
65066 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
65068 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
65070 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
65072 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
65108 … 0x5a0824UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65109 … 0x5a0828UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65110 … 0x5a082cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65111 … 0x5a0830UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65112 … 0x5a0834UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65113 … 0x5a0838UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65114 … 0x5a083cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65115 … 0x5a0840UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65116 … 0x5a0844UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
65117 … 0x5a0848UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
65118 … 0x5a084cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
65119 … 0x5a0850UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
65120 … 0x5a0854UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
65121 … 0x5a0858UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
65122 … 0x5a085cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
65123 … 0x5a0860UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
65124 … 0x5a0864UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65125 … 0x5a0868UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65126 … 0x5a086cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65127 … 0x5a0870UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65128 … 0x5a0874UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65129 … 0x5a0878UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65130 … 0x5a087cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65131 … 0x5a0880UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65132 … 0x5a0884UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65133 … 0x5a0888UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65134 … 0x5a088cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65135 … 0x5a0890UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65136 … 0x5a0894UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65137 … 0x5a0898UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65138 … 0x5a089cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65139 … 0x5a08a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65141 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
65143 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
65145 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
65147 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
65150 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
65152 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
65154 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
65156 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
65159 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
65161 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
65163 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
65165 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
65168 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
65170 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
65172 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
65174 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
65213 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
65215 … (0x1<<1) // indication if to include the flow-ID in the stream…
65216 …TLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1_E5_SHIFT 1
65217 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
65219 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
65221 … (0x1f<<4) // offset of the flow-ID, in 32b units, fro…
65223 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
65225 … (0x1f<<14) // offset of the flow-ID, in 32b units, fro…
65227 … (0x1f<<19) // offset of the flow-ID, in 32b units, fro…
65232 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 1.
65241 … (0xf<<4) // the maximal number of children in a specific aggregation. for set 1.
65248 … (0xff<<0) // The value by which to increment the event-ID in case of success…
65250 …xff<<8) // The value by which to increment the event-ID in case of successful aggregation. for set…
65252 … (0xff<<16) // The value by which to increment the event-ID in case of success…
65254 … (0xff<<24) // The value by which to increment the event-ID in case of success…
65256 … 0x5a08d4UL //Access:RW DataWidth:0xc // maximum loader size in 256 bit words
65258 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
65259 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
65260 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
65261 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
65273 …th:0x4 // Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags com…
65274 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65275 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65276 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65277 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65278 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65279 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65280 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65281 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65282 …0x5c0030UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65283 …0x5c0034UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65284 …0x5c0038UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65285 …0x5c003cUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65288 …bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message wi…
65289 …//Access:R DataWidth:0x20 // Logging register for long message error: bit 0:3 Segment message…
65295 …5 (0x1<<1) // There is a probl…
65296 …PLD_REG_INT_STS_LD_HDR_ERR_E5_SHIFT 1
65297 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
65299 … (0x1<<3) // Mini cache error - meaning that A load …
65301 … (0x1<<4) // Mini cache error - meaning that A load …
65306 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Y…
65308 … (0x1<<1) // This bit masks, when set, the Interrupt …
65309 …PLD_REG_INT_MASK_LD_HDR_ERR_E5_SHIFT 1
65310 … (0x1<<2) // This bit masks, when set, the Interrupt bit: Y…
65312 … (0x1<<3) // This bit masks, when set, the Interrupt bit: Y…
65314 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Y…
65316 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Y…
65321 …R_E5 (0x1<<1) // There is a probl…
65322 …PLD_REG_INT_STS_WR_LD_HDR_ERR_E5_SHIFT 1
65323 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
65325 … (0x1<<3) // Mini cache error - meaning that A load …
65327 … (0x1<<4) // Mini cache error - meaning that A load …
65334 …RR_E5 (0x1<<1) // There is a probl…
65335 …PLD_REG_INT_STS_CLR_LD_HDR_ERR_E5_SHIFT 1
65336 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
65338 … (0x1<<3) // Mini cache error - meaning that A load …
65340 … (0x1<<4) // Mini cache error - meaning that A load …
65345 … (0x1<<0) // This bit masks, when set, the Parity bit: YP…
65347 … (0x1<<1) // This bit masks, when set, the Parity bi…
65348 …PLD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_E5_SHIFT 1
65349 … (0x1<<2) // This bit masks, when set, the Parity bit: YP…
65351 … (0x1<<3) // This bit masks, when set, the Parity bit: YP…
65353 … (0x1<<4) // This bit masks, when set, the Parity bit: YP…
65355 … (0x1<<5) // This bit masks, when set, the Parity bit: YP…
65357 … (0x1<<6) // This bit masks, when set, the Parity bit: YP…
65359 … (0x1<<7) // This bit masks, when set, the Parity bit: YP…
65362 … 0x5c0214UL //Access:RW DataWidth:0x1 // Set parity only for memory ecc inst…
65365 … 0x5c0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
65370 …NORE_CM_AGG_MSG_E5 (0x1<<1) // indicates not to…
65371 …PLD_REG_L2MA_AGGR_CONFIG1_IGNORE_CM_AGG_MSG_E5_SHIFT 1
65372 … (0x1<<2) // defines that only back-to-back aggregatio…
65391 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
65393 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
65395 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
65397 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
65400 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
65402 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
65404 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
65406 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
65409 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
65411 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
65413 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
65415 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
65418 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
65420 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
65422 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
65424 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
65460 … 0x5c0824UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65461 … 0x5c0828UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65462 … 0x5c082cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65463 … 0x5c0830UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65464 … 0x5c0834UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65465 … 0x5c0838UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65466 … 0x5c083cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65467 … 0x5c0840UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65468 … 0x5c0844UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
65469 … 0x5c0848UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
65470 … 0x5c084cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
65471 … 0x5c0850UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
65472 … 0x5c0854UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
65473 … 0x5c0858UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
65474 … 0x5c085cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
65475 … 0x5c0860UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 par…
65476 … 0x5c0864UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65477 … 0x5c0868UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65478 … 0x5c086cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65479 … 0x5c0870UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65480 … 0x5c0874UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65481 … 0x5c0878UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65482 … 0x5c087cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65483 … 0x5c0880UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65484 … 0x5c0884UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65485 … 0x5c0888UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65486 … 0x5c088cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65487 … 0x5c0890UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65488 … 0x5c0894UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65489 … 0x5c0898UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65490 … 0x5c089cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65491 … 0x5c08a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65493 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
65495 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
65497 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
65499 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
65502 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
65504 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
65506 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
65508 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
65511 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
65513 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
65515 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
65517 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
65520 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
65522 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
65524 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
65526 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
65565 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
65567 … (0x1<<1) // indication if to include the flow-ID in the stream…
65568 …PLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1_E5_SHIFT 1
65569 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
65571 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
65573 … (0x1f<<4) // offset of the flow-ID, in 32b units, fro…
65575 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
65577 … (0x1f<<14) // offset of the flow-ID, in 32b units, fro…
65579 … (0x1f<<19) // offset of the flow-ID, in 32b units, fro…
65584 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 1.
65593 … (0xf<<4) // the maximal number of children in a specific aggregation. for set 1.
65600 … (0xff<<0) // The value by which to increment the event-ID in case of success…
65602 …xff<<8) // The value by which to increment the event-ID in case of successful aggregation. for set…
65604 … (0xff<<16) // The value by which to increment the event-ID in case of success…
65606 … (0xff<<24) // The value by which to increment the event-ID in case of success…
65608 … 0x5c08d4UL //Access:RW DataWidth:0xc // maximum loader size in 256 bit words
65610 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
65611 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
65612 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
65613 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
65626 … (0x1<<0) // This bit masks, when set, the Interrupt bit: W…
65635 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
65636 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
65637 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
65638 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
65644 … (0x1<<0) // This bit masks, when set, the Parity bit: WO…
65646 … (0x1<<1) // This bit masks, when set, the Parity bi…
65647 …OL_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2_E5_SHIFT 1
65648 … (0x1<<2) // This bit masks, when set, the Parity bit: WO…
65650 … (0x1<<3) // This bit masks, when set, the Parity bit: WO…
65652 … (0x1<<4) // This bit masks, when set, the Parity bit: WO…
65654 … (0x1<<5) // This bit masks, when set, the Parity bit: WO…
65656 … (0x1<<6) // This bit masks, when set, the Parity bit: WO…
65658 … (0x1<<7) // This bit masks, when set, the Parity bit: WO…
65660 … (0x1<<8) // This bit masks, when set, the Parity bit: WO…
65662 … (0x1<<9) // This bit masks, when set, the Parity bit: WO…
65664 … (0x1<<10) // This bit masks, when set, the Parity bit: WO…
65666 … (0x1<<11) // This bit masks, when set, the Parity bit: WO…
65668 … (0x1<<12) // This bit masks, when set, the Parity bit: WO…
65670 … (0x1<<13) // This bit masks, when set, the Parity bit: WO…
65672 … (0x1<<14) // This bit masks, when set, the Parity bit: WO…
65674 … (0x1<<15) // This bit masks, when set, the Parity bit: WO…
65676 … (0x1<<16) // This bit masks, when set, the Parity bit: WO…
65678 … (0x1<<17) // This bit masks, when set, the Parity bit: WO…
65680 … (0x1<<18) // This bit masks, when set, the Parity bit: WO…
65682 … (0x1<<19) // This bit masks, when set, the Parity bit: WO…
65684 … (0x1<<20) // This bit masks, when set, the Parity bit: WO…
65686 … (0x1<<21) // This bit masks, when set, the Parity bit: WO…
65688 … (0x1<<22) // This bit masks, when set, the Parity bit: WO…
65690 … (0x1<<23) // This bit masks, when set, the Parity bit: WO…
65693 …-port per-PF register. L2 tag removal configuration for ACPI. Bit mapped as follow: bit 0: 5 - L…
65694 …ataWidth:0x1 // Set this bit to enable ACPI and TCP SYN matching even when the packet is forwar…
65695 … 0x608080UL //Access:WB DataWidth:0x100 // This is a per-port per-PF register. Byt…
65697 …ataWidth:0x1 // This is a per-port register. When this bit is set ACPI packet recognition wil…
65698 … 0x608104UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65699 … 0x608108UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65700 …810cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC32C for pattern 1.
65701 … 0x608110UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65702 … 0x608114UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65703 … 0x608118UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65704 … 0x60811cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65705 … 0x608120UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65706 … 0x608124UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65707 … 0x608128UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65708 … 0x60812cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65709 … 0x608130UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65710 … 0x608134UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65711 … 0x608138UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65712 … 0x60813cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65713 … 0x608140UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65714 …idth:0x1 // This is a per-port per-PF register. When this bit is set Magic Packet recognition…
65715 … 0x608148UL //Access:WB DataWidth:0x30 // This is a per-port per-PF register. MAC…
65717 …/Access:RW DataWidth:0x1 // This is a per-port per-PF register. A low-to-high transition of …
65718 … 0x608160UL //Access:WB_R DataWidth:0x100 // Read-only data from the Wake…
65720 …- a low-to-high transition of this bit clears the wake_info, wake_pkt_len, and wake_details regist…
65721 …- all fields are sticky. Bits 15:0 - PF Vector: The bit-mapped vector indicating which of the gl…
65722 …length - the actual length of the 'wake' packet, in bytes. This register is sticky and is cleared …
65723 …- all fields are sticky. Bits 7:0 - ACPI MATCH: Per-function bit-mapped result from ACPI patte…
65724 … 0x608190UL //Access:RW DataWidth:0x3 // This bit selects the default…
65725 …1: Select patterns based on static PF selection - acpi_default_pf_sel. 2: Select the first of each…
65726 …cess:RW DataWidth:0x2 // This is a per-PF register. Set bit 0 to enable wake on IPv4 TCP SYN…
65727 …W DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Vali…
65728 …W DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Vali…
65729 …W DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Vali…
65730 …W DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Vali…
65731 …W DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Vali…
65732 …W DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Vali…
65743 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
65752 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
65753 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
65754 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
65755 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
65764 …ride for management packets. This field consists of {3-bit priority, 1-bit drop eligible, 12-bit …
65765 …ride for management packets. This field consists of {3-bit priority, 1-bit drop eligible, 12-bit …
65766 …W DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Vali…
65767 …01fcUL //Access:RW DataWidth:0x10 // The Ethernet type value for L2 tag 1. The reset value is…
65772 … 0x624000UL //Access:RW DataWidth:0x10 // AHB bus for pcie_phy 1.
65818 …_SOFT_RESET_CONTROL_SOFT_PHY_RST_N_K2_E5 (0x1<<1) //
65819 …HY_PCIE_REG_SOFT_RESET_CONTROL_SOFT_PHY_RST_N_K2_E5_SHIFT 1
65821 … (0xff<<0) // Firmware must set this bit to 1 after finished co…
65823 … (0x1<<8) // Firmware must set this bit to 1 after finished co…
65828 …_PHY_STATUS_PHY1_CMU_OK_O_K2_E5 (0x1<<1) //
65829 …HY_PCIE_REG_PHY_STATUS_PHY1_CMU_OK_O_K2_E5_SHIFT 1
65836 … 0x628018UL //Access:RW DataWidth:0x10 // Bit masks to be ANDed w…
65865 …5 (0x1<<0) // When set to 1, represents FW exists
65867 …MU_RESET_OVR_K2_E5 (0x1<<1) // When set to 0, H…
65868 …HY_PCIE_REG_HW_INIT_CONFIG_CMU_RESET_OVR_K2_E5_SHIFT 1
65877 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
65878 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
65879 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
65880 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
65882 …_i reset signal into the SerDes. This should be 0 (Reset value) write 1 to this bit to allow the S…
65884 …ETN_I_K2_E5 (0x1<<1) // Active low. Can …
65885 …S_REG_COMMON_CONTROL_CMU_RESETN_I_K2_E5_SHIFT 1
65886 …d on CMU0 in multiple CMU PHYs if there are any active lanes. Signal is over-riden by por_n_i so h…
65888 … (0x1<<3) // Turn off CMU master bias only. Cannot be asserted…
65890 … (0x3<<4) // Divider control for SOC 1 clock for both CMUs. 00 = Divide by 1 0…
65896 … (0x1<<8) // Turn off CMU master bias only. Cannot be asserted…
65898 … (0x3<<9) // Divider control for SOC 1 clock for both CMUs. 00 = Divide by 1 0…
65905 …down mode enable signal. ln1_pd[0] = Lane partial power down enable. ln1_pd[1] = Lane Slumber powe…
65911 …- rxsig_det_mask_i 16 - rxeii_exit_type_i 15 - rxei_infer_i 14 - bslip_req_i 13 - data_width_i - 0…
65915 …pcs_sdet 0 - ln1_stat_o[2] (RX Locked indicator) 1 - ln1_astat_o[5] (Raw signal detext indicator)…
65920 …2_E5 (0x1<<1) // Indicates CMU1 P…
65921 …S_REG_CMU_STATUS_CMU1_OK_O_K2_E5_SHIFT 1
65923 …- not used 12 - ln1_ok_o 11 - ln1_runlen_err_o 10:4 - not used 3:2 - ln1_rx_locked_o - bit 3 =rxda…
65925 …(0x3f<<14) // 19 - Raw signal detect - Bit Slip Ack 18 - ln1_bitslip_ack_o - Bit Slip Ack 17 - not…
65945 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
65958 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
65959 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
65960 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
65961 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
65962 … 0x6a023cUL //Access:RW DataWidth:0x4 // Debug only: If more than this …
65963 … 0x6a0240UL //Access:R DataWidth:0x5 // Debug only: Fill level of dbgm…
65964 … 0x6a0244UL //Access:RW DataWidth:0x14 // Debug only: Sampling interval …
65965 …48UL //Access:RW DataWidth:0x4 // Debug only: If 0 or 1, trigger on first occurrence. If grea…
65966 … 0x6a024cUL //Access:RW DataWidth:0x18 // Debug only: If greater than 0,…
65967 … 0x6a0250UL //Access:RW DataWidth:0x1 // Debug only: FW trigger is set.
65968 …-0x1ff. Reserved = 0x200-0x3ff. LANE1 registers = 0x400-0x5ff. Reserved = 0x600-0x7f…
65975 …SEL_K2 (0x3<<1) // Mode selection d…
65976 …VS_WRAP_REG_AVS_CONTROL_MODESEL_K2_SHIFT 1
65977 … registers belonging to set0 1: Using registers belonging to set1 SETS_W-1: Using set of registers…
65979 …orresponding bit in the AVSC_FLOW_CTRL is enabled. Bit [0] : corresponds to FLOW 1 Bit [1] : corre…
65984 … (0x3<<1) // It replicates the mode-sel val…
65985 …VS_WRAP_REG_AVS_INDICATION_CORE_MODEACK_K2_SHIFT 1
65986 … (0x7<<3) // It replicates the set-sel value when voltag…
65996 … (0x1<<0) // This bit masks, when set, the Interrupt bit: A…
65998 … (0x1<<2) // This bit masks, when set, the Interrupt bit: A…
66011 … (0x1<<0) // This bit masks, when set, the Parity bit: AV…
66013 … (0x1<<1) // This bit masks, when set, the Parity bi…
66014 …VS_WRAP_REG_PRTY_MASK_MEANSMEM_PERR_K2_SHIFT 1
66015 … (0x1<<2) // This bit masks, when set, the Parity bit: AV…
66018 … 0x6b402cUL //Access:R DataWidth:0x20 // Read only line 16 of eFuse da…
66019 … 0x6b4030UL //Access:R DataWidth:0x20 // Read only line 17 of eFuse da…
66020 … 0x6b4034UL //Access:R DataWidth:0x20 // Read only line 18 of eFuse da…
66021 … 0x6b4038UL //Access:R DataWidth:0x20 // Read only line 19 of eFuse da…
66022 … 0x6b403cUL //Access:R DataWidth:0x20 // Read only line 20 of eFuse da…
66023 … 0x6b4040UL //Access:R DataWidth:0x20 // Read only line 21 of eFuse da…
66024 … 0x6b4044UL //Access:R DataWidth:0x20 // Read only line 22 of eFuse da…
66025 … 0x6b4048UL //Access:R DataWidth:0x20 // Read only line 23 of eFuse da…
66027 …re control of the Traffic LED. The Traffic LED will then be controlled via bit LED_CONTROL_TRAFFIC…
66029 …ng with the LED_CONTROL_OVERRIDE_TRAFFIC bit turns on the Traffic LED. If the LED_CONTROL_BLINK_TR…
66031 …<<8) // If set along with the LED_CONTROL_OVERRIDE_TRAFFIC bit and LED_CONTROL_TRAFFIC LED bit; th…
66033 … (0x1<<12) // This bit is set to enable the use of the LED_CONTROL_BLINK_RATE field de…
66035 …1<<13) // This bit is set to enable the alternating between activity and speed LEDs of the same po…
66039 …-> MAC; 1-2 -> PHY1; 3 -> PHY3; 4 -> MAC2; 5-6 -> PHY4; 7 -> PHY6; 8 -> MAC3; …
66040 …ss:RW DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G A '1'…
66041 …ss:RW DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G A '1'…
66042 …ss:RW DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G A '1'…
66043 …-> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G This register allows the MAC (Driver/FW) to set …
66045 …only two sets of the the bits below are valid. a Four port device has all four sets of bits valid.…
66047 … Network Port 1 to the corresponding Physical function. 0 -> NW1 connects to PF0 1 -> NW1 connec…
66049 … corresponding Physical function. 0 -> NW2 connects to PF0 1 -> NW2 connects to PF1 2 -> NW2 co…
66051 … corresponding Physical function. 0 -> NW3 connects to PF0 1 -> NW3 connects to PF1 2 -> NW3 co…
66053 …1cUL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66054 …20UL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66055 …24UL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66056 …28UL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66057 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
66062 … (0x1<<0) // This bit masks, when set, the Interrupt bit: L…
66071 …the internal reset and TX resync sequence is initiated. 0 Normal Operation. 1 Reset. This reset si…
66073 …DE_E5 (0x1<<1) // Receiver AC-coupling Mode…
66074 …WS_REG_HSS0_CONTROL_COMMON_HSS0RXACMODE_E5_SHIFT 1
66075 …5 (0x1<<2) // Power-On-Reset Power Enable. …
66081 …o select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pllA (1G …
66084 …<0) // 0x0 - Select reference clock from Bump 0x1 - Select inter-macro refrence clock from the lef…
66086 … (0x3<<2) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro ref…
66088 … (0x3<<4) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro re…
66090 …l is used for nws_nwm_sd_energy_detect. 0 - use ~lnX_stat_los_o 1 - use ~lnX_stat_los_deglitch_o (…
66094 … This holds the SerDes in Reset. Once the memory is configured, write 1 to this bit to allow the S…
66096 …s. This should be 0 (Reset value) This holds the cmu0 in Reset. write 1 to this bit to allow the S…
66098 …s. This should be 0 (Reset value) This holds the cmu0 in Reset. write 1 to this bit to allow the S…
66100 …e SerDes. This should be 0 (Reset value) This holds the ln0 in Reset. write 1 to begin normal Oper…
66102 …e SerDes. This should be 0 (Reset value) This holds the ln1 in Reset. write 1 to begin normal Oper…
66104 …e SerDes. This should be 0 (Reset value) This holds the ln2 in Reset. write 1 to begin normal Oper…
66106 …e SerDes. This should be 0 (Reset value) This holds the ln3 in Reset. write 1 to begin normal Oper…
66108 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66110 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66112 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66114 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66116 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66118 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66121 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66128 … (0x1f<<0) // Sets phy_ctrl_refclk_i used for CMU0 0x09 - refclk is 257.8125Mhz
66130 … Sets phy_ctrl_rate1_i used for CMU0 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125…
66132 … Sets phy_ctrl_rate1_i used for CMU1 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125…
66137 …HSS0RESYNCA_E5 (0x1<<1) // Core Resync
66138 …WS_REG_HSS0_CONTROL1A_HSS0RESYNCA_E5_SHIFT 1
66148 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66150 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66152 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66154 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66157 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66164 … (0x1<<0) // 0x0 - No error 0x1 - Phy has inter…
66166 … (0x1<<1) // 0x1 - Indicates CMU0 …
66167 …WS_REG_COMMON_STATUS_CM0_OK_O_K2_SHIFT 1
66168 … (0x1<<2) // 0x1 - Indicates CMU1 PLL h…
66170 …- PHY is not ready to respond to cm0_rst_n_i and cm0_pd_i[1:0]. The signals should not be changed.…
66172 …- PHY is not ready to respond to cm1_rst_n_i and cm1_pd_i[1:0]. The signals should not be changed.…
66174 …- PHY is not ready to respond to ln0_rst_n_i and ln0_pd_i[1:0]. The signals should not be changed.…
66176 …- PHY is not ready to respond to ln1_rst_n_i and ln1_pd_i[1:0]. The signals should not be changed.…
66178 …- PHY is not ready to respond to ln2_rst_n_i and ln2_pd_i[1:0]. The signals should not be changed.…
66180 …- PHY is not ready to respond to ln3_rst_n_i and ln3_pd_i[1:0]. The signals should not be changed.…
66185 …HSS0RESYNCB_E5 (0x1<<1) // Core Resync
66186 …WS_REG_HSS0_CONTROL1B_HSS0RESYNCB_E5_SHIFT 1
66196 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66198 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66200 … 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS…
66204 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66207 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66209 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66210 …WS_REG_HSS0_STATUS_HSS0PLLLOCKB_E5_SHIFT 1
66211 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66213 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after…
66215 … (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX lin…
66218 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66220 … (0x1<<1) // 0x0 - data on ln0_rxdata_o is invalid. 0x…
66221 …WS_REG_LN0_STATUS_LN0_STAT_RXVALID_K2_SHIFT 1
66222 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66224 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. …
66226 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. …
66229 …the internal reset and TX resync sequence is initiated. 0 Normal Operation. 1 Reset. This reset si…
66231 …DE_E5 (0x1<<1) // Receiver AC-coupling Mode…
66232 …WS_REG_HSS1_CONTROL_COMMON_HSS1RXACMODE_E5_SHIFT 1
66233 …5 (0x1<<2) // Power-On-Reset Power Enable. …
66239 …o select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pllA (1G …
66242 …_50G_CR2_I_K2 (0x1<<0) // Set to 1 if the respective li…
66244 …STATUS_50G_KR2_I_K2 (0x1<<1) // Set to 1 if the respect…
66245 …WS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_50G_KR2_I_K2_SHIFT 1
66246 …_40G_CR4_I_K2 (0x1<<2) // Set to 1 if the respective li…
66248 …_40G_KR4_I_K2 (0x1<<3) // Set to 1 if the respective li…
66250 …_25G_CR_I_K2 (0x1<<4) // Set to 1 if the respective li…
66252 …_25G_GR_I_K2 (0x1<<5) // Set to 1 if the respective li…
66254 …_25G_KR_I_K2 (0x1<<6) // Set to 1 if the respective li…
66256 …_10G_KR_I_K2 (0x1<<7) // Set to 1 if the respective li…
66258 …_1G_KX_I_K2 (0x1<<8) // Set to 1 if the respective li…
66261 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66268 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66270 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66272 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66274 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66276 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66278 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66280 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66282 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66284 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66288 …-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high,…
66290 …C and transmitted from the output of the transmitter. When this signal is a 1, it allows the trans…
66292 …bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are sub…
66294 …s the negotiated output enable signal for the Fire-code forward error correction. If this output i…
66296 …the negotiated output enable signal for the Reed-Solomon forward error correction. If this output …
66298 …ve high signal that indicates the resolved EEE capability. If the output is 1, both the local devi…
66303 …HSS1RESYNCA_E5 (0x1<<1) // Core Resync
66304 …WS_REG_HSS1_CONTROL1A_HSS1RESYNCA_E5_SHIFT 1
66314 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66316 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66318 … 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS…
66322 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66325 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66332 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66334 … (0x1<<1) // 0x0 - data on ln1_rxdata_o is invalid. 0x…
66335 …WS_REG_LN1_STATUS_LN1_STAT_RXVALID_K2_SHIFT 1
66336 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66338 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. …
66340 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. …
66345 …HSS1RESYNCB_E5 (0x1<<1) // Core Resync
66346 …WS_REG_HSS1_CONTROL1B_HSS1RESYNCB_E5_SHIFT 1
66356 …_50G_CR2_I_K2 (0x1<<0) // Set to 1 if the respective li…
66358 …STATUS_50G_KR2_I_K2 (0x1<<1) // Set to 1 if the respect…
66359 …WS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_50G_KR2_I_K2_SHIFT 1
66360 …_40G_CR4_I_K2 (0x1<<2) // Set to 1 if the respective li…
66362 …_40G_KR4_I_K2 (0x1<<3) // Set to 1 if the respective li…
66364 …_25G_CR_I_K2 (0x1<<4) // Set to 1 if the respective li…
66366 …_25G_GR_I_K2 (0x1<<5) // Set to 1 if the respective li…
66368 …_25G_KR_I_K2 (0x1<<6) // Set to 1 if the respective li…
66370 …_10G_KR_I_K2 (0x1<<7) // Set to 1 if the respective li…
66372 …_1G_KX_I_K2 (0x1<<8) // Set to 1 if the respective li…
66375 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66377 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66378 …WS_REG_HSS1_STATUS_HSS1PLLLOCKB_E5_SHIFT 1
66379 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66381 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after…
66383 … (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX lin…
66386 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66388 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66390 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66392 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66394 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66396 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66398 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66400 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66402 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66406 …-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high,…
66408 …C and transmitted from the output of the transmitter. When this signal is a 1, it allows the trans…
66410 …bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are sub…
66412 …s the negotiated output enable signal for the Fire-code forward error correction. If this output i…
66414 …the negotiated output enable signal for the Reed-Solomon forward error correction. If this output …
66416 …ve high signal that indicates the resolved EEE capability. If the output is 1, both the local devi…
66419 …the internal reset and TX resync sequence is initiated. 0 Normal Operation. 1 Reset. This reset si…
66421 …DE_E5 (0x1<<1) // Receiver AC-coupling Mode…
66422 …WS_REG_HSS2_CONTROL_COMMON_HSS2RXACMODE_E5_SHIFT 1
66423 …5 (0x1<<2) // Power-On-Reset Power Enable. …
66429 …o select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pllA (1G …
66432 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66434 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66436 … 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS…
66440 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66443 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66450 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66452 … (0x1<<1) // 0x0 - data on ln2_rxdata_o is invalid. 0x…
66453 …WS_REG_LN2_STATUS_LN2_STAT_RXVALID_K2_SHIFT 1
66454 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66456 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. …
66458 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. …
66463 …HSS2RESYNCA_E5 (0x1<<1) // Core Resync
66464 …WS_REG_HSS2_CONTROL1A_HSS2RESYNCA_E5_SHIFT 1
66474 …_50G_CR2_I_K2 (0x1<<0) // Set to 1 if the respective li…
66476 …STATUS_50G_KR2_I_K2 (0x1<<1) // Set to 1 if the respect…
66477 …WS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_50G_KR2_I_K2_SHIFT 1
66478 …_40G_CR4_I_K2 (0x1<<2) // Set to 1 if the respective li…
66480 …_40G_KR4_I_K2 (0x1<<3) // Set to 1 if the respective li…
66482 …_25G_CR_I_K2 (0x1<<4) // Set to 1 if the respective li…
66484 …_25G_GR_I_K2 (0x1<<5) // Set to 1 if the respective li…
66486 …_25G_KR_I_K2 (0x1<<6) // Set to 1 if the respective li…
66488 …_10G_KR_I_K2 (0x1<<7) // Set to 1 if the respective li…
66490 …_1G_KX_I_K2 (0x1<<8) // Set to 1 if the respective li…
66493 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66500 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66502 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66504 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66506 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66508 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66510 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66512 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66514 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66516 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66520 …-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high,…
66522 …C and transmitted from the output of the transmitter. When this signal is a 1, it allows the trans…
66524 …bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are sub…
66526 …s the negotiated output enable signal for the Fire-code forward error correction. If this output i…
66528 …the negotiated output enable signal for the Reed-Solomon forward error correction. If this output …
66530 …ve high signal that indicates the resolved EEE capability. If the output is 1, both the local devi…
66535 …HSS2RESYNCB_E5 (0x1<<1) // Core Resync
66536 …WS_REG_HSS2_CONTROL1B_HSS2RESYNCB_E5_SHIFT 1
66546 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66548 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66550 … 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS…
66554 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66557 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66559 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66560 …WS_REG_HSS2_STATUS_HSS2PLLLOCKB_E5_SHIFT 1
66561 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66563 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after…
66565 … (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX lin…
66568 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66570 … (0x1<<1) // 0x0 - data on ln3_rxdata_o is invalid. 0x…
66571 …WS_REG_LN3_STATUS_LN3_STAT_RXVALID_K2_SHIFT 1
66572 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66574 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. …
66576 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. …
66579 …the internal reset and TX resync sequence is initiated. 0 Normal Operation. 1 Reset. This reset si…
66581 …DE_E5 (0x1<<1) // Receiver AC-coupling Mode…
66582 …WS_REG_HSS3_CONTROL_COMMON_HSS3RXACMODE_E5_SHIFT 1
66583 …5 (0x1<<2) // Power-On-Reset Power Enable. …
66589 …o select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pllA (1G …
66592 …_50G_CR2_I_K2 (0x1<<0) // Set to 1 if the respective li…
66594 …STATUS_50G_KR2_I_K2 (0x1<<1) // Set to 1 if the respect…
66595 …WS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_50G_KR2_I_K2_SHIFT 1
66596 …_40G_CR4_I_K2 (0x1<<2) // Set to 1 if the respective li…
66598 …_40G_KR4_I_K2 (0x1<<3) // Set to 1 if the respective li…
66600 …_25G_CR_I_K2 (0x1<<4) // Set to 1 if the respective li…
66602 …_25G_GR_I_K2 (0x1<<5) // Set to 1 if the respective li…
66604 …_25G_KR_I_K2 (0x1<<6) // Set to 1 if the respective li…
66606 …_10G_KR_I_K2 (0x1<<7) // Set to 1 if the respective li…
66608 …_1G_KX_I_K2 (0x1<<8) // Set to 1 if the respective li…
66611 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66618 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66620 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66622 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66624 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66626 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66628 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66630 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66632 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66634 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66638 …-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high,…
66640 …C and transmitted from the output of the transmitter. When this signal is a 1, it allows the trans…
66642 …bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are sub…
66644 …s the negotiated output enable signal for the Fire-code forward error correction. If this output i…
66646 …the negotiated output enable signal for the Reed-Solomon forward error correction. If this output …
66648 …ve high signal that indicates the resolved EEE capability. If the output is 1, both the local devi…
66653 …HSS3RESYNCA_E5 (0x1<<1) // Core Resync
66654 …WS_REG_HSS3_CONTROL1A_HSS3RESYNCA_E5_SHIFT 1
66664 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66673 …HSS3RESYNCB_E5 (0x1<<1) // Core Resync
66674 …WS_REG_HSS3_CONTROL1B_HSS3RESYNCB_E5_SHIFT 1
66684 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66686 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66687 …WS_REG_HSS3_STATUS_HSS3PLLLOCKB_E5_SHIFT 1
66688 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66690 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after…
66692 … (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX lin…
66695 … bit 10 of Receiver Configuration Mode Register is set to �1�. Otherwise, these pins are ignored. …
66697 …bit to be discarded from the recovered data stream, which results in a 1-bit alignment adjustment.…
66699 …bit 4, each rising edge of this input moves the rotator control logic down by one step. Early info…
66701 …bit 4, each rising edge of this input moves the rotator control logic up by one step. Late informa…
66703 …ust be �1� to enable this. This signal must maintain a level for a minimum of one C16 cycle to be …
66705 …ust be �1� to enable this. This signal must maintain a level for a minimum of one C16 cycle to be …
66707 …nals. 0 Disabled (normal operation). 1 Enabled (external control of phase rotators). Note: Do not …
66710 … bit 10 of Receiver Configuration Mode Register is set to �1�. Otherwise, these pins are ignored. …
66712 …bit to be discarded from the recovered data stream, which results in a 1-bit alignment adjustment.…
66714 …bit 4, each rising edge of this input moves the rotator control logic down by one step. Early info…
66716 …bit 4, each rising edge of this input moves the rotator control logic up by one step. Late informa…
66718 …ust be �1� to enable this. This signal must maintain a level for a minimum of one C16 cycle to be …
66720 …ust be �1� to enable this. This signal must maintain a level for a minimum of one C16 cycle to be …
66722 …nals. 0 Disabled (normal operation). 1 Enabled (external control of phase rotators). Note: Do not …
66725 … bit 10 of Receiver Configuration Mode Register is set to �1�. Otherwise, these pins are ignored. …
66727 …bit to be discarded from the recovered data stream, which results in a 1-bit alignment adjustment.…
66729 …bit 4, each rising edge of this input moves the rotator control logic down by one step. Early info…
66731 …bit 4, each rising edge of this input moves the rotator control logic up by one step. Late informa…
66733 …ust be �1� to enable this. This signal must maintain a level for a minimum of one C16 cycle to be …
66735 …ust be �1� to enable this. This signal must maintain a level for a minimum of one C16 cycle to be …
66737 …nals. 0 Disabled (normal operation). 1 Enabled (external control of phase rotators). Note: Do not …
66740 … bit 10 of Receiver Configuration Mode Register is set to �1�. Otherwise, these pins are ignored. …
66742 …bit to be discarded from the recovered data stream, which results in a 1-bit alignment adjustment.…
66744 …bit 4, each rising edge of this input moves the rotator control logic down by one step. Early info…
66746 …bit 4, each rising edge of this input moves the rotator control logic up by one step. Late informa…
66748 …ust be �1� to enable this. This signal must maintain a level for a minimum of one C16 cycle to be …
66750 …ust be �1� to enable this. This signal must maintain a level for a minimum of one C16 cycle to be …
66752 …nals. 0 Disabled (normal operation). 1 Enabled (external control of phase rotators). Note: Do not …
66755 …bit 10 of the Transmitter Configuration Mode Register is set to �1�. Otherwise, these pins are ign…
66757 …Bit 13. Coefficient preset. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second …
66769 … See Section 2.3.3.13 , Out of Band Signaling Mode (OBS), on page 85. 0 Normal. 1 OBS mode enabled.
66771 …-impedance state.) 1 Normal operation. Notes: 1. This pin is ignored if HSSJTAGCE = �1� and the tr…
66777 …-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Reserved. Bits 5:4. Post-cursor c…
66779 …bit 10 of the Transmitter Configuration Mode Register is set to �1�. Otherwise, these pins are ign…
66781 …Bit 13. Coefficient preset. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second …
66793 … See Section 2.3.3.13 , Out of Band Signaling Mode (OBS), on page 85. 0 Normal. 1 OBS mode enabled.
66795 …-impedance state.) 1 Normal operation. Notes: 1. This pin is ignored if HSSJTAGCE = �1� and the tr…
66801 …-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Reserved. Bits 5:4. Post-cursor c…
66803 …bit 10 of the Transmitter Configuration Mode Register is set to �1�. Otherwise, these pins are ign…
66805 …Bit 13. Coefficient preset. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second …
66817 … See Section 2.3.3.13 , Out of Band Signaling Mode (OBS), on page 85. 0 Normal. 1 OBS mode enabled.
66819 …-impedance state.) 1 Normal operation. Notes: 1. This pin is ignored if HSSJTAGCE = �1� and the tr…
66825 …-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Reserved. Bits 5:4. Post-cursor c…
66827 …bit 10 of the Transmitter Configuration Mode Register is set to �1�. Otherwise, these pins are ign…
66829 …Bit 13. Coefficient preset. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second …
66841 … See Section 2.3.3.13 , Out of Band Signaling Mode (OBS), on page 85. 0 Normal. 1 OBS mode enabled.
66843 …-impedance state.) 1 Normal operation. Notes: 1. This pin is ignored if HSSJTAGCE = �1� and the tr…
66849 …-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Reserved. Bits 5:4. Post-cursor c…
66854 …T_EXTERNAL_SIGDET_P1_K2_E5 (0x1<<1) // Used to detect t…
66855 …WS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P1_K2_E5_SHIFT 1
66864 …TATUS_EXTERNAL_PHY_LASI_B_P1_K2_E5 (0x1<<1) // Link Alarm Statu…
66865 …WS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P1_K2_E5_SHIFT 1
66877 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
66878 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
66879 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
66880 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
66881 … 0x70013cUL //Access:RW DataWidth:0x4 // Debug only: If more than this …
66882 … 0x700140UL //Access:R DataWidth:0x5 // Debug only: Fill level of dbgm…
66883 … 0x700144UL //Access:RW DataWidth:0x14 // Debug only: Sampling interval …
66884 …48UL //Access:RW DataWidth:0x4 // Debug only: If 0 or 1, trigger on first occurrence. If grea…
66885 … 0x70014cUL //Access:RW DataWidth:0x18 // Debug only: If greater than 0,…
66886 … 0x700150UL //Access:RW DataWidth:0x1 // Debug only: FW trigger is set.
66890 …LVE_50G_CR2_K2 (0x1<<1) // Autonegotiation …
66891 …WS_REG_INT_STS_0_LN0_AN_RESOLVE_50G_CR2_K2_SHIFT 1
66906 … (0x1<<9) // Autonegotiation resolved to 1g_kx
66909 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
66911 … (0x1<<1) // This bit masks, when set, the Interrupt …
66912 …WS_REG_INT_MASK_0_LN0_AN_RESOLVE_50G_CR2_K2_SHIFT 1
66913 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
66915 … (0x1<<3) // This bit masks, when set, the Interrupt bit: N…
66917 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
66919 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
66921 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
66923 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
66925 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
66927 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
66932 …ESOLVE_50G_CR2_K2 (0x1<<1) // Autonegotiation …
66933 …WS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_50G_CR2_K2_SHIFT 1
66948 … (0x1<<9) // Autonegotiation resolved to 1g_kx
66953 …RESOLVE_50G_CR2_K2 (0x1<<1) // Autonegotiation …
66954 …WS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_50G_CR2_K2_SHIFT 1
66969 … (0x1<<9) // Autonegotiation resolved to 1g_kx
66972 …LVE_50G_CR2_K2 (0x1<<1) // Autonegotiation …
66973 …WS_REG_INT_STS_1_LN1_AN_RESOLVE_50G_CR2_K2_SHIFT 1
66988 … (0x1<<9) // Autonegotiation resolved to 1g_kx
66991 … (0x1<<1) // This bit masks, when set, the Interrupt …
66992 …WS_REG_INT_MASK_1_LN1_AN_RESOLVE_50G_CR2_K2_SHIFT 1
66993 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
66995 … (0x1<<3) // This bit masks, when set, the Interrupt bit: N…
66997 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
66999 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
67001 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
67003 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
67005 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
67007 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
67010 …ESOLVE_50G_CR2_K2 (0x1<<1) // Autonegotiation …
67011 …WS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_50G_CR2_K2_SHIFT 1
67026 … (0x1<<9) // Autonegotiation resolved to 1g_kx
67029 …RESOLVE_50G_CR2_K2 (0x1<<1) // Autonegotiation …
67030 …WS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_50G_CR2_K2_SHIFT 1
67045 … (0x1<<9) // Autonegotiation resolved to 1g_kx
67048 …LVE_50G_CR2_K2 (0x1<<1) // Autonegotiation …
67049 …WS_REG_INT_STS_2_LN2_AN_RESOLVE_50G_CR2_K2_SHIFT 1
67064 … (0x1<<9) // Autonegotiation resolved to 1g_kx
67067 … (0x1<<1) // This bit masks, when set, the Interrupt …
67068 …WS_REG_INT_MASK_2_LN2_AN_RESOLVE_50G_CR2_K2_SHIFT 1
67069 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
67071 … (0x1<<3) // This bit masks, when set, the Interrupt bit: N…
67073 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
67075 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
67077 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
67079 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
67081 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
67083 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
67086 …ESOLVE_50G_CR2_K2 (0x1<<1) // Autonegotiation …
67087 …WS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_50G_CR2_K2_SHIFT 1
67102 … (0x1<<9) // Autonegotiation resolved to 1g_kx
67105 …RESOLVE_50G_CR2_K2 (0x1<<1) // Autonegotiation …
67106 …WS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_50G_CR2_K2_SHIFT 1
67121 … (0x1<<9) // Autonegotiation resolved to 1g_kx
67124 …LVE_50G_CR2_K2 (0x1<<1) // Autonegotiation …
67125 …WS_REG_INT_STS_3_LN3_AN_RESOLVE_50G_CR2_K2_SHIFT 1
67140 … (0x1<<9) // Autonegotiation resolved to 1g_kx
67143 … (0x1<<1) // This bit masks, when set, the Interrupt …
67144 …WS_REG_INT_MASK_3_LN3_AN_RESOLVE_50G_CR2_K2_SHIFT 1
67145 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
67147 … (0x1<<3) // This bit masks, when set, the Interrupt bit: N…
67149 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
67151 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
67153 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
67155 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
67157 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
67159 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
67162 …ESOLVE_50G_CR2_K2 (0x1<<1) // Autonegotiation …
67163 …WS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_50G_CR2_K2_SHIFT 1
67178 … (0x1<<9) // Autonegotiation resolved to 1g_kx
67181 …RESOLVE_50G_CR2_K2 (0x1<<1) // Autonegotiation …
67182 …WS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_50G_CR2_K2_SHIFT 1
67197 … (0x1<<9) // Autonegotiation resolved to 1g_kx
67200 … (0x1<<1) // This bit masks, when set, the Parity bi…
67201 …WS_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2_SHIFT 1
67202 … (0x1<<0) // This bit masks, when set, the Parity bit: NW…
67204 … (0x1<<0) // This bit masks, when set, the Parity bit: NW…
67206 … (0x1<<2) // This bit masks, when set, the Parity bit: NW…
67208 … (0x1<<3) // This bit masks, when set, the Parity bit: NW…
67211 …10 // PHY instance0 = 0x000-0x1fff. PHY instance1 = 0x2000-0x3fff. PHY instance2 = 0x4000-0x5fff…
67213 …-0x7ff. CMU0 registers = 0x0800-0x0bff. CMU1 registers = 0x0c00-0x0fff. Reserved = …
67215 …s[23:16] = ram address [1] bits[15:8] = ram address [2] bits[7:0] = ram address [3] register 0 …
67217 …s[23:16] = ram address [1] bits[15:8] = ram address [2] bits[7:0] = ram address [3] register 0 …
67222 …0_K2_E5 (0x1<<1) // TX fifo overflow
67223 …WM_REG_INT_STS_TX_OVERFLOW_0_K2_E5_SHIFT 1
67242 … (0x1<<18) // Lane 1 Resolved to 10Mb rate
67244 … (0x1<<19) // Lane 1 Resolved to 100Mb ra…
67255 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
67257 … (0x1<<1) // This bit masks, when set, the Interrupt …
67258 …WM_REG_INT_MASK_TX_OVERFLOW_0_K2_E5_SHIFT 1
67259 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
67261 … (0x1<<3) // This bit masks, when set, the Interrupt bit: N…
67263 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
67265 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
67267 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
67269 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
67271 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
67273 … (0x1<<16) // This bit masks, when set, the Interrupt bit: N…
67275 … (0x1<<17) // This bit masks, when set, the Interrupt bit: N…
67277 … (0x1<<18) // This bit masks, when set, the Interrupt bit: N…
67279 … (0x1<<19) // This bit masks, when set, the Interrupt bit: N…
67281 … (0x1<<20) // This bit masks, when set, the Interrupt bit: N…
67283 … (0x1<<21) // This bit masks, when set, the Interrupt bit: N…
67285 … (0x1<<22) // This bit masks, when set, the Interrupt bit: N…
67287 … (0x1<<23) // This bit masks, when set, the Interrupt bit: N…
67292 …OW_0_K2_E5 (0x1<<1) // TX fifo overflow
67293 …WM_REG_INT_STS_WR_TX_OVERFLOW_0_K2_E5_SHIFT 1
67312 … (0x1<<18) // Lane 1 Resolved to 10Mb rate
67314 … (0x1<<19) // Lane 1 Resolved to 100Mb ra…
67327 …LOW_0_K2_E5 (0x1<<1) // TX fifo overflow
67328 …WM_REG_INT_STS_CLR_TX_OVERFLOW_0_K2_E5_SHIFT 1
67347 … (0x1<<18) // Lane 1 Resolved to 10Mb rate
67349 … (0x1<<19) // Lane 1 Resolved to 100Mb ra…
67359 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67360 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67361 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67362 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67364 …bit 9 - LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bi…
67380 …bit 9 - LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bi…
67396 …bit 9 - LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bi…
67412 …bit 9 - LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bi…
67429 … (0x1<<0) // SGMII PCS Enable. When set to 1, the SGMII PCS is en…
67431 … (0x1<<1) // SGMII PCS Enable. When set to 1, t…
67432 …WM_REG_PCS_SELECT_SG1_ENA_K2_E5_SHIFT 1
67433 … (0x1<<2) // SGMII PCS Enable. When set to 1, the SGMII PCS is en…
67435 … (0x1<<3) // SGMII PCS Enable. When set to 1, the SGMII PCS is en…
67438 … (0x1<<0) // Set to '1' to indicate success…
67440 … (0x1<<1) // Auto-Negotiation status. Set to '1' when the…
67441 …WM_REG_SGMII_PCS_STATUS_SG0_AN_DONE_K2_E5_SHIFT 1
67442 … (0x1<<2) // Set to '1' to indicate success…
67444 … (0x1<<3) // Auto-Negotiation status. Set to '1' when the Auto…
67446 … (0x1<<4) // Set to '1' to indicate success…
67448 … (0x1<<5) // Auto-Negotiation status. Set to '1' when the Auto…
67450 … (0x1<<6) // Set to '1' to indicate success…
67452 … (0x1<<7) // Auto-Negotiation status. Set to '1' when the Auto…
67455 …2_E5 (0xf<<0) // Set to '1' for a given lane to…
67457 …2_E5 (0xf<<4) // Set to '1' for a given lane to…
67459 …K2_E5 (0xf<<8) // Set to '1' for a given lane to…
67470 …-wake mode for the LPI transmit and receive functions. When set to 1, the link is to use fast wake…
67480 … (0x1<<9) // A boolean value that is set true (1) when the receive is…
67491 … (0x1<<9) // A boolean value that is set true (1) when the receive is…
67502 … (0x1<<9) // A boolean value that is set true (1) when the receive is…
67513 … (0x1<<9) // A boolean value that is set true (1) when the receive is…
67518 …DE_QUIET_K2_E5 (0x1<<1) // Indicates (when 1) that the…
67519 …WM_REG_PORT0_SG_EEE_STATUS_SG0_PMA_TXMODE_QUIET_K2_E5_SHIFT 1
67520 … (0x1<<2) // Indicates (when 1) that the PCS receiv…
67522 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67527 …DE_QUIET_K2_E5 (0x1<<1) // Indicates (when 1) that the…
67528 …WM_REG_PORT1_SG_EEE_STATUS_SG1_PMA_TXMODE_QUIET_K2_E5_SHIFT 1
67529 … (0x1<<2) // Indicates (when 1) that the PCS receiv…
67531 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67536 …DE_QUIET_K2_E5 (0x1<<1) // Indicates (when 1) that the…
67537 …WM_REG_PORT2_SG_EEE_STATUS_SG2_PMA_TXMODE_QUIET_K2_E5_SHIFT 1
67538 … (0x1<<2) // Indicates (when 1) that the PCS receiv…
67540 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67545 …DE_QUIET_K2_E5 (0x1<<1) // Indicates (when 1) that the…
67546 …WM_REG_PORT3_SG_EEE_STATUS_SG3_PMA_TXMODE_QUIET_K2_E5_SHIFT 1
67547 … (0x1<<2) // Indicates (when 1) that the PCS receiv…
67549 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67552 … (0xf<<0) // Alignment Marker Lock indication, per PCS. When asserted (1) the alignment marke…
67554 … each PCS (not lane). When asserted (1) the block synchronization state machines could successfull…
67556 …Bit Error Rate indication for all lanes. Depending on mode, when asserted, at least 97 invalid syn…
67558 …1 indicates the link is in its normal operational state. It is the result of an asserted block-loc…
67561 …e XLGMII reconciliation layer detects the remote sequences received on the link. One bit per port.
67563 …GMII reconciliation layer detects the local fault sequences received on the link. One bit per port.
67565 …ation layer detects the Link Interruption (fault) sequences received on the link. One bit per port.
67568 …Only one of macN_tx_xxx_fault can be asserted at any time. Overrides the RS layer tx behavior in c…
67570 …1) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly …
67571 …WM_REG_TX_FAULT_MAC0_TX_REM_FAULT_K2_E5_SHIFT 1
67572 …es the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send…
67574 …Only one of macN_tx_xxx_fault can be asserted at any time. Overrides the RS layer tx behavior in c…
67576 …s the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send…
67578 …es the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send…
67580 …Only one of macN_tx_xxx_fault can be asserted at any time. Overrides the RS layer tx behavior in c…
67582 …s the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send…
67584 …es the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send…
67586 …Only one of macN_tx_xxx_fault can be asserted at any time. Overrides the RS layer tx behavior in c…
67588 …s the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send…
67590 …es the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send…
67601 …rrors in a block. count of the number of times fec_cerr asserted for virtual lane 1. Clear on Read.
67609 …rors in a block. count of the number of times fec_ncerr asserted for virtual lane 1. Clear on Read.
67618 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
67619 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
67620 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
67621 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
67627 … (0x1<<0) // This bit masks, when set, the Parity bit: NW…
67629 … (0x1<<1) // This bit masks, when set, the Parity bi…
67630 …WM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2_E5_SHIFT 1
67631 … (0x1<<2) // This bit masks, when set, the Parity bit: NW…
67633 … (0x1<<3) // This bit masks, when set, the Parity bit: NW…
67635 … (0x1<<4) // This bit masks, when set, the Parity bit: NW…
67637 … (0x1<<5) // This bit masks, when set, the Parity bit: NW…
67639 … (0x1<<6) // This bit masks, when set, the Parity bit: NW…
67641 … (0x1<<7) // This bit masks, when set, the Parity bit: NW…
67643 … (0x1<<8) // This bit masks, when set, the Parity bit: NW…
67645 … (0x1<<9) // This bit masks, when set, the Parity bit: NW…
67647 … (0x1<<10) // This bit masks, when set, the Parity bit: NW…
67649 … (0x1<<11) // This bit masks, when set, the Parity bit: NW…
67651 … (0x1<<12) // This bit masks, when set, the Parity bit: NW…
67653 … (0x1<<13) // This bit masks, when set, the Parity bit: NW…
67655 … (0x1<<14) // This bit masks, when set, the Parity bit: NW…
67657 … (0x1<<15) // This bit masks, when set, the Parity bit: NW…
67659 … (0x1<<16) // This bit masks, when set, the Parity bit: NW…
67661 … (0x1<<17) // This bit masks, when set, the Parity bit: NW…
67663 … (0x1<<18) // This bit masks, when set, the Parity bit: NW…
67665 … (0x1<<19) // This bit masks, when set, the Parity bit: NW…
67667 … (0x1<<20) // This bit masks, when set, the Parity bit: NW…
67669 … (0x1<<21) // This bit masks, when set, the Parity bit: NW…
67671 … (0x1<<22) // This bit masks, when set, the Parity bit: NW…
67673 … (0x1<<23) // This bit masks, when set, the Parity bit: NW…
67675 … (0x1<<24) // This bit masks, when set, the Parity bit: NW…
67677 … (0x1<<25) // This bit masks, when set, the Parity bit: NW…
67679 … (0x1<<26) // This bit masks, when set, the Parity bit: NW…
67681 … (0x1<<27) // This bit masks, when set, the Parity bit: NW…
67683 … (0x1<<28) // This bit masks, when set, the Parity bit: NW…
67685 … (0x1<<29) // This bit masks, when set, the Parity bit: NW…
67687 … (0x1<<30) // This bit masks, when set, the Parity bit: NW…
67690 … (0x1<<0) // This bit masks, when set, the Parity bit: NW…
67692 … (0x1<<1) // This bit masks, when set, the Parity bi…
67693 …WM_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_K2_E5_SHIFT 1
67694 … (0x1<<2) // This bit masks, when set, the Parity bit: NW…
67696 … (0x1<<3) // This bit masks, when set, the Parity bit: NW…
67698 … (0x1<<4) // This bit masks, when set, the Parity bit: NW…
67700 … (0x1<<5) // This bit masks, when set, the Parity bit: NW…
67702 … (0x1<<6) // This bit masks, when set, the Parity bit: NW…
67704 … (0x1<<7) // This bit masks, when set, the Parity bit: NW…
67706 … (0x1<<8) // This bit masks, when set, the Parity bit: NW…
67708 … (0x1<<9) // This bit masks, when set, the Parity bit: NW…
67710 … (0x1<<10) // This bit masks, when set, the Parity bit: NW…
67712 … (0x1<<11) // This bit masks, when set, the Parity bit: NW…
67714 … (0x1<<12) // This bit masks, when set, the Parity bit: NW…
67716 … (0x1<<13) // This bit masks, when set, the Parity bit: NW…
67718 … (0x1<<14) // This bit masks, when set, the Parity bit: NW…
67720 … (0x1<<15) // This bit masks, when set, the Parity bit: NW…
67722 … (0x1<<16) // This bit masks, when set, the Parity bit: NW…
67724 … (0x1<<17) // This bit masks, when set, the Parity bit: NW…
67726 … (0x1<<18) // This bit masks, when set, the Parity bit: NW…
67728 … (0x1<<19) // This bit masks, when set, the Parity bit: NW…
67730 … (0x1<<20) // This bit masks, when set, the Parity bit: NW…
67732 … (0x1<<21) // This bit masks, when set, the Parity bit: NW…
67734 … (0x1<<22) // This bit masks, when set, the Parity bit: NW…
67736 … (0x1<<23) // This bit masks, when set, the Parity bit: NW…
67738 … (0x1<<24) // This bit masks, when set, the Parity bit: NW…
67740 … (0x1<<25) // This bit masks, when set, the Parity bit: NW…
67742 … (0x1<<26) // This bit masks, when set, the Parity bit: NW…
67744 … (0x1<<27) // This bit masks, when set, the Parity bit: NW…
67746 … (0x1<<28) // This bit masks, when set, the Parity bit: NW…
67748 … (0x1<<29) // This bit masks, when set, the Parity bit: NW…
67750 … (0x1<<30) // This bit masks, when set, the Parity bit: NW…
67753 … (0x1<<0) // This bit masks, when set, the Parity bit: NW…
67755 … (0x1<<1) // This bit masks, when set, the Parity bi…
67756 …WM_REG_PRTY_MASK_H_2_MEM056_I_MEM_PRTY_K2_E5_SHIFT 1
67757 … (0x1<<2) // This bit masks, when set, the Parity bit: NW…
67759 … (0x1<<3) // This bit masks, when set, the Parity bit: NW…
67761 … (0x1<<4) // This bit masks, when set, the Parity bit: NW…
67763 … (0x1<<5) // This bit masks, when set, the Parity bit: NW…
67765 … (0x1<<6) // This bit masks, when set, the Parity bit: NW…
67767 … (0x1<<7) // This bit masks, when set, the Parity bit: NW…
67769 … (0x1<<8) // This bit masks, when set, the Parity bit: NW…
67771 … (0x1<<9) // This bit masks, when set, the Parity bit: NW…
67776 … 0x800800UL //Access:RW DataWidth:0x20 // Register space for MAC port 1. Registers defined i…
67784 …ss:RW DataWidth:0x10 // Register space for 10/25/40/50G PCS RS FEC port 1. Registers defined i…
67790 … 0x802400UL //Access:RW DataWidth:0x10 // Register space for 1G PCS port 0. Registe…
67792 … 0x802480UL //Access:RW DataWidth:0x10 // Register space for 1G PCS port 1. Registers def…
67794 … 0x802500UL //Access:RW DataWidth:0x10 // Register space for 1G PCS port 2. Registe…
67796 … 0x802580UL //Access:RW DataWidth:0x10 // Register space for 1G PCS port 3. Registe…
67800 … //Access:RW DataWidth:0x10 // Register space for 10/25/40/50G PCS port 1. Registers defined i…
67806 … 0xd80000UL //Access:RW DataWidth:0x1 // Init bit. When set the initi…
67809 … 0xd8000cUL //Access:RW DataWidth:0x1 // When set to 1 the cam hit parity s…
67810 … 0xd80010UL //Access:RW DataWidth:0x1 // When set to 1 the cam miss parity …
67814 …_ENABLE (0x1<<1) // Enables the ysem…
67815 …BF_REG_IF_ENABLE_REG_YSEM_IF_ENABLE_SHIFT 1
67857 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
67858 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
67859 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
67860 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
67866 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
67867 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
67869 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
67870 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
67873 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
67874 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
67877 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
67878 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
67891 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
67900 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
67903 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
67905 … (0x1<<1) // This bit masks, when set, the Parity bi…
67906 …BF_REG_PRTY_MASK_H_0_MEM050_I_ECC_RF_INT_E5_SHIFT 1
67907 … (0x1<<2) // This bit masks, when set, the Parity bit: PB…
67909 … (0x1<<3) // This bit masks, when set, the Parity bit: PB…
67911 … (0x1<<3) // This bit masks, when set, the Parity bit: PB…
67913 … (0x1<<4) // This bit masks, when set, the Parity bit: PB…
67915 … (0x1<<5) // This bit masks, when set, the Parity bit: PB…
67917 … (0x1<<6) // This bit masks, when set, the Parity bit: PB…
67919 … (0x1<<7) // This bit masks, when set, the Parity bit: PB…
67921 … (0x1<<8) // This bit masks, when set, the Parity bit: PB…
67923 … (0x1<<9) // This bit masks, when set, the Parity bit: PB…
67925 … (0x1<<10) // This bit masks, when set, the Parity bit: PB…
67927 … (0x1<<11) // This bit masks, when set, the Parity bit: PB…
67929 … (0x1<<12) // This bit masks, when set, the Parity bit: PB…
67931 … (0x1<<13) // This bit masks, when set, the Parity bit: PB…
67933 … (0x1<<14) // This bit masks, when set, the Parity bit: PB…
67935 … (0x1<<15) // This bit masks, when set, the Parity bit: PB…
67937 … (0x1<<16) // This bit masks, when set, the Parity bit: PB…
67939 … (0x1<<17) // This bit masks, when set, the Parity bit: PB…
67941 … (0x1<<18) // This bit masks, when set, the Parity bit: PB…
67943 … (0x1<<19) // This bit masks, when set, the Parity bit: PB…
67945 … (0x1<<20) // This bit masks, when set, the Parity bit: PB…
67947 … (0x1<<21) // This bit masks, when set, the Parity bit: PB…
67949 … (0x1<<22) // This bit masks, when set, the Parity bit: PB…
67951 … (0x1<<23) // This bit masks, when set, the Parity bit: PB…
67953 … (0x1<<24) // This bit masks, when set, the Parity bit: PB…
67955 … (0x1<<25) // This bit masks, when set, the Parity bit: PB…
67957 … (0x1<<26) // This bit masks, when set, the Parity bit: PB…
67959 … (0x1<<27) // This bit masks, when set, the Parity bit: PB…
67961 … (0x1<<24) // This bit masks, when set, the Parity bit: PB…
67963 … (0x1<<28) // This bit masks, when set, the Parity bit: PB…
67965 … (0x1<<25) // This bit masks, when set, the Parity bit: PB…
67967 … (0x1<<29) // This bit masks, when set, the Parity bit: PB…
67969 … (0x1<<30) // This bit masks, when set, the Parity bit: PB…
67971 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
67973 … (0x1<<1) // This bit masks, when set, the Parity bi…
67974 …BF_REG_PRTY_MASK_H_0_MEM042_I_ECC_RF_INT_BB_K2_SHIFT 1
67975 … (0x1<<2) // This bit masks, when set, the Parity bit: PB…
67977 … (0x1<<4) // This bit masks, when set, the Parity bit: PB…
67979 … (0x1<<5) // This bit masks, when set, the Parity bit: PB…
67981 … (0x1<<6) // This bit masks, when set, the Parity bit: PB…
67983 … (0x1<<7) // This bit masks, when set, the Parity bit: PB…
67985 … (0x1<<8) // This bit masks, when set, the Parity bit: PB…
67987 … (0x1<<9) // This bit masks, when set, the Parity bit: PB…
67989 … (0x1<<10) // This bit masks, when set, the Parity bit: PB…
67991 … (0x1<<11) // This bit masks, when set, the Parity bit: PB…
67993 … (0x1<<12) // This bit masks, when set, the Parity bit: PB…
67995 … (0x1<<13) // This bit masks, when set, the Parity bit: PB…
67997 … (0x1<<14) // This bit masks, when set, the Parity bit: PB…
67999 … (0x1<<15) // This bit masks, when set, the Parity bit: PB…
68001 … (0x1<<16) // This bit masks, when set, the Parity bit: PB…
68003 … (0x1<<17) // This bit masks, when set, the Parity bit: PB…
68005 … (0x1<<18) // This bit masks, when set, the Parity bit: PB…
68007 … (0x1<<19) // This bit masks, when set, the Parity bit: PB…
68009 … (0x1<<20) // This bit masks, when set, the Parity bit: PB…
68011 … (0x1<<21) // This bit masks, when set, the Parity bit: PB…
68013 … (0x1<<22) // This bit masks, when set, the Parity bit: PB…
68015 … (0x1<<23) // This bit masks, when set, the Parity bit: PB…
68017 … (0x1<<26) // This bit masks, when set, the Parity bit: PB…
68019 … (0x1<<27) // This bit masks, when set, the Parity bit: PB…
68021 … (0x1<<28) // This bit masks, when set, the Parity bit: PB…
68023 … (0x1<<29) // This bit masks, when set, the Parity bit: PB…
68025 … (0x1<<30) // This bit masks, when set, the Parity bit: PB…
68028 … (0x1<<21) // This bit masks, when set, the Parity bit: PB…
68030 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
68032 … (0x1<<23) // This bit masks, when set, the Parity bit: PB…
68034 … (0x1<<1) // This bit masks, when set, the Parity bi…
68035 …BF_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_E5_SHIFT 1
68036 … (0x1<<10) // This bit masks, when set, the Parity bit: PB…
68038 … (0x1<<2) // This bit masks, when set, the Parity bit: PB…
68040 … (0x1<<3) // This bit masks, when set, the Parity bit: PB…
68042 … (0x1<<12) // This bit masks, when set, the Parity bit: PB…
68044 … (0x1<<4) // This bit masks, when set, the Parity bit: PB…
68046 … (0x1<<11) // This bit masks, when set, the Parity bit: PB…
68048 … (0x1<<5) // This bit masks, when set, the Parity bit: PB…
68050 … (0x1<<19) // This bit masks, when set, the Parity bit: PB…
68052 … (0x1<<6) // This bit masks, when set, the Parity bit: PB…
68054 … (0x1<<20) // This bit masks, when set, the Parity bit: PB…
68056 … (0x1<<7) // This bit masks, when set, the Parity bit: PB…
68058 … (0x1<<5) // This bit masks, when set, the Parity bit: PB…
68060 … (0x1<<8) // This bit masks, when set, the Parity bit: PB…
68062 … (0x1<<4) // This bit masks, when set, the Parity bit: PB…
68064 … (0x1<<9) // This bit masks, when set, the Parity bit: PB…
68066 … (0x1<<10) // This bit masks, when set, the Parity bit: PB…
68068 … (0x1<<16) // This bit masks, when set, the Parity bit: PB…
68070 … (0x1<<11) // This bit masks, when set, the Parity bit: PB…
68072 … (0x1<<9) // This bit masks, when set, the Parity bit: PB…
68074 … (0x1<<12) // This bit masks, when set, the Parity bit: PB…
68076 … (0x1<<8) // This bit masks, when set, the Parity bit: PB…
68078 … (0x1<<13) // This bit masks, when set, the Parity bit: PB…
68080 … (0x1<<6) // This bit masks, when set, the Parity bit: PB…
68082 … (0x1<<14) // This bit masks, when set, the Parity bit: PB…
68084 … (0x1<<7) // This bit masks, when set, the Parity bit: PB…
68086 … (0x1<<15) // This bit masks, when set, the Parity bit: PB…
68088 … (0x1<<16) // This bit masks, when set, the Parity bit: PB…
68090 … (0x1<<17) // This bit masks, when set, the Parity bit: PB…
68092 … (0x1<<18) // This bit masks, when set, the Parity bit: PB…
68094 … (0x1<<1) // This bit masks, when set, the Parity bi…
68095 …BF_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY_BB_K2_SHIFT 1
68096 … (0x1<<19) // This bit masks, when set, the Parity bit: PB…
68098 … (0x1<<3) // This bit masks, when set, the Parity bit: PB…
68100 … (0x1<<20) // This bit masks, when set, the Parity bit: PB…
68102 … (0x1<<2) // This bit masks, when set, the Parity bit: PB…
68104 … (0x1<<21) // This bit masks, when set, the Parity bit: PB…
68106 … (0x1<<18) // This bit masks, when set, the Parity bit: PB…
68108 … (0x1<<22) // This bit masks, when set, the Parity bit: PB…
68110 … (0x1<<23) // This bit masks, when set, the Parity bit: PB…
68112 … (0x1<<26) // This bit masks, when set, the Parity bit: PB…
68114 … (0x1<<24) // This bit masks, when set, the Parity bit: PB…
68116 … (0x1<<24) // This bit masks, when set, the Parity bit: PB…
68118 … (0x1<<25) // This bit masks, when set, the Parity bit: PB…
68120 … (0x1<<25) // This bit masks, when set, the Parity bit: PB…
68122 … (0x1<<26) // This bit masks, when set, the Parity bit: PB…
68124 … (0x1<<27) // This bit masks, when set, the Parity bit: PB…
68126 … (0x1<<28) // This bit masks, when set, the Parity bit: PB…
68128 … (0x1<<29) // This bit masks, when set, the Parity bit: PB…
68130 … (0x1<<30) // This bit masks, when set, the Parity bit: PB…
68132 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
68134 … (0x1<<13) // This bit masks, when set, the Parity bit: PB…
68136 … (0x1<<14) // This bit masks, when set, the Parity bit: PB…
68138 … (0x1<<15) // This bit masks, when set, the Parity bit: PB…
68140 … (0x1<<17) // This bit masks, when set, the Parity bit: PB…
68142 … (0x1<<22) // This bit masks, when set, the Parity bit: PB…
68144 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
68146 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
68148 … (0x1<<1) // This bit masks, when set, the Parity bi…
68149 …BF_REG_PRTY_MASK_H_2_MEM018_I_MEM_PRTY_E5_SHIFT 1
68150 … (0x1<<2) // This bit masks, when set, the Parity bit: PB…
68152 … (0x1<<3) // This bit masks, when set, the Parity bit: PB…
68154 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
68155 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
68156 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
68157 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
68162 …50_I_ECC_EN_E5 (0x1<<1) // Enable ECC for m…
68163 …BF_REG_MEM_ECC_ENABLE_0_MEM050_I_ECC_EN_E5_SHIFT 1
68212 …42_I_ECC_EN_BB_K2 (0x1<<1) // Enable ECC for m…
68213 …BF_REG_MEM_ECC_ENABLE_0_MEM042_I_ECC_EN_BB_K2_SHIFT 1
68256 …E5 (0x1<<0) // Set parity only for memory ecc inst…
68258 …ECC_PRTY_E5 (0x1<<1) // Set parity only for memory…
68259 …BF_REG_MEM_ECC_PARITY_ONLY_0_MEM050_I_ECC_PRTY_E5_SHIFT 1
68260 …E5 (0x1<<2) // Set parity only for memory ecc inst…
68262 …E5 (0x1<<3) // Set parity only for memory ecc inst…
68264 …BB_K2 (0x1<<3) // Set parity only for memory ecc inst…
68266 …E5 (0x1<<4) // Set parity only for memory ecc inst…
68268 …E5 (0x1<<5) // Set parity only for memory ecc inst…
68270 …Y_E5 (0x1<<6) // Set parity only for memory ecc inst…
68272 …Y_E5 (0x1<<7) // Set parity only for memory ecc inst…
68274 …Y_E5 (0x1<<8) // Set parity only for memory ecc inst…
68276 …Y_E5 (0x1<<9) // Set parity only for memory ecc inst…
68278 …_E5 (0x1<<10) // Set parity only for memory ecc inst…
68280 …_E5 (0x1<<11) // Set parity only for memory ecc inst…
68282 …_E5 (0x1<<12) // Set parity only for memory ecc inst…
68284 …_E5 (0x1<<13) // Set parity only for memory ecc inst…
68286 …_E5 (0x1<<14) // Set parity only for memory ecc inst…
68288 …_E5 (0x1<<15) // Set parity only for memory ecc inst…
68290 …_E5 (0x1<<16) // Set parity only for memory ecc inst…
68292 …_E5 (0x1<<17) // Set parity only for memory ecc inst…
68294 …Y_E5 (0x1<<18) // Set parity only for memory ecc inst…
68296 …Y_E5 (0x1<<19) // Set parity only for memory ecc inst…
68298 …Y_E5 (0x1<<20) // Set parity only for memory ecc inst…
68300 …Y_E5 (0x1<<21) // Set parity only for memory ecc inst…
68302 …Y_E5 (0x1<<22) // Set parity only for memory ecc inst…
68304 …Y_E5 (0x1<<23) // Set parity only for memory ecc inst…
68306 …BB_K2 (0x1<<0) // Set parity only for memory ecc inst…
68308 …ECC_PRTY_BB_K2 (0x1<<1) // Set parity only for memory…
68309 …BF_REG_MEM_ECC_PARITY_ONLY_0_MEM042_I_ECC_PRTY_BB_K2_SHIFT 1
68310 …BB_K2 (0x1<<2) // Set parity only for memory ecc inst…
68312 …BB_K2 (0x1<<4) // Set parity only for memory ecc inst…
68314 …Y_BB_K2 (0x1<<5) // Set parity only for memory ecc inst…
68316 …Y_BB_K2 (0x1<<6) // Set parity only for memory ecc inst…
68318 …Y_BB_K2 (0x1<<7) // Set parity only for memory ecc inst…
68320 …Y_BB_K2 (0x1<<8) // Set parity only for memory ecc inst…
68322 …Y_BB_K2 (0x1<<9) // Set parity only for memory ecc inst…
68324 …_BB_K2 (0x1<<10) // Set parity only for memory ecc inst…
68326 …_BB_K2 (0x1<<11) // Set parity only for memory ecc inst…
68328 …_BB_K2 (0x1<<12) // Set parity only for memory ecc inst…
68330 …_BB_K2 (0x1<<13) // Set parity only for memory ecc inst…
68332 …_BB_K2 (0x1<<14) // Set parity only for memory ecc inst…
68334 …_BB_K2 (0x1<<15) // Set parity only for memory ecc inst…
68336 …_BB_K2 (0x1<<16) // Set parity only for memory ecc inst…
68338 …Y_BB_K2 (0x1<<17) // Set parity only for memory ecc inst…
68340 …Y_BB_K2 (0x1<<18) // Set parity only for memory ecc inst…
68342 …Y_BB_K2 (0x1<<19) // Set parity only for memory ecc inst…
68344 …Y_BB_K2 (0x1<<20) // Set parity only for memory ecc inst…
68346 …Y_BB_K2 (0x1<<21) // Set parity only for memory ecc inst…
68348 …Y_BB_K2 (0x1<<22) // Set parity only for memory ecc inst…
68354 …ED_0_MEM050_I_ECC_CORRECT_E5 (0x1<<1) // Record if a corr…
68355 …BF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM050_I_ECC_CORRECT_E5_SHIFT 1
68404 …ED_0_MEM042_I_ECC_CORRECT_BB_K2 (0x1<<1) // Record if a corr…
68405 …BF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM042_I_ECC_CORRECT_BB_K2_SHIFT 1
68448 …0400UL //Access:RW DataWidth:0x3 // PXP read request interface initial credit - transoriented.
68449 … 0xd80404UL //Access:RW DataWidth:0x6 // TDIF pass-through command inter…
68450 … 0xd80408UL //Access:RW DataWidth:0x6 // TDIF non_pass-through command inter…
68452 …10UL //Access:RW DataWidth:0x2 // PXP internal write interface initial credit - transoriented.
68453 … 0xd80414UL //Access:RW DataWidth:0x3 // TM interface initial credit - transoriented.
68471 … 0xd80484UL //Access:RW DataWidth:0x10 // The Ethernet type value for L2 tag 1.
68477 …L //Access:RW DataWidth:0x3 // The length of the info field for L2 tag 1. The length is betw…
68482 …-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port. …
68483 …-port: Bit-map indicating which L2 hdrs may appear after the LLC header on this port. This applie…
68484 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port. This applies to …
68485 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port. This applies to …
68486 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port. This applies to …
68487 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port. This applies to …
68488 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port. This applies to …
68489 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port. This applies to …
68490 …-port: Bit-map indicating which headers must appear in the packet on this port. This applies to t…
68491 …aWidth:0x8 // Per-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet he…
68492 … DataWidth:0x8 // Per-port: Bit-map indicating which L2 hdrs may appear after the LLC header o…
68493 …RW DataWidth:0x8 // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on …
68494 …RW DataWidth:0x8 // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on …
68495 …RW DataWidth:0x8 // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on …
68496 …RW DataWidth:0x8 // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on …
68497 …RW DataWidth:0x8 // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on …
68498 …RW DataWidth:0x8 // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on …
68499 …RW DataWidth:0x8 // Per-port: Bit-map indicating which headers must appear in the packet on t…
68511 … 0xd80524UL //Access:RW DataWidth:0x1 // Per-port: Flag to compar…
68515 …AL_VPORT_EN_E5 (0x1<<1) // Enables inclusio…
68516 …BF_REG_SAME_AS_LAST_CONFIG_SAL_VPORT_EN_E5_SHIFT 1
68523 …, and has following options: 0: None, the corresponding field in tuple is 0 1: Source MAC address,…
68529 … (0x1<<9) // Enables inclusion of Tenant ID Exist bit in lookup tuple. If…
68540 … upper flex field extracted from PBF2TGFS message. A value of 0 selects the 1st REGQ of the select…
68542 …he upper flex field extracted from PBF2TGFS message. 0: Basic Parsing Info; 1: Raw L3/L4; 2: Exten…
68544 …age. NOTE: The lower flex field is used only if sal_flex_upper_bytes is not 0, and number of bytes…
68548 …he lower flex field extracted from PBF2TGFS message. 0: Basic Parsing Info; 1: Raw L3/L4; 2: Exten…
68550 …ataWidth:0x20 // Masks 64 bit Flexible field used for Same-as-last lookup. A 0 in each bit masks…
68551 …ataWidth:0x20 // Masks 64 bit Flexible field used for Same-as-last lookup. A 0 in each bit masks…
68567 …DR_TYPE_1_E5 (0xff<<8) // ipv6 extension uniform header type 1
68603 … (0x7<<1) // compare the GRE version field to gre_version register if c…
68604 …BF_REG_TUNNEL_MISC_CFG_GRE_VERSION_E5_SHIFT 1
68605 …N_BIT_E5 (0x1<<4) // Chicken bit to use single fc en…
68610 …IDS_IPV6_EXT_UNIFORM_HDR_TYPE_1_VALID_E5 (0x1<<1) // If set, validate…
68611 …BF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_1_VALID_E5_SHIFT 1
68641 …rder. Reset value is in the order from left to right: tag0; tag1; tag2; tag3; tag4; tag5; llc-snap.
68642 …//Access:RW DataWidth:0x4 // Per-Port: Specifies the flexible L2 tag to be used for T-tag. T…
68645 …alue. A zero in this register will cause the corresponding bit to not be included …
68646 …alue. A zero in this register will cause the corresponding bit to not be included …
68648 … 0xd805a0UL //Access:RW DataWidth:0x10 // UDP destination port configuration 1 for match check.
68651 …D modification logic. Setting to 1 selects or unmasks the condition. Bit 0 of this mask correspond…
68653 …al Destination Mac Address Match in Event ID modification logic. Setting to 1 selects or unmasks t…
68655 …arsing Result in Event ID modification logic. Setting to 1 selects or unmasks the condition. Bit 0…
68658 …odification logic. Setting to 1 selects or unmasks the condition. Bit 0 of this mask corresponds t…
68660 …odification logic. Setting to 1 selects or unmasks the condition. Bit 0 of this mask corresponds t…
68663 …DataWidth:0xb // Number of shared BTB 256 byte blocks which can be used by all TC-s in the port.
68667 …-priority w/ anti-starvation arbiter is a RR arbiter. A value of all ones means no RR slots; i.e. …
68668 …ccess:RW DataWidth:0x8 // L2 EDPM threshold in 256 byte blocks. Only if all TC-s have allocat…
68669 …threshold in 256 byte blocks. Only if all TC-s in port N have allocated blocks above this threshol…
68670 …ess:RW DataWidth:0xb // RDMA EDPM threshold in 256 byte blocks. Only if all TC-s have allocat…
68671 … 0xd80600UL //Access:RW DataWidth:0x10 // 1st bit mask used to cont…
68672 … 0xd80604UL //Access:RW DataWidth:0x10 // 2nd bit mask used to contro…
68673 … 0xd80608UL //Access:RW DataWidth:0x10 // 3rd bit mask used to contro…
68674 … 0xd8060cUL //Access:RW DataWidth:0x10 // 4th bit mask used to contro…
68723 …Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 1.
68724 … 0xd806e4UL //Access:RW DataWidth:0x5 // Almost full threshold for VOQ 1 in the YSTORM comman…
68725 …ess:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 1 (after ending the c…
68726 … 0xd806ecUL //Access:RC DataWidth:0x20 // Number of commands received on VOQ 1 from YSTORM.
68727 … 0xd806f0UL //Access:R DataWidth:0xa // Number of commands in the Y command queue of VOQ 1.
68728 …yclic counter for number of 16 byte lines freed from the Y command queue of VOQ 1. Reset upon init.
68729 …/Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue of VOQ 1.
68730 …0xd806fcUL //Access:RW DataWidth:0xb // The number of BTB 256 byte blocks guaranteed for VOQ 1
68732 …0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 1
68738 …cess:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 1 in both guaranteed a…
68739 …idth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 1. Reset upon init.
68740 …Width:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 1. Reset upon init.
69358 …R (0x1<<1) // EOP check error.
69359 …BF_PB1_REG_INT_STS_EOP_ERROR_SHIFT 1
69375 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
69377 … (0x1<<1) // This bit masks, when set, the Interrupt …
69378 …BF_PB1_REG_INT_MASK_EOP_ERROR_SHIFT 1
69379 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
69381 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
69383 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
69385 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
69387 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
69389 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
69391 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
69396 …RROR (0x1<<1) // EOP check error.
69397 …BF_PB1_REG_INT_STS_WR_EOP_ERROR_SHIFT 1
69415 …ERROR (0x1<<1) // EOP check error.
69416 …BF_PB1_REG_INT_STS_CLR_EOP_ERROR_SHIFT 1
69432 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
69435 … (0x1<<0) // Indicates if to switch the CRC result byte ordering. 0=don't switch;1=switch.
69437 …_ERROR (0x1<<1) // Indicates if to …
69438 …BF_PB1_REG_CONTROL_DB_IGNORE_ERROR_SHIFT 1
69447 … (0x1<<6) // Debug only: Disable PB.
69451 …AX_TH (0x1<<11) // Dbug only.
69453 …ived on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
69455 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69456 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69457 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69458 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69459 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69460 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69461 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69462 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69463 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69464 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69465 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69466 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69477 …bit of this register. Bits 31:29 provide additional information about the instruction. Bit 31 in…
69479 …er being executed at the time EOP error is detected. The task passthrough bit is not kept and is …
69487 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
69488 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
69489 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
69490 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
69491 … 0xda2000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the data…
69498 …R (0x1<<1) // EOP check error.
69499 …BF_PB2_REG_INT_STS_EOP_ERROR_SHIFT 1
69515 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
69517 … (0x1<<1) // This bit masks, when set, the Interrupt …
69518 …BF_PB2_REG_INT_MASK_EOP_ERROR_SHIFT 1
69519 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
69521 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
69523 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
69525 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
69527 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
69529 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
69531 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
69536 …RROR (0x1<<1) // EOP check error.
69537 …BF_PB2_REG_INT_STS_WR_EOP_ERROR_SHIFT 1
69555 …ERROR (0x1<<1) // EOP check error.
69556 …BF_PB2_REG_INT_STS_CLR_EOP_ERROR_SHIFT 1
69572 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
69575 … (0x1<<0) // Indicates if to switch the CRC result byte ordering. 0=don't switch;1=switch.
69577 …_ERROR (0x1<<1) // Indicates if to …
69578 …BF_PB2_REG_CONTROL_DB_IGNORE_ERROR_SHIFT 1
69587 … (0x1<<6) // Debug only: Disable PB.
69591 …AX_TH (0x1<<11) // Dbug only.
69593 …ived on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
69595 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69596 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69597 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69598 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69599 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69600 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69601 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69602 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69603 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69604 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69605 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69606 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)…
69617 …bit of this register. Bits 31:29 provide additional information about the instruction. Bit 31 in…
69619 …er being executed at the time EOP error is detected. The task passthrough bit is not kept and is …
69627 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
69628 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
69629 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
69630 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
69631 … 0xda6000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the data…
69635 … // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en re…
69636 … // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en re…
69637 …bit should be set when initialization of all BRTB registers and memories is finished. BRTB will fi…
69641 …_ERROR (0x1<<1) // Read packet clie…
69642 …TB_REG_INT_STS_0_RC_PKT0_RLS_ERROR_SHIFT 1
69653 … (0x1<<11) // Read packet client NIG main port 1 release error when n…
69655 … (0x1<<13) // Read packet client NIG main port 1 length error when re…
69657 … (0x1<<15) // Read packet client NIG main port 1 error when packet do…
69659 … (0x1<<16) // Read packet client NIG LB port 1 release error when n…
69661 … (0x1<<18) // Read packet client NIG LB port 1 length error when re…
69663 … (0x1<<20) // Read packet client NIG LB port 1 error when packet do…
69672 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
69674 … (0x1<<1) // This bit masks, when set, the Interrupt …
69675 …TB_REG_INT_MASK_0_RC_PKT0_RLS_ERROR_SHIFT 1
69676 … (0x1<<3) // This bit masks, when set, the Interrupt bit: B…
69678 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
69680 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
69682 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
69684 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
69686 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
69688 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
69690 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
69692 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
69694 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
69696 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
69698 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
69700 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
69702 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
69707 …RLS_ERROR (0x1<<1) // Read packet clie…
69708 …TB_REG_INT_STS_WR_0_RC_PKT0_RLS_ERROR_SHIFT 1
69719 … (0x1<<11) // Read packet client NIG main port 1 release error when n…
69721 … (0x1<<13) // Read packet client NIG main port 1 length error when re…
69723 … (0x1<<15) // Read packet client NIG main port 1 error when packet do…
69725 … (0x1<<16) // Read packet client NIG LB port 1 release error when n…
69727 … (0x1<<18) // Read packet client NIG LB port 1 length error when re…
69729 … (0x1<<20) // Read packet client NIG LB port 1 error when packet do…
69740 …_RLS_ERROR (0x1<<1) // Read packet clie…
69741 …TB_REG_INT_STS_CLR_0_RC_PKT0_RLS_ERROR_SHIFT 1
69752 … (0x1<<11) // Read packet client NIG main port 1 release error when n…
69754 … (0x1<<13) // Read packet client NIG main port 1 length error when re…
69756 … (0x1<<15) // Read packet client NIG main port 1 error when packet do…
69758 … (0x1<<16) // Read packet client NIG LB port 1 release error when n…
69760 … (0x1<<18) // Read packet client NIG LB port 1 length error when re…
69762 … (0x1<<20) // Read packet client NIG LB port 1 error when packet do…
69771 …_ERROR (0x1<<1) // Calculations err…
69772 …TB_REG_INT_STS_1_LL_ARB_CALC_ERROR_SHIFT 1
69804 … (0x1<<1) // This bit masks, when set, the Interrupt …
69805 …TB_REG_INT_MASK_1_LL_ARB_CALC_ERROR_SHIFT 1
69806 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
69808 … (0x1<<3) // This bit masks, when set, the Interrupt bit: B…
69810 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
69812 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
69814 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
69816 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
69818 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
69820 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
69822 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
69824 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
69826 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
69828 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
69830 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
69832 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
69834 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
69837 …ALC_ERROR (0x1<<1) // Calculations err…
69838 …TB_REG_INT_STS_WR_1_LL_ARB_CALC_ERROR_SHIFT 1
69870 …CALC_ERROR (0x1<<1) // Calculations err…
69871 …TB_REG_INT_STS_CLR_1_LL_ARB_CALC_ERROR_SHIFT 1
69912 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
69914 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
69916 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
69918 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
69941 …E_FIFO_ERROR (0x1<<1) // Read packet clie…
69942 …TB_REG_INT_STS_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT 1
69973 … (0x1<<17) // Read packet client NIG main port 1 side info FIFO error…
69975 … (0x1<<18) // Read packet client NIG main port 1 request FIFO error :…
69977 … (0x1<<19) // Read packet client NIG main port 1 block FIFO error ::s…
69979 … (0x1<<20) // Read packet client NIG main port 1 releases left FIFO e…
69981 … (0x1<<21) // Read packet client NIG main port 1 start pointer FIFO e…
69983 … (0x1<<22) // Read packet client NIG main port 1 second pointer FIFO …
69985 … (0x1<<23) // Read packet client NIG main port 1 response FIFO error …
69987 … (0x1<<24) // Read packet client NIG main port 1 descriptor FIFO erro…
69989 … (0x1<<25) // Read packet client NIG LB port 1 side info FIFO error…
69991 … (0x1<<26) // Read packet client NIG LB port 1 request FIFO error :…
69993 … (0x1<<27) // Read packet client NIG LB port 1 block FIFO error ::s…
69995 … (0x1<<28) // Read packet client NIG LB port 1 releases left FIFO e…
69997 … (0x1<<29) // Read packet client NIG LB port 1 start pointer FIFO e…
69999 … (0x1<<30) // Read packet client NIG LB port 1 second pointer FIFO …
70001 … (0x1<<31) // Read packet client NIG LB port 1 response FIFO error …
70004 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
70006 … (0x1<<1) // This bit masks, when set, the Interrupt …
70007 …TB_REG_INT_MASK_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT 1
70008 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
70010 … (0x1<<3) // This bit masks, when set, the Interrupt bit: B…
70012 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
70014 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
70016 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
70018 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
70020 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
70022 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
70024 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
70026 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
70028 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
70030 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
70032 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
70034 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
70036 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
70038 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
70040 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
70042 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
70044 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
70046 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
70048 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
70050 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
70052 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
70054 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
70056 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
70058 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
70060 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
70062 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
70064 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
70066 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
70071 …SIDE_FIFO_ERROR (0x1<<1) // Read packet clie…
70072 …TB_REG_INT_STS_WR_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT 1
70103 … (0x1<<17) // Read packet client NIG main port 1 side info FIFO error…
70105 … (0x1<<18) // Read packet client NIG main port 1 request FIFO error :…
70107 … (0x1<<19) // Read packet client NIG main port 1 block FIFO error ::s…
70109 … (0x1<<20) // Read packet client NIG main port 1 releases left FIFO e…
70111 … (0x1<<21) // Read packet client NIG main port 1 start pointer FIFO e…
70113 … (0x1<<22) // Read packet client NIG main port 1 second pointer FIFO …
70115 … (0x1<<23) // Read packet client NIG main port 1 response FIFO error …
70117 … (0x1<<24) // Read packet client NIG main port 1 descriptor FIFO erro…
70119 … (0x1<<25) // Read packet client NIG LB port 1 side info FIFO error…
70121 … (0x1<<26) // Read packet client NIG LB port 1 request FIFO error :…
70123 … (0x1<<27) // Read packet client NIG LB port 1 block FIFO error ::s…
70125 … (0x1<<28) // Read packet client NIG LB port 1 releases left FIFO e…
70127 … (0x1<<29) // Read packet client NIG LB port 1 start pointer FIFO e…
70129 … (0x1<<30) // Read packet client NIG LB port 1 second pointer FIFO …
70131 … (0x1<<31) // Read packet client NIG LB port 1 response FIFO error …
70136 …_SIDE_FIFO_ERROR (0x1<<1) // Read packet clie…
70137 …TB_REG_INT_STS_CLR_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT 1
70168 … (0x1<<17) // Read packet client NIG main port 1 side info FIFO error…
70170 … (0x1<<18) // Read packet client NIG main port 1 request FIFO error :…
70172 … (0x1<<19) // Read packet client NIG main port 1 block FIFO error ::s…
70174 … (0x1<<20) // Read packet client NIG main port 1 releases left FIFO e…
70176 … (0x1<<21) // Read packet client NIG main port 1 start pointer FIFO e…
70178 … (0x1<<22) // Read packet client NIG main port 1 second pointer FIFO …
70180 … (0x1<<23) // Read packet client NIG main port 1 response FIFO error …
70182 … (0x1<<24) // Read packet client NIG main port 1 descriptor FIFO erro…
70184 … (0x1<<25) // Read packet client NIG LB port 1 side info FIFO error…
70186 … (0x1<<26) // Read packet client NIG LB port 1 request FIFO error :…
70188 … (0x1<<27) // Read packet client NIG LB port 1 block FIFO error ::s…
70190 … (0x1<<28) // Read packet client NIG LB port 1 releases left FIFO e…
70192 … (0x1<<29) // Read packet client NIG LB port 1 start pointer FIFO e…
70194 … (0x1<<30) // Read packet client NIG LB port 1 second pointer FIFO …
70196 … (0x1<<31) // Read packet client NIG LB port 1 response FIFO error …
70199 … (0x1<<0) // Read packet client NIG LB port 1 descriptor FIFO erro…
70211 … (0x1<<11) // Read packet client NIG main port 1 release fifo error
70213 … (0x1<<12) // Read packet client NIG LB port 1 release fifo error
70223 … (0x1<<19) // Read packet client NIG LB port 1 release error when n…
70225 … (0x1<<21) // Read packet client NIG LB port 1 length error when re…
70227 … (0x1<<23) // Read packet client NIG LB port 1 error when packet do…
70229 … (0x1<<24) // Read packet client NIG LB port 1 side info FIFO error…
70231 … (0x1<<25) // Read packet client NIG LB port 1 request FIFO error :…
70233 … (0x1<<26) // Read packet client NIG LB port 1 block FIFO error ::s…
70235 … (0x1<<27) // Read packet client NIG LB port 1 releases left FIFO e…
70237 … (0x1<<28) // Read packet client NIG LB port 1 start pointer FIFO e…
70239 … (0x1<<29) // Read packet client NIG LB port 1 second pointer FIFO …
70241 … (0x1<<30) // Read packet client NIG LB port 1 response FIFO error …
70243 … (0x1<<31) // Read packet client NIG LB port 1 descriptor FIFO erro…
70246 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
70248 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
70250 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
70252 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
70254 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
70256 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
70258 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
70260 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
70262 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
70264 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
70266 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
70268 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
70270 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
70272 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
70274 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
70276 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
70278 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
70280 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
70282 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
70284 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
70286 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
70288 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
70290 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
70293 … (0x1<<0) // Read packet client NIG LB port 1 descriptor FIFO erro…
70305 … (0x1<<11) // Read packet client NIG main port 1 release fifo error
70307 … (0x1<<12) // Read packet client NIG LB port 1 release fifo error
70317 … (0x1<<19) // Read packet client NIG LB port 1 release error when n…
70319 … (0x1<<21) // Read packet client NIG LB port 1 length error when re…
70321 … (0x1<<23) // Read packet client NIG LB port 1 error when packet do…
70323 … (0x1<<24) // Read packet client NIG LB port 1 side info FIFO error…
70325 … (0x1<<25) // Read packet client NIG LB port 1 request FIFO error :…
70327 … (0x1<<26) // Read packet client NIG LB port 1 block FIFO error ::s…
70329 … (0x1<<27) // Read packet client NIG LB port 1 releases left FIFO e…
70331 … (0x1<<28) // Read packet client NIG LB port 1 start pointer FIFO e…
70333 … (0x1<<29) // Read packet client NIG LB port 1 second pointer FIFO …
70335 … (0x1<<30) // Read packet client NIG LB port 1 response FIFO error …
70337 … (0x1<<31) // Read packet client NIG LB port 1 descriptor FIFO erro…
70340 … (0x1<<0) // Read packet client NIG LB port 1 descriptor FIFO erro…
70352 … (0x1<<11) // Read packet client NIG main port 1 release fifo error
70354 … (0x1<<12) // Read packet client NIG LB port 1 release fifo error
70364 … (0x1<<19) // Read packet client NIG LB port 1 release error when n…
70366 … (0x1<<21) // Read packet client NIG LB port 1 length error when re…
70368 … (0x1<<23) // Read packet client NIG LB port 1 error when packet do…
70370 … (0x1<<24) // Read packet client NIG LB port 1 side info FIFO error…
70372 … (0x1<<25) // Read packet client NIG LB port 1 request FIFO error :…
70374 … (0x1<<26) // Read packet client NIG LB port 1 block FIFO error ::s…
70376 … (0x1<<27) // Read packet client NIG LB port 1 releases left FIFO e…
70378 … (0x1<<28) // Read packet client NIG LB port 1 start pointer FIFO e…
70380 … (0x1<<29) // Read packet client NIG LB port 1 second pointer FIFO …
70382 … (0x1<<30) // Read packet client NIG LB port 1 response FIFO error …
70384 … (0x1<<31) // Read packet client NIG LB port 1 descriptor FIFO erro…
70389 …_ERROR (0x1<<1) // Read packet clie…
70390 …TB_REG_INT_STS_5_RC_PKT5_LEN_ERROR_SHIFT 1
70452 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
70454 … (0x1<<1) // This bit masks, when set, the Interrupt …
70455 …TB_REG_INT_MASK_5_RC_PKT5_LEN_ERROR_SHIFT 1
70456 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
70458 … (0x1<<3) // This bit masks, when set, the Interrupt bit: B…
70460 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
70462 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
70464 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
70466 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
70468 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
70470 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
70472 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
70474 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
70476 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
70478 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
70480 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
70482 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
70484 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
70486 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
70488 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
70490 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
70492 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
70494 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
70496 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
70498 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
70500 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
70502 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
70504 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
70506 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
70508 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
70510 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
70512 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
70514 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
70519 …LEN_ERROR (0x1<<1) // Read packet clie…
70520 …TB_REG_INT_STS_WR_5_RC_PKT5_LEN_ERROR_SHIFT 1
70584 …_LEN_ERROR (0x1<<1) // Read packet clie…
70585 …TB_REG_INT_STS_CLR_5_RC_PKT5_LEN_ERROR_SHIFT 1
70650 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
70659 … (0x1<<0) // Warning! Check this bit connection for E4 A…
70662 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
70665 … (0x1<<0) // Warning! Check this bit connection for E4 A…
70668 … (0x1<<0) // Warning! Check this bit connection for E4 A…
70671 … (0x1<<0) // Warning! Check this bit connection for E4 A…
70674 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
70677 … (0x1<<0) // Warning! Check this bit connection for E4 A…
70680 … (0x1<<0) // Warning! Check this bit connection for E4 A…
70686 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
70700 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
70702 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
70715 … (0x1<<0) // This bit masks, when set, the Parity bit: BT…
70717 … (0x1<<1) // This bit masks, when set, the Parity bi…
70718 …TB_REG_PRTY_MASK_LL_BANK1_MEM_PRTY_SHIFT 1
70719 … (0x1<<2) // This bit masks, when set, the Parity bit: BT…
70721 … (0x1<<3) // This bit masks, when set, the Parity bit: BT…
70723 … (0x1<<4) // This bit masks, when set, the Parity bit: BT…
70726 … (0x1<<0) // This bit masks, when set, the Parity bit: BT…
70728 … (0x1<<1) // This bit masks, when set, the Parity bi…
70729 …TB_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_SHIFT 1
70730 … (0x1<<2) // This bit masks, when set, the Parity bit: BT…
70732 … (0x1<<3) // This bit masks, when set, the Parity bit: BT…
70734 … (0x1<<4) // This bit masks, when set, the Parity bit: BT…
70736 … (0x1<<5) // This bit masks, when set, the Parity bit: BT…
70738 … (0x1<<6) // This bit masks, when set, the Parity bit: BT…
70740 … (0x1<<7) // This bit masks, when set, the Parity bit: BT…
70742 … (0x1<<8) // This bit masks, when set, the Parity bit: BT…
70744 … (0x1<<9) // This bit masks, when set, the Parity bit: BT…
70746 … (0x1<<10) // This bit masks, when set, the Parity bit: BT…
70748 … (0x1<<11) // This bit masks, when set, the Parity bit: BT…
70750 … (0x1<<12) // This bit masks, when set, the Parity bit: BT…
70752 … (0x1<<13) // This bit masks, when set, the Parity bit: BT…
70754 … (0x1<<14) // This bit masks, when set, the Parity bit: BT…
70756 … (0x1<<15) // This bit masks, when set, the Parity bit: BT…
70758 … (0x1<<16) // This bit masks, when set, the Parity bit: BT…
70760 … (0x1<<17) // This bit masks, when set, the Parity bit: BT…
70762 … (0x1<<18) // This bit masks, when set, the Parity bit: BT…
70764 … (0x1<<19) // This bit masks, when set, the Parity bit: BT…
70766 … (0x1<<20) // This bit masks, when set, the Parity bit: BT…
70768 … (0x1<<21) // This bit masks, when set, the Parity bit: BT…
70770 … (0x1<<22) // This bit masks, when set, the Parity bit: BT…
70772 … (0x1<<23) // This bit masks, when set, the Parity bit: BT…
70774 … (0x1<<16) // This bit masks, when set, the Parity bit: BT…
70776 … (0x1<<24) // This bit masks, when set, the Parity bit: BT…
70778 … (0x1<<17) // This bit masks, when set, the Parity bit: BT…
70780 … (0x1<<25) // This bit masks, when set, the Parity bit: BT…
70782 … (0x1<<18) // This bit masks, when set, the Parity bit: BT…
70784 … (0x1<<26) // This bit masks, when set, the Parity bit: BT…
70786 … (0x1<<19) // This bit masks, when set, the Parity bit: BT…
70788 … (0x1<<27) // This bit masks, when set, the Parity bit: BT…
70790 … (0x1<<17) // This bit masks, when set, the Parity bit: BT…
70792 … (0x1<<20) // This bit masks, when set, the Parity bit: BT…
70794 … (0x1<<28) // This bit masks, when set, the Parity bit: BT…
70796 … (0x1<<21) // This bit masks, when set, the Parity bit: BT…
70798 … (0x1<<29) // This bit masks, when set, the Parity bit: BT…
70800 … (0x1<<22) // This bit masks, when set, the Parity bit: BT…
70802 … (0x1<<30) // This bit masks, when set, the Parity bit: BT…
70804 … (0x1<<23) // This bit masks, when set, the Parity bit: BT…
70806 … (0x1<<24) // This bit masks, when set, the Parity bit: BT…
70808 … (0x1<<22) // This bit masks, when set, the Parity bit: BT…
70810 … (0x1<<25) // This bit masks, when set, the Parity bit: BT…
70812 … (0x1<<21) // This bit masks, when set, the Parity bit: BT…
70814 … (0x1<<26) // This bit masks, when set, the Parity bit: BT…
70816 … (0x1<<20) // This bit masks, when set, the Parity bit: BT…
70818 … (0x1<<27) // This bit masks, when set, the Parity bit: BT…
70820 … (0x1<<19) // This bit masks, when set, the Parity bit: BT…
70822 … (0x1<<28) // This bit masks, when set, the Parity bit: BT…
70824 … (0x1<<18) // This bit masks, when set, the Parity bit: BT…
70826 … (0x1<<29) // This bit masks, when set, the Parity bit: BT…
70828 … (0x1<<16) // This bit masks, when set, the Parity bit: BT…
70830 … (0x1<<30) // This bit masks, when set, the Parity bit: BT…
70832 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
70834 … (0x1<<0) // This bit masks, when set, the Parity bit: BT…
70836 … (0x1<<1) // This bit masks, when set, the Parity bi…
70837 …TB_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_E5_SHIFT 1
70838 … (0x1<<2) // This bit masks, when set, the Parity bit: BT…
70840 … (0x1<<3) // This bit masks, when set, the Parity bit: BT…
70842 … (0x1<<4) // This bit masks, when set, the Parity bit: BT…
70844 … (0x1<<5) // This bit masks, when set, the Parity bit: BT…
70846 … (0x1<<6) // This bit masks, when set, the Parity bit: BT…
70848 … (0x1<<7) // This bit masks, when set, the Parity bit: BT…
70850 …1].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of ea…
70851 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
70852 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
70858 … (0x1<<1) // Enable ECC for memory ecc instance btb.BB_BANK_K…
70859 …TB_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_EN_SHIFT 1
70892 … (0x1<<18) // Enable ECC for memory ecc instance btb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i…
70894 … (0x1<<19) // Enable ECC for memory ecc instance btb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i…
70904 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
70908 … (0x1<<0) // Set parity only for memory ecc inst…
70910 … (0x1<<1) // Set parity only for memory ecc instance btb.BB_BANK…
70911 …TB_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_PRTY_SHIFT 1
70912 … (0x1<<2) // Set parity only for memory ecc inst…
70914 … (0x1<<3) // Set parity only for memory ecc inst…
70916 … (0x1<<4) // Set parity only for memory ecc inst…
70918 … (0x1<<5) // Set parity only for memory ecc inst…
70920 … (0x1<<6) // Set parity only for memory ecc inst…
70922 … (0x1<<7) // Set parity only for memory ecc inst…
70924 … (0x1<<8) // Set parity only for memory ecc inst…
70926 … (0x1<<9) // Set parity only for memory ecc inst…
70928 … (0x1<<10) // Set parity only for memory ecc inst…
70930 … (0x1<<11) // Set parity only for memory ecc inst…
70932 … (0x1<<12) // Set parity only for memory ecc inst…
70934 … (0x1<<13) // Set parity only for memory ecc inst…
70936 … (0x1<<14) // Set parity only for memory ecc inst…
70938 … (0x1<<15) // Set parity only for memory ecc inst…
70940 …E5 (0x1<<16) // Set parity only for memory ecc inst…
70942 …E5 (0x1<<17) // Set parity only for memory ecc inst…
70944 … (0x1<<18) // Set parity only for memory ecc instance btb.LL_BANK_K2_GEN_…
70946 … (0x1<<19) // Set parity only for memory ecc instance btb.LL_BANK_K2_GEN_…
70948 …E5 (0x1<<20) // Set parity only for memory ecc inst…
70950 …E5 (0x1<<21) // Set parity only for memory ecc inst…
70952 …E5 (0x1<<22) // Set parity only for memory ecc inst…
70954 …E5 (0x1<<23) // Set parity only for memory ecc inst…
70956 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
70962 … (0x1<<1) // Record if a correctable error occurred on memory ecc instance …
70963 …TB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_CORRECT_SHIFT 1
70996 … a correctable error occurred on memory ecc instance btb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i…
70998 … a correctable error occurred on memory ecc instance btb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i…
71008 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
71012 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
71013 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
71014 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
71015 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
71016 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
71017 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
71018 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
71019 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
71020 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
71021 … to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_…
71022 …04UL //Access:RW DataWidth:0xa // Number of valid bytes in header in 16-bytes resolution. Aft…
71030 … 0xdb0844UL //Access:RW DataWidth:0x8 // There is bit for each PACKET read client. When bit …
71031 …mode (reset value, both BB and K2): 2880 - (34 + 2 + (9600+32)/128) = 2768 = 0xAD0 Value for 100G …
71032 …bit for each PACKET read client. Bit 0 suits to client 0 and so on. If bit is set then packet will…
71034 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71036 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71038 …1 read client that is used in link list and big ram arbiters. If all read clients have identical …
71040 …1 read client that is used in link list and big ram arbiters. If all read clients have identical …
71042 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71044 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71046 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71048 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71050 …bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then packet wil…
71051 …bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then highest pr…
71052 …is is priority for SOP read client to Big RAM arbiter. Possible values are 1-3. Priority 3 is high…
71053 …cket request of write client group to Big RAM arbiter. Possible values are 1-3. Priority 3 is high…
71054 …ll be done with round robin. Only one group with multiple clients of identical priority is support…
71064 … 0xdb08bcUL //Access:RW DataWidth:0x4 // Debug only: If more than this …
71068 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
71069 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
71070 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
71071 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
71077 …bit per each read client interface: B0-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG …
71079 … (0x1<<10) // There is bit per SOP read client interface. When bit is set then appropriate int…
71081 …bit per write client interface: B0 - NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - …
71084 …bit per each read client interface: B0-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG …
71086 … (0x1<<10) // There is bit per SOP read client interface. When bit is set then appropriate int…
71088 … (0x1<<11) // There is bit for almost full interfaces. When bit is set then almost full inte…
71090 …bit for packet avalable interfaces. When bit is set then packet avalable interface is enabled. Whe…
71092 …s bit for release interfaces. When bit is set then release interface is enabled. When bit is reset…
71097 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
71101 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71102 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71103 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71104 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71105 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71106 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71107 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71108 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71109 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71110 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71111 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71112 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71113 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71114 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71115 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71116 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71117 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71118 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71119 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71120 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71121 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71122 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71123 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71124 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71125 …4 // Debug register. Empty status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
71126 …x4 // Debug register. Full status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
71127 … register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr_fifo; B3:0-queue…
71136 …be 3, meaning after 1/(2power3) of the packet arrived it can be sent to the read client. This is b…
71141 …ter for each queue of each write client. It contains: b31 - valid; b30:16 - queue size; b15:0 - qu…
71144 …-NIG main port0; 1-NIG LB port0; 2-NIG main port1; 2-NIG LB port1. Message spelling (MSB->LSB): re…
71148 …-NIG main port0; 1-NIG LB port0; 2-NIG main port1; 2-NIG LB port1. Message spelling (MSB->LSB): op…
71153 …db4000UL //Access:RW DataWidth:0x1 // This is a bitmap per WC which is 1 for WC with high pri…
71154 …db4004UL //Access:RW DataWidth:0x1 // This is a bitmap per WC which is 1 for WC with high pri…
71155 …Access:RW DataWidth:0xc // Link list dual port memory that contains per-block descriptor::s/B…
71156 …Access:RW DataWidth:0xd // Link list dual port memory that contains per-block descriptor::s/B…
71163 …1<<31) // This bit is set by the driver before it sets the MCP_RESET bit. When set this bit disabl…
71176 …bit is set when the watchdog timer expires. This bit reflects state of the WATCHDOG_ATTN bit. When…
71178 … (0x1<<31) // This bit is set any time an …
71183 …BLE (0x1<<31) // When this bit is set by the drive…
71190 … (0x1<<31) // When set this bit validates bits 10-0 of this r…
71195 … (0x1<<30) // When set this bit causes MCP heartbea…
71197 … (0x1<<31) // When set this bit resets the heartbea…
71202 … (0x1<<30) // When set this bit resets the watchdog…
71204 … (0x1<<31) // When set this bit resets the watchdog timer #1. Typi…
71209 … (0x1<<27) // When set this bit enables watchdog ti…
71211 …STALL_ENABLE (0x1<<28) // When this bit is set, expiration …
71213 … 0 and that it requires driver's attention. Low to high transition on this bit should generate MCP…
71215 … // When set this bit enables the watchdog timer to reset the MCP instead of halting it. The watch…
71217 … (0x1<<31) // When set this bit enables watchdog timer #1. Typic…
71219 … // Timeout value for watchog timer #1. These bits specify the watchdog timeout period with respe…
71220 …#2. These bits specify the watchdog timeout period with respect to the MCP (1/2 speed) core_clk. U…
71224 …1' to this bit in order to obtain the lock over the shared resources within the chip. The actual "…
71229 … (0x1<<31) // This bit tells driver the PCIE function that is associated with. '0' correspo…
71232 … (0x3fff<<0) // Offset (in 32-bit words) of the mailb…
71236 … (0xfff<<20) // Mailbox size in 32-bit words. Default mailbox size is 1KB.
71239 … (0x3fff<<0) // Offset (in 32-bit words) of the mailb…
71243 … (0xfff<<20) // Mailbox size in 32-bit words. Default mailbox size is 1KB.
71248 …er to alert the MCP. Changing this register updates the corresponding per-PF bit in the MCP Doorbe…
71251 … (0xff<<0) // Register supports up to an 8 bit VFID. For smaller V…
71266 … Port mode for GRC Master transactions 0: 1-port mode, 1: 2-port mode, 2: 4-port mode All bits are…
71268 …W DataWidth:0x20 // EPIO mask for signal transitioning from high to low. 1 -> MASK the event
71269 …W DataWidth:0x20 // EPIO mask for signal transitioning from low to high. 1 -> MASK the event
71274 … (0x1<<0) // When this bit is written to a 1, the processor will reset as if …
71276 … (0x1<<1) // When this bit is set, the…
71277 …CP_REG_CPU_MODE_STEP_ENA_SHIFT 1
71278 …bit enables the processor to halt and to latch the value of bit 3 of the state register when data …
71280 …bit enables the processor to halt and to latch the value of bit 4 of the state register when an in…
71284 … (0x1<<6) // This is a simple RW bit.
71286 … (0x1<<7) // When this bit is set to 1, the interrupt is enabled. When this bit is zero, any inte…
71290 …bit is set, the CPU will halt. This bit is cleared by an exception or reset. If the processor does…
71292 …11) // When this bit is set, the CPU will halt when any condition that causes bit 5 in the CPU sta…
71294 …12) // When this bit is set, the CPU will halt when any condition that causes bit 6 in the CPU sta…
71296 … (0x1<<13) // When this bit is set, the CPU wil…
71300 … (0x1<<15) // When this bit is set, the CPU will halt when state bit…
71303 …bit is set while the processor is halted due reaching a hardware breakpoint as enabled in the mode…
71305 …STATE_UNUSED0 (0x1<<1) //
71306 …CP_REG_CPU_STATE_UNUSED0_SHIFT 1
71307 …1<<2) // This bit is set while the processor is halted due fetching an invalid instruction. This b…
71309 …bit is set while the processor is halted due to accessing data within page 0 (the first 256 bytes)…
71311 …bit is set while the processor is halted due to executing an instruction within page 0 (the first …
71313 …x1<<5) // This bit is set while the processor is halted due to bad data reference address. This bi…
71315 …) // This bit is set while the processor is halted due to bad value in the Program Counter (PC). T…
71317 …bit is set while the processor is halted due to bad memory alignment problem on a load or store in…
71319 …bit is set while the processor is halted due to the generation of a abort condition by one, or mor…
71323 … (0x1<<10) // This bit is set while the processor is halted due to the set…
71325 … (0x1<<11) // This bit is each time an att…
71327 … (0x1<<12) // This bit is each time an interrupt input is asserted, regardless of the i…
71331 … (0x1<<14) // This bit is set while the pr…
71333 … (0x1<<15) // This bit is set while the pr…
71337 …bit indicates that a blocking data cache miss occurred, causing the CPU to stall while data is fet…
71339 …vides one bit for each state register bit to enable it into the equation for generation the TX Pro…
71340 … (0x1<<0) // This bit enables breakpoints…
71342 …EVENT_MASK_UNUSED0 (0x1<<1) //
71343 …CP_REG_CPU_EVENT_MASK_UNUSED0_SHIFT 1
71344 …SK (0x1<<2) // This bit enables invalid ins…
71346 …_MASK (0x1<<3) // This bit enables page 0 data…
71348 …_MASK (0x1<<4) // This bit enables page 0 inst…
71350 …ED_MASK (0x1<<5) // This bit enables invalid dat…
71352 … (0x1<<6) // This bit enables invalid PC …
71354 … (0x1<<7) // This bit enables alignment e…
71356 … (0x1<<8) // This bit enables the attention output when bit …
71360 … (0x1<<10) // This bit enables soft halts …
71362 … (0x1<<11) // This bit attention when bit 11 of the …
71364 … (0x1<<12) // This bit attention when bit 12 of the …
71366 …nstruction in the decode stage of the pipeline. Bits 31-2 are implemented. '1's written to bits 1-…
71367 …code sate of the pipeline while the processor is halted. This register is only intended for debugg…
71368 … access to the address of the current data access of the processor. It is only valid when the proc…
71369 …bit 7 in mode register). This register is intended to allow a way to return from an interrupt serv…
71373 … (0x1<<0) // Reset: 1 When this bit is set, the h…
71375 …HW_BREAKPOINT_UNUSED0 (0x1<<1) //
71376 …CP_REG_CPU_HW_BREAKPOINT_UNUSED0_SHIFT 1
71377 … (0x3fffffff<<2) // This field sets the 32-bit word on which the *…
71380 …) // 11 bit set-1 debug visibility vector value. This value is selected by the 1_SEL value and ena…
71382 …bit is '0', then the debug visiblity mux is controlled by the setting in the misc. block and is av…
71384 … (0xf<<12) // 4 bit select for the peek value of the set-1 …
71386 … (0x7ff<<16) // 11 bit set-2 debug visibility…
71388 …bit is '0', then the debug visiblity mux is controlled by the setting in the misc. block and is av…
71390 … (0xf<<28) // 4 bit select for the peek value of the set-2…
71392 …hat address and branch type of the last branch that was taken. This register is for debug use only.
71395 … (0x1<<1) // This bit indicates the …
71396 …CP_REG_CPU_LAST_BRANCH_ADDR_TYPE_SHIFT 1
71399 …/ While the processor is halted, the general purpose processor registers (r0-r31) can be read and …
71402 …ff<<0) // This value is used to specify the bit at the auto-polled address that indicates "link up…
71404 …value is used to define the register address in MDIO auto-poll transactions. For Clause 22, only t…
71407 …-B0, on the first read of this register when the START_BUSY bit returns to '0', this value, in the…
71413 … field controls the type of MDIO transaction that will be performed when the START_BUSY bit is set.
71415 …bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occ…
71417 …bit is self clearing. When written to a '1', the currently programmed MDIO transaction will activa…
71420 …/ This bit is updated by the MDIO interface if auto-polling is enabled. The value of this bit is r…
71422 … (0x1<<1) // This bit is manually controlled only.…
71423 …CP_REG_MDIO_STATUS__10MB_SHIFT 1
71427 … (0x1<<1) // If this bit is set, the 32-bit pre-amble will not be gen…
71428 …CP_REG_MDIO_MODE_SHORT_PREAMBLE_SHIFT 1
71431 …bit enables auto-polling. When auto-polling is on, the START_BUSY bit in the mdio_comm register mu…
71435 … (0x1<<8) // If this bit is '1', the MDIO interface is controlled by the MDIO, MDIO_OE, and MDC bi…
71437 …// The write value of this bit controls the drive state of the MDIO pin if the BIT_BANG bit is set…
71439 …/ Setting this bit to '1' will cause the MDIO pin to drive the value written to the MDIO bit if th…
71441 …s bit to '1' will cause the MDC pin to high if the BIT_BANG bit is set. . Setting this pin low wil…
71443 …bit reflects the current state of the MDINT input pin from the Copper PHY. If the interrupt is ass…
71445 …is bit reflects the current state of the External MDINT input pin. If the interrupt is asserted, t…
71449 …. The output MDIO clock runs at a frequency equal to CORE_CLK/(2*(CLOCK_CNT+1)). A value of 0 is i…
71453 …1 this bit indicates that the current MDIO transaction will be executed as a Clause 45 transaction…
71456 …(0x1<<0) // This bit is set each time an error is detected during a auto poll sequence. The bit is…
71473 …icrocontroller program memory interfaces. All clocks are divided from the MCP (1/2 speed) core_clk.
71476 …arpCore SERDES microcontroller program memory interfaces. This register auto-increments after each…
71481 … (0x1<<0) // Write this bit as a '1' to set ext_uc_…
71483 … (0x1<<1) // Write this bit as a '1' to set ext_uc_enable fo…
71484 …CP_REG_UCINT_WARP_TARGET_ENABLE_EN_SET1_SHIFT 1
71485 … (0x1<<2) // Write this bit as a '1' to set ext_uc_…
71489 … (0x1<<8) // Write this bit as a '1' to clear ext_u…
71491 … (0x1<<9) // Write this bit as a '1' to clear ext_uc_enable for target…
71493 … (0x1<<10) // Write this bit as a '1' to clear ext_u…
71499 … (0x1<<17) // Current status of ext_uc_enable for target 1.
71518 …icrocontroller program memory interfaces. All clocks are divided from the MCP (1/2 speed) core_clk.
71521 … 2 PCIE SERDES microcontroller program memory interfaces. This register auto-increments after each…
71526 … (0x1<<0) // Write this bit as a '1' to set ext_uc_…
71528 … (0x1<<1) // Write this bit as a '1' to set ext_uc_enable fo…
71529 …CP_REG_UCINT_PCIE_TARGET_ENABLE_EN_SET1_SHIFT 1
71532 … (0x1<<8) // Write this bit as a '1' to clear ext_u…
71534 … (0x1<<9) // Write this bit as a '1' to clear ext_uc_enable for target…
71540 … (0x1<<17) // Current status of ext_uc_enable for target 1.
71542 …address offset for the AVS RBUS program memory interface. This register auto-increments after each…
71547 … (0x1f<<0) // Number of bytes to be transfered in Read or Write operation. Valid lengths are 0-16.
71551 …initial Data Register for Read or Write operation. If the transfer_count>1, additional bytes wi…
71561 … (0x1<<30) // Setting this bit will synchronously …
71563 … (0x1<<31) // Setting this bit enables the IMC Blo…
71570 …ice ID of the Slave Device. This is a 7-bit field as defined by the I2C spec, but can be written h…
71598 … (0x1<<0) // This bit indicates that M2P is currently sending a packet. …
71600 … (0x1<<1) // This bit indicates that in In-Use Error has occured. This is generated if a new V…
71601 …CP_REG_M2P_M2P_STATUS_M2P_PKT_INUSE_ERROR_SHIFT 1
71602 …RROR (0x1<<2) // This bit indicates that the …
71604 …ERROR (0x1<<3) // This bit is set when the Len…
71606 …ROR (0x1<<4) // This bit is set when a packe…
71610 … (0x3<<8) // This is the internal State Machine, for debugging purposes only.
71617 … (0x1<<0) // Setting this bit will transmit the V…
71620 … (0x7f<<0) // This is the length of the VDM packet, in 32-bit DWords. 0x0 is an i…
71642 … (0x1<<0) // This bit selects whether the VDM will be sent to Engine 0 o…
71654 … (0x1<<31) // This bit shows the current s…
71657 …0x1<<0) // Setting this bit will cause the P2M block to assert backpressure to the PXP when the pa…
71659 … (0x1<<1) // When set, this bit forces P2…
71660 …CP_REG_P2M_P2M_CONFIG_DRAIN_MODE_SHIFT 1
71661 …<<2) // When set, this bit will cause any packet that doesn't match one of the two Vendor ID Filte…
71668 … (0x1<<16) // When set, this bit causes packets whic…
71675 … (0x1<<16) // When set, this bit causes packets whic…
71698 …/Access:R DataWidth:0x20 // Reading this register will give the next 32-bits of the current H…
71707 … 0xe06240UL //Access:R DataWidth:0x20 // 32-bit Packet Data.
71709 … (0x7f<<0) // 7-bit Length from VDM Hea…
71712 … (0xffff<<0) // 16-bit PCI Requester ID fr…
71715 … (0xffff<<0) // 16-bit Vendor ID from VDM …
71718 … (0xffff<<0) // 16-bit FID from VDM Header.
71720 … 0xe06254UL //Access:R DataWidth:0x20 // 32-bit Vendor Defined DWor…
71724 …P2M_OTHER_HDR_FIELDS_UNUSED0 (0x7<<1) //
71725 …CP_REG_P2M_P2M_OTHER_HDR_FIELDS_UNUSED0_SHIFT 1
71730 … (0xff<<16) // This is the 8-bit Tag from VDM Header.
71734 …bit is cleared then the look-up is bypassed and the scratchpad is always accessed with the address…
71738 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71740 … (0x1<<1) // The data is in use. If the valid bit is clear …
71741 …CP_REG_CACHE_CACHE_CTRL_STATUS_0_ACTIVE_SHIFT 1
71746 … 0xe06310UL //Access:RW DataWidth:0x20 // Reflects the status of page 1.
71747 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71749 … (0x1<<1) // The data is in use. If the valid bit is clear …
71750 …CP_REG_CACHE_CACHE_CTRL_STATUS_1_ACTIVE_SHIFT 1
71756 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71758 … (0x1<<1) // The data is in use. If the valid bit is clear …
71759 …CP_REG_CACHE_CACHE_CTRL_STATUS_2_ACTIVE_SHIFT 1
71765 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71767 … (0x1<<1) // The data is in use. If the valid bit is clear …
71768 …CP_REG_CACHE_CACHE_CTRL_STATUS_3_ACTIVE_SHIFT 1
71774 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71776 … (0x1<<1) // The data is in use. If the valid bit is clear …
71777 …CP_REG_CACHE_CACHE_CTRL_STATUS_4_ACTIVE_SHIFT 1
71783 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71785 … (0x1<<1) // The data is in use. If the valid bit is clear …
71786 …CP_REG_CACHE_CACHE_CTRL_STATUS_5_ACTIVE_SHIFT 1
71792 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71794 … (0x1<<1) // The data is in use. If the valid bit is clear …
71795 …CP_REG_CACHE_CACHE_CTRL_STATUS_6_ACTIVE_SHIFT 1
71801 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71803 … (0x1<<1) // The data is in use. If the valid bit is clear …
71804 …CP_REG_CACHE_CACHE_CTRL_STATUS_7_ACTIVE_SHIFT 1
71810 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71812 … (0x1<<1) // The data is in use. If the valid bit is clear …
71813 …CP_REG_CACHE_CACHE_CTRL_STATUS_8_ACTIVE_SHIFT 1
71819 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71821 … (0x1<<1) // The data is in use. If the valid bit is clear …
71822 …CP_REG_CACHE_CACHE_CTRL_STATUS_9_ACTIVE_SHIFT 1
71828 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71830 … (0x1<<1) // The data is in use. If the valid bit is clear …
71831 …CP_REG_CACHE_CACHE_CTRL_STATUS_10_ACTIVE_SHIFT 1
71837 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71839 … (0x1<<1) // The data is in use. If the valid bit is clear …
71840 …CP_REG_CACHE_CACHE_CTRL_STATUS_11_ACTIVE_SHIFT 1
71846 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71848 … (0x1<<1) // The data is in use. If the valid bit is clear …
71849 …CP_REG_CACHE_CACHE_CTRL_STATUS_12_ACTIVE_SHIFT 1
71855 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71857 … (0x1<<1) // The data is in use. If the valid bit is clear …
71858 …CP_REG_CACHE_CACHE_CTRL_STATUS_13_ACTIVE_SHIFT 1
71864 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71866 … (0x1<<1) // The data is in use. If the valid bit is clear …
71867 …CP_REG_CACHE_CACHE_CTRL_STATUS_14_ACTIVE_SHIFT 1
71873 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71875 … (0x1<<1) // The data is in use. If the valid bit is clear …
71876 …CP_REG_CACHE_CACHE_CTRL_STATUS_15_ACTIVE_SHIFT 1
71906 …//Access:RW DataWidth:0x20 // Statistic: Incremented whenever a Pageable-memory instruction hi…
71907 …//Access:RW DataWidth:0x20 // Statistic: Incremented whenever a Pageable-memory instruction mi…
71911 …LAST (0x1<<1) // If set, this pag…
71912 …CP_REG_CACHE_LAST_PAGE_0_IS_LAST_SHIFT 1
71920 …LAST (0x1<<1) // If set, this pag…
71921 …CP_REG_CACHE_LAST_PAGE_1_IS_LAST_SHIFT 1
71930 …TUS_ILLEGAL_FETCH (0x1<<1) // If set, a read a…
71931 …CP_REG_CACHE_CACHE_ERROR_STATUS_ILLEGAL_FETCH_SHIFT 1
71933 … (0x1<<0) // When set, the entire NVM state machine is reset. This bit is self clearing.
71935 …COMMAND_UNUSED0 (0x3<<1) //
71936 …CP_REG_NVM_COMMAND_UNUSED0_SHIFT 1
71937 …bit that is asserted when the command requested by assertion of the doit bit has completed. done W…
71939 …om software to start the defined command. The done bit must be clear before setting this bit. This…
71941 … (0x1<<5) // The Write/Not_Read command bit. Set high to execut…
71943 …) // The erase page/sector command bit. Set high to execute a page/sector erase_cmd. This bit is i…
71945 … (0x1<<7) // This bit is passed to the SEE_FSM or SPI_FSM if the pass_…
71947 … (0x1<<8) // When this bit is set, the next co…
71949 … (0x1<<9) // When this bit is set, the address in the address register will be inc…
71953 …mmand bit. Set '1' will make flash interface state machine Generate wren_cmd to flash device throu…
71955 …mmand bit. Set '1' will make flash interface state machine Generate wrdi_cmd to flash device throu…
71957 …18) // The erase all/chip command bit. Set high to execute an all/chip erase_all_cmd. This bit is …
71961 …nd bit. When set, the flash controller will read the ID register from the external flash device. T…
71963 … (0x1<<21) // The read status command bit. When set, the flas…
71965 …bit. A 256 byte page mode has been added to the block. This mode is normally on. The mode helps co…
71972 … (0xffffff<<0) // 24 bit address value used in read, write and erase operations…
71976 … (0x1<<0) // Legacy strap_value[1]. Read only. Set based on …
71978 … (0x1<<1) // Legacy strap_value[0]. Read only. S…
71979 …CP_REG_NVM_CFG1_BUFFER_MODE_SHIFT 1
71980 … (0x1<<2) // Enable pass-thru mode to the byte…
71982 … (0x1<<3) // Enable bit-bang mode to control…
71984 …Bit offset in status command response to interpret as the "ready" flag. For Atmel, this defaults t…
71986 …1x" time for all Flash Interface I/O pin timing definition A value of 0 means that SCLK will be 1/…
71988 … (0x7ff<<11) // Legacy value. Read only.
71992 … (0x1<<23) // Legacy strap_control[1] bit. Read only set to 1, indicat…
71994 … (0x1<<24) // Legacy strap_value[2]. Read only. Set based on new s…
71996 … (0x1<<25) // Legacy strap_value[3]. Read only. Set based on new s…
71998 … (0x1<<26) // Legacy strap_value[1]. Read only. Set based on …
72000 … (0x1<<27) // Legacy strap_value[0]. Read only. Set based on new s…
72002 … (0x1<<28) // Legacy strap_value[2]. Read only. Set based on new s…
72004 … (0x1<<29) // Legacy strap_value[3]. Read only. Set based on new s…
72006 … (0x1<<30) // Legacy strap_control[1] bit. Read only set to 1, indicat…
72008 … (0x1<<31) // Legacy bit. Acts as dummy R/W bit.
72011 …this command. Reset value is 0x20h if flash_mode=1, 0x81h if buffer_mode=1, and 0xd8h if protect_m…
72015 …the commands. Reset value is 0x9Fh if flash_mode=1, 0x57h if buffer_mode=1, and 0x5h if protect_mo…
72022 …Bit[10:9] is address bit A1 and A0 of SEEPROM. User should modify those two bits base on the value…
72026 …Bit[26:25] is address bit A1 and A0 of SEEPROM. User should modify those two bits base on the valu…
72029 … (0x1<<0) // Set Software Arbitration request Bit 0. This bit is set by writing a '1' to this…
72031 … (0x1<<1) // Set Software Arbitration request Bit 1. This bit is set by wr…
72032 …CP_REG_NVM_SW_ARB_ARB_REQ_SET1_SHIFT 1
72033 … (0x1<<2) // Set Software Arbitration request Bit 2. This bit is set by writing a '1' to this…
72035 … (0x1<<3) // Set Software Arbitration request Bit 3. This bit is set by writing a '1' to this…
72037 … (0x1<<4) // Write this bit as a '1' to clear req0 bit.
72039 … (0x1<<5) // Write this bit as a '1' to clear req1 bit.
72041 … (0x1<<6) // Write this bit as a '1' to clear req2 bit.
72043 … (0x1<<7) // Write this bit as a '1' to clear req3 bit.
72045 …bit will be read as 1, when an operation is complete, then the CLR_ARB0 must be written to clear t…
72047 …rbitration is won, this bit will be read as 1, when an operation is complete, then the CLR_ARB1 mu…
72049 …rbitration is won, this bit will be read as 1, when an operation is complete, then the CLR_ARB2 mu…
72051 …rbitration is won, this bit will be read as 1, when an operation is complete, then the CLR_ARB3 mu…
72053 … (0x1<<12) // This is the current status of requester 0. When this bit is one, it means th…
72055 … (0x1<<13) // This is the current status of requester 1. When this bit is one, it me…
72057 … (0x1<<14) // This is the current status of requester 2. When this bit is one, it means th…
72059 … (0x1<<15) // This is the current status of requester 3. When this bit is one, it means th…
72069 …rface state machine through SPI interface To flash device, and make the flash device write-enabled.
72071 …face state machine through SPI interface To flash device, and make the flash device write-disabled.
72077 …0x1<<30) // When set to 1, write operations to Flash will use an internal 4KB sector buffer. Some …
72079 … (0x1<<31) // Set to 1 to use legacy/previo…
72082 …. This information is not used by FLSH hardware. It is only used by software. This value is self-c…
72084 … (0x1<<3) // This bit is self-configured on re…
72086 … (0x3<<4) // Bit location for hardware to insert an empty address bit when MODE_256 is not set …
72088 …bit determines how the status bit of the device status register is interpreted by hardware. If 0, …
72090 …bit is set in ST mode, fast read command is used. In Atmel mode, this bit should be set when using…
72092 … (0x1<<8) // When this bit is set, the SI input from the external flash device is latched one cyc…
72094 …bit is set, the pass mode data is captured one cycle later than normal. If using pass mode, this b…
72096 …bit is set, a turnaround cycle is inserted in between the address and data phases of a status read…
72102 … frequency using f(SCLK) = f(core_clk)/(2*(SPI_SLOW_CLK_DIV +1)). [Ex: SPI_SLOW_CLK_DIV=0 -> f(…
72104 …1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generate…
72106 …1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generate…
72108 …1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generate…
72110 …1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generate…
72112 …1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generate…
72114 …1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generate…
72116 …1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generate…
72118 …1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generate…
72120 …1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generate…
72122 … 0xe06430UL //Access:RW DataWidth:0x20 // NVM re-configuration registe…
72123 … (0xf<<0) // Strap value from iologic pins. Only bit[0] is used. Bits[3:1] are f…
72129 …his bit is 0 on reset. After software finishes reconfiguring FLSH, they will set this bit to 1 to …
72132 …// Enable bit for the expansion ROM engine. When '1', the expansion ROM engine will automatically …
72134 … (0x1<<1) // When this bit is set to '1', the…
72135 …CP_REG_ERNGN_EXP_ROM_CTRL_BFRD_SHIFT 1
72146 … (0x1<<28) // This bit is set to '1' when the cac…
72148 … (0x1<<29) // This bit is set to '1' when an arbi…
72150 … (0x1<<30) // This bit is set to '1' when a read …
72152 … (0x1<<31) // This bit is set to '1' when the exp…
72167 …AR area, it will place the offset from the BAR value in this register and re-try the PCI bus to ma…
72169 … (0x3<<24) // The size of the PCI BAR rom read request. This value ranges from 1 to 3 dwords
72173 …0x1<<31) // This bit will be set if there is a pending request for action. This bit is equivalent …
72175 … This register shows the first dword for the expansion ROM access. This is for debug purposes only.
72176 …This register shows the second dword for the expansion ROM access. This is for debug purposes only.
72177 … This register shows the third dword for the expansion ROM access. This is for debug purposes only.
72203 … (0x1<<24) // Setting this bit will cause the GRC …
72207 … (0x1<<28) // This bit indicates that ther…
72209 … (0x1<<29) // This bit indicates that ther…
72211 … (0x1<<30) // This bit indicates that this image loader engine is busy. Wh…
72213 … (0x1<<31) // This bit indicates that this…
72218 …gister provides the base address of the image in the NVRAM that the Image Loader Engine 1 will use.
72240 … (0x1<<24) // Setting this bit will cause the GRC …
72244 … (0x1<<28) // This bit indicates that ther…
72246 … (0x1<<29) // This bit indicates that ther…
72248 … (0x1<<30) // This bit indicates that this image loader engine is busy. Wh…
72250 … (0x1<<31) // This bit indicates that this…
72277 … (0x1<<24) // Setting this bit will cause the GRC …
72281 … (0x1<<28) // This bit indicates that ther…
72283 … (0x1<<29) // This bit indicates that ther…
72285 … (0x1<<30) // This bit indicates that this image loader engine is busy. Wh…
72287 … (0x1<<31) // This bit indicates that this…
72292 …hen this bit is set HW will service the ARP Assign Address command, set the AR_FLAG[1:0] and AV_FL…
72294 … (0x1<<8) // When this bit is set the SMBUS bl…
72296 … (0x1<<9) // When this bit is set the SMBUS bl…
72300 … (0xf<<16) // This bit indicates a number …
72304 … (0x1<<26) // When this bit is '1' the TIMESTAMP c…
72306 … (0x1<<27) // When this bit is '1' the SMBUS block…
72308 … (0x1<<28) // When this bit is '1' the SMBUS block…
72310 … (0x1<<29) // When this bit is '1', the SMBUS block is placed into bit-bang mode. SMBUS interface …
72312 … (0x1<<30) // When this bit is '1', the SMBUS bloc…
72314 … (0x1<<31) // When this bit is set it will rese…
72319 …BDAT must be high before a master can assume that bus is free. Register has 1us resolution. Defaul…
72321 …6) ~= 77us. This is assuming that random slave stretching is not used. Register has 1us resolution.
72323 …bit) when the SMBUS block acts as a slave. This is useful in "legacy mode" to allow firmware time …
72325 … (0x1<<31) // When this bit is set the SMBUS bl…
72328 …ed using ARP when the ARP function is enabled. When the PROMISCOUS_MODE bit is '1', this value is …
72330 … (0x1<<7) // When this bit is '1' NIC_SMB_ADDR0 w…
72332 …h will be used to match for incoming messages. When the PROMISCOUS_MODE bit is '1', this value is …
72334 … (0x1<<15) // When this bit is '1' NIC_SMB_ADDR1 w…
72336 …COUS_MODE bit is '1', this value is ignored. 0x0 This address is also used for ARP. The address wi…
72338 … (0x1<<23) // When this bit is '1' NIC_SMB_ADDR2 w…
72340 …h will be used to match for incoming messages. When the PROMISCOUS_MODE bit is '1', this value is …
72342 … (0x1<<31) // When this bit is '1' NIC_SMB_ADDR3 w…
72355 …O_FLUSH (0x1<<30) // When this bit is set HW will flus…
72357 …O_FLUSH (0x1<<31) // When this bit is set HW will flus…
72370 …FLUSH (0x1<<30) // When this bit is set HW will flus…
72372 …FLUSH (0x1<<31) // When this bit is set HW will flus…
72377 …for bit-bang mode, this bit controlls the output enable for the SMBDAT pin. When this bit is '0', …
72379 … (0x1<<29) // This bit reflects the current input value of the SMBDAT pin. When the SMBDAT pin …
72381 …ed for bit-bang mode, this bit controlls the output enable for the CLK pin. When this bit is '0', …
72383 … (0x1<<31) // This bit reflects the current input value of the SMBCLK pin. When the SMBCLK pin …
72386 …<<0) // This value counts down to zero once each second and sets the WG_TO bit when it reaches zer…
72389 …<<0) // This value counts down to zero once each second and sets the HB_TO bit when it reaches zer…
72392 …<0) // This value counts down to zero once each 5 msec. and sets the PA_TO bit when it reaches zer…
72395 …) // This value counts down to zero once each 250 msec. and sets the PL_TO bit when it reaches zer…
72398 …<<0) // This value counts down to zero once each second and sets the RT_TO bit when it reaches zer…
72400 …to zero each time it passes 0xffffffff. This counter only counts when the TIMESTAMP_CNT_EN bit is …
72402 … number of bytes that SMBUS block should read from the slave in Block Write - Block Read Process C…
72414 …bit can be set at any time by the firmware or the driver in order to abort the transaction. The HW…
72416 …bit is self clearing. When written to a '1', the currently programmed SMBUS transaction will activ…
72429 …bit can be set at any time by the firmware or the driver in order to abort the transaction. The HW…
72431 …bit is self clearing. When written to a '1', the currently programmed SMBUS transaction will activ…
72436 …ARTBEAT_TO_EN (0x1<<1) // When set enables…
72437 …CP_REG_SMBUS_EVENT_ENABLE_HEARTBEAT_TO_EN_SHIFT 1
72446 …are to generate smbus event any time and ARP command is received and ARP_EN0 or ARP_EN1 bit is set.
72452 … (0x1<<23) // When set enables generation of a smbus event on slave START_BUSY 1 to 0 transition.
72462 … (0x1<<28) // When set enables generation of a smbus event on master START_BUSY 1 to 0 transition.
72471 …bit changes to '1' each time the WATCHDOG timer reaches zero. Writing a '1' to this position will …
72473 …1) // This bit changes to '1' each time the HEARTBEAT timer reaches zero. Writing a '1' to this po…
72474 …CP_REG_SMBUS_EVENT_STATUS_HEARTBEAT_TO_SHIFT 1
72475 …bit changes to '1' each time the POLL_ASF timer reaches zero. Writing a '1' to this position will …
72477 …bit changes to '1' each time the POLL_LEGACY timer reaches zero. Writing a '1' to this position wi…
72479 …bit changes to '1' each time the RETRANSMIT timer reaches zero. Writing a '1' to this position wil…
72483 … (0x1<<20) // This bit set when slave hardware received an ARP command and ARP_E…
72485 …bit is set when slave hardware detected read transaction directed toward the SMBUS block. Writing …
72487 …UN (0x1<<22) // This bit is set when Slave T…
72489 …bit is set when slave START_BUSY transitions from 1 to 0. Writing a '1' to this position will clea…
72491 …bit is set when the slave receive FIFO holds at least one valid transaction. Writing a '1' to this…
72493 …bit is set when the slave receive FIFO is equal to or larger than the Slave RX_FIFO_THRESHOLD. Wri…
72495 …bit is set when the slave receive FIFO become full. Writing a '1' to this position will clear this…
72497 …RUN (0x1<<27) // This bit is set when Master …
72499 …bit is set when master START_BUSY transitions from 1 to 0. Writing a '1' to this position will cle…
72501 …bit is set when the master receive FIFO holds at least one valid transaction. Writing a '1' to thi…
72503 …bit is set when the master receive FIFO is equal to or larger than the Master RX_FIFO_THRESHOLD. W…
72505 …bit is set when the master receive FIFO become full. Writing a '1' to this position will clear thi…
72512 … (0x1<<31) // 0 - Byte other then last in an WMBUS transaction …
72519 …bit indicates status of the PEC checking. HW will check the PEC only in case where PEC bit in SMBU…
72535 … (0x3<<28) // This field is valid only when RD_STATUS = 2'…
72540 … (0x1<<0) // This bit should be set by firmware before ARP_EN0 bit is set. This bit …
72542 … (0x1<<1) // This bit should be set by firmware before ARP_EN0 bit …
72543 …CP_REG_SMBUS_ARP_STATE_AR_FLAG0_SHIFT 1
72546 … (0x1<<4) // This bit should be set by firmware before ARP_EN1 bit is set. This bit …
72548 … (0x1<<5) // This bit should be set by firmware before ARP_EN1 bit is se…
72550 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN0 bit is set.
72559 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN0 bit is set.
72568 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN0 bit is set.
72577 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN0 bit is set.
72580 …1 (0xff<<8) // UDID_0 byte 1.
72586 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN1 bit is set.
72595 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN1 bit is set.
72604 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN1 bit is set.
72613 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN1 bit is set.
72616 …1 (0xff<<8) // UDID_1 byte 1.
72624 … (0x1<<0) // Setting this bit to '1' will flush the …
72626 … (0x1<<1) // Setting this bit to '1' will set the error…
72627 …CP_REG_TO_BMB_FIFO_COMMAND__ERROR_SHIFT 1
72637 … (0x1<<0) // This bit indicates that the …
72645 … (0x1<<0) // Setting this bit to '1' will indicate t…
72647 …BMB_FIFO_COMMAND_UNUSED0 (0x7<<1) //
72648 …CP_REG_FRM_BMB_FIFO_COMMAND_UNUSED0_SHIFT 1
72649 … (0x1<<4) // Setting this bit to '1' will flush the …
72651 … (0x1<<5) // Setting this bit to '1' will clear all …
72654 … (0x1<<0) // This bit indicates that the …
72656 …BMB_FIFO_STATUS_UNUSED0 (0x1<<1) //
72657 …CP_REG_FRM_BMB_FIFO_STATUS_UNUSED0_SHIFT 1
72658 …ese bits indicate the incoming traffic class of the packet. These are bits [1:0] of the PKT_TC fro…
72660 … (0x1<<4) // This bit indicates that the …
72662 … (0x1<<5) // This bit indicates that the …
72664 … (0x1<<6) // This bit indicates that the …
72666 … (0x1<<7) // This bit indicates that the …
72684 … processor. This can be modified at any time and may be used for processor-to-processor communicat…
72690 …ATA_IN_EN (0x1<<1) // Enable for input…
72691 …SDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN_SHIFT 1
72700 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
72702 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
72704 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
72706 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
72731 …_EN (0x1<<1) // Enable for input…
72732 …SDM_REG_ENABLE_IN2_CM_ACK_IN_EN_SHIFT 1
72738 …DY_OUT_EN (0x1<<1) // Enable for outpu…
72739 …SDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN_SHIFT 1
72750 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
72781 …_OUT_EN (0x1<<1) // Enable for VF/PF…
72782 …SDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN_SHIFT 1
72786 … (0x1<<0) // This bit should be set to di…
72788 …RS (0x1<<1) // This bit should be set …
72789 …SDM_REG_DISABLE_ENGINE_DISABLE_TIMERS_SHIFT 1
72790 … (0x1<<2) // This bit should be set to di…
72792 … (0x1<<3) // This bit should be set to di…
72794 … (0x1<<4) // This bit should be set to di…
72796 … (0x1<<5) // This bit should be set to di…
72798 … (0x1<<6) // This bit should be set to di…
72800 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from …
72802 … (0x1<<8) // This bit should be set to di…
72804 … (0x1<<9) // This bit should be set to di…
72809 …ROR (0x1<<1) // Indicates that o…
72810 …SDM_REG_INT_STS_INP_QUEUE_ERROR_SHIFT 1
72815 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
72859 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
72861 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
72865 … (0x1<<29) // Last-cycle indication not …
72870 … (0x1<<0) // This bit masks, when set, the Interrupt bit: X…
72872 … (0x1<<1) // This bit masks, when set, the Interrupt …
72873 …SDM_REG_INT_MASK_INP_QUEUE_ERROR_SHIFT 1
72874 … (0x1<<2) // This bit masks, when set, the Interrupt bit: X…
72876 … (0x1<<3) // This bit masks, when set, the Interrupt bit: X…
72878 … (0x1<<4) // This bit masks, when set, the Interrupt bit: X…
72880 … (0x1<<5) // This bit masks, when set, the Interrupt bit: X…
72882 … (0x1<<6) // This bit masks, when set, the Interrupt bit: X…
72884 … (0x1<<7) // This bit masks, when set, the Interrupt bit: X…
72886 … (0x1<<8) // This bit masks, when set, the Interrupt bit: X…
72888 … (0x1<<9) // This bit masks, when set, the Interrupt bit: X…
72890 … (0x1<<10) // This bit masks, when set, the Interrupt bit: X…
72892 … (0x1<<11) // This bit masks, when set, the Interrupt bit: X…
72894 … (0x1<<12) // This bit masks, when set, the Interrupt bit: X…
72896 … (0x1<<13) // This bit masks, when set, the Interrupt bit: X…
72898 … (0x1<<14) // This bit masks, when set, the Interrupt bit: X…
72900 … (0x1<<15) // This bit masks, when set, the Interrupt bit: X…
72902 … (0x1<<16) // This bit masks, when set, the Interrupt bit: X…
72904 … (0x1<<17) // This bit masks, when set, the Interrupt bit: X…
72906 … (0x1<<18) // This bit masks, when set, the Interrupt bit: X…
72908 … (0x1<<19) // This bit masks, when set, the Interrupt bit: X…
72910 … (0x1<<20) // This bit masks, when set, the Interrupt bit: X…
72912 … (0x1<<21) // This bit masks, when set, the Interrupt bit: X…
72914 … (0x1<<22) // This bit masks, when set, the Interrupt bit: X…
72916 … (0x1<<23) // This bit masks, when set, the Interrupt bit: X…
72918 … (0x1<<24) // This bit masks, when set, the Interrupt bit: X…
72920 … (0x1<<25) // This bit masks, when set, the Interrupt bit: X…
72922 … (0x1<<26) // This bit masks, when set, the Interrupt bit: X…
72924 … (0x1<<27) // This bit masks, when set, the Interrupt bit: X…
72926 … (0x1<<28) // This bit masks, when set, the Interrupt bit: X…
72928 … (0x1<<29) // This bit masks, when set, the Interrupt bit: X…
72930 … (0x1<<30) // This bit masks, when set, the Interrupt bit: X…
72935 …_ERROR (0x1<<1) // Indicates that o…
72936 …SDM_REG_INT_STS_WR_INP_QUEUE_ERROR_SHIFT 1
72941 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
72985 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
72987 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
72991 …E5 (0x1<<29) // Last-cycle indication not …
72998 …E_ERROR (0x1<<1) // Indicates that o…
72999 …SDM_REG_INT_STS_CLR_INP_QUEUE_ERROR_SHIFT 1
73004 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73048 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
73050 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
73054 …_E5 (0x1<<29) // Last-cycle indication not …
73059 … (0x1<<5) // This bit masks, when set, the Parity bit: XS…
73061 … (0x1<<0) // This bit masks, when set, the Parity bit: XS…
73063 … (0x1<<0) // This bit masks, when set, the Parity bit: XS…
73065 … (0x1<<1) // This bit masks, when set, the Parity bi…
73066 …SDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_E5_SHIFT 1
73067 … (0x1<<1) // This bit masks, when set, the Parity bi…
73068 …SDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT 1
73069 … (0x1<<2) // This bit masks, when set, the Parity bit: XS…
73071 … (0x1<<2) // This bit masks, when set, the Parity bit: XS…
73073 … (0x1<<3) // This bit masks, when set, the Parity bit: XS…
73075 … (0x1<<4) // This bit masks, when set, the Parity bit: XS…
73077 … (0x1<<5) // This bit masks, when set, the Parity bit: XS…
73079 … (0x1<<6) // This bit masks, when set, the Parity bit: XS…
73081 … (0x1<<7) // This bit masks, when set, the Parity bit: XS…
73083 … (0x1<<8) // This bit masks, when set, the Parity bit: XS…
73085 … (0x1<<3) // This bit masks, when set, the Parity bit: XS…
73087 … (0x1<<9) // This bit masks, when set, the Parity bit: XS…
73089 … (0x1<<9) // This bit masks, when set, the Parity bit: XS…
73091 … (0x1<<10) // This bit masks, when set, the Parity bit: XS…
73100 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
73101 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
73102 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
73103 …in the event of an inp_queue_error interrupt. It contains a vector with a bit per input queue. Cl…
73104 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
73107 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
73127 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
73165 … 0xf80c80UL //Access:R DataWidth:0x1 // Remote XCM FIFO full (exist only in MSDM => XCM inte…
73166 … 0xf80c84UL //Access:R DataWidth:0x1 // Remote YCM FIFO full (exist only in MSDM => YCM inte…
73193 …0xf80d68UL //Access:R DataWidth:0x1 // Remote XCM FIFO empty (exist only within MSDM => XCM …
73194 …0xf80d6cUL //Access:R DataWidth:0x1 // Remote YCM FIFO empty (exist only within MSDM => YCM …
73200 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
73201 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
73202 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
73203 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
73204 … 0xf82000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
73206 … 0xf82400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the imme…
73208 … 0xf82800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BRB …
73210 … 0xf82c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PXP …
73212 … 0xf83000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the inte…
73214 … 0xf83400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DORQ…
73216 … 0xf83800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the exte…
73218 … 0xf83c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PRM …
73220 … 0xf84000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
73223 … 0xf85000UL //Access:WB DataWidth:0x40 // Input queue memory. Access only for debugging.
73225 … 0xf88000UL //Access:WB DataWidth:0x40 // CM queue memory. Access only for debugging.
73231 …ATA_IN_EN (0x1<<1) // Enable for input…
73232 …SDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN_SHIFT 1
73241 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
73243 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
73245 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
73247 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
73272 …_EN (0x1<<1) // Enable for input…
73273 …SDM_REG_ENABLE_IN2_CM_ACK_IN_EN_SHIFT 1
73279 …DY_OUT_EN (0x1<<1) // Enable for outpu…
73280 …SDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN_SHIFT 1
73291 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
73322 …_OUT_EN (0x1<<1) // Enable for VF/PF…
73323 …SDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN_SHIFT 1
73327 … (0x1<<0) // This bit should be set to di…
73329 …RS (0x1<<1) // This bit should be set …
73330 …SDM_REG_DISABLE_ENGINE_DISABLE_TIMERS_SHIFT 1
73331 … (0x1<<2) // This bit should be set to di…
73333 … (0x1<<3) // This bit should be set to di…
73335 … (0x1<<4) // This bit should be set to di…
73337 … (0x1<<5) // This bit should be set to di…
73339 … (0x1<<6) // This bit should be set to di…
73341 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from …
73343 … (0x1<<8) // This bit should be set to di…
73345 … (0x1<<9) // This bit should be set to di…
73350 …ROR (0x1<<1) // Indicates that o…
73351 …SDM_REG_INT_STS_INP_QUEUE_ERROR_SHIFT 1
73356 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73400 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
73402 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
73406 … (0x1<<29) // Last-cycle indication not …
73411 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Y…
73413 … (0x1<<1) // This bit masks, when set, the Interrupt …
73414 …SDM_REG_INT_MASK_INP_QUEUE_ERROR_SHIFT 1
73415 … (0x1<<2) // This bit masks, when set, the Interrupt bit: Y…
73417 … (0x1<<3) // This bit masks, when set, the Interrupt bit: Y…
73419 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Y…
73421 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Y…
73423 … (0x1<<6) // This bit masks, when set, the Interrupt bit: Y…
73425 … (0x1<<7) // This bit masks, when set, the Interrupt bit: Y…
73427 … (0x1<<8) // This bit masks, when set, the Interrupt bit: Y…
73429 … (0x1<<9) // This bit masks, when set, the Interrupt bit: Y…
73431 … (0x1<<10) // This bit masks, when set, the Interrupt bit: Y…
73433 … (0x1<<11) // This bit masks, when set, the Interrupt bit: Y…
73435 … (0x1<<12) // This bit masks, when set, the Interrupt bit: Y…
73437 … (0x1<<13) // This bit masks, when set, the Interrupt bit: Y…
73439 … (0x1<<14) // This bit masks, when set, the Interrupt bit: Y…
73441 … (0x1<<15) // This bit masks, when set, the Interrupt bit: Y…
73443 … (0x1<<16) // This bit masks, when set, the Interrupt bit: Y…
73445 … (0x1<<17) // This bit masks, when set, the Interrupt bit: Y…
73447 … (0x1<<18) // This bit masks, when set, the Interrupt bit: Y…
73449 … (0x1<<19) // This bit masks, when set, the Interrupt bit: Y…
73451 … (0x1<<20) // This bit masks, when set, the Interrupt bit: Y…
73453 … (0x1<<21) // This bit masks, when set, the Interrupt bit: Y…
73455 … (0x1<<22) // This bit masks, when set, the Interrupt bit: Y…
73457 … (0x1<<23) // This bit masks, when set, the Interrupt bit: Y…
73459 … (0x1<<24) // This bit masks, when set, the Interrupt bit: Y…
73461 … (0x1<<25) // This bit masks, when set, the Interrupt bit: Y…
73463 … (0x1<<26) // This bit masks, when set, the Interrupt bit: Y…
73465 … (0x1<<27) // This bit masks, when set, the Interrupt bit: Y…
73467 … (0x1<<28) // This bit masks, when set, the Interrupt bit: Y…
73469 … (0x1<<29) // This bit masks, when set, the Interrupt bit: Y…
73471 … (0x1<<30) // This bit masks, when set, the Interrupt bit: Y…
73476 …_ERROR (0x1<<1) // Indicates that o…
73477 …SDM_REG_INT_STS_WR_INP_QUEUE_ERROR_SHIFT 1
73482 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73526 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
73528 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
73532 …E5 (0x1<<29) // Last-cycle indication not …
73539 …E_ERROR (0x1<<1) // Indicates that o…
73540 …SDM_REG_INT_STS_CLR_INP_QUEUE_ERROR_SHIFT 1
73545 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73589 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
73591 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
73595 …_E5 (0x1<<29) // Last-cycle indication not …
73600 … (0x1<<5) // This bit masks, when set, the Parity bit: YS…
73602 … (0x1<<0) // This bit masks, when set, the Parity bit: YS…
73604 … (0x1<<0) // This bit masks, when set, the Parity bit: YS…
73606 … (0x1<<1) // This bit masks, when set, the Parity bi…
73607 …SDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_E5_SHIFT 1
73608 … (0x1<<1) // This bit masks, when set, the Parity bi…
73609 …SDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2_SHIFT 1
73610 … (0x1<<2) // This bit masks, when set, the Parity bit: YS…
73612 … (0x1<<2) // This bit masks, when set, the Parity bit: YS…
73614 … (0x1<<3) // This bit masks, when set, the Parity bit: YS…
73616 … (0x1<<4) // This bit masks, when set, the Parity bit: YS…
73618 … (0x1<<5) // This bit masks, when set, the Parity bit: YS…
73620 … (0x1<<6) // This bit masks, when set, the Parity bit: YS…
73622 … (0x1<<7) // This bit masks, when set, the Parity bit: YS…
73624 … (0x1<<8) // This bit masks, when set, the Parity bit: YS…
73626 … (0x1<<3) // This bit masks, when set, the Parity bit: YS…
73628 … (0x1<<9) // This bit masks, when set, the Parity bit: YS…
73637 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
73638 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
73639 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
73640 …in the event of an inp_queue_error interrupt. It contains a vector with a bit per input queue. Cl…
73641 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
73644 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
73665 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
73703 … 0xf90c80UL //Access:R DataWidth:0x1 // Remote XCM FIFO full (exist only in MSDM => XCM inte…
73704 … 0xf90c84UL //Access:R DataWidth:0x1 // Remote YCM FIFO full (exist only in MSDM => YCM inte…
73731 …0xf90d68UL //Access:R DataWidth:0x1 // Remote XCM FIFO empty (exist only within MSDM => XCM …
73732 …0xf90d6cUL //Access:R DataWidth:0x1 // Remote YCM FIFO empty (exist only within MSDM => YCM …
73738 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
73739 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
73740 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
73741 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
73742 … 0xf92000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
73744 … 0xf92400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the imme…
73746 … 0xf92800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BRB …
73748 … 0xf92c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PXP …
73750 … 0xf93000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the inte…
73752 … 0xf93400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DORQ…
73754 … 0xf93800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the exte…
73756 … 0xf93c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PRM …
73758 … 0xf94000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
73761 … 0xf95000UL //Access:WB DataWidth:0x40 // Input queue memory. Access only for debugging.
73763 … 0xf98000UL //Access:WB DataWidth:0x40 // CM queue memory. Access only for debugging.
73769 …ATA_IN_EN (0x1<<1) // Enable for input…
73770 …SDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN_SHIFT 1
73779 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
73781 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
73783 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
73785 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
73810 …_EN (0x1<<1) // Enable for input…
73811 …SDM_REG_ENABLE_IN2_CM_ACK_IN_EN_SHIFT 1
73817 …DY_OUT_EN (0x1<<1) // Enable for outpu…
73818 …SDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN_SHIFT 1
73829 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
73860 …_OUT_EN (0x1<<1) // Enable for VF/PF…
73861 …SDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN_SHIFT 1
73865 … (0x1<<0) // This bit should be set to di…
73867 …RS (0x1<<1) // This bit should be set …
73868 …SDM_REG_DISABLE_ENGINE_DISABLE_TIMERS_SHIFT 1
73869 … (0x1<<2) // This bit should be set to di…
73871 … (0x1<<3) // This bit should be set to di…
73873 … (0x1<<4) // This bit should be set to di…
73875 … (0x1<<5) // This bit should be set to di…
73877 … (0x1<<6) // This bit should be set to di…
73879 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from …
73881 … (0x1<<8) // This bit should be set to di…
73883 … (0x1<<9) // This bit should be set to di…
73888 …ROR (0x1<<1) // Indicates that o…
73889 …SDM_REG_INT_STS_INP_QUEUE_ERROR_SHIFT 1
73894 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73938 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
73940 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
73944 … (0x1<<29) // Last-cycle indication not …
73949 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
73951 … (0x1<<1) // This bit masks, when set, the Interrupt …
73952 …SDM_REG_INT_MASK_INP_QUEUE_ERROR_SHIFT 1
73953 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
73955 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
73957 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
73959 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
73961 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
73963 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
73965 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
73967 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
73969 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
73971 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
73973 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
73975 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
73977 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
73979 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
73981 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
73983 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
73985 … (0x1<<18) // This bit masks, when set, the Interrupt bit: P…
73987 … (0x1<<19) // This bit masks, when set, the Interrupt bit: P…
73989 … (0x1<<20) // This bit masks, when set, the Interrupt bit: P…
73991 … (0x1<<21) // This bit masks, when set, the Interrupt bit: P…
73993 … (0x1<<22) // This bit masks, when set, the Interrupt bit: P…
73995 … (0x1<<23) // This bit masks, when set, the Interrupt bit: P…
73997 … (0x1<<24) // This bit masks, when set, the Interrupt bit: P…
73999 … (0x1<<25) // This bit masks, when set, the Interrupt bit: P…
74001 … (0x1<<26) // This bit masks, when set, the Interrupt bit: P…
74003 … (0x1<<27) // This bit masks, when set, the Interrupt bit: P…
74005 … (0x1<<28) // This bit masks, when set, the Interrupt bit: P…
74007 … (0x1<<29) // This bit masks, when set, the Interrupt bit: P…
74009 … (0x1<<30) // This bit masks, when set, the Interrupt bit: P…
74014 …_ERROR (0x1<<1) // Indicates that o…
74015 …SDM_REG_INT_STS_WR_INP_QUEUE_ERROR_SHIFT 1
74020 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74064 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
74066 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
74070 …E5 (0x1<<29) // Last-cycle indication not …
74077 …E_ERROR (0x1<<1) // Indicates that o…
74078 …SDM_REG_INT_STS_CLR_INP_QUEUE_ERROR_SHIFT 1
74083 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74127 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
74129 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
74133 …_E5 (0x1<<29) // Last-cycle indication not …
74138 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
74140 … (0x1<<1) // This bit masks, when set, the Parity bi…
74141 …SDM_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_E5_SHIFT 1
74142 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
74144 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
74146 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
74148 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
74150 … (0x1<<1) // This bit masks, when set, the Parity bi…
74151 …SDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2_SHIFT 1
74152 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
74154 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
74156 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
74158 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
74160 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
74162 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
74164 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
74166 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
74168 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
74170 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
74172 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
74174 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
74179 …004_I_ECC_EN_E5 (0x1<<1) // Enable ECC for m…
74180 …SDM_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_E5_SHIFT 1
74182 …_E5 (0x1<<0) // Set parity only for memory ecc inst…
74184 …_ECC_PRTY_E5 (0x1<<1) // Set parity only for memory…
74185 …SDM_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_E5_SHIFT 1
74189 …TED_0_MEM004_I_ECC_CORRECT_E5 (0x1<<1) // Record if a corr…
74190 …SDM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_E5_SHIFT 1
74199 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
74200 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
74201 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
74202 …in the event of an inp_queue_error interrupt. It contains a vector with a bit per input queue. Cl…
74203 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
74206 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
74227 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
74265 … 0xfa0c80UL //Access:R DataWidth:0x1 // Remote XCM FIFO full (exist only in MSDM => XCM inte…
74266 … 0xfa0c84UL //Access:R DataWidth:0x1 // Remote YCM FIFO full (exist only in MSDM => YCM inte…
74293 …0xfa0d68UL //Access:R DataWidth:0x1 // Remote XCM FIFO empty (exist only within MSDM => XCM …
74294 …0xfa0d6cUL //Access:R DataWidth:0x1 // Remote YCM FIFO empty (exist only within MSDM => YCM …
74300 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
74301 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
74302 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
74303 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
74304 … 0xfa2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
74306 … 0xfa2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the imme…
74308 … 0xfa2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BRB …
74310 … 0xfa2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PXP …
74312 … 0xfa3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the inte…
74314 … 0xfa3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DORQ…
74316 … 0xfa3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the exte…
74318 … 0xfa3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PRM …
74320 … 0xfa4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
74323 … 0xfa5000UL //Access:WB DataWidth:0x40 // Input queue memory. Access only for debugging.
74325 … 0xfa8000UL //Access:WB DataWidth:0x40 // CM queue memory. Access only for debugging.
74331 …ATA_IN_EN (0x1<<1) // Enable for input…
74332 …SDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN_SHIFT 1
74341 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
74343 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
74345 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
74347 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
74372 …_EN (0x1<<1) // Enable for input…
74373 …SDM_REG_ENABLE_IN2_CM_ACK_IN_EN_SHIFT 1
74379 …DY_OUT_EN (0x1<<1) // Enable for outpu…
74380 …SDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN_SHIFT 1
74391 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
74422 …_OUT_EN (0x1<<1) // Enable for VF/PF…
74423 …SDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN_SHIFT 1
74427 … (0x1<<0) // This bit should be set to di…
74429 …RS (0x1<<1) // This bit should be set …
74430 …SDM_REG_DISABLE_ENGINE_DISABLE_TIMERS_SHIFT 1
74431 … (0x1<<2) // This bit should be set to di…
74433 … (0x1<<3) // This bit should be set to di…
74435 … (0x1<<4) // This bit should be set to di…
74437 … (0x1<<5) // This bit should be set to di…
74439 … (0x1<<6) // This bit should be set to di…
74441 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from …
74443 … (0x1<<8) // This bit should be set to di…
74445 … (0x1<<9) // This bit should be set to di…
74450 …ROR (0x1<<1) // Indicates that o…
74451 …SDM_REG_INT_STS_INP_QUEUE_ERROR_SHIFT 1
74456 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74500 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
74502 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
74506 … (0x1<<29) // Last-cycle indication not …
74511 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
74513 … (0x1<<1) // This bit masks, when set, the Interrupt …
74514 …SDM_REG_INT_MASK_INP_QUEUE_ERROR_SHIFT 1
74515 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
74517 … (0x1<<3) // This bit masks, when set, the Interrupt bit: T…
74519 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
74521 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
74523 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
74525 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
74527 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
74529 … (0x1<<9) // This bit masks, when set, the Interrupt bit: T…
74531 … (0x1<<10) // This bit masks, when set, the Interrupt bit: T…
74533 … (0x1<<11) // This bit masks, when set, the Interrupt bit: T…
74535 … (0x1<<12) // This bit masks, when set, the Interrupt bit: T…
74537 … (0x1<<13) // This bit masks, when set, the Interrupt bit: T…
74539 … (0x1<<14) // This bit masks, when set, the Interrupt bit: T…
74541 … (0x1<<15) // This bit masks, when set, the Interrupt bit: T…
74543 … (0x1<<16) // This bit masks, when set, the Interrupt bit: T…
74545 … (0x1<<17) // This bit masks, when set, the Interrupt bit: T…
74547 … (0x1<<18) // This bit masks, when set, the Interrupt bit: T…
74549 … (0x1<<19) // This bit masks, when set, the Interrupt bit: T…
74551 … (0x1<<20) // This bit masks, when set, the Interrupt bit: T…
74553 … (0x1<<21) // This bit masks, when set, the Interrupt bit: T…
74555 … (0x1<<22) // This bit masks, when set, the Interrupt bit: T…
74557 … (0x1<<23) // This bit masks, when set, the Interrupt bit: T…
74559 … (0x1<<24) // This bit masks, when set, the Interrupt bit: T…
74561 … (0x1<<25) // This bit masks, when set, the Interrupt bit: T…
74563 … (0x1<<26) // This bit masks, when set, the Interrupt bit: T…
74565 … (0x1<<27) // This bit masks, when set, the Interrupt bit: T…
74567 … (0x1<<28) // This bit masks, when set, the Interrupt bit: T…
74569 … (0x1<<29) // This bit masks, when set, the Interrupt bit: T…
74571 … (0x1<<30) // This bit masks, when set, the Interrupt bit: T…
74576 …_ERROR (0x1<<1) // Indicates that o…
74577 …SDM_REG_INT_STS_WR_INP_QUEUE_ERROR_SHIFT 1
74582 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74626 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
74628 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
74632 …E5 (0x1<<29) // Last-cycle indication not …
74639 …E_ERROR (0x1<<1) // Indicates that o…
74640 …SDM_REG_INT_STS_CLR_INP_QUEUE_ERROR_SHIFT 1
74645 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74689 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
74691 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
74695 …_E5 (0x1<<29) // Last-cycle indication not …
74700 … (0x1<<6) // This bit masks, when set, the Parity bit: TS…
74702 … (0x1<<0) // This bit masks, when set, the Parity bit: TS…
74704 … (0x1<<0) // This bit masks, when set, the Parity bit: TS…
74706 … (0x1<<1) // This bit masks, when set, the Parity bi…
74707 …SDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_E5_SHIFT 1
74708 … (0x1<<1) // This bit masks, when set, the Parity bi…
74709 …SDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT 1
74710 … (0x1<<2) // This bit masks, when set, the Parity bit: TS…
74712 … (0x1<<2) // This bit masks, when set, the Parity bit: TS…
74714 … (0x1<<3) // This bit masks, when set, the Parity bit: TS…
74716 … (0x1<<3) // This bit masks, when set, the Parity bit: TS…
74718 … (0x1<<4) // This bit masks, when set, the Parity bit: TS…
74720 … (0x1<<5) // This bit masks, when set, the Parity bit: TS…
74722 … (0x1<<6) // This bit masks, when set, the Parity bit: TS…
74724 … (0x1<<7) // This bit masks, when set, the Parity bit: TS…
74726 … (0x1<<8) // This bit masks, when set, the Parity bit: TS…
74728 … (0x1<<9) // This bit masks, when set, the Parity bit: TS…
74730 … (0x1<<4) // This bit masks, when set, the Parity bit: TS…
74732 … (0x1<<10) // This bit masks, when set, the Parity bit: TS…
74741 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
74742 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
74743 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
74744 …in the event of an inp_queue_error interrupt. It contains a vector with a bit per input queue. Cl…
74745 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
74748 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
74768 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
74806 … 0xfb0c80UL //Access:R DataWidth:0x1 // Remote XCM FIFO full (exist only in MSDM => XCM inte…
74807 … 0xfb0c84UL //Access:R DataWidth:0x1 // Remote YCM FIFO full (exist only in MSDM => YCM inte…
74834 …0xfb0d68UL //Access:R DataWidth:0x1 // Remote XCM FIFO empty (exist only within MSDM => XCM …
74835 …0xfb0d6cUL //Access:R DataWidth:0x1 // Remote YCM FIFO empty (exist only within MSDM => YCM …
74841 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
74842 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
74843 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
74844 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
74845 … 0xfb2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
74847 … 0xfb2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the imme…
74849 … 0xfb2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BRB …
74851 … 0xfb2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PXP …
74853 … 0xfb3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the inte…
74855 … 0xfb3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DORQ…
74857 … 0xfb3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the exte…
74859 … 0xfb3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PRM …
74861 … 0xfb4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
74864 … 0xfb5000UL //Access:WB DataWidth:0x40 // Input queue memory. Access only for debugging.
74866 … 0xfb8000UL //Access:WB DataWidth:0x40 // CM queue memory. Access only for debugging.
74872 …ATA_IN_EN (0x1<<1) // Enable for input…
74873 …SDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN_SHIFT 1
74882 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
74884 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
74886 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
74888 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
74913 …_EN (0x1<<1) // Enable for input…
74914 …SDM_REG_ENABLE_IN2_CM_ACK_IN_EN_SHIFT 1
74920 …DY_OUT_EN (0x1<<1) // Enable for outpu…
74921 …SDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN_SHIFT 1
74932 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
74963 …_OUT_EN (0x1<<1) // Enable for VF/PF…
74964 …SDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN_SHIFT 1
74968 … (0x1<<0) // This bit should be set to di…
74970 …RS (0x1<<1) // This bit should be set …
74971 …SDM_REG_DISABLE_ENGINE_DISABLE_TIMERS_SHIFT 1
74972 … (0x1<<2) // This bit should be set to di…
74974 … (0x1<<3) // This bit should be set to di…
74976 … (0x1<<4) // This bit should be set to di…
74978 … (0x1<<5) // This bit should be set to di…
74980 … (0x1<<6) // This bit should be set to di…
74982 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from …
74984 … (0x1<<8) // This bit should be set to di…
74986 … (0x1<<9) // This bit should be set to di…
74991 …ROR (0x1<<1) // Indicates that o…
74992 …SDM_REG_INT_STS_INP_QUEUE_ERROR_SHIFT 1
74997 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75041 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
75043 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
75047 … (0x1<<29) // Last-cycle indication not …
75052 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
75054 … (0x1<<1) // This bit masks, when set, the Interrupt …
75055 …SDM_REG_INT_MASK_INP_QUEUE_ERROR_SHIFT 1
75056 … (0x1<<2) // This bit masks, when set, the Interrupt bit: M…
75058 … (0x1<<3) // This bit masks, when set, the Interrupt bit: M…
75060 … (0x1<<4) // This bit masks, when set, the Interrupt bit: M…
75062 … (0x1<<5) // This bit masks, when set, the Interrupt bit: M…
75064 … (0x1<<6) // This bit masks, when set, the Interrupt bit: M…
75066 … (0x1<<7) // This bit masks, when set, the Interrupt bit: M…
75068 … (0x1<<8) // This bit masks, when set, the Interrupt bit: M…
75070 … (0x1<<9) // This bit masks, when set, the Interrupt bit: M…
75072 … (0x1<<10) // This bit masks, when set, the Interrupt bit: M…
75074 … (0x1<<11) // This bit masks, when set, the Interrupt bit: M…
75076 … (0x1<<12) // This bit masks, when set, the Interrupt bit: M…
75078 … (0x1<<13) // This bit masks, when set, the Interrupt bit: M…
75080 … (0x1<<14) // This bit masks, when set, the Interrupt bit: M…
75082 … (0x1<<15) // This bit masks, when set, the Interrupt bit: M…
75084 … (0x1<<16) // This bit masks, when set, the Interrupt bit: M…
75086 … (0x1<<17) // This bit masks, when set, the Interrupt bit: M…
75088 … (0x1<<18) // This bit masks, when set, the Interrupt bit: M…
75090 … (0x1<<19) // This bit masks, when set, the Interrupt bit: M…
75092 … (0x1<<20) // This bit masks, when set, the Interrupt bit: M…
75094 … (0x1<<21) // This bit masks, when set, the Interrupt bit: M…
75096 … (0x1<<22) // This bit masks, when set, the Interrupt bit: M…
75098 … (0x1<<23) // This bit masks, when set, the Interrupt bit: M…
75100 … (0x1<<24) // This bit masks, when set, the Interrupt bit: M…
75102 … (0x1<<25) // This bit masks, when set, the Interrupt bit: M…
75104 … (0x1<<26) // This bit masks, when set, the Interrupt bit: M…
75106 … (0x1<<27) // This bit masks, when set, the Interrupt bit: M…
75108 … (0x1<<28) // This bit masks, when set, the Interrupt bit: M…
75110 … (0x1<<29) // This bit masks, when set, the Interrupt bit: M…
75112 … (0x1<<30) // This bit masks, when set, the Interrupt bit: M…
75117 …_ERROR (0x1<<1) // Indicates that o…
75118 …SDM_REG_INT_STS_WR_INP_QUEUE_ERROR_SHIFT 1
75123 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75167 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
75169 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
75173 …E5 (0x1<<29) // Last-cycle indication not …
75180 …E_ERROR (0x1<<1) // Indicates that o…
75181 …SDM_REG_INT_STS_CLR_INP_QUEUE_ERROR_SHIFT 1
75186 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75230 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
75232 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
75236 …_E5 (0x1<<29) // Last-cycle indication not …
75241 … (0x1<<0) // This bit masks, when set, the Parity bit: MS…
75243 … (0x1<<1) // This bit masks, when set, the Parity bi…
75244 …SDM_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_E5_SHIFT 1
75245 … (0x1<<10) // This bit masks, when set, the Parity bit: MS…
75247 … (0x1<<2) // This bit masks, when set, the Parity bit: MS…
75249 … (0x1<<0) // This bit masks, when set, the Parity bit: MS…
75251 … (0x1<<3) // This bit masks, when set, the Parity bit: MS…
75253 … (0x1<<1) // This bit masks, when set, the Parity bi…
75254 …SDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT 1
75255 … (0x1<<4) // This bit masks, when set, the Parity bit: MS…
75257 … (0x1<<2) // This bit masks, when set, the Parity bit: MS…
75259 … (0x1<<5) // This bit masks, when set, the Parity bit: MS…
75261 … (0x1<<3) // This bit masks, when set, the Parity bit: MS…
75263 … (0x1<<6) // This bit masks, when set, the Parity bit: MS…
75265 … (0x1<<5) // This bit masks, when set, the Parity bit: MS…
75267 … (0x1<<7) // This bit masks, when set, the Parity bit: MS…
75269 … (0x1<<8) // This bit masks, when set, the Parity bit: MS…
75271 … (0x1<<7) // This bit masks, when set, the Parity bit: MS…
75273 … (0x1<<9) // This bit masks, when set, the Parity bit: MS…
75275 … (0x1<<4) // This bit masks, when set, the Parity bit: MS…
75277 … (0x1<<10) // This bit masks, when set, the Parity bit: MS…
75279 … (0x1<<6) // This bit masks, when set, the Parity bit: MS…
75281 … (0x1<<11) // This bit masks, when set, the Parity bit: MS…
75283 … (0x1<<8) // This bit masks, when set, the Parity bit: MS…
75285 … (0x1<<9) // This bit masks, when set, the Parity bit: MS…
75290 …004_I_ECC_EN_E5 (0x1<<1) // Enable ECC for m…
75291 …SDM_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_E5_SHIFT 1
75293 …_E5 (0x1<<0) // Set parity only for memory ecc inst…
75295 …_ECC_PRTY_E5 (0x1<<1) // Set parity only for memory…
75296 …SDM_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_E5_SHIFT 1
75300 …TED_0_MEM004_I_ECC_CORRECT_E5 (0x1<<1) // Record if a corr…
75301 …SDM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_E5_SHIFT 1
75310 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
75311 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
75312 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
75313 …in the event of an inp_queue_error interrupt. It contains a vector with a bit per input queue. Cl…
75314 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
75317 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
75339 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
75377 … 0xfc0c80UL //Access:R DataWidth:0x1 // Remote XCM FIFO full (exist only in MSDM => XCM inte…
75378 … 0xfc0c84UL //Access:R DataWidth:0x1 // Remote YCM FIFO full (exist only in MSDM => YCM inte…
75405 …0xfc0d68UL //Access:R DataWidth:0x1 // Remote XCM FIFO empty (exist only within MSDM => XCM …
75406 …0xfc0d6cUL //Access:R DataWidth:0x1 // Remote YCM FIFO empty (exist only within MSDM => YCM …
75412 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
75413 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
75414 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
75415 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
75416 … 0xfc2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
75418 … 0xfc2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the imme…
75420 … 0xfc2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BRB …
75422 … 0xfc2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PXP …
75424 … 0xfc3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the inte…
75426 … 0xfc3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DORQ…
75428 … 0xfc3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the exte…
75430 … 0xfc3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PRM …
75432 … 0xfc4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
75435 … 0xfc5000UL //Access:WB DataWidth:0x40 // Input queue memory. Access only for debugging.
75437 … 0xfc8000UL //Access:WB DataWidth:0x40 // CM queue memory. Access only for debugging.
75443 …ATA_IN_EN (0x1<<1) // Enable for input…
75444 …SDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN_SHIFT 1
75453 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
75455 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
75457 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
75459 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
75484 …_EN (0x1<<1) // Enable for input…
75485 …SDM_REG_ENABLE_IN2_CM_ACK_IN_EN_SHIFT 1
75491 …DY_OUT_EN (0x1<<1) // Enable for outpu…
75492 …SDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN_SHIFT 1
75503 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
75534 …_OUT_EN (0x1<<1) // Enable for VF/PF…
75535 …SDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN_SHIFT 1
75539 … (0x1<<0) // This bit should be set to di…
75541 …RS (0x1<<1) // This bit should be set …
75542 …SDM_REG_DISABLE_ENGINE_DISABLE_TIMERS_SHIFT 1
75543 … (0x1<<2) // This bit should be set to di…
75545 … (0x1<<3) // This bit should be set to di…
75547 … (0x1<<4) // This bit should be set to di…
75549 … (0x1<<5) // This bit should be set to di…
75551 … (0x1<<6) // This bit should be set to di…
75553 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from …
75555 … (0x1<<8) // This bit should be set to di…
75557 … (0x1<<9) // This bit should be set to di…
75562 …ROR (0x1<<1) // Indicates that o…
75563 …SDM_REG_INT_STS_INP_QUEUE_ERROR_SHIFT 1
75568 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75612 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
75614 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
75618 … (0x1<<29) // Last-cycle indication not …
75623 … (0x1<<0) // This bit masks, when set, the Interrupt bit: U…
75625 … (0x1<<1) // This bit masks, when set, the Interrupt …
75626 …SDM_REG_INT_MASK_INP_QUEUE_ERROR_SHIFT 1
75627 … (0x1<<2) // This bit masks, when set, the Interrupt bit: U…
75629 … (0x1<<3) // This bit masks, when set, the Interrupt bit: U…
75631 … (0x1<<4) // This bit masks, when set, the Interrupt bit: U…
75633 … (0x1<<5) // This bit masks, when set, the Interrupt bit: U…
75635 … (0x1<<6) // This bit masks, when set, the Interrupt bit: U…
75637 … (0x1<<7) // This bit masks, when set, the Interrupt bit: U…
75639 … (0x1<<8) // This bit masks, when set, the Interrupt bit: U…
75641 … (0x1<<9) // This bit masks, when set, the Interrupt bit: U…
75643 … (0x1<<10) // This bit masks, when set, the Interrupt bit: U…
75645 … (0x1<<11) // This bit masks, when set, the Interrupt bit: U…
75647 … (0x1<<12) // This bit masks, when set, the Interrupt bit: U…
75649 … (0x1<<13) // This bit masks, when set, the Interrupt bit: U…
75651 … (0x1<<14) // This bit masks, when set, the Interrupt bit: U…
75653 … (0x1<<15) // This bit masks, when set, the Interrupt bit: U…
75655 … (0x1<<16) // This bit masks, when set, the Interrupt bit: U…
75657 … (0x1<<17) // This bit masks, when set, the Interrupt bit: U…
75659 … (0x1<<18) // This bit masks, when set, the Interrupt bit: U…
75661 … (0x1<<19) // This bit masks, when set, the Interrupt bit: U…
75663 … (0x1<<20) // This bit masks, when set, the Interrupt bit: U…
75665 … (0x1<<21) // This bit masks, when set, the Interrupt bit: U…
75667 … (0x1<<22) // This bit masks, when set, the Interrupt bit: U…
75669 … (0x1<<23) // This bit masks, when set, the Interrupt bit: U…
75671 … (0x1<<24) // This bit masks, when set, the Interrupt bit: U…
75673 … (0x1<<25) // This bit masks, when set, the Interrupt bit: U…
75675 … (0x1<<26) // This bit masks, when set, the Interrupt bit: U…
75677 … (0x1<<27) // This bit masks, when set, the Interrupt bit: U…
75679 … (0x1<<28) // This bit masks, when set, the Interrupt bit: U…
75681 … (0x1<<29) // This bit masks, when set, the Interrupt bit: U…
75683 … (0x1<<30) // This bit masks, when set, the Interrupt bit: U…
75688 …_ERROR (0x1<<1) // Indicates that o…
75689 …SDM_REG_INT_STS_WR_INP_QUEUE_ERROR_SHIFT 1
75694 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75738 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
75740 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
75744 …E5 (0x1<<29) // Last-cycle indication not …
75751 …E_ERROR (0x1<<1) // Indicates that o…
75752 …SDM_REG_INT_STS_CLR_INP_QUEUE_ERROR_SHIFT 1
75757 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75801 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
75803 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM …
75807 …_E5 (0x1<<29) // Last-cycle indication not …
75812 … (0x1<<9) // This bit masks, when set, the Parity bit: US…
75814 … (0x1<<0) // This bit masks, when set, the Parity bit: US…
75816 … (0x1<<0) // This bit masks, when set, the Parity bit: US…
75818 … (0x1<<1) // This bit masks, when set, the Parity bi…
75819 …SDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_E5_SHIFT 1
75820 … (0x1<<1) // This bit masks, when set, the Parity bi…
75821 …SDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2_SHIFT 1
75822 … (0x1<<2) // This bit masks, when set, the Parity bit: US…
75824 … (0x1<<2) // This bit masks, when set, the Parity bit: US…
75826 … (0x1<<3) // This bit masks, when set, the Parity bit: US…
75828 … (0x1<<4) // This bit masks, when set, the Parity bit: US…
75830 … (0x1<<5) // This bit masks, when set, the Parity bit: US…
75832 … (0x1<<6) // This bit masks, when set, the Parity bit: US…
75834 … (0x1<<7) // This bit masks, when set, the Parity bit: US…
75836 … (0x1<<8) // This bit masks, when set, the Parity bit: US…
75838 … (0x1<<3) // This bit masks, when set, the Parity bit: US…
75840 … (0x1<<9) // This bit masks, when set, the Parity bit: US…
75842 … (0x1<<5) // This bit masks, when set, the Parity bit: US…
75844 … (0x1<<10) // This bit masks, when set, the Parity bit: US…
75853 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
75854 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
75855 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
75856 …in the event of an inp_queue_error interrupt. It contains a vector with a bit per input queue. Cl…
75857 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
75860 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
75881 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
75919 … 0xfd0c80UL //Access:R DataWidth:0x1 // Remote XCM FIFO full (exist only in MSDM => XCM inte…
75920 … 0xfd0c84UL //Access:R DataWidth:0x1 // Remote YCM FIFO full (exist only in MSDM => YCM inte…
75947 …0xfd0d68UL //Access:R DataWidth:0x1 // Remote XCM FIFO empty (exist only within MSDM => XCM …
75948 …0xfd0d6cUL //Access:R DataWidth:0x1 // Remote YCM FIFO empty (exist only within MSDM => YCM …
75954 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
75955 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
75956 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
75957 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
75958 … 0xfd2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
75960 … 0xfd2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the imme…
75962 … 0xfd2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BRB …
75964 … 0xfd2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PXP …
75966 … 0xfd3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the inte…
75968 … 0xfd3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DORQ…
75970 … 0xfd3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the exte…
75972 … 0xfd3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PRM …
75974 … 0xfd4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
75977 … 0xfd5000UL //Access:WB DataWidth:0x40 // Input queue memory. Access only for debugging.
75979 … 0xfd8000UL //Access:WB DataWidth:0x40 // CM queue memory. Access only for debugging.
75982 … // Debug only. Initialises specific states and statuses. To initialise the state - write 1 int…
75986 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
75987 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
75988 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
75989 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
76026 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76027 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76028 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76029 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76030 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76031 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76032 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76033 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76034 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76035 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76036 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76037 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76038 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76039 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76040 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76041 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76042 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76043 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76044 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76045 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76046 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76047 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76048 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76049 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76050 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76051 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76052 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76053 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76054 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76055 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76056 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76057 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76058 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76059 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76060 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76061 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76062 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76063 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76064 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76065 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76066 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76067 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76068 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76069 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76070 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76071 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76072 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76073 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76074 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76078 …FL_ERR (0x1<<1) // Write to full ST…
76079 …CM_REG_INT_STS_0_IS_STORM_OVFL_ERR_SHIFT 1
76113 … (0x1<<0) // This bit masks, when set, the Interrupt bit: X…
76115 … (0x1<<1) // This bit masks, when set, the Interrupt …
76116 …CM_REG_INT_MASK_0_IS_STORM_OVFL_ERR_SHIFT 1
76117 … (0x1<<2) // This bit masks, when set, the Interrupt bit: X…
76119 … (0x1<<3) // This bit masks, when set, the Interrupt bit: X…
76121 … (0x1<<4) // This bit masks, when set, the Interrupt bit: X…
76123 … (0x1<<5) // This bit masks, when set, the Interrupt bit: X…
76125 … (0x1<<6) // This bit masks, when set, the Interrupt bit: X…
76127 … (0x1<<7) // This bit masks, when set, the Interrupt bit: X…
76129 … (0x1<<8) // This bit masks, when set, the Interrupt bit: X…
76131 … (0x1<<9) // This bit masks, when set, the Interrupt bit: X…
76133 … (0x1<<10) // This bit masks, when set, the Interrupt bit: X…
76135 … (0x1<<11) // This bit masks, when set, the Interrupt bit: X…
76137 … (0x1<<12) // This bit masks, when set, the Interrupt bit: X…
76139 … (0x1<<13) // This bit masks, when set, the Interrupt bit: X…
76141 … (0x1<<14) // This bit masks, when set, the Interrupt bit: X…
76143 … (0x1<<15) // This bit masks, when set, the Interrupt bit: X…
76145 … (0x1<<16) // This bit masks, when set, the Interrupt bit: X…
76147 … (0x1<<17) // This bit masks, when set, the Interrupt bit: X…
76152 …_OVFL_ERR (0x1<<1) // Write to full ST…
76153 …CM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR_SHIFT 1
76189 …M_OVFL_ERR (0x1<<1) // Write to full ST…
76190 …CM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR_SHIFT 1
76226 …L_ERR (0x1<<1) // Write to full Do…
76227 …CM_REG_INT_STS_1_IS_DORQ_OVFL_ERR_SHIFT 1
76262 … (0x1<<19) // In-process Table overflo…
76275 … (0x1<<0) // This bit masks, when set, the Interrupt bit: X…
76277 … (0x1<<1) // This bit masks, when set, the Interrupt …
76278 …CM_REG_INT_MASK_1_IS_DORQ_OVFL_ERR_SHIFT 1
76279 … (0x1<<2) // This bit masks, when set, the Interrupt bit: X…
76281 … (0x1<<3) // This bit masks, when set, the Interrupt bit: X…
76283 … (0x1<<4) // This bit masks, when set, the Interrupt bit: X…
76285 … (0x1<<5) // This bit masks, when set, the Interrupt bit: X…
76287 … (0x1<<6) // This bit masks, when set, the Interrupt bit: X…
76289 … (0x1<<7) // This bit masks, when set, the Interrupt bit: X…
76291 … (0x1<<8) // This bit masks, when set, the Interrupt bit: X…
76293 … (0x1<<9) // This bit masks, when set, the Interrupt bit: X…
76295 … (0x1<<10) // This bit masks, when set, the Interrupt bit: X…
76297 … (0x1<<11) // This bit masks, when set, the Interrupt bit: X…
76299 … (0x1<<12) // This bit masks, when set, the Interrupt bit: X…
76301 … (0x1<<13) // This bit masks, when set, the Interrupt bit: X…
76303 … (0x1<<14) // This bit masks, when set, the Interrupt bit: X…
76305 … (0x1<<15) // This bit masks, when set, the Interrupt bit: X…
76307 … (0x1<<16) // This bit masks, when set, the Interrupt bit: X…
76309 … (0x1<<17) // This bit masks, when set, the Interrupt bit: X…
76311 … (0x1<<18) // This bit masks, when set, the Interrupt bit: X…
76313 … (0x1<<19) // This bit masks, when set, the Interrupt bit: X…
76315 … (0x1<<20) // This bit masks, when set, the Interrupt bit: X…
76317 … (0x1<<21) // This bit masks, when set, the Interrupt bit: X…
76319 … (0x1<<22) // This bit masks, when set, the Interrupt bit: X…
76321 … (0x1<<23) // This bit masks, when set, the Interrupt bit: X…
76323 … (0x1<<24) // This bit masks, when set, the Interrupt bit: X…
76328 …OVFL_ERR (0x1<<1) // Write to full Do…
76329 …CM_REG_INT_STS_WR_1_IS_DORQ_OVFL_ERR_SHIFT 1
76364 … (0x1<<19) // In-process Table overflo…
76379 …_OVFL_ERR (0x1<<1) // Write to full Do…
76380 …CM_REG_INT_STS_CLR_1_IS_DORQ_OVFL_ERR_SHIFT 1
76415 … (0x1<<19) // In-process Table overflo…
76430 …NT_MSG_PRCS_OVFL (0x1<<1) // QM Active State …
76431 …CM_REG_INT_STS_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL_SHIFT 1
76445 … (0x1<<0) // This bit masks, when set, the Interrupt bit: X…
76447 … (0x1<<1) // This bit masks, when set, the Interrupt …
76448 …CM_REG_INT_MASK_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL_SHIFT 1
76449 … (0x1<<2) // This bit masks, when set, the Interrupt bit: X…
76451 … (0x1<<3) // This bit masks, when set, the Interrupt bit: X…
76453 … (0x1<<4) // This bit masks, when set, the Interrupt bit: X…
76455 … (0x1<<5) // This bit masks, when set, the Interrupt bit: X…
76457 … (0x1<<6) // This bit masks, when set, the Interrupt bit: X…
76459 … (0x1<<7) // This bit masks, when set, the Interrupt bit: X…
76464 …T_CNT_MSG_PRCS_OVFL (0x1<<1) // QM Active State …
76465 …CM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL_SHIFT 1
76481 …ST_CNT_MSG_PRCS_OVFL (0x1<<1) // QM Active State …
76482 …CM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL_SHIFT 1
76496 … (0x1<<0) // This bit masks, when set, the Parity bit: XC…
76498 … (0x1<<0) // This bit masks, when set, the Parity bit: XC…
76500 … (0x1<<1) // This bit masks, when set, the Parity bi…
76501 …CM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_SHIFT 1
76502 … (0x1<<2) // This bit masks, when set, the Parity bit: XC…
76504 … (0x1<<3) // This bit masks, when set, the Parity bit: XC…
76506 … (0x1<<4) // This bit masks, when set, the Parity bit: XC…
76508 … (0x1<<5) // This bit masks, when set, the Parity bit: XC…
76510 … (0x1<<6) // This bit masks, when set, the Parity bit: XC…
76512 … (0x1<<6) // This bit masks, when set, the Parity bit: XC…
76514 … (0x1<<7) // This bit masks, when set, the Parity bit: XC…
76516 … (0x1<<7) // This bit masks, when set, the Parity bit: XC…
76518 … (0x1<<8) // This bit masks, when set, the Parity bit: XC…
76520 … (0x1<<9) // This bit masks, when set, the Parity bit: XC…
76522 … (0x1<<10) // This bit masks, when set, the Parity bit: XC…
76524 … (0x1<<11) // This bit masks, when set, the Parity bit: XC…
76526 … (0x1<<14) // This bit masks, when set, the Parity bit: XC…
76528 … (0x1<<12) // This bit masks, when set, the Parity bit: XC…
76530 … (0x1<<12) // This bit masks, when set, the Parity bit: XC…
76532 … (0x1<<13) // This bit masks, when set, the Parity bit: XC…
76534 … (0x1<<13) // This bit masks, when set, the Parity bit: XC…
76536 … (0x1<<14) // This bit masks, when set, the Parity bit: XC…
76538 … (0x1<<27) // This bit masks, when set, the Parity bit: XC…
76540 … (0x1<<15) // This bit masks, when set, the Parity bit: XC…
76542 … (0x1<<15) // This bit masks, when set, the Parity bit: XC…
76544 … (0x1<<16) // This bit masks, when set, the Parity bit: XC…
76546 … (0x1<<16) // This bit masks, when set, the Parity bit: XC…
76548 … (0x1<<17) // This bit masks, when set, the Parity bit: XC…
76550 … (0x1<<17) // This bit masks, when set, the Parity bit: XC…
76552 … (0x1<<18) // This bit masks, when set, the Parity bit: XC…
76554 … (0x1<<18) // This bit masks, when set, the Parity bit: XC…
76556 … (0x1<<19) // This bit masks, when set, the Parity bit: XC…
76558 … (0x1<<19) // This bit masks, when set, the Parity bit: XC…
76560 … (0x1<<20) // This bit masks, when set, the Parity bit: XC…
76562 … (0x1<<20) // This bit masks, when set, the Parity bit: XC…
76564 … (0x1<<21) // This bit masks, when set, the Parity bit: XC…
76566 … (0x1<<21) // This bit masks, when set, the Parity bit: XC…
76568 … (0x1<<22) // This bit masks, when set, the Parity bit: XC…
76570 … (0x1<<22) // This bit masks, when set, the Parity bit: XC…
76572 … (0x1<<24) // This bit masks, when set, the Parity bit: XC…
76574 … (0x1<<23) // This bit masks, when set, the Parity bit: XC…
76576 … (0x1<<23) // This bit masks, when set, the Parity bit: XC…
76578 … (0x1<<25) // This bit masks, when set, the Parity bit: XC…
76580 … (0x1<<24) // This bit masks, when set, the Parity bit: XC…
76582 … (0x1<<24) // This bit masks, when set, the Parity bit: XC…
76584 … (0x1<<25) // This bit masks, when set, the Parity bit: XC…
76586 … (0x1<<25) // This bit masks, when set, the Parity bit: XC…
76588 … (0x1<<26) // This bit masks, when set, the Parity bit: XC…
76590 … (0x1<<26) // This bit masks, when set, the Parity bit: XC…
76592 … (0x1<<27) // This bit masks, when set, the Parity bit: XC…
76594 … (0x1<<28) // This bit masks, when set, the Parity bit: XC…
76596 … (0x1<<28) // This bit masks, when set, the Parity bit: XC…
76598 … (0x1<<29) // This bit masks, when set, the Parity bit: XC…
76600 … (0x1<<29) // This bit masks, when set, the Parity bit: XC…
76602 … (0x1<<30) // This bit masks, when set, the Parity bit: XC…
76604 … (0x1<<0) // This bit masks, when set, the Parity bit: XC…
76606 … (0x1<<5) // This bit masks, when set, the Parity bit: XC…
76608 … (0x1<<8) // This bit masks, when set, the Parity bit: XC…
76610 … (0x1<<23) // This bit masks, when set, the Parity bit: XC…
76612 … (0x1<<27) // This bit masks, when set, the Parity bit: XC…
76614 … (0x1<<6) // This bit masks, when set, the Parity bit: XC…
76616 … (0x1<<7) // This bit masks, when set, the Parity bit: XC…
76618 … (0x1<<8) // This bit masks, when set, the Parity bit: XC…
76620 … (0x1<<30) // This bit masks, when set, the Parity bit: XC…
76623 … (0x1<<0) // This bit masks, when set, the Parity bit: XC…
76625 … (0x1<<1) // This bit masks, when set, the Parity bi…
76626 …CM_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_K2_E5_SHIFT 1
76627 … (0x1<<1) // This bit masks, when set, the Parity bi…
76628 …CM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_BB_SHIFT 1
76629 … (0x1<<2) // This bit masks, when set, the Parity bit: XC…
76631 … (0x1<<2) // This bit masks, when set, the Parity bit: XC…
76633 … (0x1<<3) // This bit masks, when set, the Parity bit: XC…
76635 … (0x1<<3) // This bit masks, when set, the Parity bit: XC…
76637 … (0x1<<4) // This bit masks, when set, the Parity bit: XC…
76639 … (0x1<<4) // This bit masks, when set, the Parity bit: XC…
76641 … (0x1<<5) // This bit masks, when set, the Parity bit: XC…
76643 … (0x1<<5) // This bit masks, when set, the Parity bit: XC…
76645 … (0x1<<6) // This bit masks, when set, the Parity bit: XC…
76647 … (0x1<<6) // This bit masks, when set, the Parity bit: XC…
76649 … (0x1<<7) // This bit masks, when set, the Parity bit: XC…
76651 … (0x1<<7) // This bit masks, when set, the Parity bit: XC…
76653 … (0x1<<8) // This bit masks, when set, the Parity bit: XC…
76655 … (0x1<<8) // This bit masks, when set, the Parity bit: XC…
76657 … (0x1<<9) // This bit masks, when set, the Parity bit: XC…
76659 … (0x1<<9) // This bit masks, when set, the Parity bit: XC…
76661 … (0x1<<10) // This bit masks, when set, the Parity bit: XC…
76663 … (0x1<<10) // This bit masks, when set, the Parity bit: XC…
76665 … (0x1<<11) // This bit masks, when set, the Parity bit: XC…
76667 … (0x1<<0) // This bit masks, when set, the Parity bit: XC…
76674 …03_I_ECC_0_EN (0x1<<1) // Enable ECC for m…
76675 …CM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_0_EN_SHIFT 1
76707 …BB (0x1<<0) // Set parity only for memory ecc inst…
76709 …E5 (0x1<<0) // Set parity only for memory ecc inst…
76711 …ECC_0_PRTY (0x1<<1) // Set parity only for memory…
76712 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_0_PRTY_SHIFT 1
76713 …Y (0x1<<2) // Set parity only for memory ecc inst…
76715 …Y (0x1<<3) // Set parity only for memory ecc inst…
76717 …Y (0x1<<4) // Set parity only for memory ecc inst…
76719 …Y_E5 (0x1<<5) // Set parity only for memory ecc inst…
76721 …Y_E5 (0x1<<6) // Set parity only for memory ecc inst…
76723 …Y_K2 (0x1<<6) // Set parity only for memory ecc inst…
76725 …Y_E5 (0x1<<7) // Set parity only for memory ecc inst…
76727 …Y_K2 (0x1<<7) // Set parity only for memory ecc inst…
76729 …Y_E5 (0x1<<8) // Set parity only for memory ecc inst…
76731 …K2 (0x1<<0) // Set parity only for memory ecc inst…
76733 …BB_K2 (0x1<<5) // Set parity only for memory ecc inst…
76735 …K2 (0x1<<8) // Set parity only for memory ecc inst…
76737 …Y_BB (0x1<<6) // Set parity only for memory ecc inst…
76739 …Y_BB (0x1<<7) // Set parity only for memory ecc inst…
76741 …BB (0x1<<8) // Set parity only for memory ecc inst…
76748 …ED_0_MEM003_I_ECC_0_CORRECT (0x1<<1) // Record if a corr…
76749 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_0_CORRECT_SHIFT 1
76781 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
76783 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76784 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76785 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76786 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76787 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76788 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76789 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76790 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76791 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76792 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76793 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76794 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76795 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76796 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76797 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76798 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76799 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76800 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76801 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76802 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76803 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76804 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76805 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76806 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76807 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76808 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76809 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76810 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76811 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76812 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76813 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76814 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76815 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76816 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76817 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76818 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76819 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76820 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76821 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76822 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76823 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76824 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76825 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76826 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76827 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76828 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76829 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76830 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76831 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76832 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76833 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76834 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76835 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76836 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
76837 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
76838 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
76839 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
76840 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
76841 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
76842 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
76843 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
76844 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
76845 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
76846 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
76847 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
76848 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
76849 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76850 …esponding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir gr…
76851 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76852 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76853 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76854 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76855 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
76856 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76857 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76858 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76859 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76860 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76861 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76862 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76863 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76864 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76865 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76866 … 0x1000680UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
76868 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
76879 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
76880 …/ Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock gro…
76881 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
76883 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
76888 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
76889 …D Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- …
76890 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
76891 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
76905 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76906 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76907 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76908 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76909 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76910 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76911 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76912 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76913 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76914 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76915 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76916 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76917 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76918 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76919 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76920 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76921 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76922 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76923 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76924 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76925 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76926 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76927 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76928 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76942 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
76943 …[9]: PQ Type (0-Other PQ; 1-TX PQ); if bit[9]=0; then [8:6] reserved; [5:0] Physical queue connect…
76944 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
76945 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
76946 … 0x1000a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
76947 … 0x1000a10UL //Access:R DataWidth:0x1 // In-process Table almost …
76953 … 0x1000a28UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76954 … 0x1000a2cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76955 … 0x1000a30UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76956 … 0x1000a34UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76957 … 0x1000a38UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76958 … 0x1000a3cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76959 … 0x1000a40UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76960 … 0x1000a44UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76961 … 0x1000a48UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76962 … 0x1000a4cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76963 … 0x1000a50UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76964 … 0x1000a54UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76965 … 0x1000a58UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76966 … 0x1000a5cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76967 … 0x1000a60UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76968 … 0x1000a64UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76969 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
76970 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
76971 …th:0x5 // QM output initial credit (XCM TX queues). Max credit available - 16.Write writes the …
76972 …RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the …
76993 …UL //Access:W DataWidth:0x20 // Used to write the GRC message. Write only. To distinguish if …
77008 …tive counter overflow/uder-run. Is reset on read. [0] - If set, there was under-run; [1] - If set,…
77025 … DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Read only.
77028 … DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Read only.
77030 … DataWidth:0x20 // Debug read from XSEM Input stage buffer with 32-bits granularity. Read only.
77032 … DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Read only.
77034 … DataWidth:0x20 // Debug read from DORQ Input stage buffer with 32-bits granularity. Read only.
77036 … DataWidth:0x20 // Debug read from USDM Input stage buffer with 32-bits granularity. Read only.
77038 … DataWidth:0x20 // Debug read from XSDM Input stage buffer with 32-bits granularity. Read only.
77040 … DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Read only.
77042 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
77043 …aWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to Aggregation Connect…
77044 …DataWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to STORM Connection…
77047 … 0x1001900UL //Access:R DataWidth:0xa // Debug only. Read only access to LCI…
77050 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
77053 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
77103 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77104 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77105 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77106 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77107 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77108 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77109 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77110 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77111 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77112 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77113 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77114 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77115 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77116 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77117 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77118 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77119 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77120 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77121 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77122 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77123 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77124 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77125 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77126 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
77247 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77248 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77249 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77250 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77251 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77252 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77253 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77254 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77255 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77256 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77257 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77258 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77259 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77260 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77261 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77262 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77263 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
77264 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
77273 … DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Read only.
77275 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
77276 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
77283 … DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.
77284 … DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.
77286 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
77288 …alue. [28:20] PQ number. [29:29] Reserved. [31:30] Command type: 0 - SET; 1 - DEC; 2 - INC; The ad…
77291 … // Debug only. Initialises specific states and statuses. To initialise the state - write 1 int…
77293 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
77294 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
77295 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
77296 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
77333 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77334 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
77335 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77336 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
77337 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77338 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
77342 …FL_ERR (0x1<<1) // Write to full ST…
77343 …CM_REG_INT_STS_0_IS_STORM_OVFL_ERR_SHIFT 1
77371 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Y…
77373 … (0x1<<1) // This bit masks, when set, the Interrupt …
77374 …CM_REG_INT_MASK_0_IS_STORM_OVFL_ERR_SHIFT 1
77375 … (0x1<<2) // This bit masks, when set, the Interrupt bit: Y…
77377 … (0x1<<3) // This bit masks, when set, the Interrupt bit: Y…
77379 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Y…
77381 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Y…
77383 … (0x1<<6) // This bit masks, when set, the Interrupt bit: Y…
77385 … (0x1<<7) // This bit masks, when set, the Interrupt bit: Y…
77387 … (0x1<<8) // This bit masks, when set, the Interrupt bit: Y…
77389 … (0x1<<9) // This bit masks, when set, the Interrupt bit: Y…
77391 … (0x1<<10) // This bit masks, when set, the Interrupt bit: Y…
77393 … (0x1<<11) // This bit masks, when set, the Interrupt bit: Y…
77395 … (0x1<<12) // This bit masks, when set, the Interrupt bit: Y…
77397 … (0x1<<13) // This bit masks, when set, the Interrupt bit: Y…
77399 … (0x1<<14) // This bit masks, when set, the Interrupt bit: Y…
77404 …_OVFL_ERR (0x1<<1) // Write to full ST…
77405 …CM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR_SHIFT 1
77435 …M_OVFL_ERR (0x1<<1) // Write to full ST…
77436 …CM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR_SHIFT 1
77466 …R_ERR (0x1<<1) // Read from empty …
77467 …CM_REG_INT_STS_1_IS_PBF_UNDER_ERR_SHIFT 1
77492 … (0x1<<14) // In-process Table overflo…
77511 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Y…
77513 … (0x1<<1) // This bit masks, when set, the Interrupt …
77514 …CM_REG_INT_MASK_1_IS_PBF_UNDER_ERR_SHIFT 1
77515 … (0x1<<2) // This bit masks, when set, the Interrupt bit: Y…
77517 … (0x1<<3) // This bit masks, when set, the Interrupt bit: Y…
77519 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Y…
77521 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Y…
77523 … (0x1<<6) // This bit masks, when set, the Interrupt bit: Y…
77525 … (0x1<<7) // This bit masks, when set, the Interrupt bit: Y…
77527 … (0x1<<8) // This bit masks, when set, the Interrupt bit: Y…
77529 … (0x1<<9) // This bit masks, when set, the Interrupt bit: Y…
77531 … (0x1<<10) // This bit masks, when set, the Interrupt bit: Y…
77533 … (0x1<<11) // This bit masks, when set, the Interrupt bit: Y…
77535 … (0x1<<12) // This bit masks, when set, the Interrupt bit: Y…
77537 … (0x1<<13) // This bit masks, when set, the Interrupt bit: Y…
77539 … (0x1<<14) // This bit masks, when set, the Interrupt bit: Y…
77541 … (0x1<<15) // This bit masks, when set, the Interrupt bit: Y…
77543 … (0x1<<16) // This bit masks, when set, the Interrupt bit: Y…
77545 … (0x1<<17) // This bit masks, when set, the Interrupt bit: Y…
77547 … (0x1<<18) // This bit masks, when set, the Interrupt bit: Y…
77549 … (0x1<<19) // This bit masks, when set, the Interrupt bit: Y…
77551 … (0x1<<20) // This bit masks, when set, the Interrupt bit: Y…
77553 … (0x1<<21) // This bit masks, when set, the Interrupt bit: Y…
77555 … (0x1<<22) // This bit masks, when set, the Interrupt bit: Y…
77560 …NDER_ERR (0x1<<1) // Read from empty …
77561 …CM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR_SHIFT 1
77586 … (0x1<<14) // In-process Table overflo…
77607 …UNDER_ERR (0x1<<1) // Read from empty …
77608 …CM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR_SHIFT 1
77633 … (0x1<<14) // In-process Table overflo…
77655 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Y…
77664 … (0x1<<0) // This bit masks, when set, the Parity bit: YC…
77666 … (0x1<<1) // This bit masks, when set, the Parity bi…
77667 …CM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_SHIFT 1
77668 … (0x1<<2) // This bit masks, when set, the Parity bit: YC…
77670 … (0x1<<3) // This bit masks, when set, the Parity bit: YC…
77672 … (0x1<<4) // This bit masks, when set, the Parity bit: YC…
77674 … (0x1<<6) // This bit masks, when set, the Parity bit: YC…
77676 … (0x1<<5) // This bit masks, when set, the Parity bit: YC…
77678 … (0x1<<7) // This bit masks, when set, the Parity bit: YC…
77680 … (0x1<<6) // This bit masks, when set, the Parity bit: YC…
77682 … (0x1<<7) // This bit masks, when set, the Parity bit: YC…
77684 … (0x1<<8) // This bit masks, when set, the Parity bit: YC…
77686 … (0x1<<9) // This bit masks, when set, the Parity bit: YC…
77688 … (0x1<<27) // This bit masks, when set, the Parity bit: YC…
77690 … (0x1<<10) // This bit masks, when set, the Parity bit: YC…
77692 … (0x1<<13) // This bit masks, when set, the Parity bit: YC…
77694 … (0x1<<14) // This bit masks, when set, the Parity bit: YC…
77696 … (0x1<<11) // This bit masks, when set, the Parity bit: YC…
77698 … (0x1<<26) // This bit masks, when set, the Parity bit: YC…
77700 … (0x1<<11) // This bit masks, when set, the Parity bit: YC…
77702 … (0x1<<12) // This bit masks, when set, the Parity bit: YC…
77704 … (0x1<<25) // This bit masks, when set, the Parity bit: YC…
77706 … (0x1<<13) // This bit masks, when set, the Parity bit: YC…
77708 … (0x1<<10) // This bit masks, when set, the Parity bit: YC…
77710 … (0x1<<14) // This bit masks, when set, the Parity bit: YC…
77712 … (0x1<<11) // This bit masks, when set, the Parity bit: YC…
77714 … (0x1<<12) // This bit masks, when set, the Parity bit: YC…
77716 … (0x1<<15) // This bit masks, when set, the Parity bit: YC…
77718 … (0x1<<16) // This bit masks, when set, the Parity bit: YC…
77720 … (0x1<<23) // This bit masks, when set, the Parity bit: YC…
77722 … (0x1<<17) // This bit masks, when set, the Parity bit: YC…
77724 … (0x1<<24) // This bit masks, when set, the Parity bit: YC…
77726 … (0x1<<18) // This bit masks, when set, the Parity bit: YC…
77728 … (0x1<<12) // This bit masks, when set, the Parity bit: YC…
77730 … (0x1<<13) // This bit masks, when set, the Parity bit: YC…
77732 … (0x1<<19) // This bit masks, when set, the Parity bit: YC…
77734 … (0x1<<16) // This bit masks, when set, the Parity bit: YC…
77736 … (0x1<<17) // This bit masks, when set, the Parity bit: YC…
77738 … (0x1<<20) // This bit masks, when set, the Parity bit: YC…
77740 … (0x1<<17) // This bit masks, when set, the Parity bit: YC…
77742 … (0x1<<18) // This bit masks, when set, the Parity bit: YC…
77744 … (0x1<<21) // This bit masks, when set, the Parity bit: YC…
77746 … (0x1<<18) // This bit masks, when set, the Parity bit: YC…
77748 … (0x1<<19) // This bit masks, when set, the Parity bit: YC…
77750 … (0x1<<22) // This bit masks, when set, the Parity bit: YC…
77752 … (0x1<<14) // This bit masks, when set, the Parity bit: YC…
77754 … (0x1<<15) // This bit masks, when set, the Parity bit: YC…
77756 … (0x1<<23) // This bit masks, when set, the Parity bit: YC…
77758 … (0x1<<24) // This bit masks, when set, the Parity bit: YC…
77760 … (0x1<<25) // This bit masks, when set, the Parity bit: YC…
77762 … (0x1<<26) // This bit masks, when set, the Parity bit: YC…
77764 … (0x1<<22) // This bit masks, when set, the Parity bit: YC…
77766 … (0x1<<23) // This bit masks, when set, the Parity bit: YC…
77768 … (0x1<<27) // This bit masks, when set, the Parity bit: YC…
77770 … (0x1<<20) // This bit masks, when set, the Parity bit: YC…
77772 … (0x1<<22) // This bit masks, when set, the Parity bit: YC…
77774 … (0x1<<28) // This bit masks, when set, the Parity bit: YC…
77776 … (0x1<<29) // This bit masks, when set, the Parity bit: YC…
77778 … (0x1<<20) // This bit masks, when set, the Parity bit: YC…
77780 … (0x1<<30) // This bit masks, when set, the Parity bit: YC…
77782 … (0x1<<0) // This bit masks, when set, the Parity bit: YC…
77784 … (0x1<<3) // This bit masks, when set, the Parity bit: YC…
77786 … (0x1<<4) // This bit masks, when set, the Parity bit: YC…
77788 … (0x1<<5) // This bit masks, when set, the Parity bit: YC…
77790 … (0x1<<8) // This bit masks, when set, the Parity bit: YC…
77792 … (0x1<<9) // This bit masks, when set, the Parity bit: YC…
77794 … (0x1<<15) // This bit masks, when set, the Parity bit: YC…
77796 … (0x1<<16) // This bit masks, when set, the Parity bit: YC…
77798 … (0x1<<19) // This bit masks, when set, the Parity bit: YC…
77800 … (0x1<<21) // This bit masks, when set, the Parity bit: YC…
77802 … (0x1<<24) // This bit masks, when set, the Parity bit: YC…
77804 … (0x1<<25) // This bit masks, when set, the Parity bit: YC…
77806 … (0x1<<26) // This bit masks, when set, the Parity bit: YC…
77808 … (0x1<<27) // This bit masks, when set, the Parity bit: YC…
77810 … (0x1<<28) // This bit masks, when set, the Parity bit: YC…
77812 … (0x1<<28) // This bit masks, when set, the Parity bit: YC…
77814 … (0x1<<29) // This bit masks, when set, the Parity bit: YC…
77816 … (0x1<<29) // This bit masks, when set, the Parity bit: YC…
77818 … (0x1<<30) // This bit masks, when set, the Parity bit: YC…
77820 … (0x1<<0) // This bit masks, when set, the Parity bit: YC…
77822 … (0x1<<3) // This bit masks, when set, the Parity bit: YC…
77824 … (0x1<<4) // This bit masks, when set, the Parity bit: YC…
77826 … (0x1<<5) // This bit masks, when set, the Parity bit: YC…
77828 … (0x1<<8) // This bit masks, when set, the Parity bit: YC…
77830 … (0x1<<9) // This bit masks, when set, the Parity bit: YC…
77832 … (0x1<<21) // This bit masks, when set, the Parity bit: YC…
77834 … (0x1<<30) // This bit masks, when set, the Parity bit: YC…
77837 … (0x1<<0) // This bit masks, when set, the Parity bit: YC…
77839 … (0x1<<1) // This bit masks, when set, the Parity bi…
77840 …CM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_0_E5_SHIFT 1
77841 … (0x1<<2) // This bit masks, when set, the Parity bit: YC…
77843 … (0x1<<0) // This bit masks, when set, the Parity bit: YC…
77845 … (0x1<<3) // This bit masks, when set, the Parity bit: YC…
77847 … (0x1<<0) // This bit masks, when set, the Parity bit: YC…
77849 … (0x1<<1) // This bit masks, when set, the Parity bi…
77850 …CM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_K2_SHIFT 1
77851 … (0x1<<4) // This bit masks, when set, the Parity bit: YC…
77853 … (0x1<<5) // This bit masks, when set, the Parity bit: YC…
77855 … (0x1<<1) // This bit masks, when set, the Parity bi…
77856 …CM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_SHIFT 1
77857 … (0x1<<2) // This bit masks, when set, the Parity bit: YC…
77859 … (0x1<<6) // This bit masks, when set, the Parity bit: YC…
77861 … (0x1<<2) // This bit masks, when set, the Parity bit: YC…
77863 … (0x1<<3) // This bit masks, when set, the Parity bit: YC…
77865 … (0x1<<7) // This bit masks, when set, the Parity bit: YC…
77867 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
77868 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
77869 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
77874 …03_I_ECC_0_EN (0x1<<1) // Enable ECC for m…
77875 …CM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_0_EN_SHIFT 1
77922 …E5 (0x1<<0) // Set parity only for memory ecc inst…
77924 …ECC_0_PRTY (0x1<<1) // Set parity only for memory…
77925 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_0_PRTY_SHIFT 1
77926 …Y (0x1<<2) // Set parity only for memory ecc inst…
77928 …Y_E5 (0x1<<3) // Set parity only for memory ecc inst…
77930 …Y_E5 (0x1<<4) // Set parity only for memory ecc inst…
77932 …Y_BB_K2 (0x1<<6) // Set parity only for memory ecc inst…
77934 …Y_E5 (0x1<<5) // Set parity only for memory ecc inst…
77936 …Y_BB_K2 (0x1<<7) // Set parity only for memory ecc inst…
77938 …Y_E5 (0x1<<6) // Set parity only for memory ecc inst…
77940 …E5 (0x1<<7) // Set parity only for memory ecc inst…
77942 …Y_E5 (0x1<<8) // Set parity only for memory ecc inst…
77944 …Y_E5 (0x1<<9) // Set parity only for memory ecc inst…
77946 …K2 (0x1<<0) // Set parity only for memory ecc inst…
77948 …Y_K2 (0x1<<3) // Set parity only for memory ecc inst…
77950 …Y_K2 (0x1<<4) // Set parity only for memory ecc inst…
77952 …K2 (0x1<<5) // Set parity only for memory ecc inst…
77954 …Y_K2 (0x1<<8) // Set parity only for memory ecc inst…
77956 …Y_K2 (0x1<<9) // Set parity only for memory ecc inst…
77958 …BB (0x1<<0) // Set parity only for memory ecc inst…
77960 …Y_BB (0x1<<3) // Set parity only for memory ecc inst…
77962 …Y_BB (0x1<<4) // Set parity only for memory ecc inst…
77964 …BB (0x1<<5) // Set parity only for memory ecc inst…
77966 …Y_BB (0x1<<8) // Set parity only for memory ecc inst…
77968 …Y_BB (0x1<<9) // Set parity only for memory ecc inst…
77974 …ED_0_MEM003_I_ECC_0_CORRECT (0x1<<1) // Record if a corr…
77975 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_0_CORRECT_SHIFT 1
78022 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
78031 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
78032 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
78033 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
78034 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
78035 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
78036 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
78037 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
78038 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
78072 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78073 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
78074 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78075 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
78076 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78077 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
78078 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78079 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
78080 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78081 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
78082 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
78083 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
78084 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
78085 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
78086 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
78087 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
78088 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
78089 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
78090 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
78091 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78092 …esponding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir gr…
78093 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78094 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78095 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78096 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78097 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
78098 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78099 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78100 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78101 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78102 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78103 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78104 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78105 … 0x1080664UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
78107 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
78108 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
78121 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
78122 …/ Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock gro…
78123 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
78125 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
78130 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
78131 …D Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- …
78132 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
78133 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
78150 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78151 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78152 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78153 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78154 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78155 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78156 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78157 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78158 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78159 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78160 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78161 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78162 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78163 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78164 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78165 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78166 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78167 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78168 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78169 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78170 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78171 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78172 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78173 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78205 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78206 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78207 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78208 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78209 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78210 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78211 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78212 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78213 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
78214 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
78216 … 0x1080908UL //Access:RW DataWidth:0x9 // Physical queue connection number (queue number 1).
78218 … 0x1080910UL //Access:RW DataWidth:0x7 // Physical queue task number (queue number 1).
78219 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78220 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78221 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78222 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78223 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78224 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78225 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78226 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78227 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78228 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78229 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78230 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78231 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78232 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78233 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78234 … 0x1080964UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
78235 … 0x1080968UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
78236 … 0x108096cUL //Access:RW DataWidth:0x3 // EventID bit width per task type…
78237 … 0x1080970UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
78238 … 0x1080974UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
78239 … 0x1080978UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
78240 … 0x108097cUL //Access:RW DataWidth:0x3 // EventID bit width per task type…
78241 … 0x1080980UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
78242 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
78243 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
78244 … 0x1080a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
78245 … 0x1080a10UL //Access:R DataWidth:0x1 // In-process Table almost …
78253 … 0x1080a30UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78254 … 0x1080a34UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78255 … 0x1080a38UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78256 … 0x1080a3cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78257 … 0x1080a40UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78258 … 0x1080a44UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78259 … 0x1080a48UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78260 … 0x1080a4cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78261 … 0x1080a50UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78262 … 0x1080a54UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78263 … 0x1080a58UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78264 … 0x1080a5cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78265 … 0x1080a60UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78266 … 0x1080a64UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78267 … 0x1080a68UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78268 … 0x1080a6cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78269 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
78270 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
78271 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
78272 … // TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the in…
78273 …th:0x3 // TCFC UC Dec Update output initial credit. Max credit available - 7.Write writes the i…
78289 …UL //Access:W DataWidth:0x20 // Used to write the GRC message. Write only. To distinguish if …
78312 … DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Read only.
78314 … DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Read only.
78316 … DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Read only.
78318 … DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Read only.
78320 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
78321 …aWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to Aggregation Connect…
78322 …DataWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to Aggregation Task…
78323 …DataWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to STORM Connection…
78324 … DataWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to STORM Task co…
78330 … 0x1081a00UL //Access:R DataWidth:0xa // Debug only. Read only access to LCI…
78333 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
78336 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
78362 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78363 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78364 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78365 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78366 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78367 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78368 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78369 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78370 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78371 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78372 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78373 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78374 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78375 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78376 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78377 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78378 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78379 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78380 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78381 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78382 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78383 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78384 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78385 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
78506 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
78507 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
78516 … DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Read only.
78517 … DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Read only.
78519 … DataWidth:0x20 // Debug read from XYLD Input stage buffer with 32-bits granularity. Read only.
78520 … DataWidth:0x20 // Debug read from XYLD Input stage buffer with 32-bits granularity. Read only.
78525 … DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.
78526 … DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.
78529 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78530 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78531 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78532 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78533 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78534 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78535 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
78536 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
78539 … // Debug only. Initialises specific states and statuses. To initialise the state - write 1 int…
78541 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
78542 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
78543 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
78544 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
78552 …FL_ERR (0x1<<1) // Write to full ST…
78553 …CM_REG_INT_STS_0_IS_STORM_OVFL_ERR_SHIFT 1
78569 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
78571 … (0x1<<1) // This bit masks, when set, the Interrupt …
78572 …CM_REG_INT_MASK_0_IS_STORM_OVFL_ERR_SHIFT 1
78573 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
78575 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
78577 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
78579 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
78581 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
78583 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
78585 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
78590 …_OVFL_ERR (0x1<<1) // Write to full ST…
78591 …CM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR_SHIFT 1
78609 …M_OVFL_ERR (0x1<<1) // Write to full ST…
78610 …CM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR_SHIFT 1
78632 …R_ERR0_E5 (0x1<<1) // Read from empty …
78633 …CM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_E5_SHIFT 1
78658 …K2 (0x1<<10) // In-process Table overflo…
78660 … (0x1<<8) // In-process Table overflo…
78676 …R_ERR_BB_K2 (0x1<<1) // Read from empty …
78677 …CM_REG_INT_STS_1_IS_PBF_UNDER_ERR_BB_K2_SHIFT 1
78679 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
78681 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
78683 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
78685 … (0x1<<1) // This bit masks, when set, the Interrupt …
78686 …CM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_E5_SHIFT 1
78687 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
78689 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
78691 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
78693 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
78695 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
78697 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
78699 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
78701 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
78703 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
78705 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
78707 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
78709 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
78711 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
78713 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
78715 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
78717 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
78719 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
78721 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
78723 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
78725 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
78727 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
78729 … (0x1<<1) // This bit masks, when set, the Interrupt …
78730 …CM_REG_INT_MASK_1_IS_PBF_UNDER_ERR_BB_K2_SHIFT 1
78738 …NDER_ERR0_E5 (0x1<<1) // Read from empty …
78739 …CM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_E5_SHIFT 1
78764 …BB_K2 (0x1<<10) // In-process Table overflo…
78766 …_E5 (0x1<<8) // In-process Table overflo…
78782 …NDER_ERR_BB_K2 (0x1<<1) // Read from empty …
78783 …CM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR_BB_K2_SHIFT 1
78791 …UNDER_ERR0_E5 (0x1<<1) // Read from empty …
78792 …CM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_E5_SHIFT 1
78817 …_BB_K2 (0x1<<10) // In-process Table overflo…
78819 …L_E5 (0x1<<8) // In-process Table overflo…
78835 …UNDER_ERR_BB_K2 (0x1<<1) // Read from empty …
78836 …CM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR_BB_K2_SHIFT 1
78841 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
78850 … (0x1<<0) // This bit masks, when set, the Parity bit: PC…
78852 … (0x1<<1) // This bit masks, when set, the Parity bi…
78853 …CM_REG_PRTY_MASK_H_0_MEM011_I_ECC_0_RF_INT_E5_SHIFT 1
78854 … (0x1<<2) // This bit masks, when set, the Parity bit: PC…
78856 … (0x1<<3) // This bit masks, when set, the Parity bit: PC…
78858 … (0x1<<4) // This bit masks, when set, the Parity bit: PC…
78860 … (0x1<<3) // This bit masks, when set, the Parity bit: PC…
78862 … (0x1<<4) // This bit masks, when set, the Parity bit: PC…
78864 … (0x1<<5) // This bit masks, when set, the Parity bit: PC…
78866 … (0x1<<4) // This bit masks, when set, the Parity bit: PC…
78868 … (0x1<<3) // This bit masks, when set, the Parity bit: PC…
78870 … (0x1<<5) // This bit masks, when set, the Parity bit: PC…
78872 … (0x1<<13) // This bit masks, when set, the Parity bit: PC…
78874 … (0x1<<6) // This bit masks, when set, the Parity bit: PC…
78876 … (0x1<<5) // This bit masks, when set, the Parity bit: PC…
78878 … (0x1<<6) // This bit masks, when set, the Parity bit: PC…
78880 … (0x1<<7) // This bit masks, when set, the Parity bit: PC…
78882 … (0x1<<6) // This bit masks, when set, the Parity bit: PC…
78884 … (0x1<<7) // This bit masks, when set, the Parity bit: PC…
78886 … (0x1<<8) // This bit masks, when set, the Parity bit: PC…
78888 … (0x1<<7) // This bit masks, when set, the Parity bit: PC…
78890 … (0x1<<8) // This bit masks, when set, the Parity bit: PC…
78892 … (0x1<<9) // This bit masks, when set, the Parity bit: PC…
78894 … (0x1<<8) // This bit masks, when set, the Parity bit: PC…
78896 … (0x1<<9) // This bit masks, when set, the Parity bit: PC…
78898 … (0x1<<10) // This bit masks, when set, the Parity bit: PC…
78900 … (0x1<<11) // This bit masks, when set, the Parity bit: PC…
78902 … (0x1<<10) // This bit masks, when set, the Parity bit: PC…
78904 … (0x1<<12) // This bit masks, when set, the Parity bit: PC…
78906 … (0x1<<13) // This bit masks, when set, the Parity bit: PC…
78908 … (0x1<<9) // This bit masks, when set, the Parity bit: PC…
78910 … (0x1<<14) // This bit masks, when set, the Parity bit: PC…
78912 … (0x1<<10) // This bit masks, when set, the Parity bit: PC…
78914 … (0x1<<14) // This bit masks, when set, the Parity bit: PC…
78916 … (0x1<<15) // This bit masks, when set, the Parity bit: PC…
78918 … (0x1<<0) // This bit masks, when set, the Parity bit: PC…
78920 … (0x1<<1) // This bit masks, when set, the Parity bi…
78921 …CM_REG_PRTY_MASK_H_0_MEM010_I_ECC_0_RF_INT_K2_SHIFT 1
78922 … (0x1<<2) // This bit masks, when set, the Parity bit: PC…
78924 … (0x1<<11) // This bit masks, when set, the Parity bit: PC…
78926 … (0x1<<12) // This bit masks, when set, the Parity bit: PC…
78928 … (0x1<<0) // This bit masks, when set, the Parity bit: PC…
78930 … (0x1<<1) // This bit masks, when set, the Parity bi…
78931 …CM_REG_PRTY_MASK_H_0_MEM009_I_ECC_0_RF_INT_BB_SHIFT 1
78932 … (0x1<<2) // This bit masks, when set, the Parity bit: PC…
78934 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
78935 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
78936 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
78937 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
78938 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
78939 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
78943 …11_I_ECC_0_EN_E5 (0x1<<1) // Enable ECC for m…
78944 …CM_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_0_EN_E5_SHIFT 1
78949 …10_I_ECC_0_EN_K2 (0x1<<1) // Enable ECC for m…
78950 …CM_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_0_EN_K2_SHIFT 1
78955 …09_I_ECC_0_EN_BB (0x1<<1) // Enable ECC for m…
78956 …CM_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_0_EN_BB_SHIFT 1
78960 …E5 (0x1<<0) // Set parity only for memory ecc inst…
78962 …ECC_0_PRTY_E5 (0x1<<1) // Set parity only for memory…
78963 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_0_PRTY_E5_SHIFT 1
78964 …Y_E5 (0x1<<2) // Set parity only for memory ecc inst…
78966 …K2 (0x1<<0) // Set parity only for memory ecc inst…
78968 …ECC_0_PRTY_K2 (0x1<<1) // Set parity only for memory…
78969 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_0_PRTY_K2_SHIFT 1
78970 …Y_K2 (0x1<<2) // Set parity only for memory ecc inst…
78972 …BB (0x1<<0) // Set parity only for memory ecc inst…
78974 …ECC_0_PRTY_BB (0x1<<1) // Set parity only for memory…
78975 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_0_PRTY_BB_SHIFT 1
78976 …Y_BB (0x1<<2) // Set parity only for memory ecc inst…
78981 …ED_0_MEM011_I_ECC_0_CORRECT_E5 (0x1<<1) // Record if a corr…
78982 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_0_CORRECT_E5_SHIFT 1
78987 …ED_0_MEM010_I_ECC_0_CORRECT_K2 (0x1<<1) // Record if a corr…
78988 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_0_CORRECT_K2_SHIFT 1
78993 …ED_0_MEM009_I_ECC_0_CORRECT_BB (0x1<<1) // Record if a corr…
78994 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_0_CORRECT_BB_SHIFT 1
78998 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
79000 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
79001 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
79002 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
79003 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79004 …esponding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir gr…
79005 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79006 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79007 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79008 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79009 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
79010 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
79011 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
79012 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
79013 … 0x110063cUL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
79015 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
79025 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
79026 …/ Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock gro…
79027 … DataWidth:0x2 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
79029 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
79034 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
79035 …D Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- …
79036 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
79037 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
79052 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
79053 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
79054 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
79055 … 0x1100a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
79056 … 0x1100a10UL //Access:R DataWidth:0x1 // In-process Table almost …
79060 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
79068 …UL //Access:W DataWidth:0x20 // Used to write the GRC message. Write only. To distinguish if …
79076 … DataWidth:0x20 // Debug read from PSEM Input stage buffer with 32-bits granularity. Read only.
79079 … DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Read only.
79081 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
79082 …DataWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to STORM Connection…
79083 … 0x1101500UL //Access:R DataWidth:0xa // Debug only. Read only access to LCI…
79085 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
79087 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
79113 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
79114 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
79123 … DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Read only.
79124 … DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Read only.
79126 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
79131 … DataWidth:0x20 // Debug read from YPLD Input stage buffer with 32-bits granularity. Read only.
79133 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
79135 … // Debug only. Initialises specific states and statuses. To initialise the state - write 1 int…
79137 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
79138 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
79139 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
79140 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
79177 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79178 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
79179 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79180 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
79181 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79182 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
79183 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79184 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
79185 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79186 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
79187 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79188 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
79189 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79190 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
79191 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79192 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
79193 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79194 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
79195 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79196 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
79197 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79198 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
79199 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
79203 …FL_ERR (0x1<<1) // Write to full ST…
79204 …CM_REG_INT_STS_0_IS_STORM_OVFL_ERR_SHIFT 1
79240 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
79242 … (0x1<<1) // This bit masks, when set, the Interrupt …
79243 …CM_REG_INT_MASK_0_IS_STORM_OVFL_ERR_SHIFT 1
79244 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
79246 … (0x1<<3) // This bit masks, when set, the Interrupt bit: T…
79248 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
79250 … (0x1<<3) // This bit masks, when set, the Interrupt bit: T…
79252 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
79254 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
79256 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
79258 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
79260 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
79262 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
79264 … (0x1<<9) // This bit masks, when set, the Interrupt bit: T…
79266 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
79268 … (0x1<<10) // This bit masks, when set, the Interrupt bit: T…
79270 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
79272 … (0x1<<11) // This bit masks, when set, the Interrupt bit: T…
79274 … (0x1<<12) // This bit masks, when set, the Interrupt bit: T…
79276 … (0x1<<13) // This bit masks, when set, the Interrupt bit: T…
79281 …_OVFL_ERR (0x1<<1) // Write to full ST…
79282 …CM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR_SHIFT 1
79320 …M_OVFL_ERR (0x1<<1) // Write to full ST…
79321 …CM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR_SHIFT 1
79359 …L_ERR (0x1<<1) // Write to full Do…
79360 …CM_REG_INT_STS_1_IS_DORQ_OVFL_ERR_SHIFT 1
79399 … (0x1<<21) // In-process Table overflo…
79426 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
79428 … (0x1<<1) // This bit masks, when set, the Interrupt …
79429 …CM_REG_INT_MASK_1_IS_DORQ_OVFL_ERR_SHIFT 1
79430 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
79432 … (0x1<<3) // This bit masks, when set, the Interrupt bit: T…
79434 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
79436 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
79438 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
79440 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
79442 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
79444 … (0x1<<9) // This bit masks, when set, the Interrupt bit: T…
79446 … (0x1<<10) // This bit masks, when set, the Interrupt bit: T…
79448 … (0x1<<11) // This bit masks, when set, the Interrupt bit: T…
79450 … (0x1<<12) // This bit masks, when set, the Interrupt bit: T…
79452 … (0x1<<13) // This bit masks, when set, the Interrupt bit: T…
79454 … (0x1<<14) // This bit masks, when set, the Interrupt bit: T…
79456 … (0x1<<15) // This bit masks, when set, the Interrupt bit: T…
79458 … (0x1<<16) // This bit masks, when set, the Interrupt bit: T…
79460 … (0x1<<17) // This bit masks, when set, the Interrupt bit: T…
79462 … (0x1<<18) // This bit masks, when set, the Interrupt bit: T…
79464 … (0x1<<19) // This bit masks, when set, the Interrupt bit: T…
79466 … (0x1<<20) // This bit masks, when set, the Interrupt bit: T…
79468 … (0x1<<21) // This bit masks, when set, the Interrupt bit: T…
79470 … (0x1<<22) // This bit masks, when set, the Interrupt bit: T…
79472 … (0x1<<23) // This bit masks, when set, the Interrupt bit: T…
79474 … (0x1<<24) // This bit masks, when set, the Interrupt bit: T…
79476 … (0x1<<25) // This bit masks, when set, the Interrupt bit: T…
79478 … (0x1<<26) // This bit masks, when set, the Interrupt bit: T…
79480 … (0x1<<27) // This bit masks, when set, the Interrupt bit: T…
79482 … (0x1<<28) // This bit masks, when set, the Interrupt bit: T…
79484 … (0x1<<29) // This bit masks, when set, the Interrupt bit: T…
79486 … (0x1<<30) // This bit masks, when set, the Interrupt bit: T…
79488 … (0x1<<31) // This bit masks, when set, the Interrupt bit: T…
79490 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
79492 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
79497 …OVFL_ERR (0x1<<1) // Write to full Do…
79498 …CM_REG_INT_STS_WR_1_IS_DORQ_OVFL_ERR_SHIFT 1
79537 … (0x1<<21) // In-process Table overflo…
79566 …_OVFL_ERR (0x1<<1) // Write to full Do…
79567 …CM_REG_INT_STS_CLR_1_IS_DORQ_OVFL_ERR_SHIFT 1
79606 … (0x1<<21) // In-process Table overflo…
79636 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
79645 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
79647 … (0x1<<1) // This bit masks, when set, the Parity bi…
79648 …CM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_SHIFT 1
79649 … (0x1<<2) // This bit masks, when set, the Parity bit: TC…
79651 … (0x1<<3) // This bit masks, when set, the Parity bit: TC…
79653 … (0x1<<4) // This bit masks, when set, the Parity bit: TC…
79655 … (0x1<<5) // This bit masks, when set, the Parity bit: TC…
79657 … (0x1<<6) // This bit masks, when set, the Parity bit: TC…
79659 … (0x1<<7) // This bit masks, when set, the Parity bit: TC…
79661 … (0x1<<8) // This bit masks, when set, the Parity bit: TC…
79663 … (0x1<<9) // This bit masks, when set, the Parity bit: TC…
79665 … (0x1<<25) // This bit masks, when set, the Parity bit: TC…
79667 … (0x1<<10) // This bit masks, when set, the Parity bit: TC…
79669 … (0x1<<23) // This bit masks, when set, the Parity bit: TC…
79671 … (0x1<<11) // This bit masks, when set, the Parity bit: TC…
79673 … (0x1<<24) // This bit masks, when set, the Parity bit: TC…
79675 … (0x1<<12) // This bit masks, when set, the Parity bit: TC…
79677 … (0x1<<26) // This bit masks, when set, the Parity bit: TC…
79679 … (0x1<<13) // This bit masks, when set, the Parity bit: TC…
79681 … (0x1<<12) // This bit masks, when set, the Parity bit: TC…
79683 … (0x1<<13) // This bit masks, when set, the Parity bit: TC…
79685 … (0x1<<14) // This bit masks, when set, the Parity bit: TC…
79687 … (0x1<<9) // This bit masks, when set, the Parity bit: TC…
79689 … (0x1<<15) // This bit masks, when set, the Parity bit: TC…
79691 … (0x1<<26) // This bit masks, when set, the Parity bit: TC…
79693 … (0x1<<15) // This bit masks, when set, the Parity bit: TC…
79695 … (0x1<<16) // This bit masks, when set, the Parity bit: TC…
79697 … (0x1<<27) // This bit masks, when set, the Parity bit: TC…
79699 … (0x1<<17) // This bit masks, when set, the Parity bit: TC…
79701 … (0x1<<15) // This bit masks, when set, the Parity bit: TC…
79703 … (0x1<<16) // This bit masks, when set, the Parity bit: TC…
79705 … (0x1<<18) // This bit masks, when set, the Parity bit: TC…
79707 … (0x1<<21) // This bit masks, when set, the Parity bit: TC…
79709 … (0x1<<19) // This bit masks, when set, the Parity bit: TC…
79711 … (0x1<<11) // This bit masks, when set, the Parity bit: TC…
79713 … (0x1<<12) // This bit masks, when set, the Parity bit: TC…
79715 … (0x1<<20) // This bit masks, when set, the Parity bit: TC…
79717 … (0x1<<14) // This bit masks, when set, the Parity bit: TC…
79719 … (0x1<<10) // This bit masks, when set, the Parity bit: TC…
79721 … (0x1<<21) // This bit masks, when set, the Parity bit: TC…
79723 … (0x1<<16) // This bit masks, when set, the Parity bit: TC…
79725 … (0x1<<17) // This bit masks, when set, the Parity bit: TC…
79727 … (0x1<<22) // This bit masks, when set, the Parity bit: TC…
79729 … (0x1<<17) // This bit masks, when set, the Parity bit: TC…
79731 … (0x1<<18) // This bit masks, when set, the Parity bit: TC…
79733 … (0x1<<23) // This bit masks, when set, the Parity bit: TC…
79735 … (0x1<<18) // This bit masks, when set, the Parity bit: TC…
79737 … (0x1<<19) // This bit masks, when set, the Parity bit: TC…
79739 … (0x1<<24) // This bit masks, when set, the Parity bit: TC…
79741 … (0x1<<10) // This bit masks, when set, the Parity bit: TC…
79743 … (0x1<<11) // This bit masks, when set, the Parity bit: TC…
79745 … (0x1<<25) // This bit masks, when set, the Parity bit: TC…
79747 … (0x1<<26) // This bit masks, when set, the Parity bit: TC…
79749 … (0x1<<27) // This bit masks, when set, the Parity bit: TC…
79751 … (0x1<<28) // This bit masks, when set, the Parity bit: TC…
79753 … (0x1<<29) // This bit masks, when set, the Parity bit: TC…
79755 … (0x1<<20) // This bit masks, when set, the Parity bit: TC…
79757 … (0x1<<30) // This bit masks, when set, the Parity bit: TC…
79759 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
79761 … (0x1<<3) // This bit masks, when set, the Parity bit: TC…
79763 … (0x1<<4) // This bit masks, when set, the Parity bit: TC…
79765 … (0x1<<5) // This bit masks, when set, the Parity bit: TC…
79767 … (0x1<<6) // This bit masks, when set, the Parity bit: TC…
79769 … (0x1<<7) // This bit masks, when set, the Parity bit: TC…
79771 … (0x1<<8) // This bit masks, when set, the Parity bit: TC…
79773 … (0x1<<13) // This bit masks, when set, the Parity bit: TC…
79775 … (0x1<<14) // This bit masks, when set, the Parity bit: TC…
79777 … (0x1<<19) // This bit masks, when set, the Parity bit: TC…
79779 … (0x1<<21) // This bit masks, when set, the Parity bit: TC…
79781 … (0x1<<20) // This bit masks, when set, the Parity bit: TC…
79783 … (0x1<<22) // This bit masks, when set, the Parity bit: TC…
79785 … (0x1<<22) // This bit masks, when set, the Parity bit: TC…
79787 … (0x1<<23) // This bit masks, when set, the Parity bit: TC…
79789 … (0x1<<24) // This bit masks, when set, the Parity bit: TC…
79791 … (0x1<<25) // This bit masks, when set, the Parity bit: TC…
79793 … (0x1<<27) // This bit masks, when set, the Parity bit: TC…
79795 … (0x1<<28) // This bit masks, when set, the Parity bit: TC…
79797 … (0x1<<28) // This bit masks, when set, the Parity bit: TC…
79799 … (0x1<<29) // This bit masks, when set, the Parity bit: TC…
79801 … (0x1<<29) // This bit masks, when set, the Parity bit: TC…
79803 … (0x1<<30) // This bit masks, when set, the Parity bit: TC…
79805 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
79807 … (0x1<<3) // This bit masks, when set, the Parity bit: TC…
79809 … (0x1<<4) // This bit masks, when set, the Parity bit: TC…
79811 … (0x1<<7) // This bit masks, when set, the Parity bit: TC…
79813 … (0x1<<8) // This bit masks, when set, the Parity bit: TC…
79815 … (0x1<<30) // This bit masks, when set, the Parity bit: TC…
79818 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
79820 … (0x1<<1) // This bit masks, when set, the Parity bi…
79821 …CM_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_E5_SHIFT 1
79822 … (0x1<<2) // This bit masks, when set, the Parity bit: TC…
79824 … (0x1<<3) // This bit masks, when set, the Parity bit: TC…
79826 … (0x1<<4) // This bit masks, when set, the Parity bit: TC…
79828 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
79830 … (0x1<<5) // This bit masks, when set, the Parity bit: TC…
79832 … (0x1<<6) // This bit masks, when set, the Parity bit: TC…
79834 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
79836 … (0x1<<1) // This bit masks, when set, the Parity bi…
79837 …CM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2_SHIFT 1
79838 … (0x1<<7) // This bit masks, when set, the Parity bit: TC…
79840 … (0x1<<1) // This bit masks, when set, the Parity bi…
79841 …CM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_SHIFT 1
79842 … (0x1<<2) // This bit masks, when set, the Parity bit: TC…
79844 … (0x1<<8) // This bit masks, when set, the Parity bit: TC…
79849 …03_I_ECC_0_EN (0x1<<1) // Enable ECC for m…
79850 …CM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_0_EN_SHIFT 1
79892 …E5 (0x1<<0) // Set parity only for memory ecc inst…
79894 …ECC_0_PRTY (0x1<<1) // Set parity only for memory…
79895 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_0_PRTY_SHIFT 1
79896 …Y (0x1<<2) // Set parity only for memory ecc inst…
79898 …E5 (0x1<<3) // Set parity only for memory ecc inst…
79900 …Y_E5 (0x1<<4) // Set parity only for memory ecc inst…
79902 …Y_E5 (0x1<<5) // Set parity only for memory ecc inst…
79904 …Y_E5 (0x1<<6) // Set parity only for memory ecc inst…
79906 …Y_E5 (0x1<<7) // Set parity only for memory ecc inst…
79908 …Y_E5 (0x1<<8) // Set parity only for memory ecc inst…
79910 …Y_E5 (0x1<<9) // Set parity only for memory ecc inst…
79912 …K2 (0x1<<0) // Set parity only for memory ecc inst…
79914 …Y_K2 (0x1<<3) // Set parity only for memory ecc inst…
79916 …Y_K2 (0x1<<4) // Set parity only for memory ecc inst…
79918 …Y_BB_K2 (0x1<<5) // Set parity only for memory ecc inst…
79920 …Y_BB_K2 (0x1<<6) // Set parity only for memory ecc inst…
79922 …Y_K2 (0x1<<7) // Set parity only for memory ecc inst…
79924 …Y_K2 (0x1<<8) // Set parity only for memory ecc inst…
79926 …BB (0x1<<0) // Set parity only for memory ecc inst…
79928 …Y_BB (0x1<<3) // Set parity only for memory ecc inst…
79930 …Y_BB (0x1<<4) // Set parity only for memory ecc inst…
79932 …Y_BB (0x1<<7) // Set parity only for memory ecc inst…
79934 …Y_BB (0x1<<8) // Set parity only for memory ecc inst…
79939 …ED_0_MEM003_I_ECC_0_CORRECT (0x1<<1) // Record if a corr…
79940 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_0_CORRECT_SHIFT 1
79982 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
79991 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
79992 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
79993 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
79994 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
79995 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
79996 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
79997 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
79998 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
80024 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80025 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
80026 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80027 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
80028 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80029 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
80030 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80031 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
80032 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80033 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
80034 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80035 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
80036 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80037 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
80038 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80039 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
80040 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80041 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
80042 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
80043 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
80044 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
80045 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
80046 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
80047 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
80048 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
80049 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
80050 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
80051 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
80052 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
80053 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80054 …esponding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir gr…
80055 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80056 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80057 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80058 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80059 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
80060 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80061 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80062 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80063 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80064 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80065 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80066 … 0x1180664UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
80068 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
80069 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
80082 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
80083 …/ Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock gro…
80084 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
80086 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
80091 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
80092 …D Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- …
80093 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
80094 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
80111 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80112 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80113 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80114 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80115 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80116 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80117 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80118 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80119 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80120 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80121 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80122 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80123 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80124 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80125 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80126 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80127 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80128 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80129 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80130 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80131 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80132 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80133 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80134 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80166 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80167 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80168 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80169 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80170 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80171 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80172 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80173 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80174 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
80175 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
80177 … 0x1180908UL //Access:RW DataWidth:0x9 // Physical queue connection number (queue number 1).
80179 … 0x1180910UL //Access:RW DataWidth:0x7 // Physical queue task number (queue number 1).
80180 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80181 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80182 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80183 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80184 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80185 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80186 … 0x118099cUL //Access:RW DataWidth:0x3 // EventID bit width per task type…
80187 … 0x11809a0UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
80188 … 0x11809a4UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
80189 … 0x11809a8UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
80190 … 0x11809acUL //Access:RW DataWidth:0x3 // EventID bit width per task type…
80191 … 0x11809b0UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
80192 … 0x11809b4UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
80193 … 0x11809b8UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
80194 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
80195 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
80196 … 0x1180a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
80197 … 0x1180a10UL //Access:R DataWidth:0x1 // In-process Table almost …
80207 … 0x1180a38UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80208 … 0x1180a3cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80209 … 0x1180a40UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80210 … 0x1180a44UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80211 … 0x1180a48UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80212 … 0x1180a4cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80213 … 0x1180a50UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80214 … 0x1180a54UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80215 … 0x1180a58UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80216 … 0x1180a5cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80217 … 0x1180a60UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80218 … 0x1180a64UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80219 … 0x1180a68UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80220 … 0x1180a6cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80221 … 0x1180a70UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80222 … 0x1180a74UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80223 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
80224 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
80225 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
80226 …RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the …
80242 …UL //Access:W DataWidth:0x20 // Used to write the GRC message. Write only. To distinguish if …
80264 … DataWidth:0x20 // Debug read from TSEM Input stage buffer with 32-bits granularity. Read only.
80267 … DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Read only.
80269 … DataWidth:0x20 // Debug read from PRS Input stage buffer with 32-bits granularity. Read only.
80271 … DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Read only.
80273 … DataWidth:0x20 // Debug read from DORQ Input stage buffer with 32-bits granularity. Read only.
80275 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
80276 …aWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to Aggregation Connect…
80277 …DataWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to Aggregation Task…
80278 …DataWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to STORM Connection…
80279 … DataWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to STORM Task co…
80285 … 0x1181600UL //Access:R DataWidth:0xa // Debug only. Read only access to LCI…
80288 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
80291 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
80341 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80342 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80343 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80344 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80345 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80346 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80347 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80348 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80349 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80350 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80351 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80352 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80353 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80354 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80355 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80356 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80357 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80358 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80359 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80360 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80361 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80362 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80363 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80364 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
80485 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
80486 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
80495 … DataWidth:0x20 // Debug read from TSDM Input stage buffer with 32-bits granularity. Read only.
80496 … DataWidth:0x20 // Debug read from TSDM Input stage buffer with 32-bits granularity. Read only.
80498 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
80503 … DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Read only.
80505 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
80510 … DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Read only.
80512 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
80513 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
80520 … DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.
80521 … DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.
80523 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
80528 … DataWidth:0x20 // Debug read from PTLD Input stage buffer with 32-bits granularity. Read only.
80530 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80531 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80532 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80533 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80534 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80535 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80536 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80537 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80538 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80539 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80540 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80541 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80542 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80543 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80544 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80545 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80546 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
80549 … // Debug only. Initialises specific states and statuses. To initialise the state - write 1 int…
80551 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
80552 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
80553 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
80554 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
80591 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80592 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
80593 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80594 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
80595 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80596 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
80600 …FL_ERR (0x1<<1) // Write to full ST…
80601 …CM_REG_INT_STS_0_IS_STORM_OVFL_ERR_SHIFT 1
80653 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
80655 … (0x1<<1) // This bit masks, when set, the Interrupt …
80656 …CM_REG_INT_MASK_0_IS_STORM_OVFL_ERR_SHIFT 1
80657 … (0x1<<2) // This bit masks, when set, the Interrupt bit: M…
80659 … (0x1<<3) // This bit masks, when set, the Interrupt bit: M…
80661 … (0x1<<4) // This bit masks, when set, the Interrupt bit: M…
80663 … (0x1<<5) // This bit masks, when set, the Interrupt bit: M…
80665 … (0x1<<6) // This bit masks, when set, the Interrupt bit: M…
80667 … (0x1<<7) // This bit masks, when set, the Interrupt bit: M…
80669 … (0x1<<8) // This bit masks, when set, the Interrupt bit: M…
80671 … (0x1<<9) // This bit masks, when set, the Interrupt bit: M…
80673 … (0x1<<10) // This bit masks, when set, the Interrupt bit: M…
80675 … (0x1<<7) // This bit masks, when set, the Interrupt bit: M…
80677 … (0x1<<11) // This bit masks, when set, the Interrupt bit: M…
80679 … (0x1<<8) // This bit masks, when set, the Interrupt bit: M…
80681 … (0x1<<12) // This bit masks, when set, the Interrupt bit: M…
80683 … (0x1<<9) // This bit masks, when set, the Interrupt bit: M…
80685 … (0x1<<13) // This bit masks, when set, the Interrupt bit: M…
80687 … (0x1<<10) // This bit masks, when set, the Interrupt bit: M…
80689 … (0x1<<14) // This bit masks, when set, the Interrupt bit: M…
80691 … (0x1<<11) // This bit masks, when set, the Interrupt bit: M…
80693 … (0x1<<15) // This bit masks, when set, the Interrupt bit: M…
80695 … (0x1<<12) // This bit masks, when set, the Interrupt bit: M…
80697 … (0x1<<16) // This bit masks, when set, the Interrupt bit: M…
80699 … (0x1<<13) // This bit masks, when set, the Interrupt bit: M…
80701 … (0x1<<17) // This bit masks, when set, the Interrupt bit: M…
80703 … (0x1<<18) // This bit masks, when set, the Interrupt bit: M…
80705 … (0x1<<19) // This bit masks, when set, the Interrupt bit: M…
80710 …_OVFL_ERR (0x1<<1) // Write to full ST…
80711 …CM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR_SHIFT 1
80765 …M_OVFL_ERR (0x1<<1) // Write to full ST…
80766 …CM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR_SHIFT 1
80820 …_ERR (0x1<<1) // Write to full Pb…
80821 …CM_REG_INT_STS_1_IS_PBF_OVFL_ERR_SHIFT 1
80848 … (0x1<<15) // In-process Table overflo…
80871 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
80873 … (0x1<<1) // This bit masks, when set, the Interrupt …
80874 …CM_REG_INT_MASK_1_IS_PBF_OVFL_ERR_SHIFT 1
80875 … (0x1<<2) // This bit masks, when set, the Interrupt bit: M…
80877 … (0x1<<3) // This bit masks, when set, the Interrupt bit: M…
80879 … (0x1<<4) // This bit masks, when set, the Interrupt bit: M…
80881 … (0x1<<5) // This bit masks, when set, the Interrupt bit: M…
80883 … (0x1<<6) // This bit masks, when set, the Interrupt bit: M…
80885 … (0x1<<7) // This bit masks, when set, the Interrupt bit: M…
80887 … (0x1<<8) // This bit masks, when set, the Interrupt bit: M…
80889 … (0x1<<9) // This bit masks, when set, the Interrupt bit: M…
80891 … (0x1<<10) // This bit masks, when set, the Interrupt bit: M…
80893 … (0x1<<11) // This bit masks, when set, the Interrupt bit: M…
80895 … (0x1<<12) // This bit masks, when set, the Interrupt bit: M…
80897 … (0x1<<13) // This bit masks, when set, the Interrupt bit: M…
80899 … (0x1<<14) // This bit masks, when set, the Interrupt bit: M…
80901 … (0x1<<15) // This bit masks, when set, the Interrupt bit: M…
80903 … (0x1<<16) // This bit masks, when set, the Interrupt bit: M…
80905 … (0x1<<17) // This bit masks, when set, the Interrupt bit: M…
80907 … (0x1<<18) // This bit masks, when set, the Interrupt bit: M…
80909 … (0x1<<19) // This bit masks, when set, the Interrupt bit: M…
80911 … (0x1<<20) // This bit masks, when set, the Interrupt bit: M…
80913 … (0x1<<21) // This bit masks, when set, the Interrupt bit: M…
80915 … (0x1<<22) // This bit masks, when set, the Interrupt bit: M…
80917 … (0x1<<23) // This bit masks, when set, the Interrupt bit: M…
80919 … (0x1<<24) // This bit masks, when set, the Interrupt bit: M…
80921 … (0x1<<25) // This bit masks, when set, the Interrupt bit: M…
80926 …VFL_ERR (0x1<<1) // Write to full Pb…
80927 …CM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR_SHIFT 1
80954 … (0x1<<15) // In-process Table overflo…
80979 …OVFL_ERR (0x1<<1) // Write to full Pb…
80980 …CM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR_SHIFT 1
81007 … (0x1<<15) // In-process Table overflo…
81033 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
81042 … (0x1<<0) // This bit masks, when set, the Parity bit: MC…
81044 … (0x1<<1) // This bit masks, when set, the Parity bi…
81045 …CM_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_SHIFT 1
81046 … (0x1<<2) // This bit masks, when set, the Parity bit: MC…
81048 … (0x1<<3) // This bit masks, when set, the Parity bit: MC…
81050 … (0x1<<4) // This bit masks, when set, the Parity bit: MC…
81052 … (0x1<<5) // This bit masks, when set, the Parity bit: MC…
81054 … (0x1<<6) // This bit masks, when set, the Parity bit: MC…
81056 … (0x1<<7) // This bit masks, when set, the Parity bit: MC…
81058 … (0x1<<8) // This bit masks, when set, the Parity bit: MC…
81060 … (0x1<<14) // This bit masks, when set, the Parity bit: MC…
81062 … (0x1<<9) // This bit masks, when set, the Parity bit: MC…
81064 … (0x1<<10) // This bit masks, when set, the Parity bit: MC…
81066 … (0x1<<13) // This bit masks, when set, the Parity bit: MC…
81068 … (0x1<<11) // This bit masks, when set, the Parity bit: MC…
81070 … (0x1<<12) // This bit masks, when set, the Parity bit: MC…
81072 … (0x1<<9) // This bit masks, when set, the Parity bit: MC…
81074 … (0x1<<13) // This bit masks, when set, the Parity bit: MC…
81076 … (0x1<<11) // This bit masks, when set, the Parity bit: MC…
81078 … (0x1<<14) // This bit masks, when set, the Parity bit: MC…
81080 … (0x1<<15) // This bit masks, when set, the Parity bit: MC…
81082 … (0x1<<26) // This bit masks, when set, the Parity bit: MC…
81084 … (0x1<<16) // This bit masks, when set, the Parity bit: MC…
81086 … (0x1<<27) // This bit masks, when set, the Parity bit: MC…
81088 … (0x1<<17) // This bit masks, when set, the Parity bit: MC…
81090 … (0x1<<18) // This bit masks, when set, the Parity bit: MC…
81092 … (0x1<<24) // This bit masks, when set, the Parity bit: MC…
81094 … (0x1<<19) // This bit masks, when set, the Parity bit: MC…
81096 … (0x1<<15) // This bit masks, when set, the Parity bit: MC…
81098 … (0x1<<20) // This bit masks, when set, the Parity bit: MC…
81100 … (0x1<<17) // This bit masks, when set, the Parity bit: MC…
81102 … (0x1<<21) // This bit masks, when set, the Parity bit: MC…
81104 … (0x1<<18) // This bit masks, when set, the Parity bit: MC…
81106 … (0x1<<22) // This bit masks, when set, the Parity bit: MC…
81108 … (0x1<<19) // This bit masks, when set, the Parity bit: MC…
81110 … (0x1<<23) // This bit masks, when set, the Parity bit: MC…
81112 … (0x1<<12) // This bit masks, when set, the Parity bit: MC…
81114 … (0x1<<24) // This bit masks, when set, the Parity bit: MC…
81116 … (0x1<<25) // This bit masks, when set, the Parity bit: MC…
81118 … (0x1<<26) // This bit masks, when set, the Parity bit: MC…
81120 … (0x1<<27) // This bit masks, when set, the Parity bit: MC…
81122 … (0x1<<23) // This bit masks, when set, the Parity bit: MC…
81124 … (0x1<<28) // This bit masks, when set, the Parity bit: MC…
81126 … (0x1<<21) // This bit masks, when set, the Parity bit: MC…
81128 … (0x1<<29) // This bit masks, when set, the Parity bit: MC…
81130 … (0x1<<30) // This bit masks, when set, the Parity bit: MC…
81132 … (0x1<<0) // This bit masks, when set, the Parity bit: MC…
81134 … (0x1<<2) // This bit masks, when set, the Parity bit: MC…
81136 … (0x1<<3) // This bit masks, when set, the Parity bit: MC…
81138 … (0x1<<6) // This bit masks, when set, the Parity bit: MC…
81140 … (0x1<<7) // This bit masks, when set, the Parity bit: MC…
81142 … (0x1<<8) // This bit masks, when set, the Parity bit: MC…
81144 … (0x1<<16) // This bit masks, when set, the Parity bit: MC…
81146 … (0x1<<20) // This bit masks, when set, the Parity bit: MC…
81148 … (0x1<<22) // This bit masks, when set, the Parity bit: MC…
81150 … (0x1<<25) // This bit masks, when set, the Parity bit: MC…
81152 … (0x1<<28) // This bit masks, when set, the Parity bit: MC…
81154 … (0x1<<29) // This bit masks, when set, the Parity bit: MC…
81156 … (0x1<<30) // This bit masks, when set, the Parity bit: MC…
81159 … (0x1<<0) // This bit masks, when set, the Parity bit: MC…
81161 … (0x1<<1) // This bit masks, when set, the Parity bi…
81162 …CM_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_E5_SHIFT 1
81163 … (0x1<<2) // This bit masks, when set, the Parity bit: MC…
81165 … (0x1<<3) // This bit masks, when set, the Parity bit: MC…
81167 … (0x1<<0) // This bit masks, when set, the Parity bit: MC…
81169 … (0x1<<4) // This bit masks, when set, the Parity bit: MC…
81171 … (0x1<<1) // This bit masks, when set, the Parity bi…
81172 …CM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_K2_SHIFT 1
81173 … (0x1<<5) // This bit masks, when set, the Parity bit: MC…
81175 … (0x1<<6) // This bit masks, when set, the Parity bit: MC…
81177 … (0x1<<2) // This bit masks, when set, the Parity bit: MC…
81179 … (0x1<<7) // This bit masks, when set, the Parity bit: MC…
81181 … (0x1<<3) // This bit masks, when set, the Parity bit: MC…
81183 … (0x1<<8) // This bit masks, when set, the Parity bit: MC…
81185 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
81186 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
81187 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
81188 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
81192 …03_I_ECC_EN (0x1<<1) // Enable ECC for m…
81193 …CM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_SHIFT 1
81221 …E5 (0x1<<0) // Set parity only for memory ecc inst…
81223 …ECC_PRTY (0x1<<1) // Set parity only for memory…
81224 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_SHIFT 1
81225 …Y_E5 (0x1<<2) // Set parity only for memory ecc inst…
81227 …Y_E5 (0x1<<3) // Set parity only for memory ecc inst…
81229 …Y (0x1<<4) // Set parity only for memory ecc inst…
81231 …Y (0x1<<5) // Set parity only for memory ecc inst…
81233 …E5 (0x1<<6) // Set parity only for memory ecc inst…
81235 …Y_E5 (0x1<<7) // Set parity only for memory ecc inst…
81237 …Y_E5 (0x1<<8) // Set parity only for memory ecc inst…
81239 …BB_K2 (0x1<<0) // Set parity only for memory ecc inst…
81241 …Y_BB_K2 (0x1<<2) // Set parity only for memory ecc inst…
81243 …Y_BB_K2 (0x1<<3) // Set parity only for memory ecc inst…
81245 …Y_BB_K2 (0x1<<6) // Set parity only for memory ecc inst…
81247 …Y_BB_K2 (0x1<<7) // Set parity only for memory ecc inst…
81249 …BB_K2 (0x1<<8) // Set parity only for memory ecc inst…
81254 …ED_0_MEM003_I_ECC_CORRECT (0x1<<1) // Record if a corr…
81255 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_SHIFT 1
81283 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
81292 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
81293 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
81294 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
81295 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
81296 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
81297 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
81298 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
81299 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
81333 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81334 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
81335 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81336 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
81337 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81338 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
81339 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81340 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
81341 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81342 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
81343 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
81344 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
81345 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
81346 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
81347 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
81348 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
81349 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
81350 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
81351 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
81352 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81353 …esponding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir gr…
81354 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81355 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81356 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81357 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81358 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
81359 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81360 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81361 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81362 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81363 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81364 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81365 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81366 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81367 … 0x120066cUL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
81369 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
81370 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
81383 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
81384 …/ Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock gro…
81385 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
81387 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
81392 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
81393 …D Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- …
81394 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
81395 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
81412 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81413 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81414 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81415 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81416 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81417 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81418 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81419 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81420 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81421 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81422 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81423 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81424 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81425 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81426 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81427 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81428 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81429 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81430 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81431 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81432 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81433 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81434 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81435 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81467 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
81468 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
81469 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
81470 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
81471 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
81472 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
81473 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
81474 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
81475 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
81476 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
81478 … 0x1200908UL //Access:RW DataWidth:0x9 // Physical queue connection number (queue number 1).
81480 … 0x1200910UL //Access:RW DataWidth:0x7 // Physical queue task number (queue number 1).
81481 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81482 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81483 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81484 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81485 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81486 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81487 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81488 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81489 … 0x1200960UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
81490 … 0x1200964UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
81491 … 0x1200968UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
81492 … 0x120096cUL //Access:RW DataWidth:0x3 // EventID bit width per task type…
81493 … 0x1200970UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
81494 … 0x1200974UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
81495 … 0x1200978UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
81496 … 0x120097cUL //Access:RW DataWidth:0x3 // EventID bit width per task type…
81497 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
81498 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
81499 … 0x1200a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
81500 … 0x1200a10UL //Access:R DataWidth:0x1 // In-process Table almost …
81508 … 0x1200a30UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81509 … 0x1200a34UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81510 … 0x1200a38UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81511 … 0x1200a3cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81512 … 0x1200a40UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81513 … 0x1200a44UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81514 … 0x1200a48UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81515 … 0x1200a4cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81516 … 0x1200a50UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81517 … 0x1200a54UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81518 … 0x1200a58UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81519 … 0x1200a5cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81520 … 0x1200a60UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81521 … 0x1200a64UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81522 … 0x1200a68UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81523 … 0x1200a6cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81524 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
81525 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
81526 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
81527 … // TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the in…
81528 …th:0x3 // TCFC UC Dec Update output initial credit. Max credit available - 7.Write writes the i…
81545 …UL //Access:W DataWidth:0x20 // Used to write the GRC message. Write only. To distinguish if …
81568 … DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Read only.
81571 … DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Read only.
81573 … DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Read only.
81575 … DataWidth:0x20 // Debug read from USDM Input stage buffer with 32-bits granularity. Read only.
81577 … DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Read only.
81579 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
81580 …aWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to Aggregation Connect…
81581 …DataWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to Aggregation Task…
81582 …DataWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to STORM Connection…
81583 … DataWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to STORM Task co…
81589 … 0x1201a00UL //Access:R DataWidth:0xa // Debug only. Read only access to LCI…
81592 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
81595 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
81621 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81622 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81623 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81624 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81625 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81626 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81627 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81628 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81629 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81630 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81631 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81632 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81633 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81634 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81635 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81636 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81637 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81638 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81639 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81640 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81641 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81642 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81643 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81644 …1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Othe…
81765 … DataWidth:0x20 // Debug read from TMLD Input stage buffer with 32-bits granularity. Read only.
81766 … DataWidth:0x20 // Debug read from TMLD Input stage buffer with 32-bits granularity. Read only.
81769 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
81774 … DataWidth:0x20 // Debug read from TSDM Input stage buffer with 32-bits granularity. Read only.
81776 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
81781 … DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Read only.
81783 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
81784 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
81793 … DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Read only.
81794 … DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Read only.
81796 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
81797 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
81804 … DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.
81805 … DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.
81808 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81809 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81810 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81811 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81812 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81813 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81814 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81815 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81816 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
81817 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
81820 … // Debug only. Initialises specific states and statuses. To initialise the state - write 1 int…
81826 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
81827 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
81828 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
81829 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
81866 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81867 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
81868 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81869 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
81870 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81871 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
81872 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81873 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
81874 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81875 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
81876 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81877 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
81878 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81879 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
81880 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
81881 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
81885 …FL_ERR (0x1<<1) // Write to full ST…
81886 …CM_REG_INT_STS_0_IS_STORM_OVFL_ERR_SHIFT 1
81924 … (0x1<<0) // This bit masks, when set, the Interrupt bit: U…
81926 … (0x1<<1) // This bit masks, when set, the Interrupt …
81927 …CM_REG_INT_MASK_0_IS_STORM_OVFL_ERR_SHIFT 1
81928 … (0x1<<2) // This bit masks, when set, the Interrupt bit: U…
81930 … (0x1<<3) // This bit masks, when set, the Interrupt bit: U…
81932 … (0x1<<4) // This bit masks, when set, the Interrupt bit: U…
81934 … (0x1<<5) // This bit masks, when set, the Interrupt bit: U…
81936 … (0x1<<6) // This bit masks, when set, the Interrupt bit: U…
81938 … (0x1<<7) // This bit masks, when set, the Interrupt bit: U…
81940 … (0x1<<8) // This bit masks, when set, the Interrupt bit: U…
81942 … (0x1<<9) // This bit masks, when set, the Interrupt bit: U…
81944 … (0x1<<10) // This bit masks, when set, the Interrupt bit: U…
81946 … (0x1<<11) // This bit masks, when set, the Interrupt bit: U…
81948 … (0x1<<12) // This bit masks, when set, the Interrupt bit: U…
81950 … (0x1<<13) // This bit masks, when set, the Interrupt bit: U…
81952 … (0x1<<14) // This bit masks, when set, the Interrupt bit: U…
81954 … (0x1<<15) // This bit masks, when set, the Interrupt bit: U…
81956 … (0x1<<16) // This bit masks, when set, the Interrupt bit: U…
81958 … (0x1<<17) // This bit masks, when set, the Interrupt bit: U…
81960 … (0x1<<15) // This bit masks, when set, the Interrupt bit: U…
81962 … (0x1<<16) // This bit masks, when set, the Interrupt bit: U…
81967 …_OVFL_ERR (0x1<<1) // Write to full ST…
81968 …CM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR_SHIFT 1
82008 …M_OVFL_ERR (0x1<<1) // Write to full ST…
82009 …CM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR_SHIFT 1
82051 …L_ERR_E5 (0x1<<1) // Write to full Do…
82052 …CM_REG_INT_STS_1_IS_DORQ_OVFL_ERR_E5_SHIFT 1
82053 …ER_ERR_BB_K2 (0x1<<1) // Read from empty …
82054 …CM_REG_INT_STS_1_IS_DORQ_UNDER_ERR_BB_K2_SHIFT 1
82121 …K2 (0x1<<18) // In-process Table overflo…
82123 … (0x1<<19) // In-process Table overflo…
82166 … (0x1<<0) // This bit masks, when set, the Interrupt bit: U…
82168 … (0x1<<0) // This bit masks, when set, the Interrupt bit: U…
82170 … (0x1<<1) // This bit masks, when set, the Interrupt …
82171 …CM_REG_INT_MASK_1_IS_DORQ_OVFL_ERR_E5_SHIFT 1
82172 … (0x1<<1) // This bit masks, when set, the Interrupt …
82173 …CM_REG_INT_MASK_1_IS_DORQ_UNDER_ERR_BB_K2_SHIFT 1
82174 … (0x1<<2) // This bit masks, when set, the Interrupt bit: U…
82176 … (0x1<<2) // This bit masks, when set, the Interrupt bit: U…
82178 … (0x1<<3) // This bit masks, when set, the Interrupt bit: U…
82180 … (0x1<<3) // This bit masks, when set, the Interrupt bit: U…
82182 … (0x1<<4) // This bit masks, when set, the Interrupt bit: U…
82184 … (0x1<<4) // This bit masks, when set, the Interrupt bit: U…
82186 … (0x1<<5) // This bit masks, when set, the Interrupt bit: U…
82188 … (0x1<<5) // This bit masks, when set, the Interrupt bit: U…
82190 … (0x1<<6) // This bit masks, when set, the Interrupt bit: U…
82192 … (0x1<<6) // This bit masks, when set, the Interrupt bit: U…
82194 … (0x1<<7) // This bit masks, when set, the Interrupt bit: U…
82196 … (0x1<<7) // This bit masks, when set, the Interrupt bit: U…
82198 … (0x1<<8) // This bit masks, when set, the Interrupt bit: U…
82200 … (0x1<<8) // This bit masks, when set, the Interrupt bit: U…
82202 … (0x1<<9) // This bit masks, when set, the Interrupt bit: U…
82204 … (0x1<<9) // This bit masks, when set, the Interrupt bit: U…
82206 … (0x1<<10) // This bit masks, when set, the Interrupt bit: U…
82208 … (0x1<<10) // This bit masks, when set, the Interrupt bit: U…
82210 … (0x1<<11) // This bit masks, when set, the Interrupt bit: U…
82212 … (0x1<<11) // This bit masks, when set, the Interrupt bit: U…
82214 … (0x1<<12) // This bit masks, when set, the Interrupt bit: U…
82216 … (0x1<<12) // This bit masks, when set, the Interrupt bit: U…
82218 … (0x1<<13) // This bit masks, when set, the Interrupt bit: U…
82220 … (0x1<<13) // This bit masks, when set, the Interrupt bit: U…
82222 … (0x1<<14) // This bit masks, when set, the Interrupt bit: U…
82224 … (0x1<<14) // This bit masks, when set, the Interrupt bit: U…
82226 … (0x1<<15) // This bit masks, when set, the Interrupt bit: U…
82228 … (0x1<<15) // This bit masks, when set, the Interrupt bit: U…
82230 … (0x1<<16) // This bit masks, when set, the Interrupt bit: U…
82232 … (0x1<<16) // This bit masks, when set, the Interrupt bit: U…
82234 … (0x1<<17) // This bit masks, when set, the Interrupt bit: U…
82236 … (0x1<<17) // This bit masks, when set, the Interrupt bit: U…
82238 … (0x1<<18) // This bit masks, when set, the Interrupt bit: U…
82240 … (0x1<<18) // This bit masks, when set, the Interrupt bit: U…
82242 … (0x1<<19) // This bit masks, when set, the Interrupt bit: U…
82244 … (0x1<<19) // This bit masks, when set, the Interrupt bit: U…
82246 … (0x1<<20) // This bit masks, when set, the Interrupt bit: U…
82248 … (0x1<<20) // This bit masks, when set, the Interrupt bit: U…
82250 … (0x1<<21) // This bit masks, when set, the Interrupt bit: U…
82252 … (0x1<<21) // This bit masks, when set, the Interrupt bit: U…
82254 … (0x1<<22) // This bit masks, when set, the Interrupt bit: U…
82256 … (0x1<<22) // This bit masks, when set, the Interrupt bit: U…
82258 … (0x1<<23) // This bit masks, when set, the Interrupt bit: U…
82260 … (0x1<<23) // This bit masks, when set, the Interrupt bit: U…
82262 … (0x1<<24) // This bit masks, when set, the Interrupt bit: U…
82264 … (0x1<<24) // This bit masks, when set, the Interrupt bit: U…
82266 … (0x1<<25) // This bit masks, when set, the Interrupt bit: U…
82268 … (0x1<<25) // This bit masks, when set, the Interrupt bit: U…
82270 … (0x1<<26) // This bit masks, when set, the Interrupt bit: U…
82272 … (0x1<<26) // This bit masks, when set, the Interrupt bit: U…
82274 … (0x1<<27) // This bit masks, when set, the Interrupt bit: U…
82276 … (0x1<<27) // This bit masks, when set, the Interrupt bit: U…
82278 … (0x1<<28) // This bit masks, when set, the Interrupt bit: U…
82280 … (0x1<<28) // This bit masks, when set, the Interrupt bit: U…
82282 … (0x1<<29) // This bit masks, when set, the Interrupt bit: U…
82289 …OVFL_ERR_E5 (0x1<<1) // Write to full Do…
82290 …CM_REG_INT_STS_WR_1_IS_DORQ_OVFL_ERR_E5_SHIFT 1
82291 …UNDER_ERR_BB_K2 (0x1<<1) // Read from empty …
82292 …CM_REG_INT_STS_WR_1_IS_DORQ_UNDER_ERR_BB_K2_SHIFT 1
82359 …BB_K2 (0x1<<18) // In-process Table overflo…
82361 …E5 (0x1<<19) // In-process Table overflo…
82408 …_OVFL_ERR_E5 (0x1<<1) // Write to full Do…
82409 …CM_REG_INT_STS_CLR_1_IS_DORQ_OVFL_ERR_E5_SHIFT 1
82410 …_UNDER_ERR_BB_K2 (0x1<<1) // Read from empty …
82411 …CM_REG_INT_STS_CLR_1_IS_DORQ_UNDER_ERR_BB_K2_SHIFT 1
82478 …_BB_K2 (0x1<<18) // In-process Table overflo…
82480 …_E5 (0x1<<19) // In-process Table overflo…
82526 … (0x1<<0) // This bit masks, when set, the Interrupt bit: U…
82535 … (0x1<<0) // This bit masks, when set, the Parity bit: UC…
82537 … (0x1<<1) // This bit masks, when set, the Parity bi…
82538 …CM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_SHIFT 1
82539 … (0x1<<2) // This bit masks, when set, the Parity bit: UC…
82541 … (0x1<<3) // This bit masks, when set, the Parity bit: UC…
82543 … (0x1<<4) // This bit masks, when set, the Parity bit: UC…
82545 … (0x1<<5) // This bit masks, when set, the Parity bit: UC…
82547 … (0x1<<6) // This bit masks, when set, the Parity bit: UC…
82549 … (0x1<<7) // This bit masks, when set, the Parity bit: UC…
82551 … (0x1<<9) // This bit masks, when set, the Parity bit: UC…
82553 … (0x1<<8) // This bit masks, when set, the Parity bit: UC…
82555 … (0x1<<10) // This bit masks, when set, the Parity bit: UC…
82557 … (0x1<<9) // This bit masks, when set, the Parity bit: UC…
82559 … (0x1<<13) // This bit masks, when set, the Parity bit: UC…
82561 … (0x1<<10) // This bit masks, when set, the Parity bit: UC…
82563 … (0x1<<17) // This bit masks, when set, the Parity bit: UC…
82565 … (0x1<<11) // This bit masks, when set, the Parity bit: UC…
82567 … (0x1<<12) // This bit masks, when set, the Parity bit: UC…
82569 … (0x1<<15) // This bit masks, when set, the Parity bit: UC…
82571 … (0x1<<13) // This bit masks, when set, the Parity bit: UC…
82573 … (0x1<<16) // This bit masks, when set, the Parity bit: UC…
82575 … (0x1<<14) // This bit masks, when set, the Parity bit: UC…
82577 … (0x1<<14) // This bit masks, when set, the Parity bit: UC…
82579 … (0x1<<15) // This bit masks, when set, the Parity bit: UC…
82581 … (0x1<<29) // This bit masks, when set, the Parity bit: UC…
82583 … (0x1<<16) // This bit masks, when set, the Parity bit: UC…
82585 … (0x1<<18) // This bit masks, when set, the Parity bit: UC…
82587 … (0x1<<17) // This bit masks, when set, the Parity bit: UC…
82589 … (0x1<<19) // This bit masks, when set, the Parity bit: UC…
82591 … (0x1<<18) // This bit masks, when set, the Parity bit: UC…
82593 … (0x1<<20) // This bit masks, when set, the Parity bit: UC…
82595 … (0x1<<19) // This bit masks, when set, the Parity bit: UC…
82597 … (0x1<<21) // This bit masks, when set, the Parity bit: UC…
82599 … (0x1<<20) // This bit masks, when set, the Parity bit: UC…
82601 … (0x1<<23) // This bit masks, when set, the Parity bit: UC…
82603 … (0x1<<21) // This bit masks, when set, the Parity bit: UC…
82605 … (0x1<<24) // This bit masks, when set, the Parity bit: UC…
82607 … (0x1<<22) // This bit masks, when set, the Parity bit: UC…
82609 … (0x1<<23) // This bit masks, when set, the Parity bit: UC…
82611 … (0x1<<24) // This bit masks, when set, the Parity bit: UC…
82613 … (0x1<<26) // This bit masks, when set, the Parity bit: UC…
82615 … (0x1<<25) // This bit masks, when set, the Parity bit: UC…
82617 … (0x1<<27) // This bit masks, when set, the Parity bit: UC…
82619 … (0x1<<26) // This bit masks, when set, the Parity bit: UC…
82621 … (0x1<<27) // This bit masks, when set, the Parity bit: UC…
82623 … (0x1<<28) // This bit masks, when set, the Parity bit: UC…
82625 … (0x1<<30) // This bit masks, when set, the Parity bit: UC…
82627 … (0x1<<29) // This bit masks, when set, the Parity bit: UC…
82629 … (0x1<<30) // This bit masks, when set, the Parity bit: UC…
82631 … (0x1<<0) // This bit masks, when set, the Parity bit: UC…
82633 … (0x1<<3) // This bit masks, when set, the Parity bit: UC…
82635 … (0x1<<4) // This bit masks, when set, the Parity bit: UC…
82637 … (0x1<<5) // This bit masks, when set, the Parity bit: UC…
82639 … (0x1<<6) // This bit masks, when set, the Parity bit: UC…
82641 … (0x1<<7) // This bit masks, when set, the Parity bit: UC…
82643 … (0x1<<8) // This bit masks, when set, the Parity bit: UC…
82645 … (0x1<<11) // This bit masks, when set, the Parity bit: UC…
82647 … (0x1<<22) // This bit masks, when set, the Parity bit: UC…
82649 … (0x1<<25) // This bit masks, when set, the Parity bit: UC…
82651 … (0x1<<28) // This bit masks, when set, the Parity bit: UC…
82654 … (0x1<<1) // This bit masks, when set, the Parity bi…
82655 …CM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_BB_K2_SHIFT 1
82656 … (0x1<<0) // This bit masks, when set, the Parity bit: UC…
82658 … (0x1<<2) // This bit masks, when set, the Parity bit: UC…
82660 … (0x1<<1) // This bit masks, when set, the Parity bi…
82661 …CM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_E5_SHIFT 1
82662 … (0x1<<3) // This bit masks, when set, the Parity bit: UC…
82664 … (0x1<<2) // This bit masks, when set, the Parity bit: UC…
82666 … (0x1<<4) // This bit masks, when set, the Parity bit: UC…
82668 … (0x1<<3) // This bit masks, when set, the Parity bit: UC…
82670 … (0x1<<5) // This bit masks, when set, the Parity bit: UC…
82672 … (0x1<<4) // This bit masks, when set, the Parity bit: UC…
82674 … (0x1<<6) // This bit masks, when set, the Parity bit: UC…
82676 … (0x1<<5) // This bit masks, when set, the Parity bit: UC…
82678 … (0x1<<0) // This bit masks, when set, the Parity bit: UC…
82680 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
82681 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
82682 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
82683 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
82687 …05_I_ECC_0_EN (0x1<<1) // Enable ECC for m…
82688 …CM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_SHIFT 1
82726 …E5 (0x1<<0) // Set parity only for memory ecc inst…
82728 …ECC_0_PRTY (0x1<<1) // Set parity only for memory…
82729 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_SHIFT 1
82730 …Y (0x1<<2) // Set parity only for memory ecc inst…
82732 …E5 (0x1<<3) // Set parity only for memory ecc inst…
82734 …Y_E5 (0x1<<4) // Set parity only for memory ecc inst…
82736 …Y_E5 (0x1<<5) // Set parity only for memory ecc inst…
82738 …Y_E5 (0x1<<6) // Set parity only for memory ecc inst…
82740 …Y_E5 (0x1<<7) // Set parity only for memory ecc inst…
82742 …Y_BB_K2 (0x1<<9) // Set parity only for memory ecc inst…
82744 …Y_E5 (0x1<<8) // Set parity only for memory ecc inst…
82746 …_BB_K2 (0x1<<10) // Set parity only for memory ecc inst…
82748 …Y_E5 (0x1<<9) // Set parity only for memory ecc inst…
82750 …BB_K2 (0x1<<0) // Set parity only for memory ecc inst…
82752 …Y_BB_K2 (0x1<<3) // Set parity only for memory ecc inst…
82754 …Y_BB_K2 (0x1<<4) // Set parity only for memory ecc inst…
82756 …BB_K2 (0x1<<5) // Set parity only for memory ecc inst…
82758 …Y_BB_K2 (0x1<<6) // Set parity only for memory ecc inst…
82760 …Y_BB_K2 (0x1<<7) // Set parity only for memory ecc inst…
82762 …BB_K2 (0x1<<8) // Set parity only for memory ecc inst…
82764 …B_K2 (0x1<<11) // Set parity only for memory ecc inst…
82769 …ED_0_MEM005_I_ECC_0_CORRECT (0x1<<1) // Record if a corr…
82770 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_SHIFT 1
82808 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
82817 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
82818 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
82819 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
82820 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
82821 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
82822 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
82823 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
82824 … size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.
82850 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82851 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
82852 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82853 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
82854 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82855 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
82856 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82857 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
82858 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82859 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
82860 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82861 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
82862 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82863 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
82864 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82865 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
82866 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82867 …- Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). …
82868 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
82869 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
82870 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
82871 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
82872 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
82873 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
82874 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
82875 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
82876 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
82877 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
82878 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
82879 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
82880 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
82881 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
82882 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82883 …esponding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir gr…
82884 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82885 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82886 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82887 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82888 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
82889 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82890 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82891 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82892 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82893 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82894 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82895 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82896 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82897 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82898 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82899 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82900 … 0x1280684UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
82902 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
82903 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
82916 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
82917 …/ Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock gro…
82918 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
82920 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
82925 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
82926 …D Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- …
82927 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
82928 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
82945 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82946 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82947 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82948 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82949 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82950 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82951 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82952 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82953 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82954 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82955 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82956 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82957 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82958 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82959 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82960 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82961 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82962 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82963 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82964 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82965 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82966 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82967 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82968 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
83000 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83001 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83002 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83003 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83004 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83005 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83006 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83007 …ten back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83008 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
83009 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
83011 … 0x1280908UL //Access:RW DataWidth:0x9 // Physical queue connection number (queue number 1).
83013 … 0x1280910UL //Access:RW DataWidth:0x7 // Physical queue task number (queue number 1).
83014 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83015 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83016 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83017 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83018 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83019 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83020 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83021 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83022 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83023 … 0x128098cUL //Access:RW DataWidth:0x3 // EventID bit width per task type…
83024 … 0x1280990UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
83025 … 0x1280994UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
83026 … 0x1280998UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
83027 … 0x128099cUL //Access:RW DataWidth:0x3 // EventID bit width per task type…
83028 … 0x12809a0UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
83029 … 0x12809a4UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
83030 … 0x12809a8UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
83031 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
83032 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
83033 … 0x1280a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
83034 … 0x1280a10UL //Access:R DataWidth:0x1 // In-process Table almost …
83044 … 0x1280a38UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83045 … 0x1280a3cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83046 … 0x1280a40UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83047 … 0x1280a44UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83048 … 0x1280a48UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83049 … 0x1280a4cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83050 … 0x1280a50UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83051 … 0x1280a54UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83052 … 0x1280a58UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83053 … 0x1280a5cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83054 … 0x1280a60UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83055 … 0x1280a64UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83056 … 0x1280a68UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83057 … 0x1280a6cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83058 … 0x1280a70UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83059 … 0x1280a74UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83060 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
83061 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
83062 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
83063 …RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the …
83090 …UL //Access:W DataWidth:0x20 // Used to write the GRC message. Write only. To distinguish if …
83124 … DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Read only.
83127 … DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Read only.
83129 … DataWidth:0x20 // Debug read from DORQ Input stage buffer with 32-bits granularity. Read only.
83131 … DataWidth:0x20 // Debug read from RDIF Input stage buffer with 32-bits granularity. Read only.
83133 … DataWidth:0x20 // Debug read from TDIF Input stage buffer with 32-bits granularity. Read only.
83135 … DataWidth:0x20 // Debug read from USDM Input stage buffer with 32-bits granularity. Read only.
83137 … DataWidth:0x20 // Debug read from XSDM Input stage buffer with 32-bits granularity. Read only.
83139 … DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Read only.
83141 … DataWidth:0x20 // Debug read from YULD Input stage buffer with 32-bits granularity. Read only.
83143 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
83144 …aWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to Aggregation Connect…
83145 …DataWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to Aggregation Task…
83146 …DataWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to STORM Connection…
83147 … DataWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to STORM Task co…
83153 … 0x1281900UL //Access:R DataWidth:0xa // Debug only. Read only access to LCI…
83156 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
83159 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
83209 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83210 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83211 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83212 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83213 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83214 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83215 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83216 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83217 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83218 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83219 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83220 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83221 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83222 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83223 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83224 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83225 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83226 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83227 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83228 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83229 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83230 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83231 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83232 …ck per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context siz…
83353 … DataWidth:0x20 // Debug read from MULD Input stage buffer with 32-bits granularity. Read only.
83354 … DataWidth:0x20 // Debug read from MULD Input stage buffer with 32-bits granularity. Read only.
83359 …iter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prio…
83363 … DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.
83365 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83366 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83367 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83368 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83369 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83370 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83371 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83372 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83373 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83374 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83375 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83376 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
83382 …A_ENABLE_IN_BB_K2 (0x1<<1) // Read data from e…
83383 …SEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_BB_K2_SHIFT 1
83384 … (0x1<<2) // FIC input enable bit used to enable/disa…
83386 … (0x1<<3) // FOC acknowledge input enable bit used to enable/disa…
83403 …Q_ENABLE_OUT_BB_K2 (0x1<<1) // Write request ou…
83404 …SEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_BB_K2_SHIFT 1
83405 … (0x1<<2) // FOC output otuput enable bit used to enable/disa…
83411 … (0x1<<5) // Stall output enable bit used to enable/disa…
83424 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
83435 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
83438 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
83440 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
83442 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
83444 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
83446 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
83449 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
83451 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
83453 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
83455 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
83458 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
83460 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
83462 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
83464 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
83483 …R_PB_DRA_WR_EN_B_E5 (0x1<<1) // Enable DRA Write…
83484 …SEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_B_E5_SHIFT 1
83485 … (0x1<<2) // When set, there may only be a single thread …
83492 …RROR (0x1<<1) // Last from FIC is…
83493 …SEM_REG_INT_STS_0_FIC_LAST_ERROR_SHIFT 1
83494 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
83522 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
83526 …that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to ru…
83530 …cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pendi…
83570 … (0x1<<11) // Signals an unknown address in the fast-memory window.
83609 … (0x1<<0) // This bit masks, when set, the Interrupt bit: X…
83611 … (0x1<<1) // This bit masks, when set, the Interrupt …
83612 …SEM_REG_INT_MASK_0_FIC_LAST_ERROR_SHIFT 1
83613 … (0x1<<2) // This bit masks, when set, the Interrupt bit: X…
83615 … (0x1<<3) // This bit masks, when set, the Interrupt bit: X…
83617 … (0x1<<4) // This bit masks, when set, the Interrupt bit: X…
83619 … (0x1<<5) // This bit masks, when set, the Interrupt bit: X…
83621 … (0x1<<6) // This bit masks, when set, the Interrupt bit: X…
83623 … (0x1<<7) // This bit masks, when set, the Interrupt bit: X…
83625 … (0x1<<8) // This bit masks, when set, the Interrupt bit: X…
83627 … (0x1<<9) // This bit masks, when set, the Interrupt bit: X…
83629 … (0x1<<23) // This bit masks, when set, the Interrupt bit: X…
83631 … (0x1<<10) // This bit masks, when set, the Interrupt bit: X…
83633 … (0x1<<25) // This bit masks, when set, the Interrupt bit: X…
83635 … (0x1<<11) // This bit masks, when set, the Interrupt bit: X…
83637 … (0x1<<12) // This bit masks, when set, the Interrupt bit: X…
83639 … (0x1<<13) // This bit masks, when set, the Interrupt bit: X…
83641 … (0x1<<14) // This bit masks, when set, the Interrupt bit: X…
83643 … (0x1<<15) // This bit masks, when set, the Interrupt bit: X…
83645 … (0x1<<16) // This bit masks, when set, the Interrupt bit: X…
83647 … (0x1<<17) // This bit masks, when set, the Interrupt bit: X…
83649 … (0x1<<18) // This bit masks, when set, the Interrupt bit: X…
83651 … (0x1<<19) // This bit masks, when set, the Interrupt bit: X…
83653 … (0x1<<20) // This bit masks, when set, the Interrupt bit: X…
83655 … (0x1<<21) // This bit masks, when set, the Interrupt bit: X…
83657 … (0x1<<22) // This bit masks, when set, the Interrupt bit: X…
83659 … (0x1<<23) // This bit masks, when set, the Interrupt bit: X…
83661 … (0x1<<24) // This bit masks, when set, the Interrupt bit: X…
83663 … (0x1<<25) // This bit masks, when set, the Interrupt bit: X…
83665 … (0x1<<26) // This bit masks, when set, the Interrupt bit: X…
83667 … (0x1<<27) // This bit masks, when set, the Interrupt bit: X…
83669 … (0x1<<28) // This bit masks, when set, the Interrupt bit: X…
83671 … (0x1<<29) // This bit masks, when set, the Interrupt bit: X…
83673 … (0x1<<30) // This bit masks, when set, the Interrupt bit: X…
83675 … (0x1<<4) // This bit masks, when set, the Interrupt bit: X…
83677 … (0x1<<5) // This bit masks, when set, the Interrupt bit: X…
83679 … (0x1<<6) // This bit masks, when set, the Interrupt bit: X…
83681 … (0x1<<7) // This bit masks, when set, the Interrupt bit: X…
83683 … (0x1<<8) // This bit masks, when set, the Interrupt bit: X…
83685 … (0x1<<9) // This bit masks, when set, the Interrupt bit: X…
83687 … (0x1<<10) // This bit masks, when set, the Interrupt bit: X…
83689 … (0x1<<11) // This bit masks, when set, the Interrupt bit: X…
83691 … (0x1<<12) // This bit masks, when set, the Interrupt bit: X…
83693 … (0x1<<13) // This bit masks, when set, the Interrupt bit: X…
83695 … (0x1<<14) // This bit masks, when set, the Interrupt bit: X…
83697 … (0x1<<15) // This bit masks, when set, the Interrupt bit: X…
83699 … (0x1<<16) // This bit masks, when set, the Interrupt bit: X…
83701 … (0x1<<17) // This bit masks, when set, the Interrupt bit: X…
83703 … (0x1<<18) // This bit masks, when set, the Interrupt bit: X…
83705 … (0x1<<19) // This bit masks, when set, the Interrupt bit: X…
83707 … (0x1<<20) // This bit masks, when set, the Interrupt bit: X…
83709 … (0x1<<21) // This bit masks, when set, the Interrupt bit: X…
83711 … (0x1<<22) // This bit masks, when set, the Interrupt bit: X…
83713 … (0x1<<24) // This bit masks, when set, the Interrupt bit: X…
83715 … (0x1<<26) // This bit masks, when set, the Interrupt bit: X…
83717 … (0x1<<27) // This bit masks, when set, the Interrupt bit: X…
83719 … (0x1<<28) // This bit masks, when set, the Interrupt bit: X…
83721 … (0x1<<29) // This bit masks, when set, the Interrupt bit: X…
83723 … (0x1<<30) // This bit masks, when set, the Interrupt bit: X…
83725 … (0x1<<31) // This bit masks, when set, the Interrupt bit: X…
83730 …T_ERROR (0x1<<1) // Last from FIC is…
83731 …SEM_REG_INT_STS_WR_0_FIC_LAST_ERROR_SHIFT 1
83732 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
83760 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
83764 …that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to ru…
83768 …cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pendi…
83808 … (0x1<<11) // Signals an unknown address in the fast-memory window.
83849 …ST_ERROR (0x1<<1) // Last from FIC is…
83850 …SEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR_SHIFT 1
83851 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
83879 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
83883 …that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to ru…
83887 …cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pendi…
83927 … (0x1<<11) // Signals an unknown address in the fast-memory window.
83968 …TORE_PUSH_ERROR_A_E5 (0x1<<1) // Fast external st…
83969 …SEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
84032 …K_OF_ATTN_BB_K2 (0x1<<1) // An overflow erro…
84033 …SEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
84038 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
84040 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
84042 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
84044 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84054 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
84057 … (0x1<<0) // This bit masks, when set, the Interrupt bit: X…
84059 … (0x1<<1) // This bit masks, when set, the Interrupt …
84060 …SEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
84061 … (0x1<<2) // This bit masks, when set, the Interrupt bit: X…
84063 … (0x1<<3) // This bit masks, when set, the Interrupt bit: X…
84065 … (0x1<<4) // This bit masks, when set, the Interrupt bit: X…
84067 … (0x1<<5) // This bit masks, when set, the Interrupt bit: X…
84069 … (0x1<<6) // This bit masks, when set, the Interrupt bit: X…
84071 … (0x1<<7) // This bit masks, when set, the Interrupt bit: X…
84073 … (0x1<<8) // This bit masks, when set, the Interrupt bit: X…
84075 … (0x1<<9) // This bit masks, when set, the Interrupt bit: X…
84077 … (0x1<<10) // This bit masks, when set, the Interrupt bit: X…
84079 … (0x1<<11) // This bit masks, when set, the Interrupt bit: X…
84081 … (0x1<<12) // This bit masks, when set, the Interrupt bit: X…
84083 … (0x1<<13) // This bit masks, when set, the Interrupt bit: X…
84085 … (0x1<<14) // This bit masks, when set, the Interrupt bit: X…
84087 … (0x1<<15) // This bit masks, when set, the Interrupt bit: X…
84089 … (0x1<<16) // This bit masks, when set, the Interrupt bit: X…
84091 … (0x1<<17) // This bit masks, when set, the Interrupt bit: X…
84093 … (0x1<<18) // This bit masks, when set, the Interrupt bit: X…
84095 … (0x1<<19) // This bit masks, when set, the Interrupt bit: X…
84097 … (0x1<<20) // This bit masks, when set, the Interrupt bit: X…
84099 … (0x1<<21) // This bit masks, when set, the Interrupt bit: X…
84101 … (0x1<<22) // This bit masks, when set, the Interrupt bit: X…
84103 … (0x1<<23) // This bit masks, when set, the Interrupt bit: X…
84105 … (0x1<<24) // This bit masks, when set, the Interrupt bit: X…
84107 … (0x1<<25) // This bit masks, when set, the Interrupt bit: X…
84109 … (0x1<<26) // This bit masks, when set, the Interrupt bit: X…
84111 … (0x1<<27) // This bit masks, when set, the Interrupt bit: X…
84113 … (0x1<<28) // This bit masks, when set, the Interrupt bit: X…
84115 … (0x1<<29) // This bit masks, when set, the Interrupt bit: X…
84117 … (0x1<<30) // This bit masks, when set, the Interrupt bit: X…
84119 … (0x1<<31) // This bit masks, when set, the Interrupt bit: X…
84121 … (0x1<<0) // This bit masks, when set, the Interrupt bit: X…
84123 … (0x1<<1) // This bit masks, when set, the Interrupt …
84124 …SEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
84125 … (0x1<<2) // This bit masks, when set, the Interrupt bit: X…
84127 … (0x1<<3) // This bit masks, when set, the Interrupt bit: X…
84129 … (0x1<<4) // This bit masks, when set, the Interrupt bit: X…
84131 … (0x1<<5) // This bit masks, when set, the Interrupt bit: X…
84133 … (0x1<<6) // This bit masks, when set, the Interrupt bit: X…
84135 … (0x1<<7) // This bit masks, when set, the Interrupt bit: X…
84137 … (0x1<<8) // This bit masks, when set, the Interrupt bit: X…
84139 … (0x1<<9) // This bit masks, when set, the Interrupt bit: X…
84141 … (0x1<<10) // This bit masks, when set, the Interrupt bit: X…
84143 … (0x1<<11) // This bit masks, when set, the Interrupt bit: X…
84145 … (0x1<<12) // This bit masks, when set, the Interrupt bit: X…
84150 …T_STORE_PUSH_ERROR_A_E5 (0x1<<1) // Fast external st…
84151 …SEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
84214 …TACK_OF_ATTN_BB_K2 (0x1<<1) // An overflow erro…
84215 …SEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
84220 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
84222 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
84224 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
84226 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84236 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
84241 …XT_STORE_PUSH_ERROR_A_E5 (0x1<<1) // Fast external st…
84242 …SEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
84305 …STACK_OF_ATTN_BB_K2 (0x1<<1) // An overflow erro…
84306 …SEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
84311 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
84313 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
84315 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
84317 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84327 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
84332 …T_FIN_FIFO_ERROR_B_E5 (0x1<<1) // Fast FIN FIFO er…
84333 …SEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
84356 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
84358 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
84393 … (0x1<<0) // This bit masks, when set, the Interrupt bit: X…
84395 … (0x1<<1) // This bit masks, when set, the Interrupt …
84396 …SEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
84397 … (0x1<<2) // This bit masks, when set, the Interrupt bit: X…
84399 … (0x1<<3) // This bit masks, when set, the Interrupt bit: X…
84401 … (0x1<<4) // This bit masks, when set, the Interrupt bit: X…
84403 … (0x1<<5) // This bit masks, when set, the Interrupt bit: X…
84405 … (0x1<<6) // This bit masks, when set, the Interrupt bit: X…
84407 … (0x1<<7) // This bit masks, when set, the Interrupt bit: X…
84409 … (0x1<<8) // This bit masks, when set, the Interrupt bit: X…
84411 … (0x1<<9) // This bit masks, when set, the Interrupt bit: X…
84413 … (0x1<<10) // This bit masks, when set, the Interrupt bit: X…
84415 … (0x1<<11) // This bit masks, when set, the Interrupt bit: X…
84417 … (0x1<<12) // This bit masks, when set, the Interrupt bit: X…
84419 … (0x1<<13) // This bit masks, when set, the Interrupt bit: X…
84421 … (0x1<<14) // This bit masks, when set, the Interrupt bit: X…
84423 … (0x1<<15) // This bit masks, when set, the Interrupt bit: X…
84425 … (0x1<<16) // This bit masks, when set, the Interrupt bit: X…
84427 … (0x1<<17) // This bit masks, when set, the Interrupt bit: X…
84429 … (0x1<<18) // This bit masks, when set, the Interrupt bit: X…
84431 … (0x1<<19) // This bit masks, when set, the Interrupt bit: X…
84433 … (0x1<<20) // This bit masks, when set, the Interrupt bit: X…
84435 … (0x1<<21) // This bit masks, when set, the Interrupt bit: X…
84437 … (0x1<<22) // This bit masks, when set, the Interrupt bit: X…
84439 … (0x1<<23) // This bit masks, when set, the Interrupt bit: X…
84441 … (0x1<<24) // This bit masks, when set, the Interrupt bit: X…
84443 … (0x1<<25) // This bit masks, when set, the Interrupt bit: X…
84445 …E5 (0x1<<26) // This bit masks, when set, the Interrupt bit: X…
84447 …E5 (0x1<<27) // This bit masks, when set, the Interrupt bit: X…
84449 … (0x1<<28) // This bit masks, when set, the Interrupt bit: X…
84451 … (0x1<<29) // This bit masks, when set, the Interrupt bit: X…
84453 … (0x1<<30) // This bit masks, when set, the Interrupt bit: X…
84458 …FAST_FIN_FIFO_ERROR_B_E5 (0x1<<1) // Fast FIN FIFO er…
84459 …SEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
84482 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
84484 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
84521 …_FAST_FIN_FIFO_ERROR_B_E5 (0x1<<1) // Fast FIN FIFO er…
84522 …SEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
84545 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
84547 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
84582 … (0x1<<0) // This bit masks, when set, the Parity bit: XS…
84584 … (0x1<<1) // This bit masks, when set, the Parity bi…
84585 …SEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_A_E5_SHIFT 1
84586 … (0x1<<2) // This bit masks, when set, the Parity bit: XS…
84588 … (0x1<<2) // This bit masks, when set, the Parity bit: XS…
84590 … (0x1<<3) // This bit masks, when set, the Parity bit: XS…
84592 … (0x1<<4) // This bit masks, when set, the Parity bit: XS…
84594 … (0x1<<1) // This bit masks, when set, the Parity bi…
84595 …SEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_BB_K2_SHIFT 1
84597 … (0x1<<0) // This bit masks, when set, the Parity bit: XS…
84599 … (0x1<<1) // This bit masks, when set, the Parity bi…
84600 …SEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_BB_K2_SHIFT 1
84601 … (0x1<<2) // This bit masks, when set, the Parity bit: XS…
84603 … (0x1<<3) // This bit masks, when set, the Parity bit: XS…
84605 … (0x1<<4) // This bit masks, when set, the Parity bit: XS…
84607 … (0x1<<5) // This bit masks, when set, the Parity bit: XS…
84609 … (0x1<<6) // This bit masks, when set, the Parity bit: XS…
84614 …006_I_ECC_1_EN_BB_K2 (0x1<<1) // Enable ECC for m…
84615 …SEM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN_BB_K2_SHIFT 1
84617 …TY_BB_K2 (0x1<<0) // Set parity only for memory ecc inst…
84619 …_ECC_1_PRTY_BB_K2 (0x1<<1) // Set parity only for memory…
84620 …SEM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY_BB_K2_SHIFT 1
84624 …TED_0_MEM006_I_ECC_1_CORRECT_BB_K2 (0x1<<1) // Record if a corr…
84625 …SEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT_BB_K2_SHIFT 1
84628 …-split register provides read/clear access to the VF error received from the SDM for a DMA transfe…
84629 …-split register provides read/clear access to the PF error received from the SDM for a DMA transfe…
84630 …_R DataWidth:0xf0 // This read-only register provides a vector of bits having an error indicatio…
84633 … DataWidth:0x10 // This read-only register provides a vector of bits having an error indicatio…
84640 … 0x1400458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mod…
84641 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
84642 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
84643 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
84647 … 0x1400600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
84649 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
84650 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
84653 …bit allows the DRA read operation to start even when there are not enough credits on all the parti…
84656 …ONLY FOR DEBUGGING! [5:0] start_rp_foc3; [11:6] start_rp_foc2; [17:12] start_rp_foc1; [23:18]…
84658 …abled even if the partition being written is owned by a thread whose valid bit is not set. Otherwi…
84659 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
84660 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
84662 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
84664 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
84667 …0x1400b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
84674 …1400b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
84675 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
84677 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
84681 …UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assign…
84683 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
84685 …L //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue pop-enable vector.
84686 … //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue wake-enable vector.
84696 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
84701 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
84711 …DataWidth:0x2 // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit 0 FIFO of Core A, bit 1 FIFO of…
84714 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
84717 …1, the correspongding Queue is empty. Queues numeration: FOC_FIFO_IF - 0, FIC0_FIFO_A - 1, FIC1_F…
84720 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
84721 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
84733 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
84734 … DataWidth:0x2 // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit 0 for Core A and bit 1 for Core…
84738 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
84749 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
84750 … 0x140140cUL //Access:RW DataWidth:0x1 // 0=output every cycle; 1= output only when there is …
84751 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
84753 … 0x1401418UL //Access:RW DataWidth:0x1 // 0=all the message; 1=partial message.
84754 … 0x140141cUL //Access:RW DataWidth:0x5 // In case DebugMode0Config = 1; the additional cycl…
84755 … 0x1401420UL //Access:RW DataWidth:0x1 // 0=without the data; 1=with the data.
84756 …bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 correspon…
84757 …eport the maximum value between following reads (when using read clear). If 1, report the current …
84759 …n between two of the following register reads. The counter is incremanted only for the event IDs w…
84772 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
84778 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
84779 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
84780 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
84781 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
84782 … 0x1408000UL //Access:WB_R DataWidth:0x4d // Provides read-only access of the exte…
84784 …nterrupt table read/write access. This register is intended to be written only when the system is …
84788 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
84790 … 0x1420000UL //Access:R DataWidth:0x20 // Passive buffer memory read only.
84793 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
84794 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
84805 …A_ENABLE_IN_BB_K2 (0x1<<1) // Read data from e…
84806 …SEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_BB_K2_SHIFT 1
84807 … (0x1<<2) // FIC input enable bit used to enable/disa…
84809 … (0x1<<3) // FOC acknowledge input enable bit used to enable/disa…
84826 …Q_ENABLE_OUT_BB_K2 (0x1<<1) // Write request ou…
84827 …SEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_BB_K2_SHIFT 1
84828 … (0x1<<2) // FOC output otuput enable bit used to enable/disa…
84834 … (0x1<<5) // Stall output enable bit used to enable/disa…
84847 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
84858 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
84861 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
84863 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
84865 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
84867 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
84869 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
84872 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
84874 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
84876 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
84878 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
84881 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
84883 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
84885 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
84887 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
84906 …R_PB_DRA_WR_EN_B_E5 (0x1<<1) // Enable DRA Write…
84907 …SEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_B_E5_SHIFT 1
84908 … (0x1<<2) // When set, there may only be a single thread …
84915 …RROR (0x1<<1) // Last from FIC is…
84916 …SEM_REG_INT_STS_0_FIC_LAST_ERROR_SHIFT 1
84917 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
84945 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84949 …that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to ru…
84953 …cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pendi…
84993 … (0x1<<11) // Signals an unknown address in the fast-memory window.
85032 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Y…
85034 … (0x1<<1) // This bit masks, when set, the Interrupt …
85035 …SEM_REG_INT_MASK_0_FIC_LAST_ERROR_SHIFT 1
85036 … (0x1<<2) // This bit masks, when set, the Interrupt bit: Y…
85038 … (0x1<<3) // This bit masks, when set, the Interrupt bit: Y…
85040 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Y…
85042 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Y…
85044 … (0x1<<6) // This bit masks, when set, the Interrupt bit: Y…
85046 … (0x1<<7) // This bit masks, when set, the Interrupt bit: Y…
85048 … (0x1<<8) // This bit masks, when set, the Interrupt bit: Y…
85050 … (0x1<<9) // This bit masks, when set, the Interrupt bit: Y…
85052 … (0x1<<23) // This bit masks, when set, the Interrupt bit: Y…
85054 … (0x1<<10) // This bit masks, when set, the Interrupt bit: Y…
85056 … (0x1<<25) // This bit masks, when set, the Interrupt bit: Y…
85058 … (0x1<<11) // This bit masks, when set, the Interrupt bit: Y…
85060 … (0x1<<12) // This bit masks, when set, the Interrupt bit: Y…
85062 … (0x1<<13) // This bit masks, when set, the Interrupt bit: Y…
85064 … (0x1<<14) // This bit masks, when set, the Interrupt bit: Y…
85066 … (0x1<<15) // This bit masks, when set, the Interrupt bit: Y…
85068 … (0x1<<16) // This bit masks, when set, the Interrupt bit: Y…
85070 … (0x1<<17) // This bit masks, when set, the Interrupt bit: Y…
85072 … (0x1<<18) // This bit masks, when set, the Interrupt bit: Y…
85074 … (0x1<<19) // This bit masks, when set, the Interrupt bit: Y…
85076 … (0x1<<20) // This bit masks, when set, the Interrupt bit: Y…
85078 … (0x1<<21) // This bit masks, when set, the Interrupt bit: Y…
85080 … (0x1<<22) // This bit masks, when set, the Interrupt bit: Y…
85082 … (0x1<<23) // This bit masks, when set, the Interrupt bit: Y…
85084 … (0x1<<24) // This bit masks, when set, the Interrupt bit: Y…
85086 … (0x1<<25) // This bit masks, when set, the Interrupt bit: Y…
85088 … (0x1<<26) // This bit masks, when set, the Interrupt bit: Y…
85090 … (0x1<<27) // This bit masks, when set, the Interrupt bit: Y…
85092 … (0x1<<28) // This bit masks, when set, the Interrupt bit: Y…
85094 … (0x1<<29) // This bit masks, when set, the Interrupt bit: Y…
85096 … (0x1<<30) // This bit masks, when set, the Interrupt bit: Y…
85098 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Y…
85100 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Y…
85102 … (0x1<<6) // This bit masks, when set, the Interrupt bit: Y…
85104 … (0x1<<7) // This bit masks, when set, the Interrupt bit: Y…
85106 … (0x1<<8) // This bit masks, when set, the Interrupt bit: Y…
85108 … (0x1<<9) // This bit masks, when set, the Interrupt bit: Y…
85110 … (0x1<<10) // This bit masks, when set, the Interrupt bit: Y…
85112 … (0x1<<11) // This bit masks, when set, the Interrupt bit: Y…
85114 … (0x1<<12) // This bit masks, when set, the Interrupt bit: Y…
85116 … (0x1<<13) // This bit masks, when set, the Interrupt bit: Y…
85118 … (0x1<<14) // This bit masks, when set, the Interrupt bit: Y…
85120 … (0x1<<15) // This bit masks, when set, the Interrupt bit: Y…
85122 … (0x1<<16) // This bit masks, when set, the Interrupt bit: Y…
85124 … (0x1<<17) // This bit masks, when set, the Interrupt bit: Y…
85126 … (0x1<<18) // This bit masks, when set, the Interrupt bit: Y…
85128 … (0x1<<19) // This bit masks, when set, the Interrupt bit: Y…
85130 … (0x1<<20) // This bit masks, when set, the Interrupt bit: Y…
85132 … (0x1<<21) // This bit masks, when set, the Interrupt bit: Y…
85134 … (0x1<<22) // This bit masks, when set, the Interrupt bit: Y…
85136 … (0x1<<24) // This bit masks, when set, the Interrupt bit: Y…
85138 … (0x1<<26) // This bit masks, when set, the Interrupt bit: Y…
85140 … (0x1<<27) // This bit masks, when set, the Interrupt bit: Y…
85142 … (0x1<<28) // This bit masks, when set, the Interrupt bit: Y…
85144 … (0x1<<29) // This bit masks, when set, the Interrupt bit: Y…
85146 … (0x1<<30) // This bit masks, when set, the Interrupt bit: Y…
85148 … (0x1<<31) // This bit masks, when set, the Interrupt bit: Y…
85153 …T_ERROR (0x1<<1) // Last from FIC is…
85154 …SEM_REG_INT_STS_WR_0_FIC_LAST_ERROR_SHIFT 1
85155 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
85183 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85187 …that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to ru…
85191 …cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pendi…
85231 … (0x1<<11) // Signals an unknown address in the fast-memory window.
85272 …ST_ERROR (0x1<<1) // Last from FIC is…
85273 …SEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR_SHIFT 1
85274 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
85302 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85306 …that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to ru…
85310 …cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pendi…
85350 … (0x1<<11) // Signals an unknown address in the fast-memory window.
85391 …TORE_PUSH_ERROR_A_E5 (0x1<<1) // Fast external st…
85392 …SEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
85455 …K_OF_ATTN_BB_K2 (0x1<<1) // An overflow erro…
85456 …SEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
85461 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
85463 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
85465 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
85467 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85477 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
85480 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Y…
85482 … (0x1<<1) // This bit masks, when set, the Interrupt …
85483 …SEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
85484 … (0x1<<2) // This bit masks, when set, the Interrupt bit: Y…
85486 … (0x1<<3) // This bit masks, when set, the Interrupt bit: Y…
85488 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Y…
85490 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Y…
85492 … (0x1<<6) // This bit masks, when set, the Interrupt bit: Y…
85494 … (0x1<<7) // This bit masks, when set, the Interrupt bit: Y…
85496 … (0x1<<8) // This bit masks, when set, the Interrupt bit: Y…
85498 … (0x1<<9) // This bit masks, when set, the Interrupt bit: Y…
85500 … (0x1<<10) // This bit masks, when set, the Interrupt bit: Y…
85502 … (0x1<<11) // This bit masks, when set, the Interrupt bit: Y…
85504 … (0x1<<12) // This bit masks, when set, the Interrupt bit: Y…
85506 … (0x1<<13) // This bit masks, when set, the Interrupt bit: Y…
85508 … (0x1<<14) // This bit masks, when set, the Interrupt bit: Y…
85510 … (0x1<<15) // This bit masks, when set, the Interrupt bit: Y…
85512 … (0x1<<16) // This bit masks, when set, the Interrupt bit: Y…
85514 … (0x1<<17) // This bit masks, when set, the Interrupt bit: Y…
85516 … (0x1<<18) // This bit masks, when set, the Interrupt bit: Y…
85518 … (0x1<<19) // This bit masks, when set, the Interrupt bit: Y…
85520 … (0x1<<20) // This bit masks, when set, the Interrupt bit: Y…
85522 … (0x1<<21) // This bit masks, when set, the Interrupt bit: Y…
85524 … (0x1<<22) // This bit masks, when set, the Interrupt bit: Y…
85526 … (0x1<<23) // This bit masks, when set, the Interrupt bit: Y…
85528 … (0x1<<24) // This bit masks, when set, the Interrupt bit: Y…
85530 … (0x1<<25) // This bit masks, when set, the Interrupt bit: Y…
85532 … (0x1<<26) // This bit masks, when set, the Interrupt bit: Y…
85534 … (0x1<<27) // This bit masks, when set, the Interrupt bit: Y…
85536 … (0x1<<28) // This bit masks, when set, the Interrupt bit: Y…
85538 … (0x1<<29) // This bit masks, when set, the Interrupt bit: Y…
85540 … (0x1<<30) // This bit masks, when set, the Interrupt bit: Y…
85542 … (0x1<<31) // This bit masks, when set, the Interrupt bit: Y…
85544 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Y…
85546 … (0x1<<1) // This bit masks, when set, the Interrupt …
85547 …SEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
85548 … (0x1<<2) // This bit masks, when set, the Interrupt bit: Y…
85550 … (0x1<<3) // This bit masks, when set, the Interrupt bit: Y…
85552 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Y…
85554 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Y…
85556 … (0x1<<6) // This bit masks, when set, the Interrupt bit: Y…
85558 … (0x1<<7) // This bit masks, when set, the Interrupt bit: Y…
85560 … (0x1<<8) // This bit masks, when set, the Interrupt bit: Y…
85562 … (0x1<<9) // This bit masks, when set, the Interrupt bit: Y…
85564 … (0x1<<10) // This bit masks, when set, the Interrupt bit: Y…
85566 … (0x1<<11) // This bit masks, when set, the Interrupt bit: Y…
85568 … (0x1<<12) // This bit masks, when set, the Interrupt bit: Y…
85573 …T_STORE_PUSH_ERROR_A_E5 (0x1<<1) // Fast external st…
85574 …SEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
85637 …TACK_OF_ATTN_BB_K2 (0x1<<1) // An overflow erro…
85638 …SEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
85643 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
85645 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
85647 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
85649 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85659 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
85664 …XT_STORE_PUSH_ERROR_A_E5 (0x1<<1) // Fast external st…
85665 …SEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
85728 …STACK_OF_ATTN_BB_K2 (0x1<<1) // An overflow erro…
85729 …SEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
85734 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
85736 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
85738 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
85740 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85750 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
85755 …T_FIN_FIFO_ERROR_B_E5 (0x1<<1) // Fast FIN FIFO er…
85756 …SEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
85779 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
85781 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
85816 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Y…
85818 … (0x1<<1) // This bit masks, when set, the Interrupt …
85819 …SEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
85820 … (0x1<<2) // This bit masks, when set, the Interrupt bit: Y…
85822 … (0x1<<3) // This bit masks, when set, the Interrupt bit: Y…
85824 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Y…
85826 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Y…
85828 … (0x1<<6) // This bit masks, when set, the Interrupt bit: Y…
85830 … (0x1<<7) // This bit masks, when set, the Interrupt bit: Y…
85832 … (0x1<<8) // This bit masks, when set, the Interrupt bit: Y…
85834 … (0x1<<9) // This bit masks, when set, the Interrupt bit: Y…
85836 … (0x1<<10) // This bit masks, when set, the Interrupt bit: Y…
85838 … (0x1<<11) // This bit masks, when set, the Interrupt bit: Y…
85840 … (0x1<<12) // This bit masks, when set, the Interrupt bit: Y…
85842 … (0x1<<13) // This bit masks, when set, the Interrupt bit: Y…
85844 … (0x1<<14) // This bit masks, when set, the Interrupt bit: Y…
85846 … (0x1<<15) // This bit masks, when set, the Interrupt bit: Y…
85848 … (0x1<<16) // This bit masks, when set, the Interrupt bit: Y…
85850 … (0x1<<17) // This bit masks, when set, the Interrupt bit: Y…
85852 … (0x1<<18) // This bit masks, when set, the Interrupt bit: Y…
85854 … (0x1<<19) // This bit masks, when set, the Interrupt bit: Y…
85856 … (0x1<<20) // This bit masks, when set, the Interrupt bit: Y…
85858 … (0x1<<21) // This bit masks, when set, the Interrupt bit: Y…
85860 … (0x1<<22) // This bit masks, when set, the Interrupt bit: Y…
85862 … (0x1<<23) // This bit masks, when set, the Interrupt bit: Y…
85864 … (0x1<<24) // This bit masks, when set, the Interrupt bit: Y…
85866 … (0x1<<25) // This bit masks, when set, the Interrupt bit: Y…
85868 …E5 (0x1<<26) // This bit masks, when set, the Interrupt bit: Y…
85870 …E5 (0x1<<27) // This bit masks, when set, the Interrupt bit: Y…
85872 … (0x1<<28) // This bit masks, when set, the Interrupt bit: Y…
85874 … (0x1<<29) // This bit masks, when set, the Interrupt bit: Y…
85876 … (0x1<<30) // This bit masks, when set, the Interrupt bit: Y…
85881 …FAST_FIN_FIFO_ERROR_B_E5 (0x1<<1) // Fast FIN FIFO er…
85882 …SEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
85905 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
85907 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
85944 …_FAST_FIN_FIFO_ERROR_B_E5 (0x1<<1) // Fast FIN FIFO er…
85945 …SEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
85968 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
85970 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
86005 … (0x1<<0) // This bit masks, when set, the Parity bit: YS…
86007 … (0x1<<1) // This bit masks, when set, the Parity bi…
86008 …SEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_A_E5_SHIFT 1
86009 … (0x1<<2) // This bit masks, when set, the Parity bit: YS…
86011 … (0x1<<2) // This bit masks, when set, the Parity bit: YS…
86013 … (0x1<<3) // This bit masks, when set, the Parity bit: YS…
86015 … (0x1<<4) // This bit masks, when set, the Parity bit: YS…
86017 … (0x1<<1) // This bit masks, when set, the Parity bi…
86018 …SEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_BB_K2_SHIFT 1
86020 … (0x1<<0) // This bit masks, when set, the Parity bit: YS…
86022 … (0x1<<1) // This bit masks, when set, the Parity bi…
86023 …SEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_BB_K2_SHIFT 1
86024 … (0x1<<2) // This bit masks, when set, the Parity bit: YS…
86026 … (0x1<<3) // This bit masks, when set, the Parity bit: YS…
86028 … (0x1<<4) // This bit masks, when set, the Parity bit: YS…
86030 … (0x1<<5) // This bit masks, when set, the Parity bit: YS…
86032 … (0x1<<6) // This bit masks, when set, the Parity bit: YS…
86037 …006_I_ECC_1_EN_BB_K2 (0x1<<1) // Enable ECC for m…
86038 …SEM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN_BB_K2_SHIFT 1
86040 …TY_BB_K2 (0x1<<0) // Set parity only for memory ecc inst…
86042 …_ECC_1_PRTY_BB_K2 (0x1<<1) // Set parity only for memory…
86043 …SEM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY_BB_K2_SHIFT 1
86047 …TED_0_MEM006_I_ECC_1_CORRECT_BB_K2 (0x1<<1) // Record if a corr…
86048 …SEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT_BB_K2_SHIFT 1
86051 …-split register provides read/clear access to the VF error received from the SDM for a DMA transfe…
86052 …-split register provides read/clear access to the PF error received from the SDM for a DMA transfe…
86053 …_R DataWidth:0xf0 // This read-only register provides a vector of bits having an error indicatio…
86056 … DataWidth:0x10 // This read-only register provides a vector of bits having an error indicatio…
86063 … 0x1500458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mod…
86064 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
86065 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
86066 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
86070 … 0x1500600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
86072 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
86073 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
86076 …bit allows the DRA read operation to start even when there are not enough credits on all the parti…
86079 …ONLY FOR DEBUGGING! [5:0] start_rp_foc3; [11:6] start_rp_foc2; [17:12] start_rp_foc1; [23:18]…
86081 …abled even if the partition being written is owned by a thread whose valid bit is not set. Otherwi…
86082 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
86083 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
86085 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
86087 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
86090 …0x1500b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
86097 …1500b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
86098 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
86100 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
86104 …UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assign…
86106 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
86108 …L //Access:RW DataWidth:0xe // Provides access to the thread ordering queue pop-enable vector.
86109 … //Access:RW DataWidth:0xe // Provides access to the thread ordering queue wake-enable vector.
86119 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
86124 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
86134 …DataWidth:0x2 // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit 0 FIFO of Core A, bit 1 FIFO of…
86137 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
86140 …1, the correspongding Queue is empty. Queues numeration: FOC_FIFO_IF - 0, FIC0_FIFO_A - 1, FIC1_F…
86143 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
86144 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
86156 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
86157 … DataWidth:0x2 // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit 0 for Core A and bit 1 for Core…
86161 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
86172 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
86173 … 0x150140cUL //Access:RW DataWidth:0x1 // 0=output every cycle; 1= output only when there is …
86174 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
86176 … 0x1501418UL //Access:RW DataWidth:0x1 // 0=all the message; 1=partial message.
86177 … 0x150141cUL //Access:RW DataWidth:0x5 // In case DebugMode0Config = 1; the additional cycl…
86178 … 0x1501420UL //Access:RW DataWidth:0x1 // 0=without the data; 1=with the data.
86179 …bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 correspon…
86180 …eport the maximum value between following reads (when using read clear). If 1, report the current …
86182 …n between two of the following register reads. The counter is incremanted only for the event IDs w…
86195 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
86201 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
86202 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
86203 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
86204 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
86205 … 0x1508000UL //Access:WB_R DataWidth:0x4c // Provides read-only access of the exte…
86207 …nterrupt table read/write access. This register is intended to be written only when the system is …
86211 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
86213 … 0x1520000UL //Access:R DataWidth:0x20 // Passive buffer memory read only.
86216 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
86217 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
86229 …A_ENABLE_IN_BB_K2 (0x1<<1) // Read data from e…
86230 …SEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_BB_K2_SHIFT 1
86231 … (0x1<<2) // FIC input enable bit used to enable/disa…
86233 … (0x1<<3) // FOC acknowledge input enable bit used to enable/disa…
86250 …Q_ENABLE_OUT_BB_K2 (0x1<<1) // Write request ou…
86251 …SEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_BB_K2_SHIFT 1
86252 … (0x1<<2) // FOC output otuput enable bit used to enable/disa…
86258 … (0x1<<5) // Stall output enable bit used to enable/disa…
86271 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
86282 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
86285 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
86287 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
86289 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
86291 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
86293 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
86296 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
86298 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
86300 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
86302 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
86305 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
86307 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
86309 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
86311 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
86330 …R_PB_DRA_WR_EN_B_E5 (0x1<<1) // Enable DRA Write…
86331 …SEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_B_E5_SHIFT 1
86332 … (0x1<<2) // When set, there may only be a single thread …
86339 …RROR (0x1<<1) // Last from FIC is…
86340 …SEM_REG_INT_STS_0_FIC_LAST_ERROR_SHIFT 1
86341 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
86369 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86373 …that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to ru…
86377 …cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pendi…
86417 … (0x1<<11) // Signals an unknown address in the fast-memory window.
86456 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
86458 … (0x1<<1) // This bit masks, when set, the Interrupt …
86459 …SEM_REG_INT_MASK_0_FIC_LAST_ERROR_SHIFT 1
86460 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
86462 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
86464 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
86466 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
86468 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
86470 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
86472 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
86474 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
86476 … (0x1<<23) // This bit masks, when set, the Interrupt bit: P…
86478 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
86480 … (0x1<<25) // This bit masks, when set, the Interrupt bit: P…
86482 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
86484 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
86486 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
86488 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
86490 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
86492 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
86494 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
86496 … (0x1<<18) // This bit masks, when set, the Interrupt bit: P…
86498 … (0x1<<19) // This bit masks, when set, the Interrupt bit: P…
86500 … (0x1<<20) // This bit masks, when set, the Interrupt bit: P…
86502 … (0x1<<21) // This bit masks, when set, the Interrupt bit: P…
86504 … (0x1<<22) // This bit masks, when set, the Interrupt bit: P…
86506 … (0x1<<23) // This bit masks, when set, the Interrupt bit: P…
86508 … (0x1<<24) // This bit masks, when set, the Interrupt bit: P…
86510 … (0x1<<25) // This bit masks, when set, the Interrupt bit: P…
86512 … (0x1<<26) // This bit masks, when set, the Interrupt bit: P…
86514 … (0x1<<27) // This bit masks, when set, the Interrupt bit: P…
86516 … (0x1<<28) // This bit masks, when set, the Interrupt bit: P…
86518 … (0x1<<29) // This bit masks, when set, the Interrupt bit: P…
86520 … (0x1<<30) // This bit masks, when set, the Interrupt bit: P…
86522 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
86524 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
86526 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
86528 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
86530 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
86532 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
86534 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
86536 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
86538 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
86540 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
86542 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
86544 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
86546 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
86548 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
86550 … (0x1<<18) // This bit masks, when set, the Interrupt bit: P…
86552 … (0x1<<19) // This bit masks, when set, the Interrupt bit: P…
86554 … (0x1<<20) // This bit masks, when set, the Interrupt bit: P…
86556 … (0x1<<21) // This bit masks, when set, the Interrupt bit: P…
86558 … (0x1<<22) // This bit masks, when set, the Interrupt bit: P…
86560 … (0x1<<24) // This bit masks, when set, the Interrupt bit: P…
86562 … (0x1<<26) // This bit masks, when set, the Interrupt bit: P…
86564 … (0x1<<27) // This bit masks, when set, the Interrupt bit: P…
86566 … (0x1<<28) // This bit masks, when set, the Interrupt bit: P…
86568 … (0x1<<29) // This bit masks, when set, the Interrupt bit: P…
86570 … (0x1<<30) // This bit masks, when set, the Interrupt bit: P…
86572 … (0x1<<31) // This bit masks, when set, the Interrupt bit: P…
86577 …T_ERROR (0x1<<1) // Last from FIC is…
86578 …SEM_REG_INT_STS_WR_0_FIC_LAST_ERROR_SHIFT 1
86579 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
86607 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86611 …that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to ru…
86615 …cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pendi…
86655 … (0x1<<11) // Signals an unknown address in the fast-memory window.
86696 …ST_ERROR (0x1<<1) // Last from FIC is…
86697 …SEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR_SHIFT 1
86698 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
86726 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86730 …that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to ru…
86734 …cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pendi…
86774 … (0x1<<11) // Signals an unknown address in the fast-memory window.
86815 …TORE_PUSH_ERROR_A_E5 (0x1<<1) // Fast external st…
86816 …SEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
86879 …K_OF_ATTN_BB_K2 (0x1<<1) // An overflow erro…
86880 …SEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
86885 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
86887 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
86889 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
86891 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86901 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
86904 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
86906 … (0x1<<1) // This bit masks, when set, the Interrupt …
86907 …SEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
86908 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
86910 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
86912 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
86914 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
86916 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
86918 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
86920 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
86922 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
86924 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
86926 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
86928 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
86930 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
86932 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
86934 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
86936 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
86938 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
86940 … (0x1<<18) // This bit masks, when set, the Interrupt bit: P…
86942 … (0x1<<19) // This bit masks, when set, the Interrupt bit: P…
86944 … (0x1<<20) // This bit masks, when set, the Interrupt bit: P…
86946 … (0x1<<21) // This bit masks, when set, the Interrupt bit: P…
86948 … (0x1<<22) // This bit masks, when set, the Interrupt bit: P…
86950 … (0x1<<23) // This bit masks, when set, the Interrupt bit: P…
86952 … (0x1<<24) // This bit masks, when set, the Interrupt bit: P…
86954 … (0x1<<25) // This bit masks, when set, the Interrupt bit: P…
86956 … (0x1<<26) // This bit masks, when set, the Interrupt bit: P…
86958 … (0x1<<27) // This bit masks, when set, the Interrupt bit: P…
86960 … (0x1<<28) // This bit masks, when set, the Interrupt bit: P…
86962 … (0x1<<29) // This bit masks, when set, the Interrupt bit: P…
86964 … (0x1<<30) // This bit masks, when set, the Interrupt bit: P…
86966 … (0x1<<31) // This bit masks, when set, the Interrupt bit: P…
86968 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
86970 … (0x1<<1) // This bit masks, when set, the Interrupt …
86971 …SEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
86972 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
86974 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
86976 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
86978 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
86980 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
86982 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
86984 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
86986 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
86988 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
86990 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
86992 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
86997 …T_STORE_PUSH_ERROR_A_E5 (0x1<<1) // Fast external st…
86998 …SEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
87061 …TACK_OF_ATTN_BB_K2 (0x1<<1) // An overflow erro…
87062 …SEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
87067 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
87069 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
87071 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
87073 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
87083 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
87088 …XT_STORE_PUSH_ERROR_A_E5 (0x1<<1) // Fast external st…
87089 …SEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
87152 …STACK_OF_ATTN_BB_K2 (0x1<<1) // An overflow erro…
87153 …SEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
87158 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
87160 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
87162 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
87164 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
87174 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
87179 …T_FIN_FIFO_ERROR_B_E5 (0x1<<1) // Fast FIN FIFO er…
87180 …SEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
87203 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
87205 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
87240 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
87242 … (0x1<<1) // This bit masks, when set, the Interrupt …
87243 …SEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
87244 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
87246 … (0x1<<3) // This bit masks, when set, the Interrupt bit: P…
87248 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
87250 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
87252 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
87254 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
87256 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
87258 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
87260 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
87262 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
87264 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
87266 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
87268 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
87270 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
87272 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
87274 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
87276 … (0x1<<18) // This bit masks, when set, the Interrupt bit: P…
87278 … (0x1<<19) // This bit masks, when set, the Interrupt bit: P…
87280 … (0x1<<20) // This bit masks, when set, the Interrupt bit: P…
87282 … (0x1<<21) // This bit masks, when set, the Interrupt bit: P…
87284 … (0x1<<22) // This bit masks, when set, the Interrupt bit: P…
87286 … (0x1<<23) // This bit masks, when set, the Interrupt bit: P…
87288 … (0x1<<24) // This bit masks, when set, the Interrupt bit: P…
87290 … (0x1<<25) // This bit masks, when set, the Interrupt bit: P…
87292 …E5 (0x1<<26) // This bit masks, when set, the Interrupt bit: P…
87294 …E5 (0x1<<27) // This bit masks, when set, the Interrupt bit: P…
87296 … (0x1<<28) // This bit masks, when set, the Interrupt bit: P…
87298 … (0x1<<29) // This bit masks, when set, the Interrupt bit: P…
87300 … (0x1<<30) // This bit masks, when set, the Interrupt bit: P…
87305 …FAST_FIN_FIFO_ERROR_B_E5 (0x1<<1) // Fast FIN FIFO er…
87306 …SEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
87329 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
87331 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
87368 …_FAST_FIN_FIFO_ERROR_B_E5 (0x1<<1) // Fast FIN FIFO er…
87369 …SEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
87392 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
87394 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
87429 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
87431 … (0x1<<1) // This bit masks, when set, the Parity bi…
87432 …SEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_A_E5_SHIFT 1
87433 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
87435 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
87437 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
87439 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
87441 … (0x1<<1) // This bit masks, when set, the Parity bi…
87442 …SEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_BB_K2_SHIFT 1
87444 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
87446 … (0x1<<1) // This bit masks, when set, the Parity bi…
87447 …SEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2_SHIFT 1
87448 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
87450 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
87452 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
87454 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
87459 …005_I_ECC_1_EN_BB_K2 (0x1<<1) // Enable ECC for m…
87460 …SEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2_SHIFT 1
87462 …TY_BB_K2 (0x1<<0) // Set parity only for memory ecc inst…
87464 …_ECC_1_PRTY_BB_K2 (0x1<<1) // Set parity only for memory…
87465 …SEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2_SHIFT 1
87469 …TED_0_MEM005_I_ECC_1_CORRECT_BB_K2 (0x1<<1) // Record if a corr…
87470 …SEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2_SHIFT 1
87473 …-split register provides read/clear access to the VF error received from the SDM for a DMA transfe…
87474 …-split register provides read/clear access to the PF error received from the SDM for a DMA transfe…
87475 …_R DataWidth:0xf0 // This read-only register provides a vector of bits having an error indicatio…
87478 … DataWidth:0x10 // This read-only register provides a vector of bits having an error indicatio…
87485 … 0x1600458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mod…
87486 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
87487 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
87488 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
87492 … 0x1600600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
87493 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
87494 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
87497 …bit allows the DRA read operation to start even when there are not enough credits on all the parti…
87500 …ONLY FOR DEBUGGING! [5:0] start_rp_foc3; [11:6] start_rp_foc2; [17:12] start_rp_foc1; [23:18]…
87502 …abled even if the partition being written is owned by a thread whose valid bit is not set. Otherwi…
87503 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
87504 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
87506 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
87508 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
87511 …0x1600b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
87518 …1600b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
87519 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
87521 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
87525 …UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assign…
87527 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
87529 …L //Access:RW DataWidth:0x4 // Provides access to the thread ordering queue pop-enable vector.
87530 … //Access:RW DataWidth:0x4 // Provides access to the thread ordering queue wake-enable vector.
87540 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
87545 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
87554 …DataWidth:0x2 // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit 0 FIFO of Core A, bit 1 FIFO of…
87557 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
87560 …1, the correspongding Queue is empty. Queues numeration: FOC_FIFO_IF - 0, FIC0_FIFO_A - 1, FIC1_F…
87563 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
87564 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
87575 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
87576 … DataWidth:0x2 // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit 0 for Core A and bit 1 for Core…
87580 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
87591 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
87592 … 0x160140cUL //Access:RW DataWidth:0x1 // 0=output every cycle; 1= output only when there is …
87593 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
87595 … 0x1601418UL //Access:RW DataWidth:0x1 // 0=all the message; 1=partial message.
87596 … 0x160141cUL //Access:RW DataWidth:0x5 // In case DebugMode0Config = 1; the additional cycl…
87597 … 0x1601420UL //Access:RW DataWidth:0x1 // 0=without the data; 1=with the data.
87598 …bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 correspon…
87599 …eport the maximum value between following reads (when using read clear). If 1, report the current …
87601 …n between two of the following register reads. The counter is incremanted only for the event IDs w…
87614 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
87620 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
87621 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
87622 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
87623 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
87624 … 0x1608000UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the exte…
87626 …nterrupt table read/write access. This register is intended to be written only when the system is …
87630 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
87632 … 0x1620000UL //Access:R DataWidth:0x20 // Passive buffer memory read only.
87635 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
87636 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
87648 …A_ENABLE_IN_BB_K2 (0x1<<1) // Read data from e…
87649 …SEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_BB_K2_SHIFT 1
87650 … (0x1<<2) // FIC input enable bit used to enable/disa…
87652 … (0x1<<3) // FOC acknowledge input enable bit used to enable/disa…
87669 …Q_ENABLE_OUT_BB_K2 (0x1<<1) // Write request ou…
87670 …SEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_BB_K2_SHIFT 1
87671 … (0x1<<2) // FOC output otuput enable bit used to enable/disa…
87677 … (0x1<<5) // Stall output enable bit used to enable/disa…
87690 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
87701 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
87704 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
87706 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
87708 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
87710 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
87712 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
87715 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
87717 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
87719 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
87721 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
87724 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
87726 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
87728 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
87730 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
87749 …R_PB_DRA_WR_EN_B_E5 (0x1<<1) // Enable DRA Write…
87750 …SEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_B_E5_SHIFT 1
87751 … (0x1<<2) // When set, there may only be a single thread …
87758 …RROR (0x1<<1) // Last from FIC is…
87759 …SEM_REG_INT_STS_0_FIC_LAST_ERROR_SHIFT 1
87760 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
87788 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
87792 …that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to ru…
87796 …cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pendi…
87836 … (0x1<<11) // Signals an unknown address in the fast-memory window.
87875 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
87877 … (0x1<<1) // This bit masks, when set, the Interrupt …
87878 …SEM_REG_INT_MASK_0_FIC_LAST_ERROR_SHIFT 1
87879 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
87881 … (0x1<<3) // This bit masks, when set, the Interrupt bit: T…
87883 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
87885 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
87887 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
87889 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
87891 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
87893 … (0x1<<9) // This bit masks, when set, the Interrupt bit: T…
87895 … (0x1<<23) // This bit masks, when set, the Interrupt bit: T…
87897 … (0x1<<10) // This bit masks, when set, the Interrupt bit: T…
87899 … (0x1<<25) // This bit masks, when set, the Interrupt bit: T…
87901 … (0x1<<11) // This bit masks, when set, the Interrupt bit: T…
87903 … (0x1<<12) // This bit masks, when set, the Interrupt bit: T…
87905 … (0x1<<13) // This bit masks, when set, the Interrupt bit: T…
87907 … (0x1<<14) // This bit masks, when set, the Interrupt bit: T…
87909 … (0x1<<15) // This bit masks, when set, the Interrupt bit: T…
87911 … (0x1<<16) // This bit masks, when set, the Interrupt bit: T…
87913 … (0x1<<17) // This bit masks, when set, the Interrupt bit: T…
87915 … (0x1<<18) // This bit masks, when set, the Interrupt bit: T…
87917 … (0x1<<19) // This bit masks, when set, the Interrupt bit: T…
87919 … (0x1<<20) // This bit masks, when set, the Interrupt bit: T…
87921 … (0x1<<21) // This bit masks, when set, the Interrupt bit: T…
87923 … (0x1<<22) // This bit masks, when set, the Interrupt bit: T…
87925 … (0x1<<23) // This bit masks, when set, the Interrupt bit: T…
87927 … (0x1<<24) // This bit masks, when set, the Interrupt bit: T…
87929 … (0x1<<25) // This bit masks, when set, the Interrupt bit: T…
87931 … (0x1<<26) // This bit masks, when set, the Interrupt bit: T…
87933 … (0x1<<27) // This bit masks, when set, the Interrupt bit: T…
87935 … (0x1<<28) // This bit masks, when set, the Interrupt bit: T…
87937 … (0x1<<29) // This bit masks, when set, the Interrupt bit: T…
87939 … (0x1<<30) // This bit masks, when set, the Interrupt bit: T…
87941 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
87943 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
87945 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
87947 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
87949 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
87951 … (0x1<<9) // This bit masks, when set, the Interrupt bit: T…
87953 … (0x1<<10) // This bit masks, when set, the Interrupt bit: T…
87955 … (0x1<<11) // This bit masks, when set, the Interrupt bit: T…
87957 … (0x1<<12) // This bit masks, when set, the Interrupt bit: T…
87959 … (0x1<<13) // This bit masks, when set, the Interrupt bit: T…
87961 … (0x1<<14) // This bit masks, when set, the Interrupt bit: T…
87963 … (0x1<<15) // This bit masks, when set, the Interrupt bit: T…
87965 … (0x1<<16) // This bit masks, when set, the Interrupt bit: T…
87967 … (0x1<<17) // This bit masks, when set, the Interrupt bit: T…
87969 … (0x1<<18) // This bit masks, when set, the Interrupt bit: T…
87971 … (0x1<<19) // This bit masks, when set, the Interrupt bit: T…
87973 … (0x1<<20) // This bit masks, when set, the Interrupt bit: T…
87975 … (0x1<<21) // This bit masks, when set, the Interrupt bit: T…
87977 … (0x1<<22) // This bit masks, when set, the Interrupt bit: T…
87979 … (0x1<<24) // This bit masks, when set, the Interrupt bit: T…
87981 … (0x1<<26) // This bit masks, when set, the Interrupt bit: T…
87983 … (0x1<<27) // This bit masks, when set, the Interrupt bit: T…
87985 … (0x1<<28) // This bit masks, when set, the Interrupt bit: T…
87987 … (0x1<<29) // This bit masks, when set, the Interrupt bit: T…
87989 … (0x1<<30) // This bit masks, when set, the Interrupt bit: T…
87991 … (0x1<<31) // This bit masks, when set, the Interrupt bit: T…
87996 …T_ERROR (0x1<<1) // Last from FIC is…
87997 …SEM_REG_INT_STS_WR_0_FIC_LAST_ERROR_SHIFT 1
87998 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
88026 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88030 …that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to ru…
88034 …cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pendi…
88074 … (0x1<<11) // Signals an unknown address in the fast-memory window.
88115 …ST_ERROR (0x1<<1) // Last from FIC is…
88116 …SEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR_SHIFT 1
88117 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
88145 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88149 …that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to ru…
88153 …cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pendi…
88193 … (0x1<<11) // Signals an unknown address in the fast-memory window.
88234 …TORE_PUSH_ERROR_A_E5 (0x1<<1) // Fast external st…
88235 …SEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
88298 …K_OF_ATTN_BB_K2 (0x1<<1) // An overflow erro…
88299 …SEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
88304 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
88306 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
88308 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
88310 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88320 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
88323 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
88325 … (0x1<<1) // This bit masks, when set, the Interrupt …
88326 …SEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
88327 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
88329 … (0x1<<3) // This bit masks, when set, the Interrupt bit: T…
88331 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
88333 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
88335 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
88337 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
88339 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
88341 … (0x1<<9) // This bit masks, when set, the Interrupt bit: T…
88343 … (0x1<<10) // This bit masks, when set, the Interrupt bit: T…
88345 … (0x1<<11) // This bit masks, when set, the Interrupt bit: T…
88347 … (0x1<<12) // This bit masks, when set, the Interrupt bit: T…
88349 … (0x1<<13) // This bit masks, when set, the Interrupt bit: T…
88351 … (0x1<<14) // This bit masks, when set, the Interrupt bit: T…
88353 … (0x1<<15) // This bit masks, when set, the Interrupt bit: T…
88355 … (0x1<<16) // This bit masks, when set, the Interrupt bit: T…
88357 … (0x1<<17) // This bit masks, when set, the Interrupt bit: T…
88359 … (0x1<<18) // This bit masks, when set, the Interrupt bit: T…
88361 … (0x1<<19) // This bit masks, when set, the Interrupt bit: T…
88363 … (0x1<<20) // This bit masks, when set, the Interrupt bit: T…
88365 … (0x1<<21) // This bit masks, when set, the Interrupt bit: T…
88367 … (0x1<<22) // This bit masks, when set, the Interrupt bit: T…
88369 … (0x1<<23) // This bit masks, when set, the Interrupt bit: T…
88371 … (0x1<<24) // This bit masks, when set, the Interrupt bit: T…
88373 … (0x1<<25) // This bit masks, when set, the Interrupt bit: T…
88375 … (0x1<<26) // This bit masks, when set, the Interrupt bit: T…
88377 … (0x1<<27) // This bit masks, when set, the Interrupt bit: T…
88379 … (0x1<<28) // This bit masks, when set, the Interrupt bit: T…
88381 … (0x1<<29) // This bit masks, when set, the Interrupt bit: T…
88383 … (0x1<<30) // This bit masks, when set, the Interrupt bit: T…
88385 … (0x1<<31) // This bit masks, when set, the Interrupt bit: T…
88387 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
88389 … (0x1<<1) // This bit masks, when set, the Interrupt …
88390 …SEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
88391 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
88393 … (0x1<<3) // This bit masks, when set, the Interrupt bit: T…
88395 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
88397 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
88399 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
88401 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
88403 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
88405 … (0x1<<9) // This bit masks, when set, the Interrupt bit: T…
88407 … (0x1<<10) // This bit masks, when set, the Interrupt bit: T…
88409 … (0x1<<11) // This bit masks, when set, the Interrupt bit: T…
88411 … (0x1<<12) // This bit masks, when set, the Interrupt bit: T…
88416 …T_STORE_PUSH_ERROR_A_E5 (0x1<<1) // Fast external st…
88417 …SEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
88480 …TACK_OF_ATTN_BB_K2 (0x1<<1) // An overflow erro…
88481 …SEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
88486 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
88488 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
88490 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
88492 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88502 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
88507 …XT_STORE_PUSH_ERROR_A_E5 (0x1<<1) // Fast external st…
88508 …SEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
88571 …STACK_OF_ATTN_BB_K2 (0x1<<1) // An overflow erro…
88572 …SEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
88577 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
88579 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
88581 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
88583 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88593 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
88598 …T_FIN_FIFO_ERROR_B_E5 (0x1<<1) // Fast FIN FIFO er…
88599 …SEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
88622 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
88624 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
88659 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
88661 … (0x1<<1) // This bit masks, when set, the Interrupt …
88662 …SEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
88663 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
88665 … (0x1<<3) // This bit masks, when set, the Interrupt bit: T…
88667 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
88669 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
88671 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
88673 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
88675 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
88677 … (0x1<<9) // This bit masks, when set, the Interrupt bit: T…
88679 … (0x1<<10) // This bit masks, when set, the Interrupt bit: T…
88681 … (0x1<<11) // This bit masks, when set, the Interrupt bit: T…
88683 … (0x1<<12) // This bit masks, when set, the Interrupt bit: T…
88685 … (0x1<<13) // This bit masks, when set, the Interrupt bit: T…
88687 … (0x1<<14) // This bit masks, when set, the Interrupt bit: T…
88689 … (0x1<<15) // This bit masks, when set, the Interrupt bit: T…
88691 … (0x1<<16) // This bit masks, when set, the Interrupt bit: T…
88693 … (0x1<<17) // This bit masks, when set, the Interrupt bit: T…
88695 … (0x1<<18) // This bit masks, when set, the Interrupt bit: T…
88697 … (0x1<<19) // This bit masks, when set, the Interrupt bit: T…
88699 … (0x1<<20) // This bit masks, when set, the Interrupt bit: T…
88701 … (0x1<<21) // This bit masks, when set, the Interrupt bit: T…
88703 … (0x1<<22) // This bit masks, when set, the Interrupt bit: T…
88705 … (0x1<<23) // This bit masks, when set, the Interrupt bit: T…
88707 … (0x1<<24) // This bit masks, when set, the Interrupt bit: T…
88709 … (0x1<<25) // This bit masks, when set, the Interrupt bit: T…
88711 …E5 (0x1<<26) // This bit masks, when set, the Interrupt bit: T…
88713 …E5 (0x1<<27) // This bit masks, when set, the Interrupt bit: T…
88715 … (0x1<<28) // This bit masks, when set, the Interrupt bit: T…
88717 … (0x1<<29) // This bit masks, when set, the Interrupt bit: T…
88719 … (0x1<<30) // This bit masks, when set, the Interrupt bit: T…
88724 …FAST_FIN_FIFO_ERROR_B_E5 (0x1<<1) // Fast FIN FIFO er…
88725 …SEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
88748 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
88750 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
88787 …_FAST_FIN_FIFO_ERROR_B_E5 (0x1<<1) // Fast FIN FIFO er…
88788 …SEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
88811 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
88813 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
88848 … (0x1<<0) // This bit masks, when set, the Parity bit: TS…
88850 … (0x1<<1) // This bit masks, when set, the Parity bi…
88851 …SEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_A_E5_SHIFT 1
88852 … (0x1<<2) // This bit masks, when set, the Parity bit: TS…
88854 … (0x1<<2) // This bit masks, when set, the Parity bit: TS…
88856 … (0x1<<3) // This bit masks, when set, the Parity bit: TS…
88858 … (0x1<<4) // This bit masks, when set, the Parity bit: TS…
88860 … (0x1<<1) // This bit masks, when set, the Parity bi…
88861 …SEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_BB_K2_SHIFT 1
88863 … (0x1<<0) // This bit masks, when set, the Parity bit: TS…
88865 … (0x1<<1) // This bit masks, when set, the Parity bi…
88866 …SEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2_SHIFT 1
88867 … (0x1<<2) // This bit masks, when set, the Parity bit: TS…
88869 … (0x1<<3) // This bit masks, when set, the Parity bit: TS…
88871 … (0x1<<4) // This bit masks, when set, the Parity bit: TS…
88873 … (0x1<<5) // This bit masks, when set, the Parity bit: TS…
88878 …005_I_ECC_1_EN_BB_K2 (0x1<<1) // Enable ECC for m…
88879 …SEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2_SHIFT 1
88881 …TY_BB_K2 (0x1<<0) // Set parity only for memory ecc inst…
88883 …_ECC_1_PRTY_BB_K2 (0x1<<1) // Set parity only for memory…
88884 …SEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2_SHIFT 1
88888 …TED_0_MEM005_I_ECC_1_CORRECT_BB_K2 (0x1<<1) // Record if a corr…
88889 …SEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2_SHIFT 1
88892 …-split register provides read/clear access to the VF error received from the SDM for a DMA transfe…
88893 …-split register provides read/clear access to the PF error received from the SDM for a DMA transfe…
88894 …_R DataWidth:0xf0 // This read-only register provides a vector of bits having an error indicatio…
88897 … DataWidth:0x10 // This read-only register provides a vector of bits having an error indicatio…
88904 … 0x1700458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mod…
88905 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
88906 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
88907 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
88911 … 0x1700600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
88912 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
88913 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
88916 …bit allows the DRA read operation to start even when there are not enough credits on all the parti…
88919 …ONLY FOR DEBUGGING! [5:0] start_rp_foc3; [11:6] start_rp_foc2; [17:12] start_rp_foc1; [23:18]…
88921 …abled even if the partition being written is owned by a thread whose valid bit is not set. Otherwi…
88922 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
88923 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
88925 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
88927 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
88930 …0x1700b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
88937 …1700b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
88938 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
88940 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
88944 …UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assign…
88946 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
88948 …L //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue pop-enable vector.
88949 … //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue wake-enable vector.
88959 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
88964 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
88973 …DataWidth:0x2 // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit 0 FIFO of Core A, bit 1 FIFO of…
88976 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
88979 …1, the correspongding Queue is empty. Queues numeration: FOC_FIFO_IF - 0, FIC0_FIFO_A - 1, FIC1_F…
88982 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
88983 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
88994 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
88995 … DataWidth:0x2 // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit 0 for Core A and bit 1 for Core…
88999 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
89010 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
89011 … 0x170140cUL //Access:RW DataWidth:0x1 // 0=output every cycle; 1= output only when there is …
89012 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
89014 … 0x1701418UL //Access:RW DataWidth:0x1 // 0=all the message; 1=partial message.
89015 … 0x170141cUL //Access:RW DataWidth:0x5 // In case DebugMode0Config = 1; the additional cycl…
89016 … 0x1701420UL //Access:RW DataWidth:0x1 // 0=without the data; 1=with the data.
89017 …bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 correspon…
89018 …eport the maximum value between following reads (when using read clear). If 1, report the current …
89020 …n between two of the following register reads. The counter is incremanted only for the event IDs w…
89033 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
89039 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
89040 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
89041 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
89042 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
89043 … 0x1708000UL //Access:WB_R DataWidth:0x4d // Provides read-only access of the exte…
89045 …nterrupt table read/write access. This register is intended to be written only when the system is …
89049 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
89051 … 0x1720000UL //Access:R DataWidth:0x20 // Passive buffer memory read only.
89054 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
89055 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
89066 …A_ENABLE_IN_BB_K2 (0x1<<1) // Read data from e…
89067 …SEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_BB_K2_SHIFT 1
89068 … (0x1<<2) // FIC input enable bit used to enable/disa…
89070 … (0x1<<3) // FOC acknowledge input enable bit used to enable/disa…
89087 …Q_ENABLE_OUT_BB_K2 (0x1<<1) // Write request ou…
89088 …SEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_BB_K2_SHIFT 1
89089 … (0x1<<2) // FOC output otuput enable bit used to enable/disa…
89095 … (0x1<<5) // Stall output enable bit used to enable/disa…
89108 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
89119 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
89122 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
89124 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
89126 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
89128 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
89130 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
89133 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
89135 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
89137 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
89139 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
89142 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
89144 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
89146 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
89148 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
89167 …R_PB_DRA_WR_EN_B_E5 (0x1<<1) // Enable DRA Write…
89168 …SEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_B_E5_SHIFT 1
89169 … (0x1<<2) // When set, there may only be a single thread …
89176 …RROR (0x1<<1) // Last from FIC is…
89177 …SEM_REG_INT_STS_0_FIC_LAST_ERROR_SHIFT 1
89178 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
89206 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89210 …that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to ru…
89214 …cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pendi…
89254 … (0x1<<11) // Signals an unknown address in the fast-memory window.
89293 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
89295 … (0x1<<1) // This bit masks, when set, the Interrupt …
89296 …SEM_REG_INT_MASK_0_FIC_LAST_ERROR_SHIFT 1
89297 … (0x1<<2) // This bit masks, when set, the Interrupt bit: M…
89299 … (0x1<<3) // This bit masks, when set, the Interrupt bit: M…
89301 … (0x1<<4) // This bit masks, when set, the Interrupt bit: M…
89303 … (0x1<<5) // This bit masks, when set, the Interrupt bit: M…
89305 … (0x1<<6) // This bit masks, when set, the Interrupt bit: M…
89307 … (0x1<<7) // This bit masks, when set, the Interrupt bit: M…
89309 … (0x1<<8) // This bit masks, when set, the Interrupt bit: M…
89311 … (0x1<<9) // This bit masks, when set, the Interrupt bit: M…
89313 … (0x1<<23) // This bit masks, when set, the Interrupt bit: M…
89315 … (0x1<<10) // This bit masks, when set, the Interrupt bit: M…
89317 … (0x1<<25) // This bit masks, when set, the Interrupt bit: M…
89319 … (0x1<<11) // This bit masks, when set, the Interrupt bit: M…
89321 … (0x1<<12) // This bit masks, when set, the Interrupt bit: M…
89323 … (0x1<<13) // This bit masks, when set, the Interrupt bit: M…
89325 … (0x1<<14) // This bit masks, when set, the Interrupt bit: M…
89327 … (0x1<<15) // This bit masks, when set, the Interrupt bit: M…
89329 … (0x1<<16) // This bit masks, when set, the Interrupt bit: M…
89331 … (0x1<<17) // This bit masks, when set, the Interrupt bit: M…
89333 … (0x1<<18) // This bit masks, when set, the Interrupt bit: M…
89335 … (0x1<<19) // This bit masks, when set, the Interrupt bit: M…
89337 … (0x1<<20) // This bit masks, when set, the Interrupt bit: M…
89339 … (0x1<<21) // This bit masks, when set, the Interrupt bit: M…
89341 … (0x1<<22) // This bit masks, when set, the Interrupt bit: M…
89343 … (0x1<<23) // This bit masks, when set, the Interrupt bit: M…
89345 … (0x1<<24) // This bit masks, when set, the Interrupt bit: M…
89347 … (0x1<<25) // This bit masks, when set, the Interrupt bit: M…
89349 … (0x1<<26) // This bit masks, when set, the Interrupt bit: M…
89351 … (0x1<<27) // This bit masks, when set, the Interrupt bit: M…
89353 … (0x1<<28) // This bit masks, when set, the Interrupt bit: M…
89355 … (0x1<<29) // This bit masks, when set, the Interrupt bit: M…
89357 … (0x1<<30) // This bit masks, when set, the Interrupt bit: M…
89359 … (0x1<<4) // This bit masks, when set, the Interrupt bit: M…
89361 … (0x1<<5) // This bit masks, when set, the Interrupt bit: M…
89363 … (0x1<<6) // This bit masks, when set, the Interrupt bit: M…
89365 … (0x1<<7) // This bit masks, when set, the Interrupt bit: M…
89367 … (0x1<<8) // This bit masks, when set, the Interrupt bit: M…
89369 … (0x1<<9) // This bit masks, when set, the Interrupt bit: M…
89371 … (0x1<<10) // This bit masks, when set, the Interrupt bit: M…
89373 … (0x1<<11) // This bit masks, when set, the Interrupt bit: M…
89375 … (0x1<<12) // This bit masks, when set, the Interrupt bit: M…
89377 … (0x1<<13) // This bit masks, when set, the Interrupt bit: M…
89379 … (0x1<<14) // This bit masks, when set, the Interrupt bit: M…
89381 … (0x1<<15) // This bit masks, when set, the Interrupt bit: M…
89383 … (0x1<<16) // This bit masks, when set, the Interrupt bit: M…
89385 … (0x1<<17) // This bit masks, when set, the Interrupt bit: M…
89387 … (0x1<<18) // This bit masks, when set, the Interrupt bit: M…
89389 … (0x1<<19) // This bit masks, when set, the Interrupt bit: M…
89391 … (0x1<<20) // This bit masks, when set, the Interrupt bit: M…
89393 … (0x1<<21) // This bit masks, when set, the Interrupt bit: M…
89395 … (0x1<<22) // This bit masks, when set, the Interrupt bit: M…
89397 … (0x1<<24) // This bit masks, when set, the Interrupt bit: M…
89399 … (0x1<<26) // This bit masks, when set, the Interrupt bit: M…
89401 … (0x1<<27) // This bit masks, when set, the Interrupt bit: M…
89403 … (0x1<<28) // This bit masks, when set, the Interrupt bit: M…
89405 … (0x1<<29) // This bit masks, when set, the Interrupt bit: M…
89407 … (0x1<<30) // This bit masks, when set, the Interrupt bit: M…
89409 … (0x1<<31) // This bit masks, when set, the Interrupt bit: M…
89414 …T_ERROR (0x1<<1) // Last from FIC is…
89415 …SEM_REG_INT_STS_WR_0_FIC_LAST_ERROR_SHIFT 1
89416 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
89444 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89448 …that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to ru…
89452 …cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pendi…
89492 … (0x1<<11) // Signals an unknown address in the fast-memory window.
89533 …ST_ERROR (0x1<<1) // Last from FIC is…
89534 …SEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR_SHIFT 1
89535 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
89563 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89567 …that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to ru…
89571 …cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pendi…
89611 … (0x1<<11) // Signals an unknown address in the fast-memory window.
89652 …TORE_PUSH_ERROR_A_E5 (0x1<<1) // Fast external st…
89653 …SEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
89716 …K_OF_ATTN_BB_K2 (0x1<<1) // An overflow erro…
89717 …SEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
89722 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
89724 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
89726 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
89728 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89738 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
89741 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
89743 … (0x1<<1) // This bit masks, when set, the Interrupt …
89744 …SEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
89745 … (0x1<<2) // This bit masks, when set, the Interrupt bit: M…
89747 … (0x1<<3) // This bit masks, when set, the Interrupt bit: M…
89749 … (0x1<<4) // This bit masks, when set, the Interrupt bit: M…
89751 … (0x1<<5) // This bit masks, when set, the Interrupt bit: M…
89753 … (0x1<<6) // This bit masks, when set, the Interrupt bit: M…
89755 … (0x1<<7) // This bit masks, when set, the Interrupt bit: M…
89757 … (0x1<<8) // This bit masks, when set, the Interrupt bit: M…
89759 … (0x1<<9) // This bit masks, when set, the Interrupt bit: M…
89761 … (0x1<<10) // This bit masks, when set, the Interrupt bit: M…
89763 … (0x1<<11) // This bit masks, when set, the Interrupt bit: M…
89765 … (0x1<<12) // This bit masks, when set, the Interrupt bit: M…
89767 … (0x1<<13) // This bit masks, when set, the Interrupt bit: M…
89769 … (0x1<<14) // This bit masks, when set, the Interrupt bit: M…
89771 … (0x1<<15) // This bit masks, when set, the Interrupt bit: M…
89773 … (0x1<<16) // This bit masks, when set, the Interrupt bit: M…
89775 … (0x1<<17) // This bit masks, when set, the Interrupt bit: M…
89777 … (0x1<<18) // This bit masks, when set, the Interrupt bit: M…
89779 … (0x1<<19) // This bit masks, when set, the Interrupt bit: M…
89781 … (0x1<<20) // This bit masks, when set, the Interrupt bit: M…
89783 … (0x1<<21) // This bit masks, when set, the Interrupt bit: M…
89785 … (0x1<<22) // This bit masks, when set, the Interrupt bit: M…
89787 … (0x1<<23) // This bit masks, when set, the Interrupt bit: M…
89789 … (0x1<<24) // This bit masks, when set, the Interrupt bit: M…
89791 … (0x1<<25) // This bit masks, when set, the Interrupt bit: M…
89793 … (0x1<<26) // This bit masks, when set, the Interrupt bit: M…
89795 … (0x1<<27) // This bit masks, when set, the Interrupt bit: M…
89797 … (0x1<<28) // This bit masks, when set, the Interrupt bit: M…
89799 … (0x1<<29) // This bit masks, when set, the Interrupt bit: M…
89801 … (0x1<<30) // This bit masks, when set, the Interrupt bit: M…
89803 … (0x1<<31) // This bit masks, when set, the Interrupt bit: M…
89805 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
89807 … (0x1<<1) // This bit masks, when set, the Interrupt …
89808 …SEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
89809 … (0x1<<2) // This bit masks, when set, the Interrupt bit: M…
89811 … (0x1<<3) // This bit masks, when set, the Interrupt bit: M…
89813 … (0x1<<4) // This bit masks, when set, the Interrupt bit: M…
89815 … (0x1<<5) // This bit masks, when set, the Interrupt bit: M…
89817 … (0x1<<6) // This bit masks, when set, the Interrupt bit: M…
89819 … (0x1<<7) // This bit masks, when set, the Interrupt bit: M…
89821 … (0x1<<8) // This bit masks, when set, the Interrupt bit: M…
89823 … (0x1<<9) // This bit masks, when set, the Interrupt bit: M…
89825 … (0x1<<10) // This bit masks, when set, the Interrupt bit: M…
89827 … (0x1<<11) // This bit masks, when set, the Interrupt bit: M…
89829 … (0x1<<12) // This bit masks, when set, the Interrupt bit: M…
89834 …T_STORE_PUSH_ERROR_A_E5 (0x1<<1) // Fast external st…
89835 …SEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
89898 …TACK_OF_ATTN_BB_K2 (0x1<<1) // An overflow erro…
89899 …SEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
89904 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
89906 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
89908 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
89910 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89920 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
89925 …XT_STORE_PUSH_ERROR_A_E5 (0x1<<1) // Fast external st…
89926 …SEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
89989 …STACK_OF_ATTN_BB_K2 (0x1<<1) // An overflow erro…
89990 …SEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
89995 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
89997 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
89999 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
90001 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
90011 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
90016 …T_FIN_FIFO_ERROR_B_E5 (0x1<<1) // Fast FIN FIFO er…
90017 …SEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
90040 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
90042 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
90077 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
90079 … (0x1<<1) // This bit masks, when set, the Interrupt …
90080 …SEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
90081 … (0x1<<2) // This bit masks, when set, the Interrupt bit: M…
90083 … (0x1<<3) // This bit masks, when set, the Interrupt bit: M…
90085 … (0x1<<4) // This bit masks, when set, the Interrupt bit: M…
90087 … (0x1<<5) // This bit masks, when set, the Interrupt bit: M…
90089 … (0x1<<6) // This bit masks, when set, the Interrupt bit: M…
90091 … (0x1<<7) // This bit masks, when set, the Interrupt bit: M…
90093 … (0x1<<8) // This bit masks, when set, the Interrupt bit: M…
90095 … (0x1<<9) // This bit masks, when set, the Interrupt bit: M…
90097 … (0x1<<10) // This bit masks, when set, the Interrupt bit: M…
90099 … (0x1<<11) // This bit masks, when set, the Interrupt bit: M…
90101 … (0x1<<12) // This bit masks, when set, the Interrupt bit: M…
90103 … (0x1<<13) // This bit masks, when set, the Interrupt bit: M…
90105 … (0x1<<14) // This bit masks, when set, the Interrupt bit: M…
90107 … (0x1<<15) // This bit masks, when set, the Interrupt bit: M…
90109 … (0x1<<16) // This bit masks, when set, the Interrupt bit: M…
90111 … (0x1<<17) // This bit masks, when set, the Interrupt bit: M…
90113 … (0x1<<18) // This bit masks, when set, the Interrupt bit: M…
90115 … (0x1<<19) // This bit masks, when set, the Interrupt bit: M…
90117 … (0x1<<20) // This bit masks, when set, the Interrupt bit: M…
90119 … (0x1<<21) // This bit masks, when set, the Interrupt bit: M…
90121 … (0x1<<22) // This bit masks, when set, the Interrupt bit: M…
90123 … (0x1<<23) // This bit masks, when set, the Interrupt bit: M…
90125 … (0x1<<24) // This bit masks, when set, the Interrupt bit: M…
90127 … (0x1<<25) // This bit masks, when set, the Interrupt bit: M…
90129 …E5 (0x1<<26) // This bit masks, when set, the Interrupt bit: M…
90131 …E5 (0x1<<27) // This bit masks, when set, the Interrupt bit: M…
90133 … (0x1<<28) // This bit masks, when set, the Interrupt bit: M…
90135 … (0x1<<29) // This bit masks, when set, the Interrupt bit: M…
90137 … (0x1<<30) // This bit masks, when set, the Interrupt bit: M…
90142 …FAST_FIN_FIFO_ERROR_B_E5 (0x1<<1) // Fast FIN FIFO er…
90143 …SEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
90166 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
90168 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
90205 …_FAST_FIN_FIFO_ERROR_B_E5 (0x1<<1) // Fast FIN FIFO er…
90206 …SEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
90229 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
90231 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
90266 … (0x1<<0) // This bit masks, when set, the Parity bit: MS…
90268 … (0x1<<1) // This bit masks, when set, the Parity bi…
90269 …SEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_A_E5_SHIFT 1
90270 … (0x1<<2) // This bit masks, when set, the Parity bit: MS…
90272 … (0x1<<2) // This bit masks, when set, the Parity bit: MS…
90274 … (0x1<<3) // This bit masks, when set, the Parity bit: MS…
90276 … (0x1<<4) // This bit masks, when set, the Parity bit: MS…
90278 … (0x1<<1) // This bit masks, when set, the Parity bi…
90279 …SEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_BB_K2_SHIFT 1
90281 … (0x1<<0) // This bit masks, when set, the Parity bit: MS…
90283 … (0x1<<1) // This bit masks, when set, the Parity bi…
90284 …SEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_SHIFT 1
90285 … (0x1<<2) // This bit masks, when set, the Parity bit: MS…
90287 … (0x1<<3) // This bit masks, when set, the Parity bit: MS…
90289 … (0x1<<4) // This bit masks, when set, the Parity bit: MS…
90291 … (0x1<<5) // This bit masks, when set, the Parity bit: MS…
90293 … (0x1<<6) // This bit masks, when set, the Parity bit: MS…
90295 … (0x1<<7) // This bit masks, when set, the Parity bit: MS…
90297 … (0x1<<5) // This bit masks, when set, the Parity bit: MS…
90299 … (0x1<<8) // This bit masks, when set, the Parity bit: MS…
90301 … (0x1<<2) // This bit masks, when set, the Parity bit: MS…
90303 … (0x1<<9) // This bit masks, when set, the Parity bit: MS…
90305 … (0x1<<10) // This bit masks, when set, the Parity bit: MS…
90307 … (0x1<<4) // This bit masks, when set, the Parity bit: MS…
90309 … (0x1<<11) // This bit masks, when set, the Parity bit: MS…
90311 … (0x1<<12) // This bit masks, when set, the Parity bit: MS…
90313 … (0x1<<3) // This bit masks, when set, the Parity bit: MS…
90315 … (0x1<<13) // This bit masks, when set, the Parity bit: MS…
90317 … (0x1<<14) // This bit masks, when set, the Parity bit: MS…
90319 … (0x1<<15) // This bit masks, when set, the Parity bit: MS…
90324 …005_I_ECC_1_EN (0x1<<1) // Enable ECC for m…
90325 …SEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_SHIFT 1
90339 …TY (0x1<<0) // Set parity only for memory ecc inst…
90341 …_ECC_1_PRTY (0x1<<1) // Set parity only for memory…
90342 …SEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_SHIFT 1
90343 …TY_E5 (0x1<<2) // Set parity only for memory ecc inst…
90345 …TY_E5 (0x1<<3) // Set parity only for memory ecc inst…
90347 …TY_E5 (0x1<<4) // Set parity only for memory ecc inst…
90349 …TY_E5 (0x1<<5) // Set parity only for memory ecc inst…
90351 …TY_E5 (0x1<<6) // Set parity only for memory ecc inst…
90353 …TY_E5 (0x1<<7) // Set parity only for memory ecc inst…
90358 …TED_0_MEM005_I_ECC_1_CORRECT (0x1<<1) // Record if a corr…
90359 …SEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_SHIFT 1
90374 …-split register provides read/clear access to the VF error received from the SDM for a DMA transfe…
90375 …-split register provides read/clear access to the PF error received from the SDM for a DMA transfe…
90376 …_R DataWidth:0xf0 // This read-only register provides a vector of bits having an error indicatio…
90379 … DataWidth:0x10 // This read-only register provides a vector of bits having an error indicatio…
90386 … 0x1800458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mod…
90387 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
90388 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
90389 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
90393 … 0x1800600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
90394 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
90395 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
90398 …bit allows the DRA read operation to start even when there are not enough credits on all the parti…
90401 …ONLY FOR DEBUGGING! [5:0] start_rp_foc3; [11:6] start_rp_foc2; [17:12] start_rp_foc1; [23:18]…
90403 …abled even if the partition being written is owned by a thread whose valid bit is not set. Otherwi…
90404 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
90405 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
90407 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
90409 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
90412 …0x1800b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
90419 …1800b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
90420 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
90422 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
90426 …UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assign…
90428 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
90430 …L //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue pop-enable vector.
90431 … //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue wake-enable vector.
90441 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
90446 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
90455 …DataWidth:0x2 // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit 0 FIFO of Core A, bit 1 FIFO of…
90458 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
90461 …1, the correspongding Queue is empty. Queues numeration: FOC_FIFO_IF - 0, FIC0_FIFO_A - 1, FIC1_F…
90464 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
90465 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
90476 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
90477 … DataWidth:0x2 // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit 0 for Core A and bit 1 for Core…
90481 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
90492 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
90493 … 0x180140cUL //Access:RW DataWidth:0x1 // 0=output every cycle; 1= output only when there is …
90494 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
90496 … 0x1801418UL //Access:RW DataWidth:0x1 // 0=all the message; 1=partial message.
90497 … 0x180141cUL //Access:RW DataWidth:0x5 // In case DebugMode0Config = 1; the additional cycl…
90498 … 0x1801420UL //Access:RW DataWidth:0x1 // 0=without the data; 1=with the data.
90499 …bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 correspon…
90500 …eport the maximum value between following reads (when using read clear). If 1, report the current …
90502 …n between two of the following register reads. The counter is incremanted only for the event IDs w…
90515 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
90521 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
90522 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
90523 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
90524 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
90525 … 0x1808000UL //Access:WB_R DataWidth:0x4d // Provides read-only access of the exte…
90527 …nterrupt table read/write access. This register is intended to be written only when the system is …
90531 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
90533 … 0x1820000UL //Access:R DataWidth:0x20 // Passive buffer memory read only.
90536 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
90537 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
90549 …A_ENABLE_IN_BB_K2 (0x1<<1) // Read data from e…
90550 …SEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_BB_K2_SHIFT 1
90551 … (0x1<<2) // FIC input enable bit used to enable/disa…
90553 … (0x1<<3) // FOC acknowledge input enable bit used to enable/disa…
90570 …Q_ENABLE_OUT_BB_K2 (0x1<<1) // Write request ou…
90571 …SEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_BB_K2_SHIFT 1
90572 … (0x1<<2) // FOC output otuput enable bit used to enable/disa…
90578 … (0x1<<5) // Stall output enable bit used to enable/disa…
90591 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
90602 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
90605 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
90607 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
90609 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
90611 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
90613 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
90616 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
90618 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
90620 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
90622 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
90625 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
90627 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
90629 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
90631 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
90650 …R_PB_DRA_WR_EN_B_E5 (0x1<<1) // Enable DRA Write…
90651 …SEM_REG_PASSIVE_BUFFER_DRA_WR_PB_DRA_WR_EN_B_E5_SHIFT 1
90652 … (0x1<<2) // When set, there may only be a single thread …
90659 …RROR (0x1<<1) // Last from FIC is…
90660 …SEM_REG_INT_STS_0_FIC_LAST_ERROR_SHIFT 1
90661 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
90689 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
90693 …that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to ru…
90697 …cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pendi…
90737 … (0x1<<11) // Signals an unknown address in the fast-memory window.
90776 … (0x1<<0) // This bit masks, when set, the Interrupt bit: U…
90778 … (0x1<<1) // This bit masks, when set, the Interrupt …
90779 …SEM_REG_INT_MASK_0_FIC_LAST_ERROR_SHIFT 1
90780 … (0x1<<2) // This bit masks, when set, the Interrupt bit: U…
90782 … (0x1<<3) // This bit masks, when set, the Interrupt bit: U…
90784 … (0x1<<4) // This bit masks, when set, the Interrupt bit: U…
90786 … (0x1<<5) // This bit masks, when set, the Interrupt bit: U…
90788 … (0x1<<6) // This bit masks, when set, the Interrupt bit: U…
90790 … (0x1<<7) // This bit masks, when set, the Interrupt bit: U…
90792 … (0x1<<8) // This bit masks, when set, the Interrupt bit: U…
90794 … (0x1<<9) // This bit masks, when set, the Interrupt bit: U…
90796 … (0x1<<23) // This bit masks, when set, the Interrupt bit: U…
90798 … (0x1<<10) // This bit masks, when set, the Interrupt bit: U…
90800 … (0x1<<25) // This bit masks, when set, the Interrupt bit: U…
90802 … (0x1<<11) // This bit masks, when set, the Interrupt bit: U…
90804 … (0x1<<12) // This bit masks, when set, the Interrupt bit: U…
90806 … (0x1<<13) // This bit masks, when set, the Interrupt bit: U…
90808 … (0x1<<14) // This bit masks, when set, the Interrupt bit: U…
90810 … (0x1<<15) // This bit masks, when set, the Interrupt bit: U…
90812 … (0x1<<16) // This bit masks, when set, the Interrupt bit: U…
90814 … (0x1<<17) // This bit masks, when set, the Interrupt bit: U…
90816 … (0x1<<18) // This bit masks, when set, the Interrupt bit: U…
90818 … (0x1<<19) // This bit masks, when set, the Interrupt bit: U…
90820 … (0x1<<20) // This bit masks, when set, the Interrupt bit: U…
90822 … (0x1<<21) // This bit masks, when set, the Interrupt bit: U…
90824 … (0x1<<22) // This bit masks, when set, the Interrupt bit: U…
90826 … (0x1<<23) // This bit masks, when set, the Interrupt bit: U…
90828 … (0x1<<24) // This bit masks, when set, the Interrupt bit: U…
90830 … (0x1<<25) // This bit masks, when set, the Interrupt bit: U…
90832 … (0x1<<26) // This bit masks, when set, the Interrupt bit: U…
90834 … (0x1<<27) // This bit masks, when set, the Interrupt bit: U…
90836 … (0x1<<28) // This bit masks, when set, the Interrupt bit: U…
90838 … (0x1<<29) // This bit masks, when set, the Interrupt bit: U…
90840 … (0x1<<30) // This bit masks, when set, the Interrupt bit: U…
90842 … (0x1<<4) // This bit masks, when set, the Interrupt bit: U…
90844 … (0x1<<5) // This bit masks, when set, the Interrupt bit: U…
90846 … (0x1<<6) // This bit masks, when set, the Interrupt bit: U…
90848 … (0x1<<7) // This bit masks, when set, the Interrupt bit: U…
90850 … (0x1<<8) // This bit masks, when set, the Interrupt bit: U…
90852 … (0x1<<9) // This bit masks, when set, the Interrupt bit: U…
90854 … (0x1<<10) // This bit masks, when set, the Interrupt bit: U…
90856 … (0x1<<11) // This bit masks, when set, the Interrupt bit: U…
90858 … (0x1<<12) // This bit masks, when set, the Interrupt bit: U…
90860 … (0x1<<13) // This bit masks, when set, the Interrupt bit: U…
90862 … (0x1<<14) // This bit masks, when set, the Interrupt bit: U…
90864 … (0x1<<15) // This bit masks, when set, the Interrupt bit: U…
90866 … (0x1<<16) // This bit masks, when set, the Interrupt bit: U…
90868 … (0x1<<17) // This bit masks, when set, the Interrupt bit: U…
90870 … (0x1<<18) // This bit masks, when set, the Interrupt bit: U…
90872 … (0x1<<19) // This bit masks, when set, the Interrupt bit: U…
90874 … (0x1<<20) // This bit masks, when set, the Interrupt bit: U…
90876 … (0x1<<21) // This bit masks, when set, the Interrupt bit: U…
90878 … (0x1<<22) // This bit masks, when set, the Interrupt bit: U…
90880 … (0x1<<24) // This bit masks, when set, the Interrupt bit: U…
90882 … (0x1<<26) // This bit masks, when set, the Interrupt bit: U…
90884 … (0x1<<27) // This bit masks, when set, the Interrupt bit: U…
90886 … (0x1<<28) // This bit masks, when set, the Interrupt bit: U…
90888 … (0x1<<29) // This bit masks, when set, the Interrupt bit: U…
90890 … (0x1<<30) // This bit masks, when set, the Interrupt bit: U…
90892 … (0x1<<31) // This bit masks, when set, the Interrupt bit: U…
90897 …T_ERROR (0x1<<1) // Last from FIC is…
90898 …SEM_REG_INT_STS_WR_0_FIC_LAST_ERROR_SHIFT 1
90899 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
90927 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
90931 …that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to ru…
90935 …cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pendi…
90975 … (0x1<<11) // Signals an unknown address in the fast-memory window.
91016 …ST_ERROR (0x1<<1) // Last from FIC is…
91017 …SEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR_SHIFT 1
91018 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
91046 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91050 …that FIC1 affinity field is not "Storm A". (Error since FIC1 messages can only be designated to ru…
91054 …cases: a. Thread STM is not at "Running", "DRA RD" , "Sleeping 0", Sleeping 1", "Partial FIN Pendi…
91094 … (0x1<<11) // Signals an unknown address in the fast-memory window.
91135 …TORE_PUSH_ERROR_A_E5 (0x1<<1) // Fast external st…
91136 …SEM_REG_INT_STS_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
91199 …K_OF_ATTN_BB_K2 (0x1<<1) // An overflow erro…
91200 …SEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
91205 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
91207 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
91209 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
91211 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91221 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
91224 … (0x1<<0) // This bit masks, when set, the Interrupt bit: U…
91226 … (0x1<<1) // This bit masks, when set, the Interrupt …
91227 …SEM_REG_INT_MASK_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
91228 … (0x1<<2) // This bit masks, when set, the Interrupt bit: U…
91230 … (0x1<<3) // This bit masks, when set, the Interrupt bit: U…
91232 … (0x1<<4) // This bit masks, when set, the Interrupt bit: U…
91234 … (0x1<<5) // This bit masks, when set, the Interrupt bit: U…
91236 … (0x1<<6) // This bit masks, when set, the Interrupt bit: U…
91238 … (0x1<<7) // This bit masks, when set, the Interrupt bit: U…
91240 … (0x1<<8) // This bit masks, when set, the Interrupt bit: U…
91242 … (0x1<<9) // This bit masks, when set, the Interrupt bit: U…
91244 … (0x1<<10) // This bit masks, when set, the Interrupt bit: U…
91246 … (0x1<<11) // This bit masks, when set, the Interrupt bit: U…
91248 … (0x1<<12) // This bit masks, when set, the Interrupt bit: U…
91250 … (0x1<<13) // This bit masks, when set, the Interrupt bit: U…
91252 … (0x1<<14) // This bit masks, when set, the Interrupt bit: U…
91254 … (0x1<<15) // This bit masks, when set, the Interrupt bit: U…
91256 … (0x1<<16) // This bit masks, when set, the Interrupt bit: U…
91258 … (0x1<<17) // This bit masks, when set, the Interrupt bit: U…
91260 … (0x1<<18) // This bit masks, when set, the Interrupt bit: U…
91262 … (0x1<<19) // This bit masks, when set, the Interrupt bit: U…
91264 … (0x1<<20) // This bit masks, when set, the Interrupt bit: U…
91266 … (0x1<<21) // This bit masks, when set, the Interrupt bit: U…
91268 … (0x1<<22) // This bit masks, when set, the Interrupt bit: U…
91270 … (0x1<<23) // This bit masks, when set, the Interrupt bit: U…
91272 … (0x1<<24) // This bit masks, when set, the Interrupt bit: U…
91274 … (0x1<<25) // This bit masks, when set, the Interrupt bit: U…
91276 … (0x1<<26) // This bit masks, when set, the Interrupt bit: U…
91278 … (0x1<<27) // This bit masks, when set, the Interrupt bit: U…
91280 … (0x1<<28) // This bit masks, when set, the Interrupt bit: U…
91282 … (0x1<<29) // This bit masks, when set, the Interrupt bit: U…
91284 … (0x1<<30) // This bit masks, when set, the Interrupt bit: U…
91286 … (0x1<<31) // This bit masks, when set, the Interrupt bit: U…
91288 … (0x1<<0) // This bit masks, when set, the Interrupt bit: U…
91290 … (0x1<<1) // This bit masks, when set, the Interrupt …
91291 …SEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
91292 … (0x1<<2) // This bit masks, when set, the Interrupt bit: U…
91294 … (0x1<<3) // This bit masks, when set, the Interrupt bit: U…
91296 … (0x1<<4) // This bit masks, when set, the Interrupt bit: U…
91298 … (0x1<<5) // This bit masks, when set, the Interrupt bit: U…
91300 … (0x1<<6) // This bit masks, when set, the Interrupt bit: U…
91302 … (0x1<<7) // This bit masks, when set, the Interrupt bit: U…
91304 … (0x1<<8) // This bit masks, when set, the Interrupt bit: U…
91306 … (0x1<<9) // This bit masks, when set, the Interrupt bit: U…
91308 … (0x1<<10) // This bit masks, when set, the Interrupt bit: U…
91310 … (0x1<<11) // This bit masks, when set, the Interrupt bit: U…
91312 … (0x1<<12) // This bit masks, when set, the Interrupt bit: U…
91317 …T_STORE_PUSH_ERROR_A_E5 (0x1<<1) // Fast external st…
91318 …SEM_REG_INT_STS_WR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
91381 …TACK_OF_ATTN_BB_K2 (0x1<<1) // An overflow erro…
91382 …SEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
91387 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
91389 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
91391 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
91393 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91403 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
91408 …XT_STORE_PUSH_ERROR_A_E5 (0x1<<1) // Fast external st…
91409 …SEM_REG_INT_STS_CLR_1_FAST_EXT_STORE_PUSH_ERROR_A_E5_SHIFT 1
91472 …STACK_OF_ATTN_BB_K2 (0x1<<1) // An overflow erro…
91473 …SEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_BB_K2_SHIFT 1
91478 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
91480 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
91482 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
91484 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91494 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
91499 …T_FIN_FIFO_ERROR_B_E5 (0x1<<1) // Fast FIN FIFO er…
91500 …SEM_REG_INT_STS_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
91523 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
91525 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
91560 … (0x1<<0) // This bit masks, when set, the Interrupt bit: U…
91562 … (0x1<<1) // This bit masks, when set, the Interrupt …
91563 …SEM_REG_INT_MASK_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
91564 … (0x1<<2) // This bit masks, when set, the Interrupt bit: U…
91566 … (0x1<<3) // This bit masks, when set, the Interrupt bit: U…
91568 … (0x1<<4) // This bit masks, when set, the Interrupt bit: U…
91570 … (0x1<<5) // This bit masks, when set, the Interrupt bit: U…
91572 … (0x1<<6) // This bit masks, when set, the Interrupt bit: U…
91574 … (0x1<<7) // This bit masks, when set, the Interrupt bit: U…
91576 … (0x1<<8) // This bit masks, when set, the Interrupt bit: U…
91578 … (0x1<<9) // This bit masks, when set, the Interrupt bit: U…
91580 … (0x1<<10) // This bit masks, when set, the Interrupt bit: U…
91582 … (0x1<<11) // This bit masks, when set, the Interrupt bit: U…
91584 … (0x1<<12) // This bit masks, when set, the Interrupt bit: U…
91586 … (0x1<<13) // This bit masks, when set, the Interrupt bit: U…
91588 … (0x1<<14) // This bit masks, when set, the Interrupt bit: U…
91590 … (0x1<<15) // This bit masks, when set, the Interrupt bit: U…
91592 … (0x1<<16) // This bit masks, when set, the Interrupt bit: U…
91594 … (0x1<<17) // This bit masks, when set, the Interrupt bit: U…
91596 … (0x1<<18) // This bit masks, when set, the Interrupt bit: U…
91598 … (0x1<<19) // This bit masks, when set, the Interrupt bit: U…
91600 … (0x1<<20) // This bit masks, when set, the Interrupt bit: U…
91602 … (0x1<<21) // This bit masks, when set, the Interrupt bit: U…
91604 … (0x1<<22) // This bit masks, when set, the Interrupt bit: U…
91606 … (0x1<<23) // This bit masks, when set, the Interrupt bit: U…
91608 … (0x1<<24) // This bit masks, when set, the Interrupt bit: U…
91610 … (0x1<<25) // This bit masks, when set, the Interrupt bit: U…
91612 …E5 (0x1<<26) // This bit masks, when set, the Interrupt bit: U…
91614 …E5 (0x1<<27) // This bit masks, when set, the Interrupt bit: U…
91616 … (0x1<<28) // This bit masks, when set, the Interrupt bit: U…
91618 … (0x1<<29) // This bit masks, when set, the Interrupt bit: U…
91620 … (0x1<<30) // This bit masks, when set, the Interrupt bit: U…
91625 …FAST_FIN_FIFO_ERROR_B_E5 (0x1<<1) // Fast FIN FIFO er…
91626 …SEM_REG_INT_STS_WR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
91649 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
91651 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
91688 …_FAST_FIN_FIFO_ERROR_B_E5 (0x1<<1) // Fast FIN FIFO er…
91689 …SEM_REG_INT_STS_CLR_2_RD_RBC_FAST_FIN_FIFO_ERROR_B_E5_SHIFT 1
91712 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
91714 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
91749 … (0x1<<0) // This bit masks, when set, the Parity bit: US…
91751 … (0x1<<1) // This bit masks, when set, the Parity bi…
91752 …SEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_A_E5_SHIFT 1
91753 … (0x1<<2) // This bit masks, when set, the Parity bit: US…
91755 … (0x1<<2) // This bit masks, when set, the Parity bit: US…
91757 … (0x1<<3) // This bit masks, when set, the Parity bit: US…
91759 … (0x1<<4) // This bit masks, when set, the Parity bit: US…
91761 … (0x1<<1) // This bit masks, when set, the Parity bi…
91762 …SEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_BB_K2_SHIFT 1
91764 … (0x1<<0) // This bit masks, when set, the Parity bit: US…
91766 … (0x1<<1) // This bit masks, when set, the Parity bi…
91767 …SEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2_SHIFT 1
91768 … (0x1<<2) // This bit masks, when set, the Parity bit: US…
91770 … (0x1<<3) // This bit masks, when set, the Parity bit: US…
91772 … (0x1<<4) // This bit masks, when set, the Parity bit: US…
91774 … (0x1<<5) // This bit masks, when set, the Parity bit: US…
91779 …005_I_ECC_1_EN_BB_K2 (0x1<<1) // Enable ECC for m…
91780 …SEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2_SHIFT 1
91782 …TY_BB_K2 (0x1<<0) // Set parity only for memory ecc inst…
91784 …_ECC_1_PRTY_BB_K2 (0x1<<1) // Set parity only for memory…
91785 …SEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2_SHIFT 1
91789 …TED_0_MEM005_I_ECC_1_CORRECT_BB_K2 (0x1<<1) // Record if a corr…
91790 …SEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2_SHIFT 1
91793 …-split register provides read/clear access to the VF error received from the SDM for a DMA transfe…
91794 …-split register provides read/clear access to the PF error received from the SDM for a DMA transfe…
91795 …_R DataWidth:0xf0 // This read-only register provides a vector of bits having an error indicatio…
91798 … DataWidth:0x10 // This read-only register provides a vector of bits having an error indicatio…
91805 … 0x1900458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mod…
91806 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
91807 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
91808 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
91812 … 0x1900600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
91813 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
91814 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
91817 …bit allows the DRA read operation to start even when there are not enough credits on all the parti…
91820 …ONLY FOR DEBUGGING! [5:0] start_rp_foc3; [11:6] start_rp_foc2; [17:12] start_rp_foc1; [23:18]…
91822 …abled even if the partition being written is owned by a thread whose valid bit is not set. Otherwi…
91823 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
91824 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
91826 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
91828 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
91831 …0x1900b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
91838 …1900b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
91839 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
91841 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
91845 …UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assign…
91847 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
91849 …L //Access:RW DataWidth:0x10 // Provides access to the thread ordering queue pop-enable vector.
91850 … //Access:RW DataWidth:0x10 // Provides access to the thread ordering queue wake-enable vector.
91860 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
91865 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
91874 …DataWidth:0x2 // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit 0 FIFO of Core A, bit 1 FIFO of…
91877 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
91880 …1, the correspongding Queue is empty. Queues numeration: FOC_FIFO_IF - 0, FIC0_FIFO_A - 1, FIC1_F…
91883 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
91884 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
91895 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
91896 … DataWidth:0x2 // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit 0 for Core A and bit 1 for Core…
91900 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
91911 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
91912 … 0x190140cUL //Access:RW DataWidth:0x1 // 0=output every cycle; 1= output only when there is …
91913 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
91915 … 0x1901418UL //Access:RW DataWidth:0x1 // 0=all the message; 1=partial message.
91916 … 0x190141cUL //Access:RW DataWidth:0x5 // In case DebugMode0Config = 1; the additional cycl…
91917 … 0x1901420UL //Access:RW DataWidth:0x1 // 0=without the data; 1=with the data.
91918 …bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 correspon…
91919 …eport the maximum value between following reads (when using read clear). If 1, report the current …
91921 …n between two of the following register reads. The counter is incremanted only for the event IDs w…
91934 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
91940 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
91941 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
91942 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
91943 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
91944 … 0x1908000UL //Access:WB_R DataWidth:0x4c // Provides read-only access of the exte…
91946 …nterrupt table read/write access. This register is intended to be written only when the system is …
91950 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
91952 … 0x1920000UL //Access:R DataWidth:0x20 // Passive buffer memory read only.
91955 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
91956 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…