Lines Matching +full:1 +full:- +full:bit +full:- +full:only
1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
10 * 1. Redistributions of source code must retain the above copyright
18 * 4. Neither the name of the author nor the names of any co-contributors
57 state to compare one bit of the boards ID.
58 This register is read only.
66 Bit[2] Reset CSN to 0
67 Bit[1] Return to the Wait for Key state
68 Bit[0] Reset all logical devices and restore configuration
69 registers to their power-up values.
71 A write to bit[0] of this register performs a reset function on
76 A write to bit[1] of this register causes all cards to enter the
80 A write to bit[2] of this register causes all cards to reset their
83 This register is write-only. The values are not sticky, that is,
94 pointer to the byte-serial device is reset. This register is
101 The Status register must be polled until bit[0] is set before this
102 register may be read. This register is read only.
107 Bit[0] when set indicates it is okay to read the next data byte
124 Check and Activate commands operate only on the selected logical
125 device. This register is read/write. If a card has only 1 logical
126 device, this location should be a read-only value of 0x00.
129 /*** addresses 0x08 - 0x1F Card Level Reserved for future use ***/
130 /*** addresses 0x20 - 0x2F Card Level, Vendor Defined ***/
135 whether or not the logical device is active on the ISA bus. Bit[0],
136 if set, activates the logical device. Bits[7:1] are reserved and
148 Bit[7:2] Reserved and must return 0 on reads
149 Bit[1] Enable I/O Range check, if set then I/O Range Check
150 is enabled. I/O range check is only valid when the logical
153 Bit[0], if set, forces the logical device to respond to I/O reads
159 /*** addr 0x32 - 0x37 Logical Device Control Reserved for future use ***/
160 /*** addr 0x38 - 0x3F Logical Device Control Vendor Define ***/
174 Offset 1: RW Memory base address bits[15:8]
176 Bit[1] specifies 8/16-bit control. This bit is set to indicate
177 16-bit memory, and cleared to indicate 8-bit memory.
178 Bit[0], if cleared, indicates the next field can be used as a range
181 Bit[0], if set, indicates the next field is the upper limit for
182 the address. - - Bit[0] is read-only.
185 Offset 5-Offset 7: filler, unused.
193 Offset 1: I/O port base address bits[7:0]
200 Offset 0: RW interrupt level (1..15, 0=unused).
201 Offset 1: Bit[1]: level(1:hi, 0:low),
202 Bit[0]: type (1:level, 0:edge)
203 byte 1 can be readonly if 1 type of int is used.
206 #define PNP_DMA_CHANNEL(i) (0x74 + 1*(i))
214 /*** 32-bit memory accesses are at 0x76 ***/
232 #define PNP_TAG_RESERVED 0xa-0xd
243 #define PNP_TAG_LARGE_RESERVED 0x7-0x7f