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/linux/arch/arm/boot/dts/xen/
H A Dxenvm-4.2.dts26 #size-cells = <0>;
28 cpu@0 {
31 reg = <0>;
51 reg = <0 0x80000000 0 0x08000000>;
57 #address-cells = <0>;
59 reg = <0 0x2c001000 0 0x1000>,
60 <0 0x2c002000 0 0x100>;
65 interrupts = <1 13 0xf08>,
66 <1 14 0xf08>,
67 <1 11 0xf08>,
[all …]
/linux/arch/arm/boot/dts/calxeda/
H A Decx-2000.dts9 /memreserve/ 0x00000000 0x0001000;
19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0>;
54 memory@0 {
57 reg = <0x00000000 0x00000000 0x00000000 0xff800000>;
63 reg = <0x00000002 0x00000000 0x00000003 0x00000000>;
67 ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;
70 compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>,
71 <1 14 0xf08>,
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Darm,arch_timer.yaml121 interrupts = <1 13 0xf08>,
122 <1 14 0xf08>,
123 <1 11 0xf08>,
124 <1 10 0xf08>;
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15-tc1.dts16 arm,hbi = <0x237>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu@0 {
41 reg = <0>;
53 reg = <0 0x80000000 0 0x40000000>;
61 /* Chipselect 2 is physically at 0x18000000 */
65 reg = <0 0x18000000 0 0x00800000>;
72 reg = <0 0x2b000000 0 0x1000>;
73 interrupts = <0 85 4>;
[all …]
H A Dvexpress-v2p-ca15_a7.dts16 arm,hbi = <0x249>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu0: cpu@0 {
41 reg = <0>;
61 reg = <0x100>;
71 reg = <0x101>;
81 reg = <0x102>;
109 reg = <0 0x80000000 0 0x40000000>;
117 /* Chipselect 2 is physically at 0x18000000 */
[all …]
/linux/drivers/media/platform/mediatek/mdp3/
H A Dmdp_reg_wdma.h10 #define WDMA_EN 0x008
11 #define WDMA_RST 0x00c
12 #define WDMA_CFG 0x014
13 #define WDMA_SRC_SIZE 0x018
14 #define WDMA_CLIP_SIZE 0x01c
15 #define WDMA_CLIP_COORD 0x020
16 #define WDMA_DST_W_IN_BYTE 0x028
17 #define WDMA_ALPHA 0x02c
18 #define WDMA_BUF_CON2 0x03c
19 #define WDMA_DST_UV_PITCH 0x078
[all …]
H A Dmdp_reg_wrot.h10 #define VIDO_CTRL 0x000
11 #define VIDO_MAIN_BUF_SIZE 0x008
12 #define VIDO_SOFT_RST 0x010
13 #define VIDO_SOFT_RST_STAT 0x014
14 #define VIDO_CROP_OFST 0x020
15 #define VIDO_TAR_SIZE 0x024
16 #define VIDO_OFST_ADDR 0x02c
17 #define VIDO_STRIDE 0x030
18 #define VIDO_OFST_ADDR_C 0x038
19 #define VIDO_STRIDE_C 0x03c
[all …]
H A Dmdp_reg_rdma.h10 #define MDP_RDMA_EN 0x000
11 #define MDP_RDMA_RESET 0x008
12 #define MDP_RDMA_CON 0x020
13 #define MDP_RDMA_GMCIF_CON 0x028
14 #define MDP_RDMA_SRC_CON 0x030
15 #define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
16 #define MDP_RDMA_MF_BKGD_SIZE_IN_PXL 0x068
17 #define MDP_RDMA_MF_SRC_SIZE 0x070
18 #define MDP_RDMA_MF_CLIP_SIZE 0x078
19 #define MDP_RDMA_MF_OFFSET_1 0x080
[all …]
/linux/drivers/soc/mediatek/
H A Dmt8183-mmsys.h6 #define MT8183_DISP_OVL0_MOUT_EN 0xf00
7 #define MT8183_DISP_OVL0_2L_MOUT_EN 0xf04
8 #define MT8183_DISP_OVL1_2L_MOUT_EN 0xf08
9 #define MT8183_DISP_DITHER0_MOUT_EN 0xf0c
10 #define MT8183_DISP_PATH0_SEL_IN 0xf24
11 #define MT8183_DISP_DSI0_SEL_IN 0xf2c
12 #define MT8183_DISP_DPI0_SEL_IN 0xf30
13 #define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
14 #define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
17 #define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
[all …]
H A Dmt8192-mmsys.h6 #define MT8192_MMSYS_OVL_MOUT_EN 0xf04
7 #define MT8192_DISP_OVL1_2L_MOUT_EN 0xf08
8 #define MT8192_DISP_OVL0_2L_MOUT_EN 0xf18
9 #define MT8192_DISP_OVL0_MOUT_EN 0xf1c
10 #define MT8192_DISP_RDMA0_SEL_IN 0xf2c
11 #define MT8192_DISP_RDMA0_SOUT_SEL 0xf30
12 #define MT8192_DISP_CCORR0_SOUT_SEL 0xf34
13 #define MT8192_DISP_AAL0_SEL_IN 0xf38
14 #define MT8192_DISP_DITHER0_MOUT_EN 0xf3c
15 #define MT8192_DISP_DSI0_SEL_IN 0xf40
[all …]
H A Dmt8188-mmsys.h9 #define MT8188_VDO0_SW0_RST_B 0x190
10 #define MT8188_VDO0_OVL_MOUT_EN 0xf14
11 #define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
18 #define MT8188_VDO0_SEL_IN 0xf34
19 #define MT8188_VDO0_SEL_OUT 0xf38
21 #define MT8188_VDO0_DISP_RDMA_SEL 0xf40
22 #define MT8188_SOUT_DISP_RDMA0_TO_MASK GENMASK(2, 0)
23 #define MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0 (0 << 0)
24 #define MT8188_SOUT_DISP_RDMA0_TO_DISP_DSI0 (1 << 0)
25 #define MT8188_SOUT_DISP_RDMA0_TO_DISP_DP_INTF0 (5 << 0)
[all …]
H A Dmt8195-mmsys.h6 #define MT8195_VDO0_OVL_MOUT_EN 0xf14
7 #define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
14 #define MT8195_VDO0_SEL_IN 0xf34
15 #define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)
16 #define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
17 #define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
18 #define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
20 #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
23 #define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
26 #define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
[all …]
/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi21 service_reserved: svcbuffer@0 {
23 reg = <0x0 0x0 0x0 0x1000000>;
24 alignment = <0x1000>;
31 #size-cells = <0>;
33 cpu0: cpu@0 {
38 reg = <0x0>;
46 reg = <0x1>;
54 reg = <0x2>;
62 reg = <0x3>;
86 #address-cells = <0x2>;
[all …]
/linux/arch/arm/boot/dts/hisilicon/
H A Dhip04.dtsi22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
27 #size-cells = <0>;
87 CPU0: cpu@0 {
90 reg = <0>;
110 reg = <0x100>;
115 reg = <0x101>;
120 reg = <0x102>;
125 reg = <0x103>;
130 reg = <0x200>;
135 reg = <0x201>;
[all …]
/linux/include/linux/amba/
H A Dsp810.h18 #define SCCTRL 0x000
19 #define SCSYSSTAT 0x004
20 #define SCIMCTRL 0x008
21 #define SCIMSTAT 0x00C
22 #define SCXTALCTRL 0x010
23 #define SCPLLCTRL 0x014
24 #define SCPLLFCTRL 0x018
25 #define SCPERCTRL0 0x01C
26 #define SCPERCTRL1 0x020
27 #define SCPEREN 0x024
[all …]
/linux/arch/arm/mach-highbank/
H A Dsysregs.h16 #define HB_SREG_A9_PWR_REQ 0xf00
17 #define HB_SREG_A9_BOOT_STAT 0xf04
18 #define HB_SREG_A9_BOOT_DATA 0xf08
20 #define HB_PWR_SUSPEND 0
25 #define SREG_CPU_PWR_CTRL(c) (0x200 + ((c) * 4))
29 int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); in highbank_set_core_pwr()
38 int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); in highbank_clear_core_pwr()
42 writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu)); in highbank_clear_core_pwr()
71 writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_clear_pwr_request()
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8084.dtsi21 reg = <0xfa00000 0x200000>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
94 reg = <0x0 0x0>;
189 interrupts = <GIC_PPI 7 0xf04>;
195 #clock-cells = <0>;
201 #clock-cells = <0>;
208 interrupts = <GIC_PPI 2 0xf08>,
209 <GIC_PPI 3 0xf08>,
[all …]
/linux/arch/m68k/include/asm/
H A Dm54xxsim.h15 #define IOMEMSIZE 0x01000000
24 #define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */
26 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
27 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
28 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
29 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
30 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
31 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
32 #define MCFINTC_IRLR 0x18 /* */
33 #define MCFINTC_IACKL 0x19 /* */
[all …]
/linux/Documentation/devicetree/bindings/arm/
H A Dxen.txt13 Region 0 is reserved for mapping grant table, it must be always present.
47 reg = <0 0xb0000000 0 0x20000>;
48 interrupts = <1 15 0xf08>;
50 xen,uefi-system-table = <0xXXXXXXXX>;
51 xen,uefi-mmap-start = <0xXXXXXXXX>;
52 xen,uefi-mmap-size = <0xXXXXXXXX>;
53 xen,uefi-mmap-desc-size = <0xXXXXXXXX>;
54 xen,uefi-mmap-desc-ver = <0xXXXXXXXX>;
/linux/drivers/media/dvb-frontends/
H A Dsp887x.c38 } while (0)
42 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = len }; in i2c_writebytes()
51 return 0; in i2c_writebytes()
56 u8 b0 [] = { reg >> 8 , reg & 0xff, data >> 8, data & 0xff }; in sp887x_writereg()
57 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 4 }; in sp887x_writereg()
64 if (!(reg == 0xf1a && data == 0x000 && in sp887x_writereg()
68 __func__, reg & 0xffff, data & 0xffff, ret); in sp887x_writereg()
73 return 0; in sp887x_writereg()
78 u8 b0 [] = { reg >> 8 , reg & 0xff }; in sp887x_readreg()
81 struct i2c_msg msg[] = {{ .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 }, in sp887x_readreg()
[all …]
/linux/drivers/firewire/
H A Dnosy.h10 #define PCILYNX_MAX_REGISTER 0xfff
11 #define PCILYNX_MAX_MEMORY 0xffff
13 #define PCI_LATENCY_CACHELINE 0x0c
15 #define MISC_CONTROL 0x40
16 #define MISC_CONTROL_SWRESET (1<<0)
18 #define SERIAL_EEPROM_CONTROL 0x44
20 #define PCI_INT_STATUS 0x48
21 #define PCI_INT_ENABLE 0x4c
42 #define PCI_INT_DMA0_HLT (1<<0)
44 #define PCI_INT_DMA_ALL 0x3ff
[all …]
/linux/sound/pci/hda/
H A Dca0132_regs.h12 #define DSP_CHIP_OFFSET 0x100000
13 #define DSP_DBGCNTL_MODULE_OFFSET 0xE30
17 #define DSP_DBGCNTL_EXEC_LOBIT 0x0
18 #define DSP_DBGCNTL_EXEC_HIBIT 0x3
19 #define DSP_DBGCNTL_EXEC_MASK 0xF
21 #define DSP_DBGCNTL_SS_LOBIT 0x4
22 #define DSP_DBGCNTL_SS_HIBIT 0x7
23 #define DSP_DBGCNTL_SS_MASK 0xF0
25 #define DSP_DBGCNTL_STATE_LOBIT 0xA
26 #define DSP_DBGCNTL_STATE_HIBIT 0xD
[all …]
/linux/include/linux/mlx4/
H A Dcmd.h43 MLX4_CMD_SYS_EN = 0x1,
44 MLX4_CMD_SYS_DIS = 0x2,
45 MLX4_CMD_MAP_FA = 0xfff,
46 MLX4_CMD_UNMAP_FA = 0xffe,
47 MLX4_CMD_RUN_FW = 0xff6,
48 MLX4_CMD_MOD_STAT_CFG = 0x34,
49 MLX4_CMD_QUERY_DEV_CAP = 0x3,
50 MLX4_CMD_QUERY_FW = 0x4,
51 MLX4_CMD_ENABLE_LAM = 0xff8,
52 MLX4_CMD_DISABLE_LAM = 0xff7,
[all …]
/linux/sound/pci/lola/
H A Dlola.h17 #define LOLA_BAR0_GCAP 0x00
18 #define LOLA_BAR0_VMIN 0x02
19 #define LOLA_BAR0_VMAJ 0x03
20 #define LOLA_BAR0_OUTPAY 0x04
21 #define LOLA_BAR0_INPAY 0x06
22 #define LOLA_BAR0_GCTL 0x08
23 #define LOLA_BAR0_WAKEEN 0x0c
24 #define LOLA_BAR0_STATESTS 0x0e
25 #define LOLA_BAR0_GSTS 0x10
26 #define LOLA_BAR0_OUTSTRMPAY 0x18
[all …]
/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A D8710b.c18 {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00},
19 {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04},
20 {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, {0x43C, 0x04},
21 {0x43D, 0x05}, {0x43E, 0x07}, {0x43F, 0x08}, {0x440, 0x5D},
22 {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00},
23 {0x446, 0x00}, {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xF0},
24 {0x44A, 0x0F}, {0x44B, 0x3E}, {0x44C, 0x10}, {0x44D, 0x00},
25 {0x44E, 0x00}, {0x44F, 0x00}, {0x450, 0x00}, {0x451, 0xF0},
26 {0x452, 0x0F}, {0x453, 0x00}, {0x456, 0x5E}, {0x460, 0x66},
27 {0x461, 0x66}, {0x4C8, 0xFF}, {0x4C9, 0x08}, {0x4CC, 0xFF},
[all …]

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