1da660b4aSCatalin Marinas /* 2da660b4aSCatalin Marinas * ARM PrimeXsys System Controller SP810 header file 3da660b4aSCatalin Marinas * 4da660b4aSCatalin Marinas * Copyright (C) 2009 ST Microelectronics 5*da89947bSViresh Kumar * Viresh Kumar <vireshk@kernel.org> 6da660b4aSCatalin Marinas * 7da660b4aSCatalin Marinas * This file is licensed under the terms of the GNU General Public 8da660b4aSCatalin Marinas * License version 2. This program is licensed "as is" without any 9da660b4aSCatalin Marinas * warranty of any kind, whether express or implied. 10da660b4aSCatalin Marinas */ 11da660b4aSCatalin Marinas 12e0ea0414SSachin Kamat #ifndef __AMBA_SP810_H 13e0ea0414SSachin Kamat #define __AMBA_SP810_H 14da660b4aSCatalin Marinas 15da660b4aSCatalin Marinas #include <linux/io.h> 16da660b4aSCatalin Marinas 17da660b4aSCatalin Marinas /* sysctl registers offset */ 18da660b4aSCatalin Marinas #define SCCTRL 0x000 19da660b4aSCatalin Marinas #define SCSYSSTAT 0x004 20da660b4aSCatalin Marinas #define SCIMCTRL 0x008 21da660b4aSCatalin Marinas #define SCIMSTAT 0x00C 22da660b4aSCatalin Marinas #define SCXTALCTRL 0x010 23da660b4aSCatalin Marinas #define SCPLLCTRL 0x014 24da660b4aSCatalin Marinas #define SCPLLFCTRL 0x018 25da660b4aSCatalin Marinas #define SCPERCTRL0 0x01C 26da660b4aSCatalin Marinas #define SCPERCTRL1 0x020 27da660b4aSCatalin Marinas #define SCPEREN 0x024 28da660b4aSCatalin Marinas #define SCPERDIS 0x028 29da660b4aSCatalin Marinas #define SCPERCLKEN 0x02C 30da660b4aSCatalin Marinas #define SCPERSTAT 0x030 31da660b4aSCatalin Marinas #define SCSYSID0 0xEE0 32da660b4aSCatalin Marinas #define SCSYSID1 0xEE4 33da660b4aSCatalin Marinas #define SCSYSID2 0xEE8 34da660b4aSCatalin Marinas #define SCSYSID3 0xEEC 35da660b4aSCatalin Marinas #define SCITCR 0xF00 36da660b4aSCatalin Marinas #define SCITIR0 0xF04 37da660b4aSCatalin Marinas #define SCITIR1 0xF08 38da660b4aSCatalin Marinas #define SCITOR 0xF0C 39da660b4aSCatalin Marinas #define SCCNTCTRL 0xF10 40da660b4aSCatalin Marinas #define SCCNTDATA 0xF14 41da660b4aSCatalin Marinas #define SCCNTSTEP 0xF18 42da660b4aSCatalin Marinas #define SCPERIPHID0 0xFE0 43da660b4aSCatalin Marinas #define SCPERIPHID1 0xFE4 44da660b4aSCatalin Marinas #define SCPERIPHID2 0xFE8 45da660b4aSCatalin Marinas #define SCPERIPHID3 0xFEC 46da660b4aSCatalin Marinas #define SCPCELLID0 0xFF0 47da660b4aSCatalin Marinas #define SCPCELLID1 0xFF4 48da660b4aSCatalin Marinas #define SCPCELLID2 0xFF8 49da660b4aSCatalin Marinas #define SCPCELLID3 0xFFC 50da660b4aSCatalin Marinas 51da660b4aSCatalin Marinas #define SCCTRL_TIMERENnSEL_SHIFT(n) (15 + ((n) * 2)) 52da660b4aSCatalin Marinas sysctl_soft_reset(void __iomem * base)53da660b4aSCatalin Marinasstatic inline void sysctl_soft_reset(void __iomem *base) 54da660b4aSCatalin Marinas { 55da660b4aSCatalin Marinas /* switch to slow mode */ 56da660b4aSCatalin Marinas writel(0x2, base + SCCTRL); 57da660b4aSCatalin Marinas 58da660b4aSCatalin Marinas /* writing any value to SCSYSSTAT reg will reset system */ 59da660b4aSCatalin Marinas writel(0, base + SCSYSSTAT); 60da660b4aSCatalin Marinas } 61da660b4aSCatalin Marinas 62e0ea0414SSachin Kamat #endif /* __AMBA_SP810_H */ 63