Lines Matching +full:0 +full:xf08
6 #define MT8195_VDO0_OVL_MOUT_EN 0xf14
7 #define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
14 #define MT8195_VDO0_SEL_IN 0xf34
15 #define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)
16 #define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
17 #define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
18 #define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
20 #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
23 #define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
26 #define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
29 #define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
31 #define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0)
35 #define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16)
38 #define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17)
41 #define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20)
44 #define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21)
47 #define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
49 #define MT8195_VDO0_SEL_OUT 0xf38
50 #define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0)
51 #define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
52 #define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
54 #define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
58 #define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
61 #define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8)
67 #define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
69 #define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12)
73 #define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16)
78 #define MT8195_VDO1_SW0_RST_B 0x1d0
79 #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
80 #define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
81 #define MT8195_VDO1_HDR_TOP_CFG 0xd00
82 #define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30
83 #define MT8195_VDO1_MIXER_IN1_PAD 0xd40
85 #define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
88 #define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
91 #define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
92 #define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0
94 #define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
95 #define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0
97 #define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
101 #define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24
104 #define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28
107 #define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c
110 #define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30
113 #define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
116 #define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
119 #define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
122 #define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
125 #define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
128 #define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
131 #define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50
134 #define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
135 #define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER 0
137 #define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
138 #define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER 0
140 #define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60
141 #define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER 0
143 #define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64
144 #define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER 0
146 #define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
147 #define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0
150 #define MT8195_VPP1_HW_DCM_1ST_DIS0 0x150
151 #define MT8195_VPP1_HW_DCM_1ST_DIS1 0x160
152 #define MT8195_VPP1_HW_DCM_2ND_DIS0 0x1a0
153 #define MT8195_VPP1_HW_DCM_2ND_DIS1 0x1b0
154 #define MT8195_SVPP2_BUF_BF_RSZ_SWITCH 0xf48
155 #define MT8195_SVPP3_BUF_BF_RSZ_SWITCH 0xf74
457 MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
461 MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
465 MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
469 MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
473 MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
477 MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
481 MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
485 MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
489 MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
493 MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
497 MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
501 MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
505 MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
509 MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
513 MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
517 MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
521 MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
525 MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),