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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmsi.txt86 reg = <0xa 0xf00>;
93 reg = <0xb 0xf00>;
101 reg = <0xc 0xf00>;
108 dev@0 {
109 reg = <0x0 0xf00>;
117 reg = <0x1 0xf00>;
123 msi-parent = <&msi_a>, <&msi_b 0x17>;
127 reg = <0x2 0xf00>;
133 msi-parent = <&msi_a>, <&msi_b 0x17>, <&msi_c 0x53>;
/freebsd/sys/crypto/openssl/
H A Dossl_x86.c46 * [0] = cpu_feature but with a few custom bits
72 OPENSSL_ia32cap_P[0] = cpu_feature & ~(CPUID_B20 | CPUID_IA64); in ossl_cpuid()
74 OPENSSL_ia32cap_P[0] |= CPUID_IA64; in ossl_cpuid()
75 if ((cpu_id & 0xf00) != 0xf00) in ossl_cpuid()
76 OPENSSL_ia32cap_P[0] |= CPUID_B20; in ossl_cpuid()
80 if (cpu_vendor_id == CPU_VENDOR_AMD && cpu_exthigh >= 0x80000008) { in ossl_cpuid()
84 OPENSSL_ia32cap_P[0] &= ~CPUID_HTT; in ossl_cpuid()
88 cpuid_count(4, 0, regs); in ossl_cpuid()
89 max_cores = (regs[0] >> 26) & 0xfff; in ossl_cpuid()
93 if (max_cores == 0) in ossl_cpuid()
[all …]
/freebsd/sys/powerpc/pseries/
H A Drtas_pci.c102 DRIVER_MODULE(rtaspci, ofwbus, rtaspci_driver, 0, 0);
114 if (OF_getproplen(ofw_bus_get_node(dev), "used-by-rtas") < 0) in rtaspci_probe()
116 if (type == NULL || strcmp(type, "pci") != 0) in rtaspci_probe()
139 sc->sc_extended_config = 0; in rtaspci_attach()
151 uint32_t retval = 0xffffffff; in rtaspci_read_config()
157 config_addr = ((bus & 0xff) << 16) | ((slot & 0x1f) << 11) | in rtaspci_read_config()
158 ((func & 0x7) << 8) | (reg & 0xff); in rtaspci_read_config()
160 config_addr |= (reg & 0xf00) << 16; in rtaspci_read_config()
180 if (error < 0 || pcierror != 0) in rtaspci_read_config()
181 retval = 0xffffffff; in rtaspci_read_config()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dnxp,lpc3220-usb-clk.txt15 ranges = <0x0 0x31020000 0x00001000>;
19 reg = <0xf00 0x100>;
H A Dnxp,lpc3220-usb-clk.yaml33 reg = <0xf00 0x100>;
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dmtk-btcvsd-snd.txt19 reg=<0 0x18000000 0 0x1000>,
20 <0 0x18080000 0 0x8000>;
23 mediatek,offset = <0xf00 0x800 0xfd0 0xfd4 0xfd8>;
/freebsd/sys/contrib/device-tree/Bindings/soc/bcm/
H A Dbrcm,bcm2711-avs-monitor.yaml37 reg = <0x7d5d2000 0xf00>;
41 #thermal-sensor-cells = <0>;
/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dbrcm,avs-ro-thermal.yaml29 const: 0
41 reg = <0x7d5d2000 0xf00>;
45 #thermal-sensor-cells = <0>;
/freebsd/sys/contrib/device-tree/Bindings/ata/
H A Data-generic.yaml42 default: 0
54 reg = <0x1a000 0x100>,
55 <0x1a100 0xf00>;
/freebsd/sys/dev/bhnd/bcma/
H A Dbcma_dmp.h47 (((_value) & _flag) != 0)
54 #define BCMA_OOB_BUSCONFIG 0x020
55 #define BCMA_OOB_STATUSA 0x100
56 #define BCMA_OOB_STATUSB 0x104
57 #define BCMA_OOB_STATUSC 0x108
58 #define BCMA_OOB_STATUSD 0x10c
59 #define BCMA_OOB_ENABLEA0 0x200
60 #define BCMA_OOB_ENABLEA1 0x204
61 #define BCMA_OOB_ENABLEA2 0x208
62 #define BCMA_OOB_ENABLEA3 0x20c
[all …]
H A Dbcma_eromreg.h29 #define BCMA_EROM_TABLE_START 0x000 /**< device enumeration table offset */
30 #define BCMA_EROM_REMAPCONTROL 0xe00
31 #define BCMA_EROM_REMAPSELECT 0xe04
32 #define BCMA_EROM_MASTERSELECT 0xe10
33 #define BCMA_EROM_ITCR 0xf00
34 #define BCMA_EROM_ITIP 0xf04
64 #define BCMA_EROM_TABLE_EOF 0xF /* end of EROM table */
66 #define BCMA_EROM_ENTRY_ISVALID_MASK 0x1 /* is entry valid? */
67 #define BCMA_EROM_ENTRY_ISVALID_SHIFT 0
70 #define BCMA_EROM_ENTRY_TYPE_MASK 0x6 /* entry type mask */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dbrcm,bcm2835-dma.txt7 The channels 0,2 and 3 have special functionality
29 reg = <0x7e007000 0xf00>;
66 brcm,dma-channel-mask = <0x7f35>;
77 reg = < 0x7e203000 0x24>;
/freebsd/sys/x86/x86/
H A Didentcpu.c75 #define IDENTBLUE_CYRIX486 0
114 /* leaf 7 %ecx = 0 */
134 &via_feature_rng, 0,
137 &via_feature_xcrypt, 0,
154 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) in sysctl_hw_machine()
163 CTLFLAG_CAPRD | CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
171 cpu_model, 0, "Machine model");
175 &hw_clockrate, 0, "CPU instruction clock rate");
181 0, "Hypervisor vendor");
242 #if 0
[all …]
/freebsd/sys/dev/bhnd/siba/
H A Dsibareg.h47 #define SIBA_ENUM_SIZE 0x00100000 /**< size of the enumeration space */
64 * [0x0000-0x0dff] core registers
65 * [0x0e00-0x0eff] SIBA_R1 registers (sonics >= 2.3)
66 * [0x0f00-0x0fff] SIBA_R0 registers
69 #define SIBA_CFG0_OFFSET 0xf00 /**< first configuration block */
70 #define SIBA_CFG1_OFFSET 0xe00 /**< second configuration block (sonics >= 2.3) */
71 #define SIBA_CFG_SIZE 0x100 /**< cfg register block size */
83 #define SIBA_CFG0_IPSFLAG 0x08 /**< initiator port ocp slave flag */
84 #define SIBA_CFG0_TPSFLAG 0x18 /**< target port ocp slave flag */
85 #define SIBA_CFG0_TMERRLOGA 0x48 /**< sonics >= 2.3 */
[all …]
/freebsd/contrib/processor-trace/libipt/internal/include/
H A Dpt_opcodes.h35 pt_opc_pad = 0x00,
36 pt_opc_ext = 0x02,
38 pt_opc_tip = 0x0d,
39 pt_opc_tnt_8 = 0x00,
40 pt_opc_tip_pge = 0x11,
41 pt_opc_tip_pgd = 0x01,
42 pt_opc_fup = 0x1d,
43 pt_opc_mode = 0x99,
44 pt_opc_tsc = 0x19,
45 pt_opc_mtc = 0x59,
[all …]
/freebsd/sys/arm64/coresight/
H A Dcoresight_funnel.h35 #define FUNNEL_FUNCTL 0x000 /* Funnel Control Register */
37 #define FUNCTL_HOLDTIME_MASK (0xf << FUNCTL_HOLDTIME_SHIFT)
38 #define FUNNEL_PRICTL 0x004 /* Priority Control Register */
39 #define FUNNEL_ITATBDATA0 0xEEC /* Integration Register, ITATBDATA0 */
40 #define FUNNEL_ITATBCTR2 0xEF0 /* Integration Register, ITATBCTR2 */
41 #define FUNNEL_ITATBCTR1 0xEF4 /* Integration Register, ITATBCTR1 */
42 #define FUNNEL_ITATBCTR0 0xEF8 /* Integration Register, ITATBCTR0 */
43 #define FUNNEL_IMCR 0xF00 /* Integration Mode Control Register */
44 #define FUNNEL_CTSR 0xFA0 /* Claim Tag Set Register */
45 #define FUNNEL_CTCR 0xFA4 /* Claim Tag Clear Register */
[all …]
H A Dcoresight.h49 #define CORESIGHT_ITCTRL 0xf00
50 #define CORESIGHT_CLAIMSET 0xfa0
51 #define CORESIGHT_CLAIMCLR 0xfa4
52 #define CORESIGHT_LAR 0xfb0
53 #define CORESIGHT_UNLOCK 0xc5acce55
54 #define CORESIGHT_LSR 0xfb4
55 #define CORESIGHT_AUTHSTATUS 0xfb8
56 #define CORESIGHT_DEVID 0xfc8
57 #define CORESIGHT_DEVTYPE 0xfcc
127 #define ETR_FLAG_ALLOCATE (1 << 0)
/freebsd/sys/contrib/device-tree/src/arm/socionext/
H A Dmilbeaut-m10v.dtsi15 #size-cells = <0>;
20 reg = <0xf00>;
25 reg = <0xf01>;
30 reg = <0xf02>;
35 reg = <0xf03>;
64 reg = <0x1d001000 0x1000>,
65 <0x1d002000 0x1000>; /* CPU I/f base and size */
71 reg = <0x1d021000 0x1000>;
77 reg = <0x1e000050 0x20>;
78 interrupts = <0 91 4>;
[all …]
/freebsd/sys/x86/cpufreq/
H A Dpowernow.c54 #define PN7_TYPE 0
58 #define A0_ERRATA 0x1 /* Bugs for the rev. A0 of Athlon (K7):
61 #define PENDING_STUCK 0x2 /* With some buggy chipset and some newer AMD64
67 #define PSB_START 0
68 #define PSB_STEP 0x10
71 #define PSB_OFF 0
93 #define MSR_AMDK7_FIDVID_CTL 0xc0010041
94 #define MSR_AMDK7_FIDVID_STATUS 0xc0010042
98 #define PN7_CTR_FID(x) ((x) & 0x1f)
99 #define PN7_CTR_VID(x) (((x) & 0x1f) << 8)
[all …]
/freebsd/sys/dev/agp/
H A Dagp_via.c48 #define REG_GARTCTRL 0
71 if (agp_find_caps(dev) == 0) in agp_via_match()
75 case 0x01981106: in agp_via_match()
77 case 0x02591106: in agp_via_match()
79 case 0x02691106: in agp_via_match()
81 case 0x02961106: in agp_via_match()
83 case 0x03051106: in agp_via_match()
85 case 0x03141106: in agp_via_match()
87 case 0x03241106: in agp_via_match()
89 case 0x03271106: in agp_via_match()
[all …]
/freebsd/sys/dev/quicc/
H A Dquicc_core.c82 if (sipnr & 0x00f00000) in quicc_bfe_intr()
136 sc->sc_irid = 0; in quicc_bfe_attach()
182 resource_list_add(&qd->qd_rlist, sc->sc_rtype, 0, start, in quicc_bfe_attach()
185 resource_list_add(&qd->qd_rlist, SYS_RES_IRQ, 0, 0xf00, 0xf00, 1); in quicc_bfe_attach()
186 rle = resource_list_find(&qd->qd_rlist, SYS_RES_IRQ, 0); in quicc_bfe_attach()
194 quicc_write4(sc->sc_rres, QUICC_REG_SIMR_L, 0x00f0000 in quicc_bfe_attach()
[all...]
/freebsd/contrib/mandoc/
H A Dlibmandoc.h27 #define ROFF_IGN 0x000 /* Don't do anything with it. */
28 #define ROFF_CONT 0x001 /* Give it to the high-level parser. */
29 #define ROFF_RERUN 0x002 /* Re-run the roff parser with an offset. */
30 #define ROFF_REPARSE 0x004 /* Recursively run the main parser on it. */
31 #define ROFF_SO 0x008 /* Include the named file. */
32 #define ROFF_MASK 0x00f /* Only one of these bits should be set. */
35 #define ROFF_APPEND 0x010 /* Append the next line to this one. */
36 #define ROFF_USERCALL 0x020 /* Start execution of a new macro. */
37 #define ROFF_USERRET 0x040 /* Abort execution of the current macro. */
38 #define ROFF_WHILE 0x100 /* Start a new .while loop. */
[all …]
/freebsd/sys/dev/hwpmc/
H A Dhwpmc_amd.h36 #define AMD_PMC_EVSEL_0 0xC0010000
37 #define AMD_PMC_EVSEL_1 0xC0010001
38 #define AMD_PMC_EVSEL_2 0xC0010002
39 #define AMD_PMC_EVSEL_3 0xC0010003
41 #define AMD_PMC_PERFCTR_0 0xC0010004
42 #define AMD_PMC_PERFCTR_1 0xC0010005
43 #define AMD_PMC_PERFCTR_2 0xC0010006
44 #define AMD_PMC_PERFCTR_3 0xC0010007
46 #define AMD_PMC_EVSEL_4 0xC0010208
47 #define AMD_PMC_EVSEL_5 0xC001020A
[all …]
/freebsd/sys/contrib/device-tree/Bindings/
H A Dchosen.txt22 kaslr-seed = <0xfeedbeef 0xc0def00d>;
45 reg = <0xf00 0x10>;
94 linux,usable-memory-range = <0x9 0xf0000000 0x0 0x10000000>;
116 linux,elfcorehdr = <0x9 0xfffff000 0x0 0x800>;
134 linux,initrd-start = <0x82000000>;
135 linux,initrd-end = <0x82800000>;
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm2835-common.dtsi13 reg = <0x7e007000 0xf00>;
49 brcm,dma-channel-mask = <0x7f35>;
54 reg = <0x7e00b200 0x200>;
63 reg = <0x7e100000 0x114>,
64 <0x7e00a000 0x2
[all...]

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