Lines Matching +full:0 +full:xf00

36 #define	AMD_PMC_EVSEL_0		0xC0010000
37 #define	AMD_PMC_EVSEL_1		0xC0010001
38 #define	AMD_PMC_EVSEL_2		0xC0010002
39 #define	AMD_PMC_EVSEL_3		0xC0010003
41 #define	AMD_PMC_PERFCTR_0	0xC0010004
42 #define	AMD_PMC_PERFCTR_1	0xC0010005
43 #define	AMD_PMC_PERFCTR_2	0xC0010006
44 #define	AMD_PMC_PERFCTR_3	0xC0010007
46 #define	AMD_PMC_EVSEL_4		0xC0010208
47 #define	AMD_PMC_EVSEL_5		0xC001020A
49 #define	AMD_PMC_PERFCTR_4	0xC0010209
50 #define	AMD_PMC_PERFCTR_5	0xC001020B
52 #define	AMD_PMC_EVSEL_EP_L3_0	0xC0010230
53 #define	AMD_PMC_EVSEL_EP_L3_1	0xC0010232
54 #define	AMD_PMC_EVSEL_EP_L3_2	0xC0010234
55 #define	AMD_PMC_EVSEL_EP_L3_3	0xC0010236
56 #define	AMD_PMC_EVSEL_EP_L3_4	0xC0010238
57 #define	AMD_PMC_EVSEL_EP_L3_5	0xC001023A
59 #define	AMD_PMC_PERFCTR_EP_L3_0	0xC0010231
60 #define	AMD_PMC_PERFCTR_EP_L3_1	0xC0010233
61 #define	AMD_PMC_PERFCTR_EP_L3_2	0xC0010235
62 #define	AMD_PMC_PERFCTR_EP_L3_3	0xC0010237
63 #define	AMD_PMC_PERFCTR_EP_L3_4	0xC0010239
64 #define	AMD_PMC_PERFCTR_EP_L3_5	0xC001023B
66 #define	AMD_PMC_EVSEL_EP_DF_0	0xC0010240
67 #define	AMD_PMC_EVSEL_EP_DF_1	0xC0010242
68 #define	AMD_PMC_EVSEL_EP_DF_2	0xC0010244
69 #define	AMD_PMC_EVSEL_EP_DF_3	0xC0010246
71 #define	AMD_PMC_PERFCTR_EP_DF_0	0xC0010241
72 #define	AMD_PMC_PERFCTR_EP_DF_1	0xC0010243
73 #define	AMD_PMC_PERFCTR_EP_DF_2	0xC0010245
74 #define	AMD_PMC_PERFCTR_EP_DF_3	0xC0010247
80 #define	AMD_PMC_COUNTERMASK	0xFF000000
89 #define	AMD_PMC_L3SLICEMASK	(0x000F000000000000)
90 #define	AMD_PMC_L3COREMASK	(0xFF00000000000000)
94 #define	AMD_PMC_UNITMASK_M	0x10
95 #define	AMD_PMC_UNITMASK_O	0x08
96 #define	AMD_PMC_UNITMASK_E	0x04
97 #define	AMD_PMC_UNITMASK_S	0x02
98 #define	AMD_PMC_UNITMASK_I	0x01
99 #define	AMD_PMC_UNITMASK_MOESI	0x1F
101 #define	AMD_PMC_UNITMASK	0xFF00
102 #define	AMD_PMC_EVENTMASK 	0xF000000FF
105 #define	AMD_PMC_TO_EVENTMASK(x)	(((x) & 0xFF) | (((uint64_t)(x) & 0xF00) << 24))
106 #define	AMD_PMC_TO_EVENTMASK_DF(x)	(((x) & 0xFF) | (((uint64_t)(x) & 0x0F00) << 24)) | (((uint64_t)…
115 #define AMD_PMC_IS_STOPPED(evsel) ((rdmsr((evsel)) & AMD_PMC_ENABLE) == 0)
116 #define AMD_PMC_HAS_OVERFLOWED(pmc) ((rdpmc(pmc) & (1ULL << 47)) == 0)