54 #define PN7_TYPE	0
58 #define A0_ERRATA	0x1	/* Bugs for the rev. A0 of Athlon (K7):
61 #define PENDING_STUCK	0x2	/* With some buggy chipset and some newer AMD64
67 #define PSB_START	0
68 #define PSB_STEP	0x10
71 #define PSB_OFF		0
93 #define MSR_AMDK7_FIDVID_CTL		0xc0010041
94 #define MSR_AMDK7_FIDVID_STATUS		0xc0010042
98 #define PN7_CTR_FID(x)			((x) & 0x1f)
99 #define PN7_CTR_VID(x)			(((x) & 0x1f) << 8)
100 #define PN7_CTR_FIDC			0x00010000
101 #define PN7_CTR_VIDC			0x00020000
102 #define PN7_CTR_FIDCHRATIO		0x00100000
103 #define PN7_CTR_SGTC(x)			(((uint64_t)(x) & 0x000fffff) << 32)
105 #define PN7_STA_CFID(x)			((x) & 0x1f)
106 #define PN7_STA_SFID(x)			(((x) >> 8) & 0x1f)
107 #define PN7_STA_MFID(x)			(((x) >> 16) & 0x1f)
108 #define PN7_STA_CVID(x)			(((x) >> 32) & 0x1f)
109 #define PN7_STA_SVID(x)			(((x) >> 40) & 0x1f)
110 #define PN7_STA_MVID(x)			(((x) >> 48) & 0x1f)
113 #define ACPI_PN7_CTRL_TO_FID(x)		((x) & 0x1f)
114 #define ACPI_PN7_CTRL_TO_VID(x)		(((x) >> 5) & 0x1f)
115 #define ACPI_PN7_CTRL_TO_SGTC(x)	(((x) >> 10) & 0xffff)
119 #define PN8_CTR_FID(x)			((x) & 0x3f)
120 #define PN8_CTR_VID(x)			(((x) & 0x1f) << 8)
123 #define PN8_STA_CFID(x)			((x) & 0x3f)
124 #define PN8_STA_SFID(x)			(((x) >> 8) & 0x3f)
125 #define PN8_STA_MFID(x)			(((x) >> 16) & 0x3f)
126 #define PN8_STA_PENDING(x)		(((x) >> 31) & 0x01)
127 #define PN8_STA_CVID(x)			(((x) >> 32) & 0x1f)
128 #define PN8_STA_SVID(x)			(((x) >> 40) & 0x1f)
129 #define PN8_STA_MVID(x)			(((x) >> 48) & 0x1f)
132 #define PN8_PSB_TO_RVO(x)		((x) & 0x03)
133 #define PN8_PSB_TO_IRT(x)		(((x) >> 2) & 0x03)
134 #define PN8_PSB_TO_MVS(x)		(((x) >> 4) & 0x03)
135 #define PN8_PSB_TO_BATT(x)		(((x) >> 6) & 0x03)
138 #define ACPI_PN8_CTRL_TO_FID(x)		((x) & 0x3f)
139 #define ACPI_PN8_CTRL_TO_VID(x)		(((x) >> 6) & 0x1f)
140 #define ACPI_PN8_CTRL_TO_VST(x)		(((x) >> 11) & 0x1f)
141 #define ACPI_PN8_CTRL_TO_MVS(x)		(((x) >> 18) & 0x03)
142 #define ACPI_PN8_CTRL_TO_PLL(x)		(((x) >> 20) & 0x7f)
143 #define ACPI_PN8_CTRL_TO_RVO(x)		(((x) >> 28) & 0x03)
144 #define ACPI_PN8_CTRL_TO_IRT(x)		(((x) >> 30) & 0x03)
165 	150, 225, 160, 165, 170, 180, 0, 0,
185 	1600, 1550, 1500, 1450, 1400, 1350, 1300, 0,
187 	1075, 1050, 1025, 1000, 975, 950, 925, 0,
192 	1600, 1550, 1500, 1450, 1400, 1350, 1300, 0,
194 	1075, 1050, 1025, 1000, 975, 950, 925, 0,
201 	950, 925, 900, 875, 850, 825, 800, 0,
235 #define PX_SPEC_CONTROL		0
260 	{0, 0}
269 DRIVER_MODULE(powernow, cpu, pn_driver, 0, 0);
283 		return (0);  in pn7_setfidvid()
307 	return (0);  in pn7_setfidvid()
319 	return (i == 0 ? ENXIO : 0);  in pn8_read_pending_wait()
331 	return (i == 0 ? ENXIO : 0);  in pn8_write_fidvid()
351 		return (0);  in pn8_setfidvid()
359 		rv = pn8_write_fidvid(cfid, (val > 0) ? val : 0, 1ULL, &status);  in pn8_setfidvid()
369 	for (rvo = sc->rvo; rvo > 0 && cvid > 0; --rvo) {  in pn8_setfidvid()
451 	for (i = 0; i < sc->powernow_max_states; ++i)  in pn_set()
476 	u_int cfid = 0, cvid = 0;  in pn_get()
498 	for (i = 0; i < sc->powernow_max_states; ++i)  in pn_get()
514 	return (0);  in pn_get()
528 	for (i = 0; i < sc->powernow_max_states; ++i) {  in pn_settings()
537 	return (0);  in pn_settings()
548 	return (0);  in pn_type()
561 	for (i = 0; i < POWERNOW_MAX_STATES; ++i)  in decode_pst()
564 	for (n = 0, i = 0; i < npstates; ++i) {  in decode_pst()
582 		while (j > 0 && sc->powernow_states[j - 1].freq < state.freq) {  in decode_pst()
600 		for (i = 0; i < sc->powernow_max_states; ++i) {  in decode_pst()
611 	return (0);  in decode_pst()
619 	case 0x760:  in cpuid_is_k7()
620 	case 0x761:  in cpuid_is_k7()
621 	case 0x762:  in cpuid_is_k7()
622 	case 0x770:  in cpuid_is_k7()
623 	case 0x771:  in cpuid_is_k7()
624 	case 0x780:  in cpuid_is_k7()
625 	case 0x781:  in cpuid_is_k7()
626 	case 0x7a0:  in cpuid_is_k7()
646 	do_cpuid(0x80000001, regs);  in pn_decode_pst()
647 	cpuid = regs[0];  in pn_decode_pst()
649 	if ((cpuid & 0xfff) == 0x760)  in pn_decode_pst()
672 		device_printf(dev, "STATUS: 0x%jx\n", status);  in pn_decode_pst()
673 		device_printf(dev, "STATUS: maxfid: 0x%02x\n", maxfid);  in pn_decode_pst()
674 		device_printf(dev, "STATUS: %s: 0x%02x\n",  in pn_decode_pst()
688 		case 0x14:  in pn_decode_pst()
713 		case 0x12:  in pn_decode_pst()
778 	if (rv || (type & CPUFREQ_FLAG_INFO_ONLY) == 0)  in pn_decode_acpi()
783 	do_cpuid(0x80000001, regs);  in pn_decode_acpi()
784 	cpuid = regs[0];  in pn_decode_acpi()
785 	if ((cpuid & 0xfff) == 0x760)  in pn_decode_acpi()
788 	ctrl = 0;  in pn_decode_acpi()
789 	sc->sgtc = 0;  in pn_decode_acpi()
790 	for (n = 0, i = 0; i < count; ++i) {  in pn_decode_acpi()
809 		while (j > 0 && sc->powernow_states[j - 1].freq < state.freq) {  in pn_decode_acpi()
821 	state = sc->powernow_states[0];  in pn_decode_acpi()
845 		sc->low = 0; /* XXX */  in pn_decode_acpi()
857 	return (0);  in pn_decode_acpi()
864 	if ((amd_pminfo & AMDPM_FID) == 0 || (amd_pminfo & AMDPM_VID) == 0)  in pn_identify()
866 	switch (cpu_id & 0xf00) {  in pn_identify()
867 	case 0x600:  in pn_identify()
868 	case 0xf00:  in pn_identify()
890 	sc->errata = 0;  in pn_probe()
899 	switch (cpu_id & 0xf00) {  in pn_probe()
900 	case 0x600:  in pn_probe()
921 	case 0xf00:  in pn_probe()
938 	return (0);  in pn_probe()
956 	if (rv != 0)  in pn_attach()
959 	return (0);  in pn_attach()