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/freebsd/sys/contrib/dev/iwlwifi/cfg/
H A Ddr.c18 #define IWL_DR_SMEM_OFFSET 0x400000
19 #define IWL_DR_SMEM_LEN 0xD0000
38 .mac_addr_from_csr = 0x30,
39 .min_umac_error_event_table = 0xD0000,
40 .d3_debug_data_base_addr = 0x401000,
53 .gp2_reg_addr = 0xd02c68,
62 .mask = 0xffffffff,
86 .umac_prph_offset = 0x300000,
H A Dsc.c19 #define IWL_SC_NVM_VERSION 0x0a1d
22 #define IWL_SC_SMEM_OFFSET 0x400000
23 #define IWL_SC_SMEM_LEN 0xD0000
43 .mac_addr_from_csr = 0x30,
44 .min_umac_error_event_table = 0xD0000,
45 .d3_debug_data_base_addr = 0x401000,
58 .gp2_reg_addr = 0xd02c68,
67 .mask = 0xffffffff,
91 .umac_prph_offset = 0x300000,
H A Dbz.c19 #define IWL_BZ_SMEM_OFFSET 0x400000
20 #define IWL_BZ_SMEM_LEN 0xD0000
40 .mac_addr_from_csr = 0x30,
41 .min_umac_error_event_table = 0xD0000,
42 .d3_debug_data_base_addr = 0x401000,
55 .gp2_reg_addr = 0xd02c68,
64 .mask = 0xffffffff,
88 .umac_prph_offset = 0x300000,
99 .umac_prph_offset = 0x300000,
H A Dax210.c19 #define IWL_AX210_SMEM_OFFSET 0x400000
20 #define IWL_AX210_SMEM_LEN 0xD0000
35 .mac_addr_from_csr = 0x380,
36 .min_umac_error_event_table = 0x400000,
37 .d3_debug_data_base_addr = 0x401000,
50 .gp2_reg_addr = 0xd02c68,
59 .mask = 0xffffffff,
75 .umac_prph_offset = 0x300000,
85 .umac_prph_offset = 0x300000,
97 .umac_prph_offset = 0x300000,
[all …]
H A D22000.c19 #define IWL_22000_SMEM_OFFSET 0x400000
20 #define IWL_22000_SMEM_LEN 0xD0000
40 .mac_addr_from_csr = 0x380,
41 .min_umac_error_event_table = 0x400000,
42 .d3_debug_data_base_addr = 0x401000,
54 .gp2_reg_addr = 0xa02c68,
58 .mask = 0xffffffff,
62 .mask = 0xffffffff,
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Dkirkwood-t5325.dts23 reg = <0x00000000 0x20000000>;
33 pinctrl-0 = <&pmx_i2s &pmx_sysrst>;
76 flash@0 {
81 reg = <0>;
82 mode = <0>;
84 partition@0 {
85 reg = <0x0 0x80000>;
90 reg = <0x80000 0x40000>;
95 reg = <0xc0000 0x10000>;
100 reg = <0xd0000 0x10000>;
[all …]
H A Darmada-370-xp.dtsi29 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
47 pcie-mem-aperture = <0xf8000000 0x7e00000>;
48 pcie-io-aperture = <0xffe00000 0x100000>;
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
[all …]
H A Darmada-39x.dtsi32 #size-cells = <0>;
35 cpu@0 {
38 reg = <0>;
59 pcie-mem-aperture = <0xe0000000 0x8000000>;
60 pcie-io-aperture = <0xe8000000 0x100000>;
64 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
75 reg = <0x8000 0x1000>;
78 arm,double-linefill-incr = <0>;
79 arm,double-linefill-wrap = <0>;
[all …]
H A Darmada-375.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0>;
75 pcie-mem-aperture = <0xe0000000 0x8000000>;
76 pcie-io-aperture = <0xe8000000 0x100000>;
80 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
85 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
86 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm53340-ubnt-unifi-switch8.dts22 memory@0 {
24 reg = <0x00000000 0x08000000>,
25 <0x68000000 0x08000000>;
35 bspi-sel = <0>;
37 flash: flash@0 {
39 reg = <0>;
46 partition@0 {
48 reg = <0x0 0xc0000>;
53 reg = <0xc0000 0x10000>;
58 reg = <0xd0000 0x10000>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/dove/
H A Dpmu.txt24 - #power-domain-cells: must be 0.
35 reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
43 #power-domain-cells = <0>;
44 marvell,pmu_pwr_mask = <0x00000008>;
45 marvell,pmu_iso_mask = <0x00000001>;
50 #power-domain-cells = <0>;
51 marvell,pmu_pwr_mask = <0x00000004>;
52 marvell,pmu_iso_mask = <0x00000002>;
/freebsd/crypto/heimdal/lib/wind/
H A Dtest-prohibited.c41 0x00A0, 0x3000,
42 0x0080, 0x009F, 0x206A, 0x206F, 0xFEFF,
43 0xFFF9, 0xFFFD, 0xFFFE, 0xFFFF,
44 0x1D173, 0x1D17A,
45 0xE000, 0xF8FF, 0xF0000, 0xFFFFD,
46 0x100000, 0x10FFFD,
47 0xFDD0, 0xFDEF,
48 0xFFFE, 0xFFFF,
49 0x1FFFE, 0x1FFFF,
50 0x2FFFE, 0x2FFFF,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dmarvell,nand-controller.yaml66 minimum: 0
71 - minimum: 0
156 reg = <0xd0000 0x54>;
158 #size-cells = <0>;
160 clocks = <&coredivclk 0>;
162 nand@0 {
163 reg = <0>;
165 nand-rb = <0>;
[all...]
H A Dmarvell-nand.txt15 - #size-cells: shall be set to 0.
38 - reg: shall contain the native Chip Select ids (0-3).
39 - nand-rb: see nand-controller.yaml (0-1).
68 reg = <0xd0000 0x54>;
70 #size-cells = <0>;
72 clocks = <&coredivclk 0>;
74 nand@0 {
75 reg = <0>;
77 nand-rb = <0>;
89 partition@0 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx7-mba7.dtsi27 gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>;
43 button-0 {
86 io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>,
87 <&adc2 0>, <&adc2 1>, <&adc2 2>, <&adc2 3>;
226 pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_ss0>;
227 cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>,
234 pinctrl-0 = <&pinctrl_ecspi2>;
240 pinctrl-0 = <&pinctrl_enet1>;
249 #size-cells = <0>;
251 ethphy1_0: ethernet-phy@0 {
[all …]
H A Dimx6q-ba16.dtsi51 reg = <0x10000000 0x40000000>;
57 pinctrl-0 = <&pinctrl_display>;
58 pwms = <&pwm1 0 5000000 0>;
59 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
86 enable-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
127 pinctrl-0 = <&pinctrl_usbotg_vbus>;
135 pinctrl-0 = <&pinctrl_audmux>;
142 pinctrl-0 = <&pinctrl_ecspi1>;
145 flash: flash@0 {
150 reg = <0>;
[all …]
/freebsd/sys/dev/rtwn/rtl8192e/
H A Dr92e_priv.h34 { 0x011, 0xeb }, { 0x012, 0x07 }, { 0x014, 0x75 }, { 0x303, 0xa7 },
35 { 0x428, 0x0a }, { 0x429, 0x10 }, { 0x430, 0x00 }, { 0x431, 0x00 },
36 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 },
37 { 0x436, 0x07 }, { 0x437, 0x08 }, { 0x43c, 0x04 }, { 0x43d, 0x05 },
38 { 0x43e, 0x07 }, { 0x43f, 0x08 }, { 0x440, 0x5d }, { 0x441, 0x01 },
39 { 0x442, 0x00 }, { 0x444, 0x10 }, { 0x445, 0x00 }, { 0x446, 0x00 },
40 { 0x447, 0x00 }, { 0x448, 0x00 }, { 0x449, 0xf0 }, { 0x44a, 0x0f },
41 { 0x44b, 0x3e }, { 0x44c, 0x10 }, { 0x44d, 0x00 }, { 0x44e, 0x00 },
42 { 0x44f, 0x00 }, { 0x450, 0x00 }, { 0x451, 0xf0 }, { 0x452, 0x0f },
43 { 0x453, 0x00 }, { 0x456, 0x5e }, { 0x460, 0x66 }, { 0x461, 0x66 },
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7996/
H A Dmmio.c24 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } },
25 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } },
26 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } },
27 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } },
28 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } },
29 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } },
30 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } },
31 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } },
32 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } },
33 [WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } },
[all …]
/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun5i.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
97 #clock-cells = <0>;
104 #clock-cells = <0>;
119 size = <0x6000000>;
120 alloc-ranges = <0x40000000 0x10000000>;
135 reg = <0x01c00000 0x30>;
140 sram_a: sram@0 {
142 reg = <0x00000000 0xc000>;
[all …]
H A Dsun4i-a10.dtsi111 #size-cells = <0>;
112 cpu0: cpu@0 {
115 reg = <0x0>;
166 #clock-cells = <0>;
173 #clock-cells = <0>;
199 size = <0x6000000>;
200 alloc-ranges = <0x40000000 0x10000000>;
214 reg = <0x01c00000 0x30>;
219 sram_a: sram@0 {
221 reg = <0x00000000 0xc000>;
[all …]
H A Dsun8i-r40.dtsi64 #clock-cells = <0>;
72 #clock-cells = <0>;
82 #size-cells = <0>;
84 cpu0: cpu@0 {
87 reg = <0>;
130 polling-delay-passive = <0>;
131 polling-delay = <0>;
132 thermal-sensors = <&ths 0>;
143 hysteresis = <0>;
161 polling-delay-passive = <0>;
[all...]
H A Dsun7i-a20.dtsi101 #size-cells = <0>;
103 cpu0: cpu@0 {
106 reg = <0>;
181 size = <0x6000000>;
182 alloc-ranges = <0x40000000 0x10000000>;
208 #clock-cells = <0>;
215 #clock-cells = <0>;
231 #clock-cells = <0>;
238 #clock-cells = <0>;
245 #clock-cells = <0>;
[all …]
/freebsd/sys/dev/rtwn/rtl8188e/
H A Dr88e_priv.h39 { 0x026, 0x41 }, { 0x027, 0x35 }, { 0x040, 0x00 }, { 0x428, 0x0a },
40 { 0x429, 0x10 }, { 0x430, 0x00 }, { 0x431, 0x01 }, { 0x432, 0x02 },
41 { 0x433, 0x04 }, { 0x434, 0x05 }, { 0x435, 0x06 }, { 0x436, 0x07 },
42 { 0x437, 0x08 }, { 0x438, 0x00 }, { 0x439, 0x00 }, { 0x43a, 0x01 },
43 { 0x43b, 0x02 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, { 0x43e, 0x06 },
44 { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, { 0x442, 0x00 },
45 { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, { 0x447, 0x00 },
46 { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, { 0x45b, 0xb9 },
47 { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x480, 0x08 }, { 0x4c8, 0xff },
48 { 0x4c9, 0x08 }, { 0x4cc, 0xff }, { 0x4cd, 0xff }, { 0x4ce, 0x01 },
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A Darmada-37xx.dtsi35 reg = <0 0x4000000 0 0x200000>;
40 reg = <0 0x4400000 0 0x1000000>;
47 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0>;
85 /* 32M internal register @ 0xd000_0000 */
86 ranges = <0x0 0x0 0xd0000000 0x2000000>;
90 reg = <0x8300 0x40>;
98 reg = <0xd000 0x1000>;
104 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7921/
H A Dpci.c21 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961),
23 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922),
25 { PCI_DEVICE(PCI_VENDOR_ID_ITTIM, 0x7922),
27 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608),
29 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616),
31 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7920),
74 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ in __mt7921_reg_addr()
75 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ in __mt7921_reg_addr()
76 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ in __mt7921_reg_addr()
77 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ in __mt7921_reg_addr()
[all …]

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