1*c66ec88fSEmmanuel VadotDevice Tree bindings for Marvell PMU 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotRequired properties: 4*c66ec88fSEmmanuel Vadot - compatible: value should be "marvell,dove-pmu". 5*c66ec88fSEmmanuel Vadot May also include "simple-bus" if there are child devices, in which 6*c66ec88fSEmmanuel Vadot case the ranges node is required. 7*c66ec88fSEmmanuel Vadot - reg: two base addresses and sizes of the PM controller and PMU. 8*c66ec88fSEmmanuel Vadot - interrupts: single interrupt number for the PMU interrupt 9*c66ec88fSEmmanuel Vadot - interrupt-controller: must be specified as the PMU itself is an 10*c66ec88fSEmmanuel Vadot interrupt controller. 11*c66ec88fSEmmanuel Vadot - #interrupt-cells: must be 1. 12*c66ec88fSEmmanuel Vadot - #reset-cells: must be 1. 13*c66ec88fSEmmanuel Vadot - domains: sub-node containing domain descriptions 14*c66ec88fSEmmanuel Vadot 15*c66ec88fSEmmanuel VadotOptional properties: 16*c66ec88fSEmmanuel Vadot - ranges: defines the address mapping for child devices, as per the 17*c66ec88fSEmmanuel Vadot standard property of this name. Required when compatible includes 18*c66ec88fSEmmanuel Vadot "simple-bus". 19*c66ec88fSEmmanuel Vadot 20*c66ec88fSEmmanuel VadotPower domain descriptions are listed as child nodes of the "domains" 21*c66ec88fSEmmanuel Vadotsub-node. Each domain has the following properties: 22*c66ec88fSEmmanuel Vadot 23*c66ec88fSEmmanuel VadotRequired properties: 24*c66ec88fSEmmanuel Vadot - #power-domain-cells: must be 0. 25*c66ec88fSEmmanuel Vadot 26*c66ec88fSEmmanuel VadotOptional properties: 27*c66ec88fSEmmanuel Vadot - marvell,pmu_pwr_mask: specifies the mask value for PMU power register 28*c66ec88fSEmmanuel Vadot - marvell,pmu_iso_mask: specifies the mask value for PMU isolation register 29*c66ec88fSEmmanuel Vadot - resets: points to the reset manager (PMU node) and reset index. 30*c66ec88fSEmmanuel Vadot 31*c66ec88fSEmmanuel VadotExample: 32*c66ec88fSEmmanuel Vadot 33*c66ec88fSEmmanuel Vadot pmu: power-management@d0000 { 34*c66ec88fSEmmanuel Vadot compatible = "marvell,dove-pmu"; 35*c66ec88fSEmmanuel Vadot reg = <0xd0000 0x8000>, <0xd8000 0x8000>; 36*c66ec88fSEmmanuel Vadot interrupts = <33>; 37*c66ec88fSEmmanuel Vadot interrupt-controller; 38*c66ec88fSEmmanuel Vadot #interrupt-cells = <1>; 39*c66ec88fSEmmanuel Vadot #reset-cells = <1>; 40*c66ec88fSEmmanuel Vadot 41*c66ec88fSEmmanuel Vadot domains { 42*c66ec88fSEmmanuel Vadot vpu_domain: vpu-domain { 43*c66ec88fSEmmanuel Vadot #power-domain-cells = <0>; 44*c66ec88fSEmmanuel Vadot marvell,pmu_pwr_mask = <0x00000008>; 45*c66ec88fSEmmanuel Vadot marvell,pmu_iso_mask = <0x00000001>; 46*c66ec88fSEmmanuel Vadot resets = <&pmu 16>; 47*c66ec88fSEmmanuel Vadot }; 48*c66ec88fSEmmanuel Vadot 49*c66ec88fSEmmanuel Vadot gpu_domain: gpu-domain { 50*c66ec88fSEmmanuel Vadot #power-domain-cells = <0>; 51*c66ec88fSEmmanuel Vadot marvell,pmu_pwr_mask = <0x00000004>; 52*c66ec88fSEmmanuel Vadot marvell,pmu_iso_mask = <0x00000002>; 53*c66ec88fSEmmanuel Vadot resets = <&pmu 18>; 54*c66ec88fSEmmanuel Vadot }; 55*c66ec88fSEmmanuel Vadot }; 56*c66ec88fSEmmanuel Vadot }; 57