| /linux/drivers/media/dvb-frontends/ |
| H A D | af9013_priv.h | 39 { 28800000, 8000000, { 0x02, 0x8a, 0x28, 0xa3, 0x05, 0x14,
40 0x51, 0x11, 0x00, 0xa2, 0x8f, 0x3d, 0x00, 0xa2, 0x8a,
41 0x29, 0x00, 0xa2, 0x85, 0x14, 0x01, 0x45, 0x14, 0x14 } },
42 { 28800000, 7000000, { 0x02, 0x38, 0xe3, 0x8e, 0x04, 0x71,
43 0xc7, 0x07, 0x00, 0x8e, 0x3d, 0x55, 0x00, 0x8e, 0x38,
44 0xe4, 0x00, 0x8e, 0x34, 0x72, 0x01, 0x1c, 0x71, 0x32 } },
45 { 28800000, 6000000, { 0x01, 0xe7, 0x9e, 0x7a, 0x03, 0xcf,
46 0x3c, 0x3d, 0x00, 0x79, 0xeb, 0x6e, 0x00, 0x79, 0xe7,
47 0x9e, 0x00, 0x79, 0xe3, 0xcf, 0x00, 0xf3, 0xcf, 0x0f } },
49 { 20480000, 8000000, { 0x03, 0x92, 0x49, 0x26, 0x07, 0x24,
[all …]
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| /linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/ |
| H A D | gaudi2_blocks_linux_driver.h | 16 #define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull
17 #define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
18 #define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000
19 #define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull
20 #define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000
21 #define DCORE0_TPC0_EML_SPMU_SECTION 0x1000
22 #define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull
23 #define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000
24 #define DCORE0_TPC0_EML_ETF_SECTION 0x1000
25 #define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull
[all …]
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| /linux/arch/powerpc/boot/dts/ |
| H A D | media5200.dts | 28 PowerPC,5200@0 {
35 memory@0 {
36 reg = <0x00000000 0x08000000>; // 128MB RAM
72 phy0: ethernet-phy@0 {
73 reg = <0>;
78 reg = <0x1000 0x100>;
83 interrupt-map-mask = <0xf800 0 0 7>;
84 interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
85 0xc000 0 0 2 &media5200_fpga 0 3
86 0xc000 0 0 3 &media5200_fpga 0 4
[all …]
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| /linux/Documentation/devicetree/bindings/watchdog/ |
| H A D | armada-37xx-wdt.txt | 15 reg = <0xd000 0x1000>;
20 reg = <0x8300 0x40>;
|
| /linux/arch/powerpc/include/asm/ |
| H A D | io-workarounds.h | 30 #define SPIDER_PCI_REG_BASE 0xd000
31 #define SPIDER_PCI_REG_SIZE 0x1000
32 #define SPIDER_PCI_VCI_CNTL_STAT 0x0110
33 #define SPIDER_PCI_DUMMY_READ 0x0810
34 #define SPIDER_PCI_DUMMY_READ_BASE 0x0814
|
| /linux/drivers/net/ethernet/netronome/nfp/nfpcore/ |
| H A D | nfp_dev.c | 13 .qc_idx_mask = GENMASK(8, 0),
14 .qc_addr_offset = 0x400000,
19 .pcie_cfg_expbar_offset = 0x0a00,
20 .pcie_expl_offset = 0xd000,
21 .qc_area_sz = 0x100000,
25 .qc_idx_mask = GENMASK(8, 0),
26 .qc_addr_offset = 0,
32 .qc_idx_mask = GENMASK(7, 0),
33 .qc_addr_offset = 0x80000,
38 .pcie_cfg_expbar_offset = 0x0400,
[all …]
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| /linux/Documentation/devicetree/bindings/media/ |
| H A D | qcom,sm8250-camss.yaml | 113 port@0:
308 reg = <0 0xac6a000 0 0x2000>,
309 <0 0xac6c000 0 0x2000>,
310 <0 0xac6e000 0 0x1000>,
311 <0 0xac70000 0 0x1000>,
312 <0 0xac72000 0 0x1000>,
313 <0 0xac74000 0 0x1000>,
314 <0 0xacb4000 0 0xd000>,
315 <0 0xacc3000 0 0xd000>,
316 <0 0xacd9000 0 0x2200>,
[all …]
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| /linux/drivers/media/platform/mediatek/mdp/ |
| H A D | mtk_mdp_ipi.h | 14 AP_MDP_INIT = 0xd000,
15 AP_MDP_DEINIT = 0xd001,
16 AP_MDP_PROCESS = 0xd002,
18 VPU_MDP_INIT_ACK = 0xe000,
19 VPU_MDP_DEINIT_ACK = 0xe001,
20 VPU_MDP_PROCESS_ACK = 0xe002
104 int32_t orientation; /* 0, 90, 180, 270 */
|
| /linux/Documentation/devicetree/bindings/display/mediatek/ |
| H A D | mediatek,postmask.yaml | 77 reg = <0 0x1400d000 0 0x1000>;
78 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
81 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
|
| H A D | mediatek,padding.yaml | 19 register must be cleared to 0, or undefined behaviors could happen.
78 reg = <0 0x1c11d000 0 0x1000>;
81 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>;
|
| /linux/Documentation/devicetree/bindings/arm/ |
| H A D | syna.txt | 45 reg = <0xf7dd0000 0x10000>;
79 reg = <0xea0000 0x400>;
86 reg = <0xd000 0x100>;
|
| /linux/include/linux/mdio/ |
| H A D | mdio-xgene.h | 15 #define BLOCK_XG_MDIO_CSR_OFFSET 0x5000
16 #define BLOCK_DIAG_CSR_OFFSET 0xd000
17 #define XGENET_CONFIG_REG_ADDR 0x20
19 #define MAC_ADDR_REG_OFFSET 0x00
20 #define MAC_COMMAND_REG_OFFSET 0x04
21 #define MAC_WRITE_REG_OFFSET 0x08
22 #define MAC_READ_REG_OFFSET 0x0c
23 #define MAC_COMMAND_DONE_REG_OFFSET 0x10
25 #define CLKEN_OFFSET 0x08
26 #define SRST_OFFSET 0x00
[all …]
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| /linux/drivers/leds/rgb/ |
| H A D | leds-qcom-lpg.c | 19 #define LPG_SUBTYPE_REG 0x05
20 #define LPG_SUBTYPE_LPG 0x2
21 #define LPG_SUBTYPE_PWM 0xb
22 #define LPG_SUBTYPE_HI_RES_PWM 0xc
23 #define LPG_SUBTYPE_LPG_LITE 0x11
24 #define LPG_PATTERN_CONFIG_REG 0x40
25 #define LPG_SIZE_CLK_REG 0x41
26 #define PWM_CLK_SELECT_MASK GENMASK(1, 0)
27 #define PWM_CLK_SELECT_HI_RES_MASK GENMASK(2, 0)
29 #define LPG_PREDIV_CLK_REG 0x42
[all …]
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| /linux/drivers/staging/media/meson/vdec/ |
| H A D | hevc_regs.h | 9 #define HEVC_ASSIST_MMU_MAP_ADDR 0xc024
11 #define HEVC_ASSIST_MBOX1_CLR_REG 0xc1d4
12 #define HEVC_ASSIST_MBOX1_MASK 0xc1d8
14 #define HEVC_ASSIST_SCRATCH_0 0xc300
15 #define HEVC_ASSIST_SCRATCH_1 0xc304
16 #define HEVC_ASSIST_SCRATCH_2 0xc308
17 #define HEVC_ASSIST_SCRATCH_3 0xc30c
18 #define HEVC_ASSIST_SCRATCH_4 0xc310
19 #define HEVC_ASSIST_SCRATCH_5 0xc314
20 #define HEVC_ASSIST_SCRATCH_6 0xc318
[all …]
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| /linux/arch/powerpc/boot/dts/fsl/ |
| H A D | interlaken-lac-portals.dtsi | 34 #address-cells = <0x1>;
35 #size-cells = <0x1>;
38 lportal0: lac-portal@0 {
39 compatible = "fsl,interlaken-lac-portal-v1.0";
40 reg = <0x0 0x1000>;
44 compatible = "fsl,interlaken-lac-portal-v1.0";
45 reg = <0x1000 0x1000>;
49 compatible = "fsl,interlaken-lac-portal-v1.0";
50 reg = <0x2000 0x1000>;
54 compatible = "fsl,interlaken-lac-portal-v1.0";
[all …]
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| /linux/arch/loongarch/include/asm/ |
| H A D | cpu.h | 18 * 31 24 23 16 15 12 11 0
25 #define PRID_COMP_MASK 0xff0000
27 #define PRID_COMP_LOONGSON 0x140000
35 #define PRID_SERIES_MASK 0xf000
37 #define PRID_SERIES_LA132 0x8000 /* Loongson 32bit */
38 #define PRID_SERIES_LA264 0xa000 /* Loongson 64bit, 2-issue */
39 #define PRID_SERIES_LA364 0xb000 /* Loongson 64bit, 3-issue */
40 #define PRID_SERIES_LA464 0xc000 /* Loongson 64bit, 4-issue */
41 #define PRID_SERIES_LA664 0xd000 /* Loongson 64bit, 6-issue */
44 * Particular Product ID values for bits 11:0 of the PRID register.
[all …]
|
| /linux/drivers/media/platform/mediatek/vcodec/encoder/ |
| H A D | venc_ipi_msg.h | 12 #define AP_IPIMSG_VENC_BASE 0xC000
13 #define VPU_IPIMSG_VENC_BASE 0xD000
|
| /linux/arch/arm/boot/dts/broadcom/ |
| H A D | bcm53573.dtsi | 26 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x0>;
37 ranges = <0x00000000 0x18310000 0x00008000>;
44 #address-cells = <0>;
46 reg = <0x1000 0x1000>,
47 <0x2000 0x0100>;
65 #clock-cells = <0>;
73 reg = <0x18000000 0x1000>;
74 ranges = <0x00000000 0x18000000 0x00100000>;
[all …]
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| /linux/drivers/net/ethernet/broadcom/asp2/ |
| H A D | bcmasp_intf_defs.h | 6 ((((intf)->port) * 0x800) + 0xc000)
7 #define UMC_CMD 0x008
8 #define UMC_CMD_TX_EN BIT(0)
10 #define UMC_CMD_SPEED_SHIFT 0x2
11 #define UMC_CMD_SPEED_MASK 0x3
12 #define UMC_CMD_SPEED_10 0x0
13 #define UMC_CMD_SPEED_100 0x1
14 #define UMC_CMD_SPEED_1000 0x2
15 #define UMC_CMD_SPEED_2500 0x3
33 #define UMC_MAC0 0x0c
[all …]
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| /linux/arch/mips/include/asm/xtalk/ |
| H A D | xwidget.h | 18 #define WIDGET_ID 0x04
19 #define WIDGET_STATUS 0x0c
20 #define WIDGET_ERR_UPPER_ADDR 0x14
21 #define WIDGET_ERR_LOWER_ADDR 0x1c
22 #define WIDGET_CONTROL 0x24
23 #define WIDGET_REQ_TIMEOUT 0x2c
24 #define WIDGET_INTDEST_UPPER_ADDR 0x34
25 #define WIDGET_INTDEST_LOWER_ADDR 0x3c
26 #define WIDGET_ERR_CMD_WORD 0x44
27 #define WIDGET_LLP_CFG 0x4c
[all …]
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| /linux/arch/mips/sgi-ip27/ |
| H A D | ip27-xtalk.c | 22 #define XBOW_WIDGET_PART_NUM 0x0
23 #define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbow in Xbridge */
46 memset(&w1_res, 0, sizeof(w1_res)); in bridge_platform_create()
85 bd->intr_addr = BIT_ULL(47) + 0x01800000 + PI_INT_PEND_MOD; in bridge_platform_create()
143 pr_info("xtalk:n%d/%d unknown widget (0x%x)\n", in probe_one_port()
148 return 0; in probe_one_port()
199 return 0; in xbow_probe()
215 (RAW_NODE_SWIN_BASE(nasid, 0x0) + WIDGET_ID); in xtalk_probe_node()
220 bridge_platform_create(nasid, 0x8, 0xa); in xtalk_probe_node()
224 pr_info("xtalk:n%d/0 xbow widget\n", nasid); in xtalk_probe_node()
[all …]
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| /linux/arch/csky/abiv1/ |
| H A D | alignment.c | 10 static int align_kern_count = 0;
11 static int align_usr_count = 0;
29 * Success: return 0
38 "movi %0, 0\n" in ldb_asm()
43 "movi %0, 1\n" in ldb_asm()
62 * Success: return 0
70 "movi %0, 0\n" in stb_asm()
75 "movi %0, 1\n" in stb_asm()
92 * Success: return 0
108 return 0; in ldh_c()
[all …]
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| /linux/arch/mips/include/asm/txx9/ |
| H A D | tx4927.h | 36 #define TX4927_REG_BASE 0xffffffffff1f0000UL
38 #define TX4927_REG_BASE 0xff1f0000UL
40 #define TX4927_REG_SIZE 0x00010000
42 #define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000)
43 #define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000)
44 #define TX4927_DMA_REG (TX4927_REG_BASE + 0xb000)
45 #define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000)
46 #define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000)
47 #define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600)
49 #define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
[all …]
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| /linux/drivers/ata/ |
| H A D | pata_buddha.c | 35 #define BUDDHA_BASE1 0x800
36 #define BUDDHA_BASE2 0xa00
37 #define BUDDHA_BASE3 0xc00
38 #define XSURF_BASE1 0xb000 /* 2.5" interface */
39 #define XSURF_BASE2 0xd000 /* 3.5" interface */
40 #define BUDDHA_CONTROL 0x11a
41 #define BUDDHA_IRQ 0xf00
42 #define XSURF_IRQ 0x7e
43 #define BUDDHA_IRQ_MR 0xfc0 /* master interrupt enable */
46 BOARD_BUDDHA = 0,
[all …]
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| /linux/drivers/net/wireless/ath/ath9k/ |
| H A D | ar9003_eeprom.h | 22 #define AR9300_EEP_VER 0xD000
23 #define AR9300_EEP_VER_MINOR_MASK 0xFFF
24 #define AR9300_EEP_MINOR_VER_1 0x1
41 #define AR9300_EEPMISC_WOW 0x02
48 #define AR9300_PAPRD_RATE_MASK 0x01ffffff
49 #define AR9300_PAPRD_SCALE_1 0x0e000000
51 #define AR9300_PAPRD_SCALE_2 0x70000000
54 #define AR9300_EEP_ANTDIV_CONTROL_DEFAULT_VALUE 0xc9
63 #define AR9300_PWR_TABLE_OFFSET 0
78 #define AR9300_BASE_ADDR_4K 0xfff
[all …]
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