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/linux/drivers/media/dvb-frontends/
H A Daf9013_priv.h39 { 28800000, 8000000, { 0x02, 0x8a, 0x28, 0xa3, 0x05, 0x14,
40 0x51, 0x11, 0x00, 0xa2, 0x8f, 0x3d, 0x00, 0xa2, 0x8a,
41 0x29, 0x00, 0xa2, 0x85, 0x14, 0x01, 0x45, 0x14, 0x14 } },
42 { 28800000, 7000000, { 0x02, 0x38, 0xe3, 0x8e, 0x04, 0x71,
43 0xc7, 0x07, 0x00, 0x8e, 0x3d, 0x55, 0x00, 0x8e, 0x38,
44 0xe4, 0x00, 0x8e, 0x34, 0x72, 0x01, 0x1c, 0x71, 0x32 } },
45 { 28800000, 6000000, { 0x01, 0xe7, 0x9e, 0x7a, 0x03, 0xcf,
46 0x3c, 0x3d, 0x00, 0x79, 0xeb, 0x6e, 0x00, 0x79, 0xe7,
47 0x9e, 0x00, 0x79, 0xe3, 0xcf, 0x00, 0xf3, 0xcf, 0x0f } },
49 { 20480000, 8000000, { 0x03, 0x92, 0x49, 0x26, 0x07, 0x24,
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dgaudi2_blocks_linux_driver.h16 #define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull
17 #define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
18 #define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000
19 #define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull
20 #define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000
21 #define DCORE0_TPC0_EML_SPMU_SECTION 0x1000
22 #define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull
23 #define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000
24 #define DCORE0_TPC0_EML_ETF_SECTION 0x1000
25 #define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmedia5200.dts28 PowerPC,5200@0 {
35 memory@0 {
36 reg = <0x00000000 0x08000000>; // 128MB RAM
72 phy0: ethernet-phy@0 {
73 reg = <0>;
78 reg = <0x1000 0x100>;
83 interrupt-map-mask = <0xf800 0 0 7>;
84 interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
85 0xc000 0 0 2 &media5200_fpga 0 3
86 0xc000 0 0 3 &media5200_fpga 0 4
[all …]
/linux/drivers/net/ethernet/netronome/nfp/nfpcore/
H A Dnfp_dev.c13 .qc_idx_mask = GENMASK(8, 0),
14 .qc_addr_offset = 0x400000,
19 .pcie_cfg_expbar_offset = 0x0a00,
20 .pcie_expl_offset = 0xd000,
21 .qc_area_sz = 0x100000,
25 .qc_idx_mask = GENMASK(8, 0),
26 .qc_addr_offset = 0,
32 .qc_idx_mask = GENMASK(7, 0),
33 .qc_addr_offset = 0x80000,
38 .pcie_cfg_expbar_offset = 0x0400,
[all …]
/linux/drivers/media/platform/mediatek/mdp/
H A Dmtk_mdp_ipi.h14 AP_MDP_INIT = 0xd000,
15 AP_MDP_DEINIT = 0xd001,
16 AP_MDP_PROCESS = 0xd002,
18 VPU_MDP_INIT_ACK = 0xe000,
19 VPU_MDP_DEINIT_ACK = 0xe001,
20 VPU_MDP_PROCESS_ACK = 0xe002
104 int32_t orientation; /* 0, 90, 180, 270 */
/linux/arch/arm64/boot/dts/xilinx/
H A Dversal-net-vn-x-b2197-01-revA.dts22 memory: memory@0 {
23 reg = <0 0 0 0x80000000>;
28 reg = <8 0 3 0x80000000>;
33 reg = <0x500 0 4 0>;
47 reg = <0 0xbbf14000 0 0x1000>;
51 reg = <0 0xbbf15000 0 0x1000>;
55 reg = <0 0xbbf16000 0 0x1000>;
59 reg = <0 0xbbf17000 0 0xD000>;
62 reserve_others: reserveothers@0 {
63 reg = <0 0x0 0 0x1c200000>;
[all …]
/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,padding.yaml19 register must be cleared to 0, or undefined behaviors could happen.
82 reg = <0 0x1c11d000 0 0x1000>;
85 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>;
/linux/include/linux/mdio/
H A Dmdio-xgene.h15 #define BLOCK_XG_MDIO_CSR_OFFSET 0x5000
16 #define BLOCK_DIAG_CSR_OFFSET 0xd000
17 #define XGENET_CONFIG_REG_ADDR 0x20
19 #define MAC_ADDR_REG_OFFSET 0x00
20 #define MAC_COMMAND_REG_OFFSET 0x04
21 #define MAC_WRITE_REG_OFFSET 0x08
22 #define MAC_READ_REG_OFFSET 0x0c
23 #define MAC_COMMAND_DONE_REG_OFFSET 0x10
25 #define CLKEN_OFFSET 0x08
26 #define SRST_OFFSET 0x00
[all …]
/linux/drivers/staging/media/meson/vdec/
H A Dhevc_regs.h9 #define HEVC_ASSIST_MMU_MAP_ADDR 0xc024
11 #define HEVC_ASSIST_MBOX1_CLR_REG 0xc1d4
12 #define HEVC_ASSIST_MBOX1_MASK 0xc1d8
14 #define HEVC_ASSIST_SCRATCH_0 0xc300
15 #define HEVC_ASSIST_SCRATCH_1 0xc304
16 #define HEVC_ASSIST_SCRATCH_2 0xc308
17 #define HEVC_ASSIST_SCRATCH_3 0xc30c
18 #define HEVC_ASSIST_SCRATCH_4 0xc310
19 #define HEVC_ASSIST_SCRATCH_5 0xc314
20 #define HEVC_ASSIST_SCRATCH_6 0xc318
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dinterlaken-lac-portals.dtsi34 #address-cells = <0x1>;
35 #size-cells = <0x1>;
38 lportal0: lac-portal@0 {
39 compatible = "fsl,interlaken-lac-portal-v1.0";
40 reg = <0x0 0x1000>;
44 compatible = "fsl,interlaken-lac-portal-v1.0";
45 reg = <0x1000 0x1000>;
49 compatible = "fsl,interlaken-lac-portal-v1.0";
50 reg = <0x2000 0x1000>;
54 compatible = "fsl,interlaken-lac-portal-v1.0";
[all …]
/linux/arch/loongarch/include/asm/
H A Dcpu.h18 * 31 24 23 16 15 12 11 0
25 #define PRID_COMP_MASK 0xff0000
27 #define PRID_COMP_LOONGSON 0x140000
35 #define PRID_SERIES_MASK 0xf000
37 #define PRID_SERIES_LA132 0x8000 /* Loongson 32bit */
38 #define PRID_SERIES_LA264 0xa000 /* Loongson 64bit, 2-issue */
39 #define PRID_SERIES_LA364 0xb000 /* Loongson 64bit, 3-issue */
40 #define PRID_SERIES_LA464 0xc000 /* Loongson 64bit, 4-issue */
41 #define PRID_SERIES_LA664 0xd000 /* Loongson 64bit, 6-issue */
44 * Particular Product ID values for bits 11:0 of the PRID register.
[all …]
/linux/drivers/media/platform/mediatek/vcodec/encoder/
H A Dvenc_ipi_msg.h12 #define AP_IPIMSG_VENC_BASE 0xC000
13 #define VPU_IPIMSG_VENC_BASE 0xD000
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm53573.dtsi26 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x0>;
37 ranges = <0x00000000 0x18310000 0x00008000>;
44 #address-cells = <0>;
46 reg = <0x1000 0x1000>,
47 <0x2000 0x0100>;
65 #clock-cells = <0>;
73 reg = <0x18000000 0x1000>;
74 ranges = <0x00000000 0x18000000 0x00100000>;
[all …]
H A Dbcm63138.dtsi23 #size-cells = <0>;
25 cpu@0 {
29 reg = <0>;
46 #clock-cells = <0>;
54 #clock-cells = <0>;
63 #clock-cells = <0>;
72 #clock-cells = <0>;
80 ranges = <0 0x80000000 0x784000>;
86 reg = <0x1d000 0x1000>;
92 interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
[all …]
/linux/arch/mips/include/asm/xtalk/
H A Dxwidget.h18 #define WIDGET_ID 0x04
19 #define WIDGET_STATUS 0x0c
20 #define WIDGET_ERR_UPPER_ADDR 0x14
21 #define WIDGET_ERR_LOWER_ADDR 0x1c
22 #define WIDGET_CONTROL 0x24
23 #define WIDGET_REQ_TIMEOUT 0x2c
24 #define WIDGET_INTDEST_UPPER_ADDR 0x34
25 #define WIDGET_INTDEST_LOWER_ADDR 0x3c
26 #define WIDGET_ERR_CMD_WORD 0x44
27 #define WIDGET_LLP_CFG 0x4c
[all …]
/linux/arch/mips/sgi-ip27/
H A Dip27-xtalk.c22 #define XBOW_WIDGET_PART_NUM 0x0
23 #define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbow in Xbridge */
46 memset(&w1_res, 0, sizeof(w1_res)); in bridge_platform_create()
85 bd->intr_addr = BIT_ULL(47) + 0x01800000 + PI_INT_PEND_MOD; in bridge_platform_create()
143 pr_info("xtalk:n%d/%d unknown widget (0x%x)\n", in probe_one_port()
148 return 0; in probe_one_port()
199 return 0; in xbow_probe()
215 (RAW_NODE_SWIN_BASE(nasid, 0x0) + WIDGET_ID); in xtalk_probe_node()
220 bridge_platform_create(nasid, 0x8, 0xa); in xtalk_probe_node()
224 pr_info("xtalk:n%d/0 xbow widget\n", nasid); in xtalk_probe_node()
[all …]
/linux/arch/csky/abiv1/
H A Dalignment.c10 static int align_kern_count = 0;
11 static int align_usr_count = 0;
29 * Success: return 0
38 "movi %0, 0\n" in ldb_asm()
43 "movi %0, 1\n" in ldb_asm()
62 * Success: return 0
70 "movi %0, 0\n" in stb_asm()
75 "movi %0, 1\n" in stb_asm()
92 * Success: return 0
108 return 0; in ldh_c()
[all …]
/linux/arch/mips/include/asm/txx9/
H A Dtx4927.h36 #define TX4927_REG_BASE 0xffffffffff1f0000UL
38 #define TX4927_REG_BASE 0xff1f0000UL
40 #define TX4927_REG_SIZE 0x00010000
42 #define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000)
43 #define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000)
44 #define TX4927_DMA_REG (TX4927_REG_BASE + 0xb000)
45 #define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000)
46 #define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000)
47 #define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600)
49 #define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
[all …]
H A Dtx4938.h19 #define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */
21 #define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */
23 #define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
26 #define TX4938_NDFMC_REG (TX4938_REG_BASE + 0x5000)
27 #define TX4938_SRAMC_REG (TX4938_REG_BASE + 0x6000)
28 #define TX4938_PCIC1_REG (TX4938_REG_BASE + 0x7000)
29 #define TX4938_SDRAMC_REG (TX4938_REG_BASE + 0x8000)
30 #define TX4938_EBUSC_REG (TX4938_REG_BASE + 0x9000)
31 #define TX4938_DMA_REG(ch) (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)
32 #define TX4938_PCIC_REG (TX4938_REG_BASE + 0xd000)
[all …]
/linux/drivers/ata/
H A Dpata_buddha.c35 #define BUDDHA_BASE1 0x800
36 #define BUDDHA_BASE2 0xa00
37 #define BUDDHA_BASE3 0xc00
38 #define XSURF_BASE1 0xb000 /* 2.5" interface */
39 #define XSURF_BASE2 0xd000 /* 3.5" interface */
40 #define BUDDHA_CONTROL 0x11a
41 #define BUDDHA_IRQ 0xf00
42 #define XSURF_IRQ 0x7e
43 #define BUDDHA_IRQ_MR 0xfc0 /* master interrupt enable */
46 BOARD_BUDDHA = 0,
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_eeprom.h22 #define AR9300_EEP_VER 0xD000
23 #define AR9300_EEP_VER_MINOR_MASK 0xFFF
24 #define AR9300_EEP_MINOR_VER_1 0x1
41 #define AR9300_EEPMISC_WOW 0x02
48 #define AR9300_PAPRD_RATE_MASK 0x01ffffff
49 #define AR9300_PAPRD_SCALE_1 0x0e000000
51 #define AR9300_PAPRD_SCALE_2 0x70000000
54 #define AR9300_EEP_ANTDIV_CONTROL_DEFAULT_VALUE 0xc9
63 #define AR9300_PWR_TABLE_OFFSET 0
78 #define AR9300_BASE_ADDR_4K 0xfff
[all …]
/linux/arch/arm64/boot/dts/synaptics/
H A Dberlin4ct.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0x0>;
41 reg = <0x1>;
50 reg = <0x2>;
59 reg = <0x3>;
73 CPU_SLEEP_0: cpu-sleep-0 {
76 arm,psci-suspend-param = <0x0010000>;
86 #clock-cells = <0>;
114 ranges = <0 0 0xf7000000 0x1000000>;
[all …]
/linux/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_hw.h40 #define CSR_RING_ID 0x0008
44 #define CSR_RING_ID_BUF 0x000c
45 #define CSR_PBM_COAL 0x0014
46 #define CSR_PBM_CTICK0 0x0018
47 #define CSR_PBM_CTICK1 0x001c
48 #define CSR_PBM_CTICK2 0x0020
49 #define CSR_PBM_CTICK3 0x0024
50 #define CSR_THRESHOLD0_SET1 0x0030
51 #define CSR_THRESHOLD1_SET1 0x0034
52 #define CSR_RING_NE_INT_MODE 0x017c
[all …]
/linux/include/media/
H A Ddvb-usb-ids.h23 #define USB_VID_774 0x7a69
24 #define USB_VID_ADSTECH 0x06e1
25 #define USB_VID_AFATECH 0x15a4
26 #define USB_VID_ALCOR_MICRO 0x058f
27 #define USB_VID_ALINK 0x05e3
28 #define USB_VID_AME 0x06be
29 #define USB_VID_AMT 0x1c73
30 #define USB_VID_ANCHOR 0x0547
31 #define USB_VID_ANSONIC 0x10b9
32 #define USB_VID_ANUBIS_ELECTRONIC 0x10fd
[all …]
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dinterlaken-lac.txt31 There is a full register set at 0x0000-0x0FFF (also known as the "hypervisor"
32 version), and a subset at 0x1000-0x1FFF. The former is a superset of the
45 IP Block Revision Register (IPBRR0) at offset 0x0BF8.
51 0x02000100 T4240
78 reg = <0x229000 0x1000>;
84 reg = <0x228000 0x1000>;
136 Register (IPBRR0), at offset 0x0BF8, and Y is the Minor version
161 #address-cells = <0x1>;
162 #size-cells = <0x1>;
164 ranges = <0x0 0xf 0xf4400000 0x20000>;
[all …]

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