Lines Matching +full:0 +full:xd000
26 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x0>;
37 ranges = <0x00000000 0x18310000 0x00008000>;
44 #address-cells = <0>;
46 reg = <0x1000 0x1000>,
47 <0x2000 0x0100>;
65 #clock-cells = <0>;
73 reg = <0x18000000 0x1000>;
74 ranges = <0x00000000 0x18000000 0x00100000>;
79 interrupt-map-mask = <0x000fffff 0xffff>;
82 <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
84 /* IEEE 802.11 0 */
85 <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
87 /* PCIe Controller 0 */
88 <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
89 <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
90 <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
91 <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
92 <0x00002000 4 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
93 <0x00002000 5 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
96 <0x00004000 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
98 /* Ethernet Controller 0 */
99 <0x00005000 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
102 <0x0000a000 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
105 <0x0000b000 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
107 chipcommon: chipcommon@0 {
109 reg = <0x00000000 0x1000>;
120 reg = <0x0300 0x100>;
129 reg = <0x00002000 0x1000>;
136 reg = <0x4000 0x1000>;
143 reg = <0x4000 0x1000>;
148 #size-cells = <0>;
152 #trigger-source-cells = <0>;
157 #trigger-source-cells = <0>;
163 reg = <0xd000 0x1000>;
168 #size-cells = <0>;
172 #trigger-source-cells = <0>;
177 #trigger-source-cells = <0>;
183 reg = <0x5000 0x1000>;
193 #size-cells = <0>;
197 reg = <0x1e>;
203 #size-cells = <0>;
205 port@0 {
206 reg = <0>;
245 reg = <0xb000 0x1000>;
256 reg = <0x00012000 0x00001000>;
261 #clock-cells = <0>;