Lines Matching +full:0 +full:xd000
36 #define TX4927_REG_BASE 0xffffffffff1f0000UL
38 #define TX4927_REG_BASE 0xff1f0000UL
40 #define TX4927_REG_SIZE 0x00010000
42 #define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000)
43 #define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000)
44 #define TX4927_DMA_REG (TX4927_REG_BASE + 0xb000)
45 #define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000)
46 #define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000)
47 #define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600)
49 #define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
51 #define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100)
52 #define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500)
53 #define TX4927_ACLC_REG (TX4927_REG_BASE + 0xf700)
55 #define TX4927_IR_ECCERR 0
107 #define TX4927_CCFG_WDRST 0x0000020000000000ULL
108 #define TX4927_CCFG_WDREXEN 0x0000010000000000ULL
109 #define TX4927_CCFG_BCFG_MASK 0x000000ff00000000ULL
110 #define TX4927_CCFG_TINTDIS 0x01000000
111 #define TX4927_CCFG_PCI66 0x00800000
112 #define TX4927_CCFG_PCIMODE 0x00400000
113 #define TX4927_CCFG_DIVMODE_MASK 0x000e0000
114 #define TX4927_CCFG_DIVMODE_8 (0x0 << 17)
115 #define TX4927_CCFG_DIVMODE_12 (0x1 << 17)
116 #define TX4927_CCFG_DIVMODE_16 (0x2 << 17)
117 #define TX4927_CCFG_DIVMODE_10 (0x3 << 17)
118 #define TX4927_CCFG_DIVMODE_2 (0x4 << 17)
119 #define TX4927_CCFG_DIVMODE_3 (0x5 << 17)
120 #define TX4927_CCFG_DIVMODE_4 (0x6 << 17)
121 #define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
122 #define TX4927_CCFG_BEOW 0x00010000
123 #define TX4927_CCFG_WR 0x00008000
124 #define TX4927_CCFG_TOE 0x00004000
125 #define TX4927_CCFG_PCIARB 0x00002000
126 #define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
127 #define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
128 #define TX4927_CCFG_PCIDIVMODE_3 0x00000800
129 #define TX4927_CCFG_PCIDIVMODE_5 0x00001000
130 #define TX4927_CCFG_PCIDIVMODE_6 0x00001800
131 #define TX4927_CCFG_SYSSP_MASK 0x000000c0
132 #define TX4927_CCFG_ENDIAN 0x00000004
133 #define TX4927_CCFG_HALT 0x00000002
134 #define TX4927_CCFG_ACEHOLD 0x00000001
138 #define TX4927_PCFG_SDCLKDLY_MASK 0x30000000
140 #define TX4927_PCFG_SYSCLKEN 0x08000000
141 #define TX4927_PCFG_SDCLKEN_ALL 0x07800000
142 #define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
143 #define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
144 #define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
145 #define TX4927_PCFG_SEL2 0x00000200
146 #define TX4927_PCFG_SEL1 0x00000100
147 #define TX4927_PCFG_DMASEL_ALL 0x000000ff
148 #define TX4927_PCFG_DMASEL0_MASK 0x00000003
149 #define TX4927_PCFG_DMASEL1_MASK 0x0000000c
150 #define TX4927_PCFG_DMASEL2_MASK 0x00000030
151 #define TX4927_PCFG_DMASEL3_MASK 0x000000c0
152 #define TX4927_PCFG_DMASEL0_DRQ0 0x00000000
153 #define TX4927_PCFG_DMASEL0_SIO1 0x00000001
154 #define TX4927_PCFG_DMASEL0_ACL0 0x00000002
155 #define TX4927_PCFG_DMASEL0_ACL2 0x00000003
156 #define TX4927_PCFG_DMASEL1_DRQ1 0x00000000
157 #define TX4927_PCFG_DMASEL1_SIO1 0x00000004
158 #define TX4927_PCFG_DMASEL1_ACL1 0x00000008
159 #define TX4927_PCFG_DMASEL1_ACL3 0x0000000c
160 #define TX4927_PCFG_DMASEL2_DRQ2 0x00000000 /* SEL2=0 */
161 #define TX4927_PCFG_DMASEL2_SIO0 0x00000010 /* SEL2=0 */
162 #define TX4927_PCFG_DMASEL2_ACL1 0x00000000 /* SEL2=1 */
163 #define TX4927_PCFG_DMASEL2_ACL2 0x00000020 /* SEL2=1 */
164 #define TX4927_PCFG_DMASEL2_ACL0 0x00000030 /* SEL2=1 */
165 #define TX4927_PCFG_DMASEL3_DRQ3 0x00000000
166 #define TX4927_PCFG_DMASEL3_SIO0 0x00000040
167 #define TX4927_PCFG_DMASEL3_ACL3 0x00000080
168 #define TX4927_PCFG_DMASEL3_ACL1 0x000000c0
171 #define TX4927_CLKCTR_ACLCKD 0x02000000
172 #define TX4927_CLKCTR_PIOCKD 0x01000000
173 #define TX4927_CLKCTR_DMACKD 0x00800000
174 #define TX4927_CLKCTR_PCICKD 0x00400000
175 #define TX4927_CLKCTR_TM0CKD 0x00100000
176 #define TX4927_CLKCTR_TM1CKD 0x00080000
177 #define TX4927_CLKCTR_TM2CKD 0x00040000
178 #define TX4927_CLKCTR_SIO0CKD 0x00020000
179 #define TX4927_CLKCTR_SIO1CKD 0x00010000
180 #define TX4927_CLKCTR_ACLRST 0x00000200
181 #define TX4927_CLKCTR_PIORST 0x00000100
182 #define TX4927_CLKCTR_DMARST 0x00000080
183 #define TX4927_CLKCTR_PCIRST 0x00000040
184 #define TX4927_CLKCTR_TM0RST 0x00000010
185 #define TX4927_CLKCTR_TM1RST 0x00000008
186 #define TX4927_CLKCTR_TM2RST 0x00000004
187 #define TX4927_CLKCTR_SIO0RST 0x00000002
188 #define TX4927_CLKCTR_SIO1RST 0x00000001
206 ((((TX4927_SDRAMC_CR(ch) >> 33) & 0x7fff) + 1) << 21)
211 (0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf))
213 (64 >> ((__u32)(TX4927_EBUSC_CR(ch) >> 20) & 0x3))