Lines Matching +full:0 +full:xd000
22 #define AR9300_EEP_VER 0xD000
23 #define AR9300_EEP_VER_MINOR_MASK 0xFFF
24 #define AR9300_EEP_MINOR_VER_1 0x1
41 #define AR9300_EEPMISC_WOW 0x02
48 #define AR9300_PAPRD_RATE_MASK 0x01ffffff
49 #define AR9300_PAPRD_SCALE_1 0x0e000000
51 #define AR9300_PAPRD_SCALE_2 0x70000000
54 #define AR9300_EEP_ANTDIV_CONTROL_DEFAULT_VALUE 0xc9
63 #define AR9300_PWR_TABLE_OFFSET 0
78 #define AR9300_BASE_ADDR_4K 0xfff
79 #define AR9300_BASE_ADDR 0x3ff
80 #define AR9300_BASE_ADDR_512 0x1ff
83 #define AR9300_EEPMISC_LITTLE_ENDIAN 0
86 ((AR_SREV_9340(_ah) || AR_SREV_9550(_ah)) ? 0x30000 : 0x14000)
88 ((AR_SREV_9340(_ah) || AR_SREV_9550(_ah)) ? 0x31018 : 0x15f18)
89 #define AR9300_OTP_STATUS_TYPE 0x7
90 #define AR9300_OTP_STATUS_VALID 0x4
91 #define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
92 #define AR9300_OTP_STATUS_SM_BUSY 0x1
94 ((AR_SREV_9340(_ah) || AR_SREV_9550(_ah)) ? 0x3101c : 0x15f1c)
174 _CompressNone = 0,
225 /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
227 /* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */
293 * BIT 0 - TX Gain Cap enable.