Home
last modified time | relevance | path

Searched +full:0 +full:x8500 (Results 1 – 25 of 48) sorted by relevance

12

/linux/drivers/soc/ux500/
H A Dux500-soc-id.c25 * @process: the manufacturing process, 0x40 is 40 nm 0x00 is "standard"
26 * @partnumber: hithereto 0x8500 for DB8500
43 return 0; in ux500_read_asicid()
57 if (rev == 0x01) in ux500_print_soc_info()
59 else if (rev >= 0xA0) in ux500_print_soc_info()
60 pr_cont("v%d.%d" , (rev >> 4) - 0xA + 1, rev & 0xf); in ux500_print_soc_info()
69 return (asicid >> 8) & 0xffff; in partnumber()
74 * DB8500ed 0x410fc090 0x9001FFF4 0x00850001
75 * DB8500v1 0x411fc091 0x9001FFF4 0x008500A0
76 * DB8500v1.1 0x411fc091 0x9001FFF4 0x008500A1
[all …]
/linux/arch/arm/mach-omap2/
H A Dprcm43xx.h15 #define AM43XX_PRM_OCP_SOCKET_INST 0x0000
16 #define AM43XX_PRM_MPU_INST 0x0300
17 #define AM43XX_PRM_GFX_INST 0x0400
18 #define AM43XX_PRM_RTC_INST 0x0500
19 #define AM43XX_PRM_TAMPER_INST 0x0600
20 #define AM43XX_PRM_CEFUSE_INST 0x0700
21 #define AM43XX_PRM_PER_INST 0x0800
22 #define AM43XX_PRM_WKUP_INST 0x2000
23 #define AM43XX_PRM_DEVICE_INST 0x4000
26 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsc8280xp-pmics.dtsi23 hysteresis = <0>;
29 hysteresis = <0>;
43 hysteresis = <0>;
49 hysteresis = <0>;
63 hysteresis = <0>;
69 hysteresis = <0>;
83 hysteresis = <0>;
89 hysteresis = <0>;
98 pmk8280: pmic@0 {
100 reg = <0x0 SPMI_USID>;
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dsocionext,uniphier-ave4.yaml124 reg = <0x65000000 0x8500>;
125 interrupts = <0 66 4>;
132 socionext,syscon-phy-mode = <&soc_glue 0>;
136 #size-cells = <0>;
/linux/drivers/media/usb/gspca/
H A Dspca561.c37 #define Rev012A 0
64 .priv = 0},
87 .priv = 0},
112 #define SPCA561_INDEX_I2C_BASE 0x8800
113 #define SPCA561_SNAPBIT 0x20
114 #define SPCA561_SNAPCTRL 0x40
117 {0x0000, 0x8114}, /* Software GPIO output data */
118 {0x0001, 0x8114}, /* Software GPIO output data */
119 {0x0000, 0x8112}, /* Some kind of reset */
123 {0x0003, 0x8701}, /* PCLK clock delay adjustment */
[all …]
H A Dspca508.c23 #define CreativeVista 0
51 .priv = 0},
62 {0x0000, 0x870b},
64 {0x0020, 0x8112}, /* Video drop enable, ISO streaming disable */
65 {0x0003, 0x8111}, /* Reset compression & memory */
66 {0x0000, 0x8110}, /* Disable all outputs */
67 /* READ {0x0000, 0x8114} -> 0000: 00 */
68 {0x0000, 0x8114}, /* SW GPIO data */
69 {0x0008, 0x8110}, /* Enable charge pump output */
70 {0x0002, 0x8116}, /* 200 kHz pump clock */
[all …]
H A Ddtcs033.c32 if (gspca_dev->usb_err < 0) in reg_rw()
36 usb_rcvctrlpipe(udev, 0), in reg_rw()
42 if (ret < 0) { in reg_rw()
53 int i = 0; in reg_reqs()
56 while ((i < n_reqs) && (gspca_dev->usb_err >= 0)) { in reg_reqs()
63 if (gspca_dev->usb_err < 0) { in reg_reqs()
111 return 0; in sd_config()
117 return 0; in sd_init()
137 gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0); in dtcs033_pkt_scan()
141 gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0); in dtcs033_pkt_scan()
[all …]
H A Dtouptek.c24 * 0.000400, 0x0002
25 * 0.001000, 0x0005
26 * 0.005000, 0x0019
27 * 0.020000, 0x0064
28 * 0.080000, 0x0190
29 * 0.400000, 0x07D0
30 * 1.000000, 0x1388
31 * 2.000000, 0x2710
34 * 0x1000: master channel enable bit
35 * 0x007F: low gain bits
[all …]
/linux/include/video/
H A Dtrident.h4 #define TRIDENTFB_DEBUG 0
20 #define CYBER9320 0x9320
21 #define CYBER9388 0x9388
22 #define CYBER9382 0x9382 /* the real PCI id for this is 9660 */
23 #define CYBER9385 0x9385 /* ditto */
24 #define CYBER9397 0x9397
25 #define CYBER9397DVD 0x939A
26 #define CYBER9520 0x9520
27 #define CYBER9525DVD 0x9525
28 #define TGUI9440 0x9440
[all …]
/linux/tools/perf/tests/shell/attr/
H A Dtest-stat-default33 type=0
34 config=0
40 type=0
46 type=0
53 type=0
60 type=0
67 type=0
71 # PERF_TYPE_RAW / slots (0x400)
80 # PERF_TYPE_RAW / topdown-retiring (0x8000)
86 disabled=0
[all …]
H A Dtest-stat-detailed-134 type=0
35 config=0
41 type=0
48 type=0
55 type=0
62 type=0
69 type=0
73 # PERF_TYPE_RAW / slots (0x400)
82 # PERF_TYPE_RAW / topdown-retiring (0x8000)
88 disabled=0
[all …]
H A Dtest-stat-detailed-334 type=0
35 config=0
41 type=0
48 type=0
55 type=0
62 type=0
69 type=0
73 # PERF_TYPE_RAW / slots (0x400)
82 # PERF_TYPE_RAW / topdown-retiring (0x8000)
88 disabled=0
[all …]
H A Dtest-stat-detailed-234 type=0
35 config=0
41 type=0
48 type=0
55 type=0
62 type=0
69 type=0
73 # PERF_TYPE_RAW / slots (0x400)
82 # PERF_TYPE_RAW / topdown-retiring (0x8000)
88 disabled=0
[all …]
/linux/lib/crc/
H A Dcrc-ccitt.c11 * be seen in entry 128, 0x8408. This corresponds to x^0 + x^5 + x^12.
15 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
16 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
17 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
18 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
19 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
20 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
21 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
22 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
23 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
[all …]
/linux/arch/powerpc/boot/dts/
H A Dep8248e.dts26 #size-cells = <0>;
28 PowerPC,8248@0 {
30 reg = <0>;
35 timebase-frequency = <0>;
36 clock-frequency = <0>;
46 reg = <0xf0010100 0x40>;
48 ranges = <0 0 0xfc000000 0x04000000
49 1 0 0xfa000000 0x00008000>;
51 flash@0,3800000 {
53 reg = <0 0x3800000 0x800000>;
[all …]
H A Dmgcoge.dts23 #size-cells = <0>;
25 PowerPC,8247@0 {
27 reg = <0>;
32 timebase-frequency = <0>; /* Filled in by U-Boot */
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 bus-frequency = <0>; /* Filled in by U-Boot */
44 reg = <0xf0010100 0x40>;
46 ranges = <0 0 0xfe000000 0x00400000
47 1 0 0x30000000 0x00010000
48 2 0 0x40000000 0x00010000
[all …]
/linux/arch/powerpc/sysdev/
H A Dfsl_pci.c70 u32 val = 0; in fsl_pcie_check_link()
74 __indirect_read_config(hose, hose->first_busno, 0, in fsl_pcie_check_link()
77 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); in fsl_pcie_check_link()
89 return 0; in fsl_pcie_check_link()
140 dev->bus_dma_limit = 0; in fsl_pci_dma_set_mask()
152 u32 flags = 0x80044000; /* enable & mem R/W */ in setup_one_atmu()
155 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", in setup_one_atmu()
159 flags |= 0x10000000; /* enable relaxed ordering */ in setup_one_atmu()
161 for (i = 0; size > 0; i++) { in setup_one_atmu()
203 u64 mem, sz, paddr_hi = 0; in setup_pci_atmu()
[all …]
/linux/drivers/net/usb/
H A Dsr9800.h16 #define SR_CMD_SET_SW_MII 0x06
18 #define SR_CMD_READ_MII_REG 0x07
20 #define SR_CMD_WRITE_MII_REG 0x08
22 #define SR_CMD_SET_HW_MII 0x0a
24 #define SR_CMD_READ_EEPROM 0x0b
26 #define SR_CMD_WRITE_EEPROM 0x0c
28 #define SR_CMD_WRITE_ENABLE 0x0d
30 #define SR_CMD_WRITE_DISABLE 0x0e
32 #define SR_CMD_READ_RX_CTL 0x0f
33 #define SR_RX_CTL_PRO (1 << 0)
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam43xx-clocks.dtsi9 #clock-cells = <0>;
14 reg = <0x0040>;
18 #clock-cells = <0>;
23 reg = <0x0040>;
27 #clock-cells = <0>;
32 reg = <0x0040>;
36 #clock-cells = <0>;
45 #clock-cells = <0>;
54 #clock-cells = <0>;
63 #clock-cells = <0>;
[all …]
/linux/include/linux/mfd/mt6332/
H A Dregisters.h10 #define MT6332_HWCID 0x8000
11 #define MT6332_SWCID 0x8002
12 #define MT6332_TOP_CON 0x8004
13 #define MT6332_DDR_VREF_AP_CON 0x8006
14 #define MT6332_DDR_VREF_DQ_CON 0x8008
15 #define MT6332_DDR_VREF_CA_CON 0x800A
16 #define MT6332_TEST_OUT 0x800C
17 #define MT6332_TEST_CON0 0x800E
18 #define MT6332_TEST_CON1 0x8010
19 #define MT6332_TESTMODE_SW 0x8012
[all …]
/linux/arch/arm64/boot/dts/socionext/
H A Duniphier-ld11.dtsi20 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0 0x000>;
46 reg = <0 0x001>;
102 #clock-cells = <0>;
126 reg = <0x0 0x81000000 0x0 0x01000000>;
131 soc@0 {
135 ranges = <0 0 0 0xffffffff>;
140 reg = <0x54006000 0x100>;
142 #size-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Ddove.dtsi22 #size-cells = <0>;
24 cpu0: cpu@0 {
28 reg = <0>;
34 marvell,tauros2-cache-features = <0>;
46 #size-cells = <0>;
51 pinctrl-0 = <&pmx_i2cmux_0>;
55 i2c0: i2c@0 {
56 reg = <0>;
58 #size-cells = <0>;
65 #size-cells = <0>;
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dlontium-lt9211.c31 #define REG_PAGE_CONTROL 0xff
32 #define REG_CHIPID0 0x8100
33 #define REG_CHIPID0_VALUE 0x18
34 #define REG_CHIPID1 0x8101
35 #define REG_CHIPID1_VALUE 0x01
36 #define REG_CHIPID2 0x8102
37 #define REG_CHIPID2_VALUE 0xe3
39 #define REG_DSI_LANE 0xd000
40 /* DSI lane count - 0 means 4 lanes ; 1, 2, 3 means 1, 2, 3 lanes. */
56 regmap_reg_range(0xff, 0xff),
[all …]
/linux/arch/arm/boot/dts/socionext/
H A Duniphier-pro4.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
65 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
66 <0x506c0000 0x400>;
79 reg = <0x54006000 0x100>;
81 #size-cells = <0>;
84 pinctrl-0 = <&pinctrl_spi0>;
[all …]
H A Duniphier-pxs2.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0>;
112 #clock-cells = <0>;
117 #clock-cells = <0>;
163 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
164 <0x506c0000 0x400>;
179 reg = <0x54006000 0x100>;
181 #size-cells = <0>;
184 pinctrl-0 = <&pinctrl_spi0>;
[all …]

12