xref: /linux/tools/perf/tests/shell/attr/test-stat-detailed-1 (revision c771600c6af14749609b49565ffb4cac2959710d) 
1*8296aa0fSIan Rogers[config]
2*8296aa0fSIan Rogerscommand = stat
3*8296aa0fSIan Rogersargs    = -d kill >/dev/null 2>&1
4*8296aa0fSIan Rogersret     = 1
5*8296aa0fSIan Rogers
6*8296aa0fSIan Rogers
7*8296aa0fSIan Rogers# PERF_TYPE_SOFTWARE / PERF_COUNT_SW_TASK_CLOCK
8*8296aa0fSIan Rogers[event1:base-stat]
9*8296aa0fSIan Rogersfd=1
10*8296aa0fSIan Rogerstype=1
11*8296aa0fSIan Rogersconfig=1
12*8296aa0fSIan Rogers
13*8296aa0fSIan Rogers# PERF_TYPE_SOFTWARE / PERF_COUNT_SW_CONTEXT_SWITCHES
14*8296aa0fSIan Rogers[event2:base-stat]
15*8296aa0fSIan Rogersfd=2
16*8296aa0fSIan Rogerstype=1
17*8296aa0fSIan Rogersconfig=3
18*8296aa0fSIan Rogers
19*8296aa0fSIan Rogers# PERF_TYPE_SOFTWARE / PERF_COUNT_SW_CPU_MIGRATIONS
20*8296aa0fSIan Rogers[event3:base-stat]
21*8296aa0fSIan Rogersfd=3
22*8296aa0fSIan Rogerstype=1
23*8296aa0fSIan Rogersconfig=4
24*8296aa0fSIan Rogers
25*8296aa0fSIan Rogers# PERF_TYPE_SOFTWARE / PERF_COUNT_SW_PAGE_FAULTS
26*8296aa0fSIan Rogers[event4:base-stat]
27*8296aa0fSIan Rogersfd=4
28*8296aa0fSIan Rogerstype=1
29*8296aa0fSIan Rogersconfig=2
30*8296aa0fSIan Rogers
31*8296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_CPU_CYCLES
32*8296aa0fSIan Rogers[event5:base-stat]
33*8296aa0fSIan Rogersfd=5
34*8296aa0fSIan Rogerstype=0
35*8296aa0fSIan Rogersconfig=0
36*8296aa0fSIan Rogersoptional=1
37*8296aa0fSIan Rogers
38*8296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
39*8296aa0fSIan Rogers[event6:base-stat]
40*8296aa0fSIan Rogersfd=6
41*8296aa0fSIan Rogerstype=0
42*8296aa0fSIan Rogersconfig=7
43*8296aa0fSIan Rogersoptional=1
44*8296aa0fSIan Rogers
45*8296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_STALLED_CYCLES_BACKEND
46*8296aa0fSIan Rogers[event7:base-stat]
47*8296aa0fSIan Rogersfd=7
48*8296aa0fSIan Rogerstype=0
49*8296aa0fSIan Rogersconfig=8
50*8296aa0fSIan Rogersoptional=1
51*8296aa0fSIan Rogers
52*8296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_INSTRUCTIONS
53*8296aa0fSIan Rogers[event8:base-stat]
54*8296aa0fSIan Rogersfd=8
55*8296aa0fSIan Rogerstype=0
56*8296aa0fSIan Rogersconfig=1
57*8296aa0fSIan Rogersoptional=1
58*8296aa0fSIan Rogers
59*8296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_BRANCH_INSTRUCTIONS
60*8296aa0fSIan Rogers[event9:base-stat]
61*8296aa0fSIan Rogersfd=9
62*8296aa0fSIan Rogerstype=0
63*8296aa0fSIan Rogersconfig=4
64*8296aa0fSIan Rogersoptional=1
65*8296aa0fSIan Rogers
66*8296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_BRANCH_MISSES
67*8296aa0fSIan Rogers[event10:base-stat]
68*8296aa0fSIan Rogersfd=10
69*8296aa0fSIan Rogerstype=0
70*8296aa0fSIan Rogersconfig=5
71*8296aa0fSIan Rogersoptional=1
72*8296aa0fSIan Rogers
73*8296aa0fSIan Rogers# PERF_TYPE_RAW / slots (0x400)
74*8296aa0fSIan Rogers[event11:base-stat]
75*8296aa0fSIan Rogersfd=11
76*8296aa0fSIan Rogersgroup_fd=-1
77*8296aa0fSIan Rogerstype=4
78*8296aa0fSIan Rogersconfig=1024
79*8296aa0fSIan Rogersread_format=15
80*8296aa0fSIan Rogersoptional=1
81*8296aa0fSIan Rogers
82*8296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-retiring (0x8000)
83*8296aa0fSIan Rogers[event12:base-stat]
84*8296aa0fSIan Rogersfd=12
85*8296aa0fSIan Rogersgroup_fd=11
86*8296aa0fSIan Rogerstype=4
87*8296aa0fSIan Rogersconfig=32768
88*8296aa0fSIan Rogersdisabled=0
89*8296aa0fSIan Rogersenable_on_exec=0
90*8296aa0fSIan Rogersread_format=15
91*8296aa0fSIan Rogersoptional=1
92*8296aa0fSIan Rogers
93*8296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-bad-spec (0x8100)
94*8296aa0fSIan Rogers[event13:base-stat]
95*8296aa0fSIan Rogersfd=13
96*8296aa0fSIan Rogersgroup_fd=11
97*8296aa0fSIan Rogerstype=4
98*8296aa0fSIan Rogersconfig=33024
99*8296aa0fSIan Rogersdisabled=0
100*8296aa0fSIan Rogersenable_on_exec=0
101*8296aa0fSIan Rogersread_format=15
102*8296aa0fSIan Rogersoptional=1
103*8296aa0fSIan Rogers
104*8296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-fe-bound (0x8200)
105*8296aa0fSIan Rogers[event14:base-stat]
106*8296aa0fSIan Rogersfd=14
107*8296aa0fSIan Rogersgroup_fd=11
108*8296aa0fSIan Rogerstype=4
109*8296aa0fSIan Rogersconfig=33280
110*8296aa0fSIan Rogersdisabled=0
111*8296aa0fSIan Rogersenable_on_exec=0
112*8296aa0fSIan Rogersread_format=15
113*8296aa0fSIan Rogersoptional=1
114*8296aa0fSIan Rogers
115*8296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-be-bound (0x8300)
116*8296aa0fSIan Rogers[event15:base-stat]
117*8296aa0fSIan Rogersfd=15
118*8296aa0fSIan Rogersgroup_fd=11
119*8296aa0fSIan Rogerstype=4
120*8296aa0fSIan Rogersconfig=33536
121*8296aa0fSIan Rogersdisabled=0
122*8296aa0fSIan Rogersenable_on_exec=0
123*8296aa0fSIan Rogersread_format=15
124*8296aa0fSIan Rogersoptional=1
125*8296aa0fSIan Rogers
126*8296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-heavy-ops (0x8400)
127*8296aa0fSIan Rogers[event16:base-stat]
128*8296aa0fSIan Rogersfd=16
129*8296aa0fSIan Rogersgroup_fd=11
130*8296aa0fSIan Rogerstype=4
131*8296aa0fSIan Rogersconfig=33792
132*8296aa0fSIan Rogersdisabled=0
133*8296aa0fSIan Rogersenable_on_exec=0
134*8296aa0fSIan Rogersread_format=15
135*8296aa0fSIan Rogersoptional=1
136*8296aa0fSIan Rogers
137*8296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-br-mispredict (0x8500)
138*8296aa0fSIan Rogers[event17:base-stat]
139*8296aa0fSIan Rogersfd=17
140*8296aa0fSIan Rogersgroup_fd=11
141*8296aa0fSIan Rogerstype=4
142*8296aa0fSIan Rogersconfig=34048
143*8296aa0fSIan Rogersdisabled=0
144*8296aa0fSIan Rogersenable_on_exec=0
145*8296aa0fSIan Rogersread_format=15
146*8296aa0fSIan Rogersoptional=1
147*8296aa0fSIan Rogers
148*8296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-fetch-lat (0x8600)
149*8296aa0fSIan Rogers[event18:base-stat]
150*8296aa0fSIan Rogersfd=18
151*8296aa0fSIan Rogersgroup_fd=11
152*8296aa0fSIan Rogerstype=4
153*8296aa0fSIan Rogersconfig=34304
154*8296aa0fSIan Rogersdisabled=0
155*8296aa0fSIan Rogersenable_on_exec=0
156*8296aa0fSIan Rogersread_format=15
157*8296aa0fSIan Rogersoptional=1
158*8296aa0fSIan Rogers
159*8296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-mem-bound (0x8700)
160*8296aa0fSIan Rogers[event19:base-stat]
161*8296aa0fSIan Rogersfd=19
162*8296aa0fSIan Rogersgroup_fd=11
163*8296aa0fSIan Rogerstype=4
164*8296aa0fSIan Rogersconfig=34560
165*8296aa0fSIan Rogersdisabled=0
166*8296aa0fSIan Rogersenable_on_exec=0
167*8296aa0fSIan Rogersread_format=15
168*8296aa0fSIan Rogersoptional=1
169*8296aa0fSIan Rogers
170*8296aa0fSIan Rogers# PERF_TYPE_RAW / INT_MISC.UOP_DROPPING
171*8296aa0fSIan Rogers[event20:base-stat]
172*8296aa0fSIan Rogersfd=20
173*8296aa0fSIan Rogerstype=4
174*8296aa0fSIan Rogersconfig=4109
175*8296aa0fSIan Rogersoptional=1
176*8296aa0fSIan Rogers
177*8296aa0fSIan Rogers# PERF_TYPE_RAW / cpu/INT_MISC.RECOVERY_CYCLES,cmask=1,edge/
178*8296aa0fSIan Rogers[event21:base-stat]
179*8296aa0fSIan Rogersfd=21
180*8296aa0fSIan Rogerstype=4
181*8296aa0fSIan Rogersconfig=17039629
182*8296aa0fSIan Rogersoptional=1
183*8296aa0fSIan Rogers
184*8296aa0fSIan Rogers# PERF_TYPE_RAW / CPU_CLK_UNHALTED.THREAD
185*8296aa0fSIan Rogers[event22:base-stat]
186*8296aa0fSIan Rogersfd=22
187*8296aa0fSIan Rogerstype=4
188*8296aa0fSIan Rogersconfig=60
189*8296aa0fSIan Rogersoptional=1
190*8296aa0fSIan Rogers
191*8296aa0fSIan Rogers# PERF_TYPE_RAW / INT_MISC.RECOVERY_CYCLES_ANY
192*8296aa0fSIan Rogers[event23:base-stat]
193*8296aa0fSIan Rogersfd=23
194*8296aa0fSIan Rogerstype=4
195*8296aa0fSIan Rogersconfig=2097421
196*8296aa0fSIan Rogersoptional=1
197*8296aa0fSIan Rogers
198*8296aa0fSIan Rogers# PERF_TYPE_RAW / CPU_CLK_UNHALTED.REF_XCLK
199*8296aa0fSIan Rogers[event24:base-stat]
200*8296aa0fSIan Rogersfd=24
201*8296aa0fSIan Rogerstype=4
202*8296aa0fSIan Rogersconfig=316
203*8296aa0fSIan Rogersoptional=1
204*8296aa0fSIan Rogers
205*8296aa0fSIan Rogers# PERF_TYPE_RAW / IDQ_UOPS_NOT_DELIVERED.CORE
206*8296aa0fSIan Rogers[event25:base-stat]
207*8296aa0fSIan Rogersfd=25
208*8296aa0fSIan Rogerstype=4
209*8296aa0fSIan Rogersconfig=412
210*8296aa0fSIan Rogersoptional=1
211*8296aa0fSIan Rogers
212*8296aa0fSIan Rogers# PERF_TYPE_RAW / CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE
213*8296aa0fSIan Rogers[event26:base-stat]
214*8296aa0fSIan Rogersfd=26
215*8296aa0fSIan Rogerstype=4
216*8296aa0fSIan Rogersconfig=572
217*8296aa0fSIan Rogersoptional=1
218*8296aa0fSIan Rogers
219*8296aa0fSIan Rogers# PERF_TYPE_RAW / UOPS_RETIRED.RETIRE_SLOTS
220*8296aa0fSIan Rogers[event27:base-stat]
221*8296aa0fSIan Rogersfd=27
222*8296aa0fSIan Rogerstype=4
223*8296aa0fSIan Rogersconfig=706
224*8296aa0fSIan Rogersoptional=1
225*8296aa0fSIan Rogers
226*8296aa0fSIan Rogers# PERF_TYPE_RAW / UOPS_ISSUED.ANY
227*8296aa0fSIan Rogers[event28:base-stat]
228*8296aa0fSIan Rogersfd=28
229*8296aa0fSIan Rogerstype=4
230*8296aa0fSIan Rogersconfig=270
231*8296aa0fSIan Rogersoptional=1
232*8296aa0fSIan Rogers
233*8296aa0fSIan Rogers# PERF_TYPE_HW_CACHE /
234*8296aa0fSIan Rogers#  PERF_COUNT_HW_CACHE_L1D                <<  0  |
235*8296aa0fSIan Rogers# (PERF_COUNT_HW_CACHE_OP_READ            <<  8) |
236*8296aa0fSIan Rogers# (PERF_COUNT_HW_CACHE_RESULT_ACCESS      << 16)
237*8296aa0fSIan Rogers[event29:base-stat]
238*8296aa0fSIan Rogersfd=29
239*8296aa0fSIan Rogerstype=3
240*8296aa0fSIan Rogersconfig=0
241*8296aa0fSIan Rogersoptional=1
242*8296aa0fSIan Rogers
243*8296aa0fSIan Rogers# PERF_TYPE_HW_CACHE /
244*8296aa0fSIan Rogers#  PERF_COUNT_HW_CACHE_L1D                <<  0  |
245*8296aa0fSIan Rogers# (PERF_COUNT_HW_CACHE_OP_READ            <<  8) |
246*8296aa0fSIan Rogers# (PERF_COUNT_HW_CACHE_RESULT_MISS        << 16)
247*8296aa0fSIan Rogers[event30:base-stat]
248*8296aa0fSIan Rogersfd=30
249*8296aa0fSIan Rogerstype=3
250*8296aa0fSIan Rogersconfig=65536
251*8296aa0fSIan Rogersoptional=1
252*8296aa0fSIan Rogers
253*8296aa0fSIan Rogers# PERF_TYPE_HW_CACHE /
254*8296aa0fSIan Rogers#  PERF_COUNT_HW_CACHE_LL                 <<  0  |
255*8296aa0fSIan Rogers# (PERF_COUNT_HW_CACHE_OP_READ            <<  8) |
256*8296aa0fSIan Rogers# (PERF_COUNT_HW_CACHE_RESULT_ACCESS      << 16)
257*8296aa0fSIan Rogers[event31:base-stat]
258*8296aa0fSIan Rogersfd=31
259*8296aa0fSIan Rogerstype=3
260*8296aa0fSIan Rogersconfig=2
261*8296aa0fSIan Rogersoptional=1
262*8296aa0fSIan Rogers
263*8296aa0fSIan Rogers# PERF_TYPE_HW_CACHE,
264*8296aa0fSIan Rogers#  PERF_COUNT_HW_CACHE_LL                 <<  0  |
265*8296aa0fSIan Rogers# (PERF_COUNT_HW_CACHE_OP_READ            <<  8) |
266*8296aa0fSIan Rogers# (PERF_COUNT_HW_CACHE_RESULT_MISS        << 16)
267*8296aa0fSIan Rogers[event32:base-stat]
268*8296aa0fSIan Rogersfd=32
269*8296aa0fSIan Rogerstype=3
270*8296aa0fSIan Rogersconfig=65538
271*8296aa0fSIan Rogersoptional=1
272