18296aa0fSIan Rogers[config] 28296aa0fSIan Rogerscommand = stat 38296aa0fSIan Rogersargs = kill >/dev/null 2>&1 48296aa0fSIan Rogersret = 1 58296aa0fSIan Rogers 68296aa0fSIan Rogers# PERF_TYPE_SOFTWARE / PERF_COUNT_SW_TASK_CLOCK 78296aa0fSIan Rogers[event1:base-stat] 88296aa0fSIan Rogersfd=1 98296aa0fSIan Rogerstype=1 108296aa0fSIan Rogersconfig=1 118296aa0fSIan Rogers 128296aa0fSIan Rogers# PERF_TYPE_SOFTWARE / PERF_COUNT_SW_CONTEXT_SWITCHES 138296aa0fSIan Rogers[event2:base-stat] 148296aa0fSIan Rogersfd=2 158296aa0fSIan Rogerstype=1 168296aa0fSIan Rogersconfig=3 178296aa0fSIan Rogers 188296aa0fSIan Rogers# PERF_TYPE_SOFTWARE / PERF_COUNT_SW_CPU_MIGRATIONS 198296aa0fSIan Rogers[event3:base-stat] 208296aa0fSIan Rogersfd=3 218296aa0fSIan Rogerstype=1 228296aa0fSIan Rogersconfig=4 238296aa0fSIan Rogers 248296aa0fSIan Rogers# PERF_TYPE_SOFTWARE / PERF_COUNT_SW_PAGE_FAULTS 258296aa0fSIan Rogers[event4:base-stat] 268296aa0fSIan Rogersfd=4 278296aa0fSIan Rogerstype=1 288296aa0fSIan Rogersconfig=2 298296aa0fSIan Rogers 308296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_CPU_CYCLES 318296aa0fSIan Rogers[event5:base-stat] 328296aa0fSIan Rogersfd=5 338296aa0fSIan Rogerstype=0 348296aa0fSIan Rogersconfig=0 358296aa0fSIan Rogersoptional=1 368296aa0fSIan Rogers 378296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_STALLED_CYCLES_FRONTEND 388296aa0fSIan Rogers[event6:base-stat] 398296aa0fSIan Rogersfd=6 408296aa0fSIan Rogerstype=0 418296aa0fSIan Rogersconfig=7 428296aa0fSIan Rogersoptional=1 438296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_STALLED_CYCLES_BACKEND 448296aa0fSIan Rogers[event7:base-stat] 458296aa0fSIan Rogersfd=7 468296aa0fSIan Rogerstype=0 478296aa0fSIan Rogersconfig=8 488296aa0fSIan Rogersoptional=1 498296aa0fSIan Rogers 508296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_INSTRUCTIONS 518296aa0fSIan Rogers[event8:base-stat] 528296aa0fSIan Rogersfd=8 538296aa0fSIan Rogerstype=0 548296aa0fSIan Rogersconfig=1 558296aa0fSIan Rogersoptional=1 568296aa0fSIan Rogers 578296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_BRANCH_INSTRUCTIONS 588296aa0fSIan Rogers[event9:base-stat] 598296aa0fSIan Rogersfd=9 608296aa0fSIan Rogerstype=0 618296aa0fSIan Rogersconfig=4 628296aa0fSIan Rogersoptional=1 638296aa0fSIan Rogers 648296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_BRANCH_MISSES 658296aa0fSIan Rogers[event10:base-stat] 668296aa0fSIan Rogersfd=10 678296aa0fSIan Rogerstype=0 688296aa0fSIan Rogersconfig=5 698296aa0fSIan Rogersoptional=1 708296aa0fSIan Rogers 718296aa0fSIan Rogers# PERF_TYPE_RAW / slots (0x400) 728296aa0fSIan Rogers[event11:base-stat] 738296aa0fSIan Rogersfd=11 748296aa0fSIan Rogersgroup_fd=-1 758296aa0fSIan Rogerstype=4 768296aa0fSIan Rogersconfig=1024 778296aa0fSIan Rogersread_format=15 788296aa0fSIan Rogersoptional=1 798296aa0fSIan Rogers 808296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-retiring (0x8000) 818296aa0fSIan Rogers[event12:base-stat] 828296aa0fSIan Rogersfd=12 838296aa0fSIan Rogersgroup_fd=11 848296aa0fSIan Rogerstype=4 858296aa0fSIan Rogersconfig=32768 868296aa0fSIan Rogersdisabled=0 878296aa0fSIan Rogersenable_on_exec=0 888296aa0fSIan Rogersread_format=15 898296aa0fSIan Rogersoptional=1 908296aa0fSIan Rogers 918296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-bad-spec (0x8100) 928296aa0fSIan Rogers[event13:base-stat] 938296aa0fSIan Rogersfd=13 948296aa0fSIan Rogersgroup_fd=11 958296aa0fSIan Rogerstype=4 968296aa0fSIan Rogersconfig=33024 978296aa0fSIan Rogersdisabled=0 988296aa0fSIan Rogersenable_on_exec=0 998296aa0fSIan Rogersread_format=15 1008296aa0fSIan Rogersoptional=1 1018296aa0fSIan Rogers 1028296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-fe-bound (0x8200) 1038296aa0fSIan Rogers[event14:base-stat] 1048296aa0fSIan Rogersfd=14 1058296aa0fSIan Rogersgroup_fd=11 1068296aa0fSIan Rogerstype=4 1078296aa0fSIan Rogersconfig=33280 1088296aa0fSIan Rogersdisabled=0 1098296aa0fSIan Rogersenable_on_exec=0 1108296aa0fSIan Rogersread_format=15 1118296aa0fSIan Rogersoptional=1 1128296aa0fSIan Rogers 1138296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-be-bound (0x8300) 1148296aa0fSIan Rogers[event15:base-stat] 1158296aa0fSIan Rogersfd=15 1168296aa0fSIan Rogersgroup_fd=11 1178296aa0fSIan Rogerstype=4 1188296aa0fSIan Rogersconfig=33536 1198296aa0fSIan Rogersdisabled=0 1208296aa0fSIan Rogersenable_on_exec=0 1218296aa0fSIan Rogersread_format=15 1228296aa0fSIan Rogersoptional=1 1238296aa0fSIan Rogers 1248296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-heavy-ops (0x8400) 1258296aa0fSIan Rogers[event16:base-stat] 1268296aa0fSIan Rogersfd=16 1278296aa0fSIan Rogersgroup_fd=11 1288296aa0fSIan Rogerstype=4 1298296aa0fSIan Rogersconfig=33792 1308296aa0fSIan Rogersdisabled=0 1318296aa0fSIan Rogersenable_on_exec=0 1328296aa0fSIan Rogersread_format=15 1338296aa0fSIan Rogersoptional=1 1348296aa0fSIan Rogers 1358296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-br-mispredict (0x8500) 1368296aa0fSIan Rogers[event17:base-stat] 1378296aa0fSIan Rogersfd=17 1388296aa0fSIan Rogersgroup_fd=11 1398296aa0fSIan Rogerstype=4 1408296aa0fSIan Rogersconfig=34048 1418296aa0fSIan Rogersdisabled=0 1428296aa0fSIan Rogersenable_on_exec=0 1438296aa0fSIan Rogersread_format=15 1448296aa0fSIan Rogersoptional=1 1458296aa0fSIan Rogers 1468296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-fetch-lat (0x8600) 1478296aa0fSIan Rogers[event18:base-stat] 1488296aa0fSIan Rogersfd=18 1498296aa0fSIan Rogersgroup_fd=11 1508296aa0fSIan Rogerstype=4 1518296aa0fSIan Rogersconfig=34304 1528296aa0fSIan Rogersdisabled=0 1538296aa0fSIan Rogersenable_on_exec=0 1548296aa0fSIan Rogersread_format=15 1558296aa0fSIan Rogersoptional=1 1568296aa0fSIan Rogers 1578296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-mem-bound (0x8700) 1588296aa0fSIan Rogers[event19:base-stat] 1598296aa0fSIan Rogersfd=19 1608296aa0fSIan Rogersgroup_fd=11 1618296aa0fSIan Rogerstype=4 1628296aa0fSIan Rogersconfig=34560 1638296aa0fSIan Rogersdisabled=0 1648296aa0fSIan Rogersenable_on_exec=0 1658296aa0fSIan Rogersread_format=15 1668296aa0fSIan Rogersoptional=1 1678296aa0fSIan Rogers 1688296aa0fSIan Rogers# PERF_TYPE_RAW / INT_MISC.UOP_DROPPING 1698296aa0fSIan Rogers[event20:base-stat] 1708296aa0fSIan Rogersfd=20 1718296aa0fSIan Rogerstype=4 1728296aa0fSIan Rogersconfig=4109 1738296aa0fSIan Rogersoptional=1 1748296aa0fSIan Rogers 1758296aa0fSIan Rogers# PERF_TYPE_RAW / cpu/INT_MISC.RECOVERY_CYCLES,cmask=1,edge/ 1768296aa0fSIan Rogers[event21:base-stat] 1778296aa0fSIan Rogersfd=21 1788296aa0fSIan Rogerstype=4 1798296aa0fSIan Rogersconfig=17039629 1808296aa0fSIan Rogersoptional=1 1818296aa0fSIan Rogers 1828296aa0fSIan Rogers# PERF_TYPE_RAW / CPU_CLK_UNHALTED.THREAD 1838296aa0fSIan Rogers[event22:base-stat] 1848296aa0fSIan Rogersfd=22 1858296aa0fSIan Rogerstype=4 1868296aa0fSIan Rogersconfig=60 1878296aa0fSIan Rogersoptional=1 1888296aa0fSIan Rogers 1898296aa0fSIan Rogers# PERF_TYPE_RAW / INT_MISC.RECOVERY_CYCLES_ANY 1908296aa0fSIan Rogers[event23:base-stat] 1918296aa0fSIan Rogersfd=23 1928296aa0fSIan Rogerstype=4 1938296aa0fSIan Rogersconfig=2097421 1948296aa0fSIan Rogersoptional=1 1958296aa0fSIan Rogers 1968296aa0fSIan Rogers# PERF_TYPE_RAW / CPU_CLK_UNHALTED.REF_XCLK 1978296aa0fSIan Rogers[event24:base-stat] 1988296aa0fSIan Rogersfd=24 1998296aa0fSIan Rogerstype=4 2008296aa0fSIan Rogersconfig=316 2018296aa0fSIan Rogersoptional=1 2028296aa0fSIan Rogers 2038296aa0fSIan Rogers# PERF_TYPE_RAW / IDQ_UOPS_NOT_DELIVERED.CORE 2048296aa0fSIan Rogers[event25:base-stat] 2058296aa0fSIan Rogersfd=25 2068296aa0fSIan Rogerstype=4 2078296aa0fSIan Rogersconfig=412 2088296aa0fSIan Rogersoptional=1 2098296aa0fSIan Rogers 2108296aa0fSIan Rogers# PERF_TYPE_RAW / CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE 2118296aa0fSIan Rogers[event26:base-stat] 2128296aa0fSIan Rogersfd=26 2138296aa0fSIan Rogerstype=4 2148296aa0fSIan Rogersconfig=572 2158296aa0fSIan Rogersoptional=1 2168296aa0fSIan Rogers 2178296aa0fSIan Rogers# PERF_TYPE_RAW / UOPS_RETIRED.RETIRE_SLOTS 2188296aa0fSIan Rogers[event27:base-stat] 2198296aa0fSIan Rogersfd=27 2208296aa0fSIan Rogerstype=4 2218296aa0fSIan Rogersconfig=706 2228296aa0fSIan Rogersoptional=1 2238296aa0fSIan Rogers 2248296aa0fSIan Rogers# PERF_TYPE_RAW / UOPS_ISSUED.ANY 2258296aa0fSIan Rogers[event28:base-stat] 2268296aa0fSIan Rogersfd=28 2278296aa0fSIan Rogerstype=4 2288296aa0fSIan Rogersconfig=270 2298296aa0fSIan Rogersoptional=1 230*0e9e7bc1STrevor Allison 231*0e9e7bc1STrevor Allison# PERF_TYPE_RAW / INT_MISC.UOP_DROPPING 232*0e9e7bc1STrevor Allison[event29:base-stat] 233*0e9e7bc1STrevor Allisonfd=29 234*0e9e7bc1STrevor Allisontype=4 235*0e9e7bc1STrevor Allisonconfig=4269 236*0e9e7bc1STrevor Allisonoptional=1