1*8296aa0fSIan Rogers[config] 2*8296aa0fSIan Rogerscommand = stat 3*8296aa0fSIan Rogersargs = kill >/dev/null 2>&1 4*8296aa0fSIan Rogersret = 1 5*8296aa0fSIan Rogers 6*8296aa0fSIan Rogers# PERF_TYPE_SOFTWARE / PERF_COUNT_SW_TASK_CLOCK 7*8296aa0fSIan Rogers[event1:base-stat] 8*8296aa0fSIan Rogersfd=1 9*8296aa0fSIan Rogerstype=1 10*8296aa0fSIan Rogersconfig=1 11*8296aa0fSIan Rogers 12*8296aa0fSIan Rogers# PERF_TYPE_SOFTWARE / PERF_COUNT_SW_CONTEXT_SWITCHES 13*8296aa0fSIan Rogers[event2:base-stat] 14*8296aa0fSIan Rogersfd=2 15*8296aa0fSIan Rogerstype=1 16*8296aa0fSIan Rogersconfig=3 17*8296aa0fSIan Rogers 18*8296aa0fSIan Rogers# PERF_TYPE_SOFTWARE / PERF_COUNT_SW_CPU_MIGRATIONS 19*8296aa0fSIan Rogers[event3:base-stat] 20*8296aa0fSIan Rogersfd=3 21*8296aa0fSIan Rogerstype=1 22*8296aa0fSIan Rogersconfig=4 23*8296aa0fSIan Rogers 24*8296aa0fSIan Rogers# PERF_TYPE_SOFTWARE / PERF_COUNT_SW_PAGE_FAULTS 25*8296aa0fSIan Rogers[event4:base-stat] 26*8296aa0fSIan Rogersfd=4 27*8296aa0fSIan Rogerstype=1 28*8296aa0fSIan Rogersconfig=2 29*8296aa0fSIan Rogers 30*8296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_CPU_CYCLES 31*8296aa0fSIan Rogers[event5:base-stat] 32*8296aa0fSIan Rogersfd=5 33*8296aa0fSIan Rogerstype=0 34*8296aa0fSIan Rogersconfig=0 35*8296aa0fSIan Rogersoptional=1 36*8296aa0fSIan Rogers 37*8296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_STALLED_CYCLES_FRONTEND 38*8296aa0fSIan Rogers[event6:base-stat] 39*8296aa0fSIan Rogersfd=6 40*8296aa0fSIan Rogerstype=0 41*8296aa0fSIan Rogersconfig=7 42*8296aa0fSIan Rogersoptional=1 43*8296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_STALLED_CYCLES_BACKEND 44*8296aa0fSIan Rogers[event7:base-stat] 45*8296aa0fSIan Rogersfd=7 46*8296aa0fSIan Rogerstype=0 47*8296aa0fSIan Rogersconfig=8 48*8296aa0fSIan Rogersoptional=1 49*8296aa0fSIan Rogers 50*8296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_INSTRUCTIONS 51*8296aa0fSIan Rogers[event8:base-stat] 52*8296aa0fSIan Rogersfd=8 53*8296aa0fSIan Rogerstype=0 54*8296aa0fSIan Rogersconfig=1 55*8296aa0fSIan Rogersoptional=1 56*8296aa0fSIan Rogers 57*8296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_BRANCH_INSTRUCTIONS 58*8296aa0fSIan Rogers[event9:base-stat] 59*8296aa0fSIan Rogersfd=9 60*8296aa0fSIan Rogerstype=0 61*8296aa0fSIan Rogersconfig=4 62*8296aa0fSIan Rogersoptional=1 63*8296aa0fSIan Rogers 64*8296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_BRANCH_MISSES 65*8296aa0fSIan Rogers[event10:base-stat] 66*8296aa0fSIan Rogersfd=10 67*8296aa0fSIan Rogerstype=0 68*8296aa0fSIan Rogersconfig=5 69*8296aa0fSIan Rogersoptional=1 70*8296aa0fSIan Rogers 71*8296aa0fSIan Rogers# PERF_TYPE_RAW / slots (0x400) 72*8296aa0fSIan Rogers[event11:base-stat] 73*8296aa0fSIan Rogersfd=11 74*8296aa0fSIan Rogersgroup_fd=-1 75*8296aa0fSIan Rogerstype=4 76*8296aa0fSIan Rogersconfig=1024 77*8296aa0fSIan Rogersread_format=15 78*8296aa0fSIan Rogersoptional=1 79*8296aa0fSIan Rogers 80*8296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-retiring (0x8000) 81*8296aa0fSIan Rogers[event12:base-stat] 82*8296aa0fSIan Rogersfd=12 83*8296aa0fSIan Rogersgroup_fd=11 84*8296aa0fSIan Rogerstype=4 85*8296aa0fSIan Rogersconfig=32768 86*8296aa0fSIan Rogersdisabled=0 87*8296aa0fSIan Rogersenable_on_exec=0 88*8296aa0fSIan Rogersread_format=15 89*8296aa0fSIan Rogersoptional=1 90*8296aa0fSIan Rogers 91*8296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-bad-spec (0x8100) 92*8296aa0fSIan Rogers[event13:base-stat] 93*8296aa0fSIan Rogersfd=13 94*8296aa0fSIan Rogersgroup_fd=11 95*8296aa0fSIan Rogerstype=4 96*8296aa0fSIan Rogersconfig=33024 97*8296aa0fSIan Rogersdisabled=0 98*8296aa0fSIan Rogersenable_on_exec=0 99*8296aa0fSIan Rogersread_format=15 100*8296aa0fSIan Rogersoptional=1 101*8296aa0fSIan Rogers 102*8296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-fe-bound (0x8200) 103*8296aa0fSIan Rogers[event14:base-stat] 104*8296aa0fSIan Rogersfd=14 105*8296aa0fSIan Rogersgroup_fd=11 106*8296aa0fSIan Rogerstype=4 107*8296aa0fSIan Rogersconfig=33280 108*8296aa0fSIan Rogersdisabled=0 109*8296aa0fSIan Rogersenable_on_exec=0 110*8296aa0fSIan Rogersread_format=15 111*8296aa0fSIan Rogersoptional=1 112*8296aa0fSIan Rogers 113*8296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-be-bound (0x8300) 114*8296aa0fSIan Rogers[event15:base-stat] 115*8296aa0fSIan Rogersfd=15 116*8296aa0fSIan Rogersgroup_fd=11 117*8296aa0fSIan Rogerstype=4 118*8296aa0fSIan Rogersconfig=33536 119*8296aa0fSIan Rogersdisabled=0 120*8296aa0fSIan Rogersenable_on_exec=0 121*8296aa0fSIan Rogersread_format=15 122*8296aa0fSIan Rogersoptional=1 123*8296aa0fSIan Rogers 124*8296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-heavy-ops (0x8400) 125*8296aa0fSIan Rogers[event16:base-stat] 126*8296aa0fSIan Rogersfd=16 127*8296aa0fSIan Rogersgroup_fd=11 128*8296aa0fSIan Rogerstype=4 129*8296aa0fSIan Rogersconfig=33792 130*8296aa0fSIan Rogersdisabled=0 131*8296aa0fSIan Rogersenable_on_exec=0 132*8296aa0fSIan Rogersread_format=15 133*8296aa0fSIan Rogersoptional=1 134*8296aa0fSIan Rogers 135*8296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-br-mispredict (0x8500) 136*8296aa0fSIan Rogers[event17:base-stat] 137*8296aa0fSIan Rogersfd=17 138*8296aa0fSIan Rogersgroup_fd=11 139*8296aa0fSIan Rogerstype=4 140*8296aa0fSIan Rogersconfig=34048 141*8296aa0fSIan Rogersdisabled=0 142*8296aa0fSIan Rogersenable_on_exec=0 143*8296aa0fSIan Rogersread_format=15 144*8296aa0fSIan Rogersoptional=1 145*8296aa0fSIan Rogers 146*8296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-fetch-lat (0x8600) 147*8296aa0fSIan Rogers[event18:base-stat] 148*8296aa0fSIan Rogersfd=18 149*8296aa0fSIan Rogersgroup_fd=11 150*8296aa0fSIan Rogerstype=4 151*8296aa0fSIan Rogersconfig=34304 152*8296aa0fSIan Rogersdisabled=0 153*8296aa0fSIan Rogersenable_on_exec=0 154*8296aa0fSIan Rogersread_format=15 155*8296aa0fSIan Rogersoptional=1 156*8296aa0fSIan Rogers 157*8296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-mem-bound (0x8700) 158*8296aa0fSIan Rogers[event19:base-stat] 159*8296aa0fSIan Rogersfd=19 160*8296aa0fSIan Rogersgroup_fd=11 161*8296aa0fSIan Rogerstype=4 162*8296aa0fSIan Rogersconfig=34560 163*8296aa0fSIan Rogersdisabled=0 164*8296aa0fSIan Rogersenable_on_exec=0 165*8296aa0fSIan Rogersread_format=15 166*8296aa0fSIan Rogersoptional=1 167*8296aa0fSIan Rogers 168*8296aa0fSIan Rogers# PERF_TYPE_RAW / INT_MISC.UOP_DROPPING 169*8296aa0fSIan Rogers[event20:base-stat] 170*8296aa0fSIan Rogersfd=20 171*8296aa0fSIan Rogerstype=4 172*8296aa0fSIan Rogersconfig=4109 173*8296aa0fSIan Rogersoptional=1 174*8296aa0fSIan Rogers 175*8296aa0fSIan Rogers# PERF_TYPE_RAW / cpu/INT_MISC.RECOVERY_CYCLES,cmask=1,edge/ 176*8296aa0fSIan Rogers[event21:base-stat] 177*8296aa0fSIan Rogersfd=21 178*8296aa0fSIan Rogerstype=4 179*8296aa0fSIan Rogersconfig=17039629 180*8296aa0fSIan Rogersoptional=1 181*8296aa0fSIan Rogers 182*8296aa0fSIan Rogers# PERF_TYPE_RAW / CPU_CLK_UNHALTED.THREAD 183*8296aa0fSIan Rogers[event22:base-stat] 184*8296aa0fSIan Rogersfd=22 185*8296aa0fSIan Rogerstype=4 186*8296aa0fSIan Rogersconfig=60 187*8296aa0fSIan Rogersoptional=1 188*8296aa0fSIan Rogers 189*8296aa0fSIan Rogers# PERF_TYPE_RAW / INT_MISC.RECOVERY_CYCLES_ANY 190*8296aa0fSIan Rogers[event23:base-stat] 191*8296aa0fSIan Rogersfd=23 192*8296aa0fSIan Rogerstype=4 193*8296aa0fSIan Rogersconfig=2097421 194*8296aa0fSIan Rogersoptional=1 195*8296aa0fSIan Rogers 196*8296aa0fSIan Rogers# PERF_TYPE_RAW / CPU_CLK_UNHALTED.REF_XCLK 197*8296aa0fSIan Rogers[event24:base-stat] 198*8296aa0fSIan Rogersfd=24 199*8296aa0fSIan Rogerstype=4 200*8296aa0fSIan Rogersconfig=316 201*8296aa0fSIan Rogersoptional=1 202*8296aa0fSIan Rogers 203*8296aa0fSIan Rogers# PERF_TYPE_RAW / IDQ_UOPS_NOT_DELIVERED.CORE 204*8296aa0fSIan Rogers[event25:base-stat] 205*8296aa0fSIan Rogersfd=25 206*8296aa0fSIan Rogerstype=4 207*8296aa0fSIan Rogersconfig=412 208*8296aa0fSIan Rogersoptional=1 209*8296aa0fSIan Rogers 210*8296aa0fSIan Rogers# PERF_TYPE_RAW / CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE 211*8296aa0fSIan Rogers[event26:base-stat] 212*8296aa0fSIan Rogersfd=26 213*8296aa0fSIan Rogerstype=4 214*8296aa0fSIan Rogersconfig=572 215*8296aa0fSIan Rogersoptional=1 216*8296aa0fSIan Rogers 217*8296aa0fSIan Rogers# PERF_TYPE_RAW / UOPS_RETIRED.RETIRE_SLOTS 218*8296aa0fSIan Rogers[event27:base-stat] 219*8296aa0fSIan Rogersfd=27 220*8296aa0fSIan Rogerstype=4 221*8296aa0fSIan Rogersconfig=706 222*8296aa0fSIan Rogersoptional=1 223*8296aa0fSIan Rogers 224*8296aa0fSIan Rogers# PERF_TYPE_RAW / UOPS_ISSUED.ANY 225*8296aa0fSIan Rogers[event28:base-stat] 226*8296aa0fSIan Rogersfd=28 227*8296aa0fSIan Rogerstype=4 228*8296aa0fSIan Rogersconfig=270 229*8296aa0fSIan Rogersoptional=1 230