70 	u32 val = 0;  in fsl_pcie_check_link()
74 			__indirect_read_config(hose, hose->first_busno, 0,  in fsl_pcie_check_link()
77 			early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);  in fsl_pcie_check_link()
89 	return 0;  in fsl_pcie_check_link()
140 		dev->bus_dma_limit = 0;  in fsl_pci_dma_set_mask()
152 	u32 flags = 0x80044000; /* enable & mem R/W */  in setup_one_atmu()
155 	pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",  in setup_one_atmu()
159 		flags |= 0x10000000; /* enable relaxed ordering */  in setup_one_atmu()
161 	for (i = 0; size > 0; i++) {  in setup_one_atmu()
203 	u64 mem, sz, paddr_hi = 0;  in setup_pci_atmu()
204 	u64 offset = 0, paddr_lo = ULLONG_MAX;  in setup_pci_atmu()
205 	u32 pcicsrbar = 0, pcicsrbar_sz;  in setup_pci_atmu()
223 		 * BSC9132 Rev1.0 has an issue where all the PEX inbound  in setup_pci_atmu()
224 		 * windows have implemented the default target value as 0xf  in setup_pci_atmu()
226 		 * of 0xf is reserved for local memory space. 9132 Rev1.0  in setup_pci_atmu()
227 		 * now has local memory space mapped to target 0x0 instead of  in setup_pci_atmu()
228 		 * 0xf. Hence adding a workaround to remove the target 0xf  in setup_pci_atmu()
234 	if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {  in setup_pci_atmu()
237 			start_idx = 0;  in setup_pci_atmu()
244 		out_be32(&pci->pow[i].powar, 0);  in setup_pci_atmu()
248 			out_be32(&pci->piw[i].piwar, 0);  in setup_pci_atmu()
252 	for(i = 0, j = 1; i < 3; i++) {  in setup_pci_atmu()
263 		if (n < 0 || j >= 5) {  in setup_pci_atmu()
275 			pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "  in setup_pci_atmu()
276 				 "phy base 0x%016llx.\n",  in setup_pci_atmu()
281 			out_be32(&pci->pow[j].potear, 0);  in setup_pci_atmu()
284 			out_be32(&pci->pow[j].powar, 0x80088000  in setup_pci_atmu()
299 	if (paddr_lo == 0) {  in setup_pci_atmu()
305 	early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);  in setup_pci_atmu()
306 	early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);  in setup_pci_atmu()
309 	if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||  in setup_pci_atmu()
310 		(paddr_lo > 0x100000000ull))  in setup_pci_atmu()
311 		pcicsrbar = 0x100000000ull - pcicsrbar_sz;  in setup_pci_atmu()
314 	early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);  in setup_pci_atmu()
318 	pr_info("%pOF: PCICSRBAR @ 0x%x\n", hose->dn, pcicsrbar);  in setup_pci_atmu()
354 	if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {  in setup_pci_atmu()
367 			out_be32(&pci->piw[win_idx].pitar,  0x00000000);  in setup_pci_atmu()
368 			out_be32(&pci->piw[win_idx].piwbar, 0x00000000);  in setup_pci_atmu()
373 		hose->dma_window_base_cur = 0x00000000;  in setup_pci_atmu()
393 				out_be32(&pci->piw[win_idx].pitar,  0x00000000);  in setup_pci_atmu()
410 		u64 paddr = 0;  in setup_pci_atmu()
440 		hose->dma_window_base_cur = 0x00000000;  in setup_pci_atmu()
453 		if (paddr_hi < 0xffffffffull)  in setup_pci_atmu()
459 		pr_info("%pOF: DMA window size is 0x%llx\n", hose->dn,  in setup_pci_atmu()
469 	early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);  in setup_pci_cmd()
472 	early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);  in setup_pci_cmd()
474 	cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);  in setup_pci_cmd()
479 		early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);  in setup_pci_cmd()
481 		early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);  in setup_pci_cmd()
488 	int i, is_pcie = 0, no_link;  in fsl_pcibios_fixup_bus()
494 	 * has bus->resource[0..4] set, so things are a bit more  in fsl_pcibios_fixup_bus()
499 		is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);  in fsl_pcibios_fixup_bus()
503 		for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {  in fsl_pcibios_fixup_bus()
509 			if (i == 0)  in fsl_pcibios_fixup_bus()
515 			res->start = par ? par->start : 0;  in fsl_pcibios_fixup_bus()
516 			res->end   = par ? par->end   : 0;  in fsl_pcibios_fixup_bus()
517 			res->flags = par ? par->flags : 0;  in fsl_pcibios_fixup_bus()
545 	if (of_address_to_resource(dev, 0, &rsrc)) {  in fsl_add_bridge()
554 			" bus 0\n", dev);  in fsl_add_bridge()
563 	hose->first_busno = bus_range ? bus_range[0] : 0x0;  in fsl_add_bridge()
564 	hose->last_busno = bus_range ? bus_range[1] : 0xff;  in fsl_add_bridge()
566 	pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",  in fsl_add_bridge()
573 	setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,  in fsl_add_bridge()
579 	if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {  in fsl_add_bridge()
583 		early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);  in fsl_add_bridge()
589 		early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);  in fsl_add_bridge()
598 	if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {  in fsl_add_bridge()
605 			early_read_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, &class_code);  in fsl_add_bridge()
606 			class_code &= 0xff;  in fsl_add_bridge()
608 			early_write_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, class_code);  in fsl_add_bridge()
618 #define PCI_BUS_FUNCTION 0x44  in fsl_add_bridge()
619 #define PCI_BUS_FUNCTION_MDS 0x400	/* Master disable streaming */  in fsl_add_bridge()
624 		    !early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) {  in fsl_add_bridge()
625 			early_read_config_word(hose, 0, 0,  in fsl_add_bridge()
628 			early_write_config_word(hose, 0, 0,  in fsl_add_bridge()
633 	printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "  in fsl_add_bridge()
638 	pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",  in fsl_add_bridge()
651 	return 0;  in fsl_add_bridge()
683  * With the convention of u-boot, the PCIE outbound window 0 serves
686 #define PEX_OUTWIN0_BAR		0xCA4
687 #define PEX_OUTWIN0_TAL		0xCA8
688 #define PEX_OUTWIN0_TAH		0xCAC
689 #define PEX_RC_INWIN_BASE	0xE60
690 #define PEX_RCIWARn_EN		0x1
699 	 * Workaround for the HW bug: for Type 0 configure transactions the  in mpc83xx_pcie_exclude_device()
701 	 * assumes that the device number bits are 0.  in mpc83xx_pcie_exclude_device()
705 		if (devfn & 0xf8)  in mpc83xx_pcie_exclude_device()
729 	offset &= 0xfff;  in mpc83xx_pcie_remap_cfg()
731 	/* Type 0 */  in mpc83xx_pcie_remap_cfg()
752 		val &= 0xffffff00;  in mpc83xx_pcie_write_config()
785 	pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);  in mpc83xx_pcie_setup()
794 	out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);  in mpc83xx_pcie_setup()
795 	out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);  in mpc83xx_pcie_setup()
800 	return 0;  in mpc83xx_pcie_setup()
829 	if (of_address_to_resource(dev, 0, &rsrc_reg)) {  in mpc83xx_add_bridge()
834 	memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));  in mpc83xx_add_bridge()
842 		 * 	one at 0x8500 has config space registers at 0x8300  in mpc83xx_add_bridge()
843 		 * 	one at 0x8600 has config space registers at 0x8380  in mpc83xx_add_bridge()
845 		if ((rsrc_reg.start & 0xfffff) == 0x8500)  in mpc83xx_add_bridge()
846 			rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;  in mpc83xx_add_bridge()
847 		else if ((rsrc_reg.start & 0xfffff) == 0x8600)  in mpc83xx_add_bridge()
848 			rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;  in mpc83xx_add_bridge()
851 	 * Controller at offset 0x8500 is primary  in mpc83xx_add_bridge()
853 	if ((rsrc_reg.start & 0xfffff) == 0x8500)  in mpc83xx_add_bridge()
856 		primary = 0;  in mpc83xx_add_bridge()
862 		       " bus 0\n", dev);  in mpc83xx_add_bridge()
870 	hose->first_busno = bus_range ? bus_range[0] : 0;  in mpc83xx_add_bridge()
871 	hose->last_busno = bus_range ? bus_range[1] : 0xff;  in mpc83xx_add_bridge()
879 				   rsrc_cfg.start + 4, 0);  in mpc83xx_add_bridge()
882 	printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "  in mpc83xx_add_bridge()
887 	pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",  in mpc83xx_add_bridge()
894 	return 0;  in mpc83xx_add_bridge()
911 		for (i = 0; i < 4; i++) {  in fsl_pci_immrbar_base()
930 			PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);  in fsl_pci_immrbar_base()
933 		 * For PEXCSRBAR, bit 3-0 indicate prefetchable and  in fsl_pci_immrbar_base()
943 	return 0;  in fsl_pci_immrbar_base()
961 			regs->gpr[rd] = 0xffffffff;  in mcheck_handle_load()
965 			regs->gpr[rd] = 0xffffffff;  in mcheck_handle_load()
970 			regs->gpr[rd] = 0xff;  in mcheck_handle_load()
974 			regs->gpr[rd] = 0xff;  in mcheck_handle_load()
980 			regs->gpr[rd] = 0xffff;  in mcheck_handle_load()
984 			regs->gpr[rd] = 0xffff;  in mcheck_handle_load()
989 			regs->gpr[rd] = ~0UL;  in mcheck_handle_load()
993 			regs->gpr[rd] = ~0UL;  in mcheck_handle_load()
998 			return 0;  in mcheck_handle_load()
1003 		regs->gpr[rd] = 0xffffffff;  in mcheck_handle_load()
1007 		regs->gpr[rd] = 0xffffffff;  in mcheck_handle_load()
1012 		regs->gpr[rd] = 0xff;  in mcheck_handle_load()
1016 		regs->gpr[rd] = 0xff;  in mcheck_handle_load()
1021 		regs->gpr[rd] = 0xffff;  in mcheck_handle_load()
1025 		regs->gpr[rd] = 0xffff;  in mcheck_handle_load()
1030 		regs->gpr[rd] = ~0UL;  in mcheck_handle_load()
1034 		regs->gpr[rd] = ~0UL;  in mcheck_handle_load()
1039 		return 0;  in mcheck_handle_load()
1055 		for (i = 0; i < 3; i++) {  in is_in_pci_mem_space()
1062 	return 0;  in is_in_pci_mem_space()
1069 	phys_addr_t addr = 0;  in fsl_pci_mcheck_exception()
1073 		return 0;  in fsl_pci_mcheck_exception()
1094 	return 0;  in fsl_pci_mcheck_exception()
1109 	{ .compatible = "fsl,qoriq-pcie-v3.0", },
1199 	pme_irq = irq_of_parse_and_map(hose->dn, 0);  in fsl_pci_pme_probe()
1210 	if (res < 0) {  in fsl_pci_pme_probe()
1223 	out_be32(&pci->pex_pme_mes_ier, 0);  in fsl_pci_pme_probe()
1232 	return 0;  in fsl_pci_pme_probe()
1245 	for (i = 0; i < 150; i++) {  in send_pme_turnoff_message()
1268 	return 0;  in fsl_pci_syscore_suspend()
1281 	for (i = 0; i < 150; i++) {  in fsl_pci_syscore_do_resume()
1347 	return 0;  in fsl_pci_probe()