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/freebsd/sys/dev/syscons/
H A Dscvgarndr.c54 #define SC_RENDER_DEBUG 0
108 RENDERER(mda, 0, txtrndrsw, vga_set);
109 RENDERER(cga, 0, txtrndrsw, vga_set);
110 RENDERER(ega, 0, txtrndrsw, vga_set);
111 RENDERER(vga, 0, txtrndrsw, vga_set);
161 0xC000, 0xA000, 0x9000, 0x8800, 0x8400, 0x8200, 0x8100, 0x8200,
162 0x8400, 0x8400, 0x8400, 0x9200, 0xB200, 0xA900, 0xC900, 0x8600, }, {
163 0x0000, 0x4000, 0x6000, 0x7000, 0x7800, 0x7C00, 0x7E00, 0x7C00,
164 0x7800, 0x7800, 0x7800, 0x6C00, 0x4C00, 0x4600, 0x0600, 0x0000, },
169 0xC000, 0xA000, 0x9000, 0x8800, 0x8400, 0x8200, 0x8100, 0x8700,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dfsl,cpm-enet.yaml52 reg = <0x11300 0x20 0x8400 0x100 0x11390 1>;
57 fsl,cpm-command = <0x12000300>;
/freebsd/sys/contrib/device-tree/src/c6x/
H A Dtms320c6457.dtsi9 #size-cells = <0>;
11 cpu@0 {
14 reg = <0>;
36 reg = <0x1800000 0x1000>;
41 reg = <0x01840000 0x8400>;
46 reg = <0x02880800 0x400>;
48 ti,dscr-devstat = <0x20>;
49 ti,dscr-silicon-rev = <0x18 28 0xf>;
50 ti,dscr-mac-fuse-regs = <0x114 3 4 5 6
51 0x118 0 0 1 2>;
[all …]
H A Dtms320c6474.dtsi9 #size-cells = <0>;
11 cpu@0 {
13 reg = <0>;
45 reg = <0x1800000 0x1000>;
51 reg = <0x01840000 0x8400>;
56 ti,core-mask = < 0x04 >;
57 reg = <0x2940000 0x40>;
62 ti,core-mask = < 0x02 >;
63 reg = <0x2950000 0x40>;
68 ti,core-mask = < 0x01 >;
[all …]
H A Dtms320c6455.dtsi9 #size-cells = <0>;
11 cpu@0 {
14 reg = <0>;
38 reg = <0x1800000 0x1000>;
44 reg = <0x01840000 0x8400>;
51 reg = <0x70000000 0x100>;
52 ranges = <0x2 0x0 0xa0000000 0x00000008
53 0x3 0x0 0xb0000000 0x00400000
54 0x4 0x0 0xc0000000 0x10000000
55 0x5 0x0 0xD0000000 0x10000000>;
[all …]
H A Dtms320c6472.dtsi9 #size-cells = <0>;
11 cpu@0 {
13 reg = <0>;
60 reg = <0x1800000 0x1000>;
66 reg = <0x01840000 0x8400>;
71 ti,core-mask = < 0x01 >;
72 reg = <0x25e0000 0x40>;
77 ti,core-mask = < 0x02 >;
78 reg = <0x25f0000 0x40>;
83 ti,core-mask = < 0x04 >;
[all …]
H A Dtms320c6678.dtsi9 #size-cells = <0>;
11 cpu@0 {
13 reg = <0>;
70 reg = <0x1800000 0x1000>;
76 reg = <0x01840000 0x8400>;
81 ti,core-mask = < 0x01 >;
82 reg = <0x2280000 0x40>;
87 ti,core-mask = < 0x02 >;
88 reg = <0x2290000 0x40>;
93 ti,core-mask = < 0x04 >;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dep8248e.dts26 #size-cells = <0>;
28 PowerPC,8248@0 {
30 reg = <0>;
35 timebase-frequency = <0>;
36 clock-frequency = <0>;
46 reg = <0xf0010100 0x40>;
48 ranges = <0 0 0xfc000000 0x04000000
49 1 0 0xfa000000 0x00008000>;
51 flash@0,3800000 {
53 reg = <0 0x3800000 0x800000>;
[all …]
H A Dmgcoge.dts23 #size-cells = <0>;
25 PowerPC,8247@0 {
27 reg = <0>;
32 timebase-frequency = <0>; /* Filled in by U-Boot */
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 bus-frequency = <0>; /* Filled in by U-Boot */
44 reg = <0xf0010100 0x40>;
46 ranges = <0 0 0xfe000000 0x00400000
47 1 0 0x30000000 0x00010000
48 2 0 0x40000000 0x00010000
[all …]
H A Dmpc8272ads.dts25 #size-cells = <0>;
27 PowerPC,8272@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>;
35 bus-frequency = <0>;
36 clock-frequency = <0>;
42 reg = <0x0 0x0>;
50 reg = <0xf0010100 0x40>;
52 ranges = <0x0 0x0 0xff800000 0x00800000
53 0x1 0x0 0xf4500000 0x8000
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam43xx-clocks.dtsi9 #clock-cells = <0>;
14 reg = <0x0040>;
18 #clock-cells = <0>;
23 reg = <0x0040>;
27 #clock-cells = <0>;
32 reg = <0x0040>;
36 #clock-cells = <0>;
45 #clock-cells = <0>;
54 #clock-cells = <0>;
63 #clock-cells = <0>;
[all …]
/freebsd/sys/dev/bhnd/cores/pci/
H A Dbhnd_pcireg.h32 #define BHND_PCI_DMA32_TRANSLATION 0x40000000 /**< PCI DMA32 address translation (sbtopci2) */
35 #define BHND_PCIE_DMA32_TRANSLATION 0x80000000 /**< PCIe-Gen1 DMA32 address translation (sb2pcitr…
45 #define BHND_PCI_CTL 0x000 /**< PCI core control*/
46 #define BHND_PCI_ARB_CTL 0x010 /**< PCI arbiter control */
47 #define BHND_PCI_CLKRUN_CTL 0x014 /**< PCI clckrun control (>= rev11) */
48 #define BHND_PCI_INTR_STATUS 0x020 /**< Interrupt status */
49 #define BHND_PCI_INTR_MASK 0x024 /**< Interrupt mask */
50 #define BHND_PCI_SBTOPCI_MBOX 0x028 /**< Sonics to PCI mailbox */
51 #define BHND_PCI_BCAST_ADDR 0x050 /**< Sonics broadcast address (pci) */
52 #define BHND_PCI_BCAST_DATA 0x054 /**< Sonics broadcast data (pci) */
[all …]
/freebsd/sys/dev/ata/
H A Data-all.h29 #if 0
35 #define ATA_DATA 0 /* (RW) data */
38 #define ATA_F_DMA 0x01 /* enable DMA */
39 #define ATA_F_OVL 0x02 /* enable overlap */
47 #define ATA_D_LBA 0x40 /* use LBA addressing */
48 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
53 #define ATA_E_ILI 0x01 /* illegal length */
54 #define ATA_E_NM 0x02 /* no media */
55 #define ATA_E_ABORT 0x04 /* command aborted */
56 #define ATA_E_MCR 0x08 /* media change request */
[all …]
/freebsd/sys/arm64/freescale/imx/
H A Dimx8mp_ccm.c350 FIXED(IMX8MP_CLK_DUMMY, "dummy", 0),
359 MUX(IMX8MP_AUDIO_PLL1_REF_SEL, "audio_pll1_ref_sel", pll_ref_p, 0, 0x00, 0, 2),
360 MUX(IMX8MP_AUDIO_PLL2_REF_SEL, "audio_pll2_ref_sel", pll_ref_p, 0, 0x14, 0, 2),
361 MUX(IMX8MP_VIDEO_PLL1_REF_SEL, "video_pll1_ref_sel", pll_ref_p, 0, 0x28, 0, 2),
362 MUX(IMX8MP_DRAM_PLL_REF_SEL, "dram_pll_ref_sel", pll_ref_p, 0, 0x50, 0, 2),
363 MUX(IMX8MP_GPU_PLL_REF_SEL, "gpu_pll_ref_sel", pll_ref_p, 0, 0x64, 0, 2),
364 MUX(IMX8MP_VPU_PLL_REF_SEL, "vpu_pll_ref_sel", pll_ref_p, 0, 0x74, 0, 2),
365 MUX(IMX8MP_ARM_PLL_REF_SEL, "arm_pll_ref_sel", pll_ref_p, 0, 0x84, 0, 2),
366 MUX(IMX8MP_SYS_PLL1_REF_SEL, "sys_pll1_ref_sel", pll_ref_p, 0, 0x94, 0, 2),
367 MUX(IMX8MP_SYS_PLL2_REF_SEL, "sys_pll2_ref_sel", pll_ref_p, 0, 0x104, 0, 2),
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/davinci/
H A Dda850.dtsi16 reg = <0xc0000000 0x0>;
21 #size-cells = <0>;
23 cpu: cpu@0 {
26 reg = <0>;
78 reg = <0xfffee000 0x2000>;
84 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #clock-cells = <0>;
102 reg = <0x11800000 0x40000>,
103 <0x11e00000 0x8000>,
[all …]
/freebsd/sys/dev/isp/
H A Dispmbox.h41 #define MBOX_NO_OP 0x0000
42 #define MBOX_LOAD_RAM 0x0001
43 #define MBOX_EXEC_FIRMWARE 0x0002
44 #define MBOX_LOAD_FLASH_FIRMWARE 0x0003
45 #define MBOX_WRITE_RAM_WORD 0x0004
46 #define MBOX_READ_RAM_WORD 0x0005
47 #define MBOX_MAILBOX_REG_TEST 0x0006
48 #define MBOX_VERIFY_CHECKSUM 0x0007
49 #define MBOX_ABOUT_FIRMWARE 0x0008
50 #define MBOX_LOAD_RISC_RAM_2100 0x0009
[all …]
/freebsd/sys/dev/usb/net/
H A Dif_axe.c121 * 0 2048 bytes
136 static int axe_debug = 0;
138 static SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
140 SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RWTUN, &axe_debug, 0,
149 AXE_DEV(ABOCOM, UF200, 0),
150 AXE_DEV(ACERCM, EP1427X2, 0),
152 AXE_DEV(ASIX, AX88172, 0),
158 AXE_DEV(ATEN, UC210T, 0),
160 AXE_DEV(BILLIONTON, USB2AR, 0),
162 AXE_DEV(COREGA, FETHER_USB2_TX, 0),
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32mp131.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
43 #size-cells = <0>;
44 linaro,optee-channel-id = <0>;
47 reg = <0x14>;
52 reg = <0x16>;
57 reg = <0x17>;
61 #size-cells = <0>;
63 scmi_reg11: regulator@0 {
[all …]
/freebsd/sys/dev/bge/
H A Dif_bgereg.h54 * device register space at offset 0x8000 to read any 32K chunk
60 * accessed directly. NIC memory addresses are offset by 0x01000000.
64 #define BGE_PAGE_ZERO 0x00000000
65 #define BGE_PAGE_ZERO_END 0x000000FF
66 #define BGE_SEND_RING_RCB 0x00000100
67 #define BGE_SEND_RING_RCB_END 0x000001FF
68 #define BGE_RX_RETURN_RING_RCB 0x00000200
69 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF
70 #define BGE_STATS_BLOCK 0x00000300
71 #define BGE_STATS_BLOCK_END 0x00000AFF
[all …]
/freebsd/sys/dev/bxe/
H A Decore_reg.h35 (0x1<<0)
37 (0x1<<2)
39 (0x1<<5)
41 (0x1<<3)
43 (0x1<<4)
45 (0x1<<1)
47 0x1100bcUL
49 0x1101c0UL
51 0x1101d8UL
53 0x1101d0UL
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dosprey_reg_map.h86 volatile char pad__0[0x8]; /* 0x0 - 0x8 */
87 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
88 volatile char pad__1[0x8]; /* 0xc - 0x14 */
89 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
90 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
91 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
92 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
93 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
94 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
95 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
[all …]
/freebsd/share/i18n/csmapper/BIG5/
H A DBig5EXT@E%UCS.src5 SRC_ZONE 0x81-0xA0 / 0x40-0xFE / 8
7 DST_INVALID 0xFFFE
23 0x8140 = 0x7E27
24 0x8141 = 0x7E26
25 0x8142 = 0x806E
26 0x8143 = 0x81AF
27 0x8144 = 0x81AD
28 0x8145 = 0x81AA
29 0x8146 = 0x8218
30 0x8147 = 0x856F
[all …]
H A DUCS%Big5EXT@E.src5 SRC_ZONE 0x3007 - 0x9FA5
7 DST_INVALID 0xFFFF
23 0x3007 = 0x875C
24 0x4E04 = 0x8E48
25 0x4E05 = 0x8E47
26 0x4E20 = 0x8EDE
27 0x4E21 = 0x8EDD
28 0x4E22 = 0x8EDF
29 0x4E24 = 0x8FA4
30 0x4E28 = 0x8E43
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Dreg.h8 #define R_AX_SYS_WL_EFUSE_CTRL 0x000A
11 #define R_AX_SYS_ISO_CTRL 0x0000
17 #define R_AX_SYS_FUNC_EN 0x0002
19 #define B_AX_FEN_BBRSTB BIT(0)
21 #define R_AX_SYS_PW_CTRL 0x0004
36 #define R_AX_SYS_CLK_CTRL 0x0008
39 #define R_AX_SYS_SWR_CTRL1 0x0010
42 #define R_AX_SYS_ADIE_PAD_PWR_CTRL 0x0018
46 #define R_AX_RSV_CTRL 0x001C
50 #define R_AX_AFE_LDO_CTRL 0x002
[all...]
/freebsd/share/i18n/csmapper/CNS/
H A DCNS11643-3%UCS@BMP.src5 SRC_ZONE 0x21-0x7E / 0x21-0x7E / 8
7 DST_INVALID 0xFFFE
13 # Unicode version: 5.0.0
47 0x2121 = 0x4E28
48 0x2122 = 0x4E36
49 0x2123 = 0x4E3F
50 0x2124 = 0x4E85
51 0x2125 = 0x4E05
52 0x2126 = 0x4E04
53 0x2127 = 0x5182
[all …]

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