1// SPDX-License-Identifier: GPL-2.0 2 3/ { 4 #address-cells = <1>; 5 #size-cells = <1>; 6 7 cpus { 8 #address-cells = <1>; 9 #size-cells = <0>; 10 11 cpu@0 { 12 device_type = "cpu"; 13 reg = <0>; 14 model = "ti,c64x+"; 15 }; 16 cpu@1 { 17 device_type = "cpu"; 18 reg = <1>; 19 model = "ti,c64x+"; 20 }; 21 cpu@2 { 22 device_type = "cpu"; 23 reg = <2>; 24 model = "ti,c64x+"; 25 }; 26 }; 27 28 soc { 29 compatible = "simple-bus"; 30 model = "tms320c6474"; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges; 34 35 core_pic: interrupt-controller { 36 interrupt-controller; 37 #interrupt-cells = <1>; 38 compatible = "ti,c64x+core-pic"; 39 }; 40 41 megamod_pic: interrupt-controller@1800000 { 42 compatible = "ti,c64x+megamod-pic"; 43 interrupt-controller; 44 #interrupt-cells = <1>; 45 reg = <0x1800000 0x1000>; 46 interrupt-parent = <&core_pic>; 47 }; 48 49 cache-controller@1840000 { 50 compatible = "ti,c64x+cache"; 51 reg = <0x01840000 0x8400>; 52 }; 53 54 timer3: timer@2940000 { 55 compatible = "ti,c64x+timer64"; 56 ti,core-mask = < 0x04 >; 57 reg = <0x2940000 0x40>; 58 }; 59 60 timer4: timer@2950000 { 61 compatible = "ti,c64x+timer64"; 62 ti,core-mask = < 0x02 >; 63 reg = <0x2950000 0x40>; 64 }; 65 66 timer5: timer@2960000 { 67 compatible = "ti,c64x+timer64"; 68 ti,core-mask = < 0x01 >; 69 reg = <0x2960000 0x40>; 70 }; 71 72 device-state-controller@2880800 { 73 compatible = "ti,c64x+dscr"; 74 reg = <0x02880800 0x400>; 75 76 ti,dscr-devstat = <0x004>; 77 ti,dscr-silicon-rev = <0x014 28 0xf>; 78 ti,dscr-mac-fuse-regs = <0x34 3 4 5 6 79 0x38 0 0 1 2>; 80 }; 81 82 clock-controller@29a0000 { 83 compatible = "ti,c6474-pll", "ti,c64x+pll"; 84 reg = <0x029a0000 0x200>; 85 ti,c64x+pll-bypass-delay = <120>; 86 ti,c64x+pll-reset-delay = <30000>; 87 ti,c64x+pll-lock-delay = <60000>; 88 }; 89 }; 90}; 91