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/linux/drivers/media/usb/gspca/
H A Dspca508.c23 #define CreativeVista 0
51 .priv = 0},
62 {0x0000, 0x870b},
64 {0x0020, 0x8112}, /* Video drop enable, ISO streaming disable */
65 {0x0003, 0x8111}, /* Reset compression & memory */
66 {0x0000, 0x8110}, /* Disable all outputs */
67 /* READ {0x0000, 0x8114} -> 0000: 00 */
68 {0x0000, 0x8114}, /* SW GPIO data */
69 {0x0008, 0x8110}, /* Enable charge pump output */
70 {0x0002, 0x8116}, /* 200 kHz pump clock */
[all …]
H A Dspca561.c37 #define Rev012A 0
64 .priv = 0},
87 .priv = 0},
112 #define SPCA561_INDEX_I2C_BASE 0x8800
113 #define SPCA561_SNAPBIT 0x20
114 #define SPCA561_SNAPCTRL 0x40
117 {0x0000, 0x8114}, /* Software GPIO output data */
118 {0x0001, 0x8114}, /* Software GPIO output data */
119 {0x0000, 0x8112}, /* Some kind of reset */
123 {0x0003, 0x8701}, /* PCLK clock delay adjustment */
[all …]
H A Ddtcs033.c32 if (gspca_dev->usb_err < 0) in reg_rw()
36 usb_rcvctrlpipe(udev, 0), in reg_rw()
42 if (ret < 0) { in reg_rw()
53 int i = 0; in reg_reqs()
56 while ((i < n_reqs) && (gspca_dev->usb_err >= 0)) { in reg_reqs()
63 if (gspca_dev->usb_err < 0) { in reg_reqs()
111 return 0; in sd_config()
117 return 0; in sd_init()
137 gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0); in dtcs033_pkt_scan()
141 gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0); in dtcs033_pkt_scan()
[all …]
H A Dtouptek.c24 * 0.000400, 0x0002
25 * 0.001000, 0x0005
26 * 0.005000, 0x0019
27 * 0.020000, 0x0064
28 * 0.080000, 0x0190
29 * 0.400000, 0x07D0
30 * 1.000000, 0x1388
31 * 2.000000, 0x2710
34 * 0x1000: master channel enable bit
35 * 0x007F: low gain bits
[all …]
/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,qcm2290.yaml64 reg = <0x01880000 0x60200>;
85 reg = <0x01900000 0x8200>;
91 reg = <0x04480000 0x80000>;
H A Dqcom,sm6115.yaml121 reg = <0x01880000 0x60200>;
150 reg = <0x01900000 0x8200>;
/linux/tools/perf/tests/attr/
H A Dtest-stat-default
H A Dtest-stat-detailed-1
H A Dtest-stat-detailed-2
H A Dtest-stat-detailed-3
/linux/drivers/video/fbdev/sis/
H A Dsis_accel.h39 #define PATREGSIZE 384 /* Pattern register size. 384 bytes @ 0x8300 */
40 #define BR(x) (0x8200 | (x) << 2)
41 #define PBR(x) (0x8300 | (x) << 2)
44 #define BITBLT 0x00000000 /* Blit */
45 #define COLOREXP 0x00000001 /* Color expand */
46 #define ENCOLOREXP 0x00000002 /* Enhanced color expand */
47 #define MULTIPLE_SCANLINE 0x00000003 /* ? */
48 #define LINE 0x00000004 /* Draw line */
49 #define TRAPAZOID_FILL 0x00000005 /* Fill trapezoid */
50 #define TRANSPARENT_BITBLT 0x00000006 /* Transparent Blit */
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmvme5100.dts26 #size-cells = <0>;
30 reg = <0x0>;
44 reg = <0x0 0x20000000>;
51 ranges = <0x0 0xfef80000 0x10000>;
52 reg = <0xfef80000 0x10000>;
57 reg = <0x8000 0x80>;
68 reg = <0x8200 0x80>;
78 #address-cells = <0>;
82 reg = <0xf3f80000 0x40000>;
92 reg = <0xfec00000 0x400000>;
[all …]
/linux/drivers/net/usb/
H A Dsr9800.h16 #define SR_CMD_SET_SW_MII 0x06
18 #define SR_CMD_READ_MII_REG 0x07
20 #define SR_CMD_WRITE_MII_REG 0x08
22 #define SR_CMD_SET_HW_MII 0x0a
24 #define SR_CMD_READ_EEPROM 0x0b
26 #define SR_CMD_WRITE_EEPROM 0x0c
28 #define SR_CMD_WRITE_ENABLE 0x0d
30 #define SR_CMD_WRITE_DISABLE 0x0e
32 #define SR_CMD_READ_RX_CTL 0x0f
33 #define SR_RX_CTL_PRO (1 << 0)
[all …]
/linux/drivers/media/dvb-frontends/
H A Dmxl5xx_regs.h13 #define HYDRA_INTR_STATUS_REG 0x80030008
14 #define HYDRA_INTR_MASK_REG 0x8003000C
16 #define HYDRA_CRYSTAL_SETTING 0x3FFFC5F0 /* 0 - 24 MHz & 1 - 27 MHz */
17 #define HYDRA_CRYSTAL_CAP 0x3FFFEDA4 /* 0 - 24 MHz & 1 - 27 MHz */
19 #define HYDRA_CPU_RESET_REG 0x8003003C
20 #define HYDRA_CPU_RESET_DATA 0x00000400
22 #define HYDRA_RESET_TRANSPORT_FIFO_REG 0x80030028
23 #define HYDRA_RESET_TRANSPORT_FIFO_DATA 0x00000000
25 #define HYDRA_RESET_BBAND_REG 0x80030024
26 #define HYDRA_RESET_BBAND_DATA 0x00000000
[all …]
H A Ddib3000mc.c23 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
27 MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (default: 0)");
33 } while (0)
56 { .addr = state->i2c_addr >> 1, .flags = 0, .len = 2 }, in dib3000mc_read_word()
64 return 0; in dib3000mc_read_word()
66 b[0] = (reg >> 8) | 0x80; in dib3000mc_read_word()
68 b[2] = 0; in dib3000mc_read_word()
69 b[3] = 0; in dib3000mc_read_word()
71 msg[0].buf = b; in dib3000mc_read_word()
86 .addr = state->i2c_addr >> 1, .flags = 0, .len = 4 in dib3000mc_write_word()
[all …]
/linux/drivers/media/usb/au0828/
H A Dau0828-cards.c20 au0828_set(dev, REG_000, 0x10); in hvr950q_cs5340_audio()
22 au0828_clear(dev, REG_000, 0x10); in hvr950q_cs5340_audio()
39 .tuner_addr = 0x61,
66 .tuner_addr = 0x61,
93 .tuner_addr = 0x61,
99 .tuner_addr = 0x61,
105 .tuner_addr = 0x60,
124 if (command == 0) { in au0828_tuner_callback()
131 return 0; in au0828_tuner_callback()
139 return 0; /* Should never be here */ in au0828_tuner_callback()
[all …]
/linux/drivers/video/fbdev/savage/
H A Dsavagefb.h29 #define PCI_CHIP_SAVAGE4 0x8a22
30 #define PCI_CHIP_SAVAGE3D 0x8a20
31 #define PCI_CHIP_SAVAGE3D_MV 0x8a21
32 #define PCI_CHIP_SAVAGE2000 0x9102
33 #define PCI_CHIP_SAVAGE_MX_MV 0x8c10
34 #define PCI_CHIP_SAVAGE_MX 0x8c11
35 #define PCI_CHIP_SAVAGE_IX_MV 0x8c12
36 #define PCI_CHIP_SAVAGE_IX 0x8c13
37 #define PCI_CHIP_PROSAVAGE_PM 0x8a25
38 #define PCI_CHIP_PROSAVAGE_KM 0x8a26
[all …]
/linux/sound/pci/hda/
H A Dhp_x360_helper.c10 { 0x17, 0x90170110 }, in alc295_fixup_hp_top_speakers()
14 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x0000), WRITE_COEF(0x28, 0x0000), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers()
15 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x003f), WRITE_COEF(0x28, 0x1000), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers()
16 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x0004), WRITE_COEF(0x28, 0x0600), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers()
17 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x006a), WRITE_COEF(0x28, 0x0006), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers()
18 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x006c), WRITE_COEF(0x28, 0xc0c0), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers()
19 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x0008), WRITE_COEF(0x28, 0xb000), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers()
20 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x002e), WRITE_COEF(0x28, 0x0800), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers()
21 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x006a), WRITE_COEF(0x28, 0x00c1), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers()
22 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x006c), WRITE_COEF(0x28, 0x0320), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers()
[all …]
/linux/drivers/edac/
H A Dr82600_edac.c47 #define R82600_BRIDGE_ID 0x8200
49 /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
50 #define R82600_DRAMC 0x57 /* Various SDRAM related control bits
55 * 5 ECC Enable: 1=ECC 0=noECC
59 * 1:0 SDRAM Refresh Rate: 00=Disabled
64 #define R82600_SDRAMC 0x76 /* "SDRAM Control Register"
74 * 1=Drive ECC bits to 0 during
77 * 0=Normal ECC functioning
81 * 2 CAS# Latency 0=3clks 1=2clks
83 * 1 RAS# to CAS# Delay 0=3 1=2
[all …]
/linux/sound/soc/codecs/
H A Drt1305.c31 #define RT1305_PR_RANGE_BASE (0xff + 1)
32 #define RT1305_PR_SPACING 0x100
34 #define RT1305_PR_BASE (RT1305_PR_RANGE_BASE + (0 * RT1305_PR_SPACING))
41 .range_max = RT1305_PR_BASE + 0xff,
43 .selector_mask = 0xff,
44 .selector_shift = 0x0,
46 .window_len = 0x1,
53 { RT1305_PR_BASE + 0xcf, 0x5548 },
54 { RT1305_PR_BASE + 0x5d, 0x0442 },
55 { RT1305_PR_BASE + 0xc1, 0x0320 },
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dvlv_dpio_phy_regs.h11 #define _VLV_CMN(dw) (0x8100 + (dw) * 4)
12 #define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4)
13 #define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */
14 #define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4)
15 #define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */
16 #define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + (dw) * 4)
17 #define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4)
18 #define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4)
19 #define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4)
20 #define _VLV_TX_GRP(ch, dw) (0x8280 + (ch) * 0x200 + (dw) * 4)
[all …]
/linux/arch/mips/include/asm/
H A Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
/linux/drivers/gpu/drm/i915/
H A Dintel_uncore.c67 uncore->debug->unclaimed_mmio_check = 0; in mmio_debug_suspend()
116 if (id >= 0 && id < FW_DOMAIN_ID_COUNT) in intel_uncore_forcewake_domain_to_str()
138 fw_clear(d, 0xefff); in fw_domain_reset()
140 fw_clear(d, 0xffff); in fw_domain_reset()
168 return __wait_for_ack(d, ack, 0); in wait_ack_clear()
184 if (fw_ack(d) == ~0) { in fw_domain_wait_ack_clear()
186 "%s: MMIO unreliable (forcewake register returns 0xFFFFFFFF)!\n", in fw_domain_wait_ack_clear()
199 ACK_CLEAR = 0,
208 const u32 value = type == ACK_SET ? ack_bit : 0; in fw_domain_wait_ack_with_fallback()
241 "%s had to use fallback to %s ack, 0x%x (passes %u)\n", in fw_domain_wait_ack_with_fallback()
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dlontium-lt9211.c31 #define REG_PAGE_CONTROL 0xff
32 #define REG_CHIPID0 0x8100
33 #define REG_CHIPID0_VALUE 0x18
34 #define REG_CHIPID1 0x8101
35 #define REG_CHIPID1_VALUE 0x01
36 #define REG_CHIPID2 0x8102
37 #define REG_CHIPID2_VALUE 0xe3
39 #define REG_DSI_LANE 0xd000
40 /* DSI lane count - 0 means 4 lanes ; 1, 2, 3 means 1, 2, 3 lanes. */
56 regmap_reg_range(0xff, 0xff),
[all …]
/linux/drivers/net/ethernet/freescale/enetc/
H A Denetc_hw.h12 #define ENETC_DEV_ID_PF 0xe100
13 #define ENETC_DEV_ID_VF 0xef00
14 #define ENETC_DEV_ID_PTP 0xee02
17 #define ENETC_BAR_REGS 0
19 /** SI regs, offset: 0h */
20 #define ENETC_SIMR 0
22 #define ENETC_SIMR_RSSE BIT(0)
23 #define ENETC_SICTR0 0x18
24 #define ENETC_SICTR1 0x1c
25 #define ENETC_SIPCAPR0 0x20
[all …]

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