47 #define R82600_BRIDGE_ID  0x8200
49 /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
50 #define R82600_DRAMC	0x57	/* Various SDRAM related control bits
55 				 * 5    ECC Enable: 1=ECC 0=noECC
59 				 * 1:0  SDRAM Refresh Rate: 00=Disabled
64 #define R82600_SDRAMC	0x76	/* "SDRAM Control Register"
74 				 *        1=Drive ECC bits to 0 during
77 				 *        0=Normal ECC functioning
81 				 * 2    CAS# Latency 0=3clks 1=2clks
83 				 * 1    RAS# to CAS# Delay 0=3 1=2
85 				 * 0    RAS# Precharge     0=3 1=2
88 #define R82600_EAP	0x80	/* ECC Error Address Pointer Register
91 				 *        0=Scrub on corrected read
100 				 *        1=enable 0=disable
105 				 *        0=NMI not triggered
109 				 *        read 0=no MBE, or SBE occurred first
112 				 *        write 0=NOP
116 				 *        read 0=no SBE, or MBE occurred first
119 				 *        write 0=NOP
122 #define R82600_DRBA	0x60	/* + 0x60..0x63 SDRAM Row Boundary Address
125 				 * 7:0  Address lines 30:24 - upper limit of
145 	if (info->eapr & BIT(0))  in r82600_get_error_info()
148 				 ((u32) BIT(0) & (u32) BIT(1)),  in r82600_get_error_info()
149 				 ((u32) BIT(0) & (u32) BIT(1)));  in r82600_get_error_info()
154 				 ((u32) BIT(0) & (u32) BIT(1)),  in r82600_get_error_info()
155 				 ((u32) BIT(0) & (u32) BIT(1)));  in r82600_get_error_info()
166 	error_found = 0;  in r82600_process_error_info()
169 	eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13;  in r82600_process_error_info()
171 	syndrome = (info->eapr >> 4) & 0xFF;  in r82600_process_error_info()
177 	if (info->eapr & BIT(0)) {	/* CE? */  in r82600_process_error_info()
182 					     page, 0, syndrome,  in r82600_process_error_info()
184 					     0, -1,  in r82600_process_error_info()
194 					     page, 0, 0,  in r82600_process_error_info()
196 					     0, -1,  in r82600_process_error_info()
228 	row_high_limit_last = 0;  in r82600_init_csrows()
230 	for (index = 0; index < mci->nr_csrows; index++) {  in r82600_init_csrows()
232 		dimm = csrow->channels[0]->dimm;  in r82600_init_csrows()
237 		edac_dbg(1, "Row=%d DRBA = %#0x\n", index, drbar);  in r82600_init_csrows()
240 /*		row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */  in r82600_init_csrows()
242 		edac_dbg(1, "Row=%d, Boundary Address=%#0x, Last = %#0x\n",  in r82600_init_csrows()
278 	edac_dbg(0, "\n");  in r82600_probe1()
282 	sdram_refresh_rate = dramcr & (BIT(0) | BIT(1));  in r82600_probe1()
283 	edac_dbg(2, "sdram refresh rate = %#0x\n", sdram_refresh_rate);  in r82600_probe1()
284 	edac_dbg(2, "DRAMC register = %#0x\n", dramcr);  in r82600_probe1()
285 	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;  in r82600_probe1()
286 	layers[0].size = R82600_NR_CSROWS;  in r82600_probe1()
287 	layers[0].is_virt_csrow = true;  in r82600_probe1()
291 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);  in r82600_probe1()
295 	edac_dbg(0, "mci = %p\n", mci);  in r82600_probe1()
311 			edac_dbg(3, "mci = %p - Scrubbing disabled! EAP: %#0x\n",  in r82600_probe1()
325 	 * type of memory controller.  The ID is therefore hardcoded to 0.  in r82600_probe1()
351 	return 0;  in r82600_probe1()
358 /* returns count (>= 0), or negative on error */
362 	edac_dbg(0, "\n");  in r82600_init_one()
372 	edac_dbg(0, "\n");  in r82600_remove_one()
388 	 0,
389 	 }			/* 0 terminated list. */
426 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");