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/linux/drivers/clk/qcom/
H A Dvideocc-sm8450.c35 { 249600000, 2020000000, 0 },
40 .l = 0x0044001e,
41 .alpha = 0x0,
42 .config_ctl_val = 0x20485699,
43 .config_ctl_hi_val = 0x00182261,
44 .config_ctl_hi1_val = 0x32aa299c,
45 .user_ctl_val = 0x00000000,
46 .user_ctl_hi_val = 0x00000805,
51 .l = 0x1e,
52 .alpha = 0x0,
[all …]
H A Dvideocc-sa8775p.c43 { 249600000, 2020000000, 0 },
47 .l = 0x39,
48 .alpha = 0x3000,
49 .config_ctl_val = 0x20485699,
50 .config_ctl_hi_val = 0x00182261,
51 .config_ctl_hi1_val = 0x32aa299c,
52 .user_ctl_val = 0x00000000,
53 .user_ctl_hi_val = 0x00400805,
57 .offset = 0x0,
74 .l = 0x39,
[all …]
H A Ddispcc-sm4450.c46 { 249600000, 2020000000, 0 },
51 .l = 0x1f,
52 .alpha = 0x4000,
53 .config_ctl_val = 0x20485699,
54 .config_ctl_hi_val = 0x00182261,
55 .config_ctl_hi1_val = 0x32aa299c,
56 .user_ctl_val = 0x00000000,
57 .user_ctl_hi_val = 0x00000805,
61 .offset = 0x0,
78 .offset = 0x1000,
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Damlogic,meson8-pinctrl-cbus.yaml32 "^bank@[0-9a-f]+$":
65 reg = <0x80b0 0x28>,
66 <0x80e8 0x18>,
67 <0x8120 0x18>,
68 <0x8030 0x30>;
72 gpio-ranges = <&pinctrl_cbus 0 0 120>;
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drpm.h14 #define PCI_DEVID_CN10K_RPM 0xA060
15 #define PCI_SUBSYS_DEVID_CNF10KB_RPM 0xBC00
16 #define PCI_DEVID_CN10KB_RPM 0xA09F
19 #define RPMX_CMRX_CFG 0x00
20 #define RPMX_CMR_GLOBAL_CFG 0x08
24 #define RPMX_CMRX_RX_ID_MAP 0x80
25 #define RPMX_CMRX_SW_INT 0x180
26 #define RPMX_CMRX_SW_INT_W1S 0x188
27 #define RPMX_CMRX_SW_INT_ENA_W1S 0x198
28 #define RPMX_CMRX_LINK_CFG 0x1070
[all …]
/linux/include/linux/mfd/mt6332/
H A Dregisters.h10 #define MT6332_HWCID 0x8000
11 #define MT6332_SWCID 0x8002
12 #define MT6332_TOP_CON 0x8004
13 #define MT6332_DDR_VREF_AP_CON 0x8006
14 #define MT6332_DDR_VREF_DQ_CON 0x8008
15 #define MT6332_DDR_VREF_CA_CON 0x800A
16 #define MT6332_TEST_OUT 0x800C
17 #define MT6332_TEST_CON0 0x800E
18 #define MT6332_TEST_CON1 0x8010
19 #define MT6332_TESTMODE_SW 0x8012
[all …]
/linux/drivers/net/phy/
H A Dmicrochip_t1.c14 #define PHY_ID_LAN87XX 0x0007c150
15 #define PHY_ID_LAN937X 0x0007c180
16 #define PHY_ID_LAN887X 0x0007c1f0
19 #define LAN87XX_EXT_REG_CTL (0x14)
20 #define LAN87XX_EXT_REG_CTL_RD_CTL (0x1000)
21 #define LAN87XX_EXT_REG_CTL_WR_CTL (0x0800)
23 #define LAN87XX_REG_ADDR_MASK GENMASK(7, 0)
26 #define LAN87XX_EXT_REG_RD_DATA (0x15)
29 #define LAN87XX_EXT_REG_WR_DATA (0x16)
32 #define LAN87XX_INTERRUPT_SOURCE (0x18)
[all …]
/linux/drivers/net/ethernet/freescale/
H A Dgianfar.c127 struct gfar __iomem *regs = priv->gfargrp[0].regs; in gfar_init_tx_rx_base()
132 for (i = 0; i < priv->num_tx_queues; i++) { in gfar_init_tx_rx_base()
138 for (i = 0; i < priv->num_rx_queues; i++) { in gfar_init_tx_rx_base()
146 struct gfar __iomem *regs = priv->gfargrp[0].regs; in gfar_init_rqprm()
151 for (i = 0; i < priv->num_rx_queues; i++) { in gfar_init_rqprm()
161 priv->uses_rxfcb = 0; in gfar_rx_offload_en()
172 struct gfar __iomem *regs = priv->gfargrp[0].regs; in gfar_mac_rx_config()
173 u32 rctrl = 0; in gfar_mac_rx_config()
216 struct gfar __iomem *regs = priv->gfargrp[0].regs; in gfar_mac_tx_config()
217 u32 tctrl = 0; in gfar_mac_tx_config()
[all …]
/linux/drivers/net/ethernet/realtek/
H A Dr8169_phy_config.c23 int oldpage = phy_select_page(phydev, 0x0007); in r8168d_modify_extpage()
25 __phy_write(phydev, 0x1e, extpage); in r8168d_modify_extpage()
28 phy_restore_page(phydev, oldpage, 0); in r8168d_modify_extpage()
34 int oldpage = phy_select_page(phydev, 0x0005); in r8168d_phy_param()
36 __phy_write(phydev, 0x05, parm); in r8168d_phy_param()
37 __phy_modify(phydev, 0x06, mask, val); in r8168d_phy_param()
39 phy_restore_page(phydev, oldpage, 0); in r8168d_phy_param()
45 int oldpage = phy_select_page(phydev, 0x0a43); in r8168g_phy_param()
47 __phy_write(phydev, 0x13, parm); in r8168g_phy_param()
48 __phy_modify(phydev, 0x14, mask, val); in r8168g_phy_param()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_9_0_offset.h29 // base address: 0x0
30 …BIF_BX0_PCIE_INDEX 0x000c
31 …e regBIF_BX0_PCIE_INDEX_BASE_IDX 0
32 …BIF_BX0_PCIE_DATA 0x000d
33 …e regBIF_BX0_PCIE_DATA_BASE_IDX 0
34 …BIF_BX0_PCIE_INDEX2 0x000e
35 …e regBIF_BX0_PCIE_INDEX2_BASE_IDX 0
36 …BIF_BX0_PCIE_DATA2 0x000f
37 …e regBIF_BX0_PCIE_DATA2_BASE_IDX 0
38 …BIF_BX0_PCIE_INDEX_HI 0x0010
[all …]
H A Dnbio_4_3_0_offset.h29 // base address: 0x0
30 …BIF_BX0_PCIE_INDEX 0x000c
31 …e regBIF_BX0_PCIE_INDEX_BASE_IDX 0
32 …BIF_BX0_PCIE_DATA 0x000d
33 …e regBIF_BX0_PCIE_DATA_BASE_IDX 0
34 …BIF_BX0_PCIE_INDEX2 0x000e
35 …e regBIF_BX0_PCIE_INDEX2_BASE_IDX 0
36 …BIF_BX0_PCIE_DATA2 0x000f
37 …e regBIF_BX0_PCIE_DATA2_BASE_IDX 0
38 …BIF_BX0_PCIE_INDEX_HI 0x0010
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_3_1_offset.h28 // base address: 0x0
29 …IRQ_BRIDGE_CNTL 0x003e
33 // base address: 0x0
34 …BIF_CFG_DEV0_EPF0_VENDOR_ID 0x0000
35 …BIF_CFG_DEV0_EPF0_DEVICE_ID 0x0002
36 …BIF_CFG_DEV0_EPF0_COMMAND 0x0004
37 …BIF_CFG_DEV0_EPF0_STATUS 0x0006
38 …BIF_CFG_DEV0_EPF0_REVISION_ID 0x0008
39 …BIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x0009
40 …BIF_CFG_DEV0_EPF0_SUB_CLASS 0x000a
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Dreg.h8 #define R_AX_SYS_WL_EFUSE_CTRL 0x000A
11 #define R_AX_SYS_ISO_CTRL 0x0000
17 #define R_AX_SYS_FUNC_EN 0x0002
19 #define B_AX_FEN_BBRSTB BIT(0)
21 #define R_AX_SYS_PW_CTRL 0x0004
36 #define R_AX_SYS_CLK_CTRL 0x0008
39 #define R_AX_SYS_SWR_CTRL1 0x0010
42 #define R_AX_SYS_ADIE_PAD_PWR_CTRL 0x0018
46 #define R_AX_RSV_CTRL 0x001C
50 #define R_AX_AFE_LDO_CTRL 0x0020
[all …]
H A Drtw8851b_table.c10 {0x704, 0x601E0500},
11 {0x4000, 0x00000000},
12 {0x4004, 0xCA014000},
13 {0x4008, 0xC751D4F0},
14 {0x400C, 0x44511475},
15 {0x4010, 0x00000000},
16 {0x4014, 0x00000000},
17 {0x47BC, 0x00000380},
18 {0x4018, 0x4F4C084B},
19 {0x401C, 0x084A4E52},
[all …]
H A Drtw8852b_table.c10 {0x704, 0x601E0100},
11 {0x4000, 0x00000000},
12 {0x4004, 0xCA014000},
13 {0x4008, 0xC751D4F0},
14 {0x400C, 0x44511475},
15 {0x4010, 0x00000000},
16 {0x4014, 0x00000000},
17 {0x4018, 0x4F4C084B},
18 {0x401C, 0x084A4E52},
19 {0x4020, 0x4D504E4B},
[all …]
H A Drtw8852c_table.c10 {0xF0FF0000, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03400FF, 0x00000002},
13 {0xF03500FF, 0x00000003},
14 {0xF03600FF, 0x00000004},
15 {0x70C, 0x00000020},
16 {0x704, 0x601E0100},
17 {0x4000, 0x00000000},
18 {0x4004, 0xCA014000},
19 {0x4008, 0xC751D4F0},
[all …]
H A Drtw8852a_table.c10 {0xF0FF0001, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03500FF, 0x00000002},
13 {0xF03200FF, 0x00000003},
14 {0xF03400FF, 0x00000004},
15 {0xF03600FF, 0x00000005},
16 {0x704, 0x601E0100},
17 {0x714, 0x00000000},
18 {0x718, 0x13332333},
19 {0x714, 0x00010000},
[all …]
/linux/drivers/net/usb/
H A Dr8152.c46 #define PLA_IDR 0xc000
47 #define PLA_RCR 0xc010
48 #define PLA_RCR1 0xc012
49 #define PLA_RMS 0xc016
50 #define PLA_RXFIFO_CTRL0 0xc0a0
51 #define PLA_RXFIFO_FULL 0xc0a2
52 #define PLA_RXFIFO_CTRL1 0xc0a4
53 #define PLA_RX_FIFO_FULL 0xc0a6
54 #define PLA_RXFIFO_CTRL2 0xc0a8
55 #define PLA_RX_FIFO_EMPTY 0xc0aa
[all …]
/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da6xx.xml25 <value name="TILE6_LINEAR" value="0"/>
31 <value value="0x02" name="FMT6_A8_UNORM"/>
32 <value value="0x03" name="FMT6_8_UNORM"/>
33 <value value="0x04" name="FMT6_8_SNORM"/>
34 <value value="0x05" name="FMT6_8_UINT"/>
35 <value value="0x06" name="FMT6_8_SINT"/>
37 <value value="0x08" name="FMT6_4_4_4_4_UNORM"/>
38 <value value="0x0a" name="FMT6_5_5_5_1_UNORM"/>
39 <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only -->
40 <value value="0x0e" name="FMT6_5_6_5_UNORM"/>
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_reg.h26 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
27 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
28 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
29 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
30 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
31 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
33 #define ATC_REG_ATC_INIT_ARRAY 0x1100b8
35 #define ATC_REG_ATC_INIT_DONE 0x1100bc
36 /* [RC 6] Interrupt register #0 read clear */
37 #define ATC_REG_ATC_INT_STS_CLR 0x1101c0
[all …]
H A Dbnx2x_link.c40 #define I2C_BSC0 0
54 #define NIG_LATCH_BC_ENABLE_MI_INT 0
152 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
153 #define SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0
154 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
155 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
156 #define SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
159 #define SFP_EEPROM_10G_COMP_CODE_ADDR 0x3
164 #define SFP_EEPROM_1G_COMP_CODE_ADDR 0x6
165 #define SFP_EEPROM_1G_COMP_CODE_SX (1<<0)
[all …]
/linux/fs/nls/
H A Dnls_cp936.c17 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x00-0x07 */
18 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x08-0x0F */
19 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x10-0x17 */
20 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x18-0x1F */
21 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x20-0x27 */
22 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x28-0x2F */
23 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x30-0x37 */
24 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x38-0x3F */
25 0x4E02,0x4E04,0x4E05,0x4E06,0x4E0F,0x4E12,0x4E17,0x4E1F,/* 0x40-0x47 */
26 0x4E20,0x4E21,0x4E23,0x4E26,0x4E29,0x4E2E,0x4E2F,0x4E31,/* 0x48-0x4F */
[all …]