Lines Matching +full:0 +full:x80b0
35 { 249600000, 2020000000, 0 },
40 .l = 0x0044001e,
41 .alpha = 0x0,
42 .config_ctl_val = 0x20485699,
43 .config_ctl_hi_val = 0x00182261,
44 .config_ctl_hi1_val = 0x32aa299c,
45 .user_ctl_val = 0x00000000,
46 .user_ctl_hi_val = 0x00000805,
51 .l = 0x1e,
52 .alpha = 0x0,
53 .config_ctl_val = 0x20485699,
54 .config_ctl_hi_val = 0x00182261,
55 .config_ctl_hi1_val = 0x82aa299c,
56 .test_ctl_val = 0x00000000,
57 .test_ctl_hi_val = 0x00000003,
58 .test_ctl_hi1_val = 0x00009000,
59 .test_ctl_hi2_val = 0x00000034,
60 .user_ctl_val = 0x00000000,
61 .user_ctl_hi_val = 0x00000005,
65 .offset = 0x0,
83 .l = 0x0044002b,
84 .alpha = 0xc000,
85 .config_ctl_val = 0x20485699,
86 .config_ctl_hi_val = 0x00182261,
87 .config_ctl_hi1_val = 0x32aa299c,
88 .user_ctl_val = 0x00000000,
89 .user_ctl_hi_val = 0x00000805,
94 .l = 0x2b,
95 .alpha = 0xc000,
96 .config_ctl_val = 0x20485699,
97 .config_ctl_hi_val = 0x00182261,
98 .config_ctl_hi1_val = 0x82aa299c,
99 .test_ctl_val = 0x00000000,
100 .test_ctl_hi_val = 0x00000003,
101 .test_ctl_hi1_val = 0x00009000,
102 .test_ctl_hi2_val = 0x00000034,
103 .user_ctl_val = 0x00000000,
104 .user_ctl_hi_val = 0x00000005,
108 .offset = 0x1000,
125 { P_BI_TCXO, 0 },
135 { P_BI_TCXO, 0 },
145 F(576000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
146 F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
147 F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
148 F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
149 F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
154 .cmd_rcgr = 0x8000,
155 .mnd_width = 0,
169 F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
170 F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
171 F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
172 F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
173 F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
178 .cmd_rcgr = 0x8018,
179 .mnd_width = 0,
193 .reg = 0x80b8,
194 .shift = 0,
208 .reg = 0x806c,
209 .shift = 0,
223 .reg = 0x80dc,
224 .shift = 0,
238 .reg = 0x8094,
239 .shift = 0,
253 .halt_reg = 0x80b0,
255 .hwcg_reg = 0x80b0,
258 .enable_reg = 0x80b0,
259 .enable_mask = BIT(0),
273 .halt_reg = 0x8064,
276 .enable_reg = 0x8064,
277 .enable_mask = BIT(0),
291 .halt_reg = 0x80d4,
293 .hwcg_reg = 0x80d4,
296 .enable_reg = 0x80d4,
297 .enable_mask = BIT(0),
311 .halt_reg = 0x808c,
314 .enable_reg = 0x808c,
315 .enable_mask = BIT(0),
329 .gdscr = 0x804c,
330 .en_rest_wait_val = 0x2,
331 .en_few_wait_val = 0x2,
332 .clk_dis_wait_val = 0x6,
341 .gdscr = 0x809c,
342 .en_rest_wait_val = 0x2,
343 .en_few_wait_val = 0x2,
344 .clk_dis_wait_val = 0x6,
354 .gdscr = 0x8074,
355 .en_rest_wait_val = 0x2,
356 .en_few_wait_val = 0x2,
357 .clk_dis_wait_val = 0x6,
366 .gdscr = 0x80c0,
367 .en_rest_wait_val = 0x2,
368 .en_few_wait_val = 0x2,
369 .clk_dis_wait_val = 0x6,
401 [CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80e0 },
402 [CVP_VIDEO_CC_MVS0_BCR] = { 0x8098 },
403 [CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
404 [CVP_VIDEO_CC_MVS1_BCR] = { 0x80bc },
405 [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8070 },
406 [VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 },
407 [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x808c, .bit = 2, .udelay = 1000 },
414 .max_register = 0x9f4c,
469 qcom_branch_set_clk_en(regmap, 0x80e4); /* VIDEO_CC_AHB_CLK */ in video_cc_sm8450_probe()
470 qcom_branch_set_clk_en(regmap, 0x8130); /* VIDEO_CC_SLEEP_CLK */ in video_cc_sm8450_probe()
471 qcom_branch_set_clk_en(regmap, 0x8114); /* VIDEO_CC_XO_CLK */ in video_cc_sm8450_probe()