Lines Matching +full:0 +full:x80b0
43 { 249600000, 2020000000, 0 },
47 .l = 0x39,
48 .alpha = 0x3000,
49 .config_ctl_val = 0x20485699,
50 .config_ctl_hi_val = 0x00182261,
51 .config_ctl_hi1_val = 0x32aa299c,
52 .user_ctl_val = 0x00000000,
53 .user_ctl_hi_val = 0x00400805,
57 .offset = 0x0,
74 .l = 0x39,
75 .alpha = 0x3000,
76 .config_ctl_val = 0x20485699,
77 .config_ctl_hi_val = 0x00182261,
78 .config_ctl_hi1_val = 0x32aa299c,
79 .user_ctl_val = 0x00000000,
80 .user_ctl_hi_val = 0x00400805,
84 .offset = 0x1000,
101 { P_BI_TCXO_AO, 0 },
109 { P_BI_TCXO, 0 },
119 { P_BI_TCXO, 0 },
129 { P_SLEEP_CLK, 0 },
137 F(19200000, P_BI_TCXO_AO, 1, 0, 0),
142 .cmd_rcgr = 0x8030,
143 .mnd_width = 0,
157 F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
158 F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
159 F(1599000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
160 F(1680000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
165 .cmd_rcgr = 0x8000,
166 .mnd_width = 0,
180 F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
181 F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
182 F(1600000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
183 F(1800000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
188 .cmd_rcgr = 0x8018,
189 .mnd_width = 0,
203 F(32000, P_SLEEP_CLK, 1, 0, 0),
208 .cmd_rcgr = 0x812c,
209 .mnd_width = 0,
223 .cmd_rcgr = 0x8110,
224 .mnd_width = 0,
238 .reg = 0x80b8,
239 .shift = 0,
253 .reg = 0x806c,
254 .shift = 0,
268 .reg = 0x80dc,
269 .shift = 0,
283 .reg = 0x8094,
284 .shift = 0,
298 .reg = 0x8108,
299 .shift = 0,
308 .halt_reg = 0x80b0,
310 .hwcg_reg = 0x80b0,
313 .enable_reg = 0x80b0,
314 .enable_mask = BIT(0),
328 .halt_reg = 0x8064,
331 .enable_reg = 0x8064,
332 .enable_mask = BIT(0),
346 .halt_reg = 0x80d4,
348 .hwcg_reg = 0x80d4,
351 .enable_reg = 0x80d4,
352 .enable_mask = BIT(0),
366 .halt_reg = 0x808c,
369 .enable_reg = 0x808c,
370 .enable_mask = BIT(0),
384 .halt_reg = 0x9000,
387 .enable_reg = 0x9000,
388 .enable_mask = BIT(0),
402 .halt_reg = 0x810c,
405 .enable_reg = 0x810c,
406 .enable_mask = BIT(0),
420 .gdscr = 0x804c,
421 .en_rest_wait_val = 0x2,
422 .en_few_wait_val = 0x2,
423 .clk_dis_wait_val = 0x6,
432 .gdscr = 0x809c,
433 .en_rest_wait_val = 0x2,
434 .en_few_wait_val = 0x2,
435 .clk_dis_wait_val = 0x6,
445 .gdscr = 0x8074,
446 .en_rest_wait_val = 0x2,
447 .en_few_wait_val = 0x2,
448 .clk_dis_wait_val = 0x6,
457 .gdscr = 0x80c0,
458 .en_rest_wait_val = 0x2,
459 .en_few_wait_val = 0x2,
460 .clk_dis_wait_val = 0x6,
498 [VIDEO_CC_INTERFACE_BCR] = { 0x80e8 },
499 [VIDEO_CC_MVS0_BCR] = { 0x8098 },
500 [VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
501 [VIDEO_CC_MVS0C_BCR] = { 0x8048 },
502 [VIDEO_CC_MVS1_BCR] = { 0x80bc },
503 [VIDEO_CC_MVS1C_CLK_ARES] = { 0x808c, 2 },
504 [VIDEO_CC_MVS1C_BCR] = { 0x8070 },
511 .max_register = 0xb000,
554 qcom_branch_set_clk_en(regmap, 0x80ec); /* VIDEO_CC_AHB_CLK */ in video_cc_sa8775p_probe()
555 qcom_branch_set_clk_en(regmap, 0x8144); /* VIDEO_CC_SLEEP_CLK */ in video_cc_sa8775p_probe()
556 qcom_branch_set_clk_en(regmap, 0x8128); /* VIDEO_CC_XO_CLK */ in video_cc_sa8775p_probe()