Lines Matching +full:0 +full:x80b0
15 #define PHY_ID_LAN87XX 0x0007c150
16 #define PHY_ID_LAN937X 0x0007c180
17 #define PHY_ID_LAN887X 0x0007c1f0
19 #define MCHP_RDS_PTP_LTC_BASE_ADDR 0xe000
20 #define MCHP_RDS_PTP_PORT_BASE_ADDR (MCHP_RDS_PTP_LTC_BASE_ADDR + 0x800)
23 #define LAN87XX_EXT_REG_CTL (0x14)
24 #define LAN87XX_EXT_REG_CTL_RD_CTL (0x1000)
25 #define LAN87XX_EXT_REG_CTL_WR_CTL (0x0800)
27 #define LAN87XX_REG_ADDR_MASK GENMASK(7, 0)
30 #define LAN87XX_EXT_REG_RD_DATA (0x15)
33 #define LAN87XX_EXT_REG_WR_DATA (0x16)
36 #define LAN87XX_INTERRUPT_SOURCE (0x18)
37 #define LAN87XX_INTERRUPT_SOURCE_2 (0x08)
40 #define LAN87XX_INTERRUPT_MASK (0x19)
41 #define LAN87XX_MASK_LINK_UP (0x0004)
42 #define LAN87XX_MASK_LINK_DOWN (0x0002)
44 #define LAN87XX_INTERRUPT_MASK_2 (0x09)
48 #define LAN87XX_CTRL_1 (0x11)
49 #define LAN87XX_MASK_RGMII_TXC_DLY_EN (0x4000)
50 #define LAN87XX_MASK_RGMII_RXC_DLY_EN (0x2000)
53 #define PHYACC_ATTR_MODE_READ 0
58 #define PHYACC_ATTR_BANK_SMI 0
66 #define LAN87XX_CABLE_TEST_OK 0
71 #define T1_AFE_PORT_CFG1_REG 0x0B
72 #define T1_POWER_DOWN_CONTROL_REG 0x1A
73 #define T1_SLV_FD_MULT_CFG_REG 0x18
74 #define T1_CDR_CFG_PRE_LOCK_REG 0x05
75 #define T1_CDR_CFG_POST_LOCK_REG 0x06
76 #define T1_LCK_STG2_MUFACT_CFG_REG 0x1A
77 #define T1_LCK_STG3_MUFACT_CFG_REG 0x1B
78 #define T1_POST_LCK_MUFACT_CFG_REG 0x1C
79 #define T1_TX_RX_FIFO_CFG_REG 0x02
80 #define T1_TX_LPF_FIR_CFG_REG 0x55
81 #define T1_COEF_CLK_PWR_DN_CFG 0x04
82 #define T1_COEF_RW_CTL_CFG 0x0D
83 #define T1_SQI_CONFIG_REG 0x2E
84 #define T1_SQI_CONFIG2_REG 0x4A
85 #define T1_DCQ_SQI_REG 0xC3
87 #define T1_MDIO_CONTROL2_REG 0x10
88 #define T1_INTERRUPT_SOURCE_REG 0x18
89 #define T1_INTERRUPT2_SOURCE_REG 0x08
90 #define T1_EQ_FD_STG1_FRZ_CFG 0x69
91 #define T1_EQ_FD_STG2_FRZ_CFG 0x6A
92 #define T1_EQ_FD_STG3_FRZ_CFG 0x6B
93 #define T1_EQ_FD_STG4_FRZ_CFG 0x6C
94 #define T1_EQ_WT_FD_LCK_FRZ_CFG 0x6D
95 #define T1_PST_EQ_LCK_STG1_FRZ_CFG 0x6E
97 #define T1_MODE_STAT_REG 0x11
98 #define T1_LINK_UP_MSK BIT(0)
101 #define LAN87XX_MAX_SQI 0x07
104 #define LAN887X_PMA_EXT_ABILITY_2 0x12
106 #define LAN887X_PMA_EXT_ABILITY_2_100T1 BIT(0)
109 #define LAN887x_CDR_CONFIG1_100 0x0405
110 #define LAN887x_LOCK1_EQLSR_CONFIG_100 0x0411
111 #define LAN887x_SLV_HD_MUFAC_CONFIG_100 0x0417
112 #define LAN887x_PLOCK_MUFAC_CONFIG_100 0x041c
113 #define LAN887x_PROT_DISABLE_100 0x0425
114 #define LAN887x_KF_LOOP_SAT_CONFIG_100 0x0454
117 #define LAN887X_LOCK1_EQLSR_CONFIG 0x0811
118 #define LAN887X_LOCK3_EQLSR_CONFIG 0x0813
119 #define LAN887X_PROT_DISABLE 0x0825
120 #define LAN887X_FFE_GAIN6 0x0843
121 #define LAN887X_FFE_GAIN7 0x0844
122 #define LAN887X_FFE_GAIN8 0x0845
123 #define LAN887X_FFE_GAIN9 0x0846
124 #define LAN887X_ECHO_DELAY_CONFIG 0x08ec
125 #define LAN887X_FFE_MAX_CONFIG 0x08ee
128 #define LAN887X_SCR_CONFIG_3 0x8043
129 #define LAN887X_INFO_FLD_CONFIG_5 0x8048
132 #define LAN887X_ZQCAL_CONTROL_1 0x8080
133 #define LAN887X_AFE_PORT_TESTBUS_CTRL2 0x8089
134 #define LAN887X_AFE_PORT_TESTBUS_CTRL4 0x808b
135 #define LAN887X_AFE_PORT_TESTBUS_CTRL6 0x808d
136 #define LAN887X_TX_AMPLT_1000T1_REG 0x80b0
137 #define LAN887X_INIT_COEFF_DFE1_100 0x0422
140 #define LAN887X_DSP_PMA_CONTROL 0x810e
144 #define LAN887X_IDLE_ERR_TIMER_WIN 0x8204
145 #define LAN887X_IDLE_ERR_CNT_THRESH 0x8213
148 #define LAN887X_REG_REG26 0x001a
152 #define LAN887X_MIS_CFG_REG0 0xa00
154 #define LAN887X_MIS_CFG_REG0_MAC_MODE_SEL GENMASK(1, 0)
156 #define LAN887X_MAC_MODE_RGMII 0x01
157 #define LAN887X_MAC_MODE_SGMII 0x03
159 #define LAN887X_MIS_DLL_CFG_REG0 0xa01
160 #define LAN887X_MIS_DLL_CFG_REG1 0xa02
163 #define LAN887X_MIS_DLL_EN BIT(0)
167 #define LAN887X_MIS_CFG_REG2 0xa03
170 #define LAN887X_MIS_PKT_STAT_REG0 0xa06
171 #define LAN887X_MIS_PKT_STAT_REG1 0xa07
172 #define LAN887X_MIS_PKT_STAT_REG3 0xa09
173 #define LAN887X_MIS_PKT_STAT_REG4 0xa0a
174 #define LAN887X_MIS_PKT_STAT_REG5 0xa0b
175 #define LAN887X_MIS_PKT_STAT_REG6 0xa0c
178 #define LAN887X_COMMON_LED3_LED2 0xc05
179 #define LAN887X_COMMON_LED2_MODE_SEL_MASK GENMASK(4, 0)
180 #define LAN887X_LED_LINK_ACT_ANY_SPEED 0x0
183 #define LAN887X_CHIP_HARD_RST 0xf03e
184 #define LAN887X_CHIP_HARD_RST_RESET BIT(0)
186 #define LAN887X_CHIP_SOFT_RST 0xf03f
187 #define LAN887X_CHIP_SOFT_RST_RESET BIT(0)
189 #define LAN887X_SGMII_CTL 0xf01a
190 #define LAN887X_SGMII_CTL_SGMII_MUX_EN BIT(0)
192 #define LAN887X_SGMII_PCS_CFG 0xf034
195 #define LAN887X_EFUSE_READ_DAT9 0xf209
197 #define LAN887X_EFUSE_READ_DAT9_MAC_MODE GENMASK(1, 0)
199 #define LAN887X_CALIB_CONFIG_100 0x437
208 #define LAN887X_MAX_PGA_GAIN_100 0x44f
209 #define LAN887X_MIN_PGA_GAIN_100 0x450
210 #define LAN887X_START_CBL_DIAG_100 0x45a
212 #define LAN887X_CBL_DIAG_START BIT(0)
213 #define LAN887X_CBL_DIAG_STOP 0x0
215 #define LAN887X_CBL_DIAG_TDR_THRESH_100 0x45b
216 #define LAN887X_CBL_DIAG_AGC_THRESH_100 0x45c
217 #define LAN887X_CBL_DIAG_MIN_WAIT_CONFIG_100 0x45d
218 #define LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100 0x45e
219 #define LAN887X_CBL_DIAG_CYC_CONFIG_100 0x45f
220 #define LAN887X_CBL_DIAG_TX_PULSE_CONFIG_100 0x460
221 #define LAN887X_CBL_DIAG_MIN_PGA_GAIN_100 0x462
222 #define LAN887X_CBL_DIAG_AGC_GAIN_100 0x497
223 #define LAN887X_CBL_DIAG_POS_PEAK_VALUE_100 0x499
224 #define LAN887X_CBL_DIAG_NEG_PEAK_VALUE_100 0x49a
225 #define LAN887X_CBL_DIAG_POS_PEAK_TIME_100 0x49c
226 #define LAN887X_CBL_DIAG_NEG_PEAK_TIME_100 0x49d
234 #define LAN887X_INT_STS 0xf000
235 #define LAN887X_INT_MSK 0xf001
239 #define LAN887X_INT_MSK_LINK_DOWN_MSK BIT(0)
241 #define LAN887X_MX_CHIP_TOP_REG_CONTROL1 0xF002
250 #define LAN887X_COEFF_PWR_DN_CONFIG_100 0x0404
251 #define LAN887X_COEFF_PWR_DN_CONFIG_100_V 0x16d6
252 #define LAN887X_SQI_CONFIG_100 0x042e
253 #define LAN887X_SQI_CONFIG_100_V 0x9572
254 #define LAN887X_SQI_MSE_100 0x483
256 #define LAN887X_POKE_PEEK_100 0x040d
257 #define LAN887X_POKE_PEEK_100_EN BIT(0)
259 #define LAN887X_COEFF_MOD_CONFIG 0x080d
262 #define LAN887X_DCQ_SQI_STATUS 0x08b2
337 int rc = 0;
343 if (rc < 0)
368 u16 ereg = 0;
369 int rc = 0;
385 if (rc < 0)
396 if (rc < 0)
401 if (rc < 0)
413 int new = 0, rc = 0;
419 if (rc < 0)
422 new = val | (rc & (mask ^ 0xFFFF));
442 return 0;
445 PHYACC_ATTR_BANK_MISC, LAN87XX_CTRL_1, 0);
446 if (rc < 0)
467 return 0;
479 for (i = 0; i < cnt; i++) {
491 if (ret < 0)
503 T1_AFE_PORT_CFG1_REG, 0x002D, 0 },
506 T1_POWER_DOWN_CONTROL_REG, 0x0308, 0 },
512 T1_EQ_FD_STG1_FRZ_CFG, 0x0002, 0 },
514 T1_EQ_FD_STG2_FRZ_CFG, 0x0002, 0 },
516 T1_EQ_FD_STG3_FRZ_CFG, 0x0002, 0 },
518 T1_EQ_FD_STG4_FRZ_CFG, 0x0002, 0 },
520 T1_EQ_WT_FD_LCK_FRZ_CFG, 0x0002, 0 },
522 T1_PST_EQ_LCK_STG1_FRZ_CFG, 0x0002, 0 },
528 T1_SLV_FD_MULT_CFG_REG, 0x0D53, 0 },
531 T1_CDR_CFG_PRE_LOCK_REG, 0x0AB2, 0 },
533 T1_CDR_CFG_POST_LOCK_REG, 0x0AB3, 0 },
536 T1_LCK_STG2_MUFACT_CFG_REG, 0x0AEA, 0 },
538 T1_LCK_STG3_MUFACT_CFG_REG, 0x0AEB, 0 },
540 T1_POST_LCK_MUFACT_CFG_REG, 0x0AEB, 0 },
543 T1_TX_RX_FIFO_CFG_REG, 0x1C00, 0 },
546 T1_TX_LPF_FIR_CFG_REG, 0x1000, 0 },
548 T1_TX_LPF_FIR_CFG_REG, 0x1861, 0 },
550 T1_TX_LPF_FIR_CFG_REG, 0x1061, 0 },
552 T1_TX_LPF_FIR_CFG_REG, 0x1922, 0 },
554 T1_TX_LPF_FIR_CFG_REG, 0x1122, 0 },
556 T1_TX_LPF_FIR_CFG_REG, 0x1983, 0 },
558 T1_TX_LPF_FIR_CFG_REG, 0x1183, 0 },
560 T1_TX_LPF_FIR_CFG_REG, 0x1944, 0 },
562 T1_TX_LPF_FIR_CFG_REG, 0x1144, 0 },
564 T1_TX_LPF_FIR_CFG_REG, 0x18c5, 0 },
566 T1_TX_LPF_FIR_CFG_REG, 0x10c5, 0 },
568 T1_TX_LPF_FIR_CFG_REG, 0x1846, 0 },
570 T1_TX_LPF_FIR_CFG_REG, 0x1046, 0 },
572 T1_TX_LPF_FIR_CFG_REG, 0x1807, 0 },
574 T1_TX_LPF_FIR_CFG_REG, 0x1007, 0 },
576 T1_TX_LPF_FIR_CFG_REG, 0x1808, 0 },
578 T1_TX_LPF_FIR_CFG_REG, 0x1008, 0 },
580 T1_TX_LPF_FIR_CFG_REG, 0x1809, 0 },
582 T1_TX_LPF_FIR_CFG_REG, 0x1009, 0 },
584 T1_TX_LPF_FIR_CFG_REG, 0x180A, 0 },
586 T1_TX_LPF_FIR_CFG_REG, 0x100A, 0 },
588 T1_TX_LPF_FIR_CFG_REG, 0x180B, 0 },
590 T1_TX_LPF_FIR_CFG_REG, 0x100B, 0 },
592 T1_TX_LPF_FIR_CFG_REG, 0x180C, 0 },
594 T1_TX_LPF_FIR_CFG_REG, 0x100C, 0 },
596 T1_TX_LPF_FIR_CFG_REG, 0x180D, 0 },
598 T1_TX_LPF_FIR_CFG_REG, 0x100D, 0 },
600 T1_TX_LPF_FIR_CFG_REG, 0x180E, 0 },
602 T1_TX_LPF_FIR_CFG_REG, 0x100E, 0 },
604 T1_TX_LPF_FIR_CFG_REG, 0x180F, 0 },
606 T1_TX_LPF_FIR_CFG_REG, 0x100F, 0 },
608 T1_TX_LPF_FIR_CFG_REG, 0x1810, 0 },
610 T1_TX_LPF_FIR_CFG_REG, 0x1010, 0 },
612 T1_TX_LPF_FIR_CFG_REG, 0x1811, 0 },
614 T1_TX_LPF_FIR_CFG_REG, 0x1011, 0 },
616 T1_TX_LPF_FIR_CFG_REG, 0x1000, 0 },
619 T1_COEF_CLK_PWR_DN_CFG, 0x16d6, 0 },
622 T1_SQI_CONFIG_REG, 0x9572, 0 },
625 T1_SQI_CONFIG2_REG, 0x0001, 0 },
628 T1_COEF_RW_CTL_CFG, 0x0301, 0 },
630 T1_DCQ_SQI_REG, 0, 0 },
633 T1_MDIO_CONTROL2_REG, 0x0014, 0 },
636 T1_POWER_DOWN_CONTROL_REG, 0x0200, 0 },
639 T1_MDIO_CONTROL2_REG, 0x0094, 0 },
642 T1_MDIO_CONTROL2_REG, 0x0080, 0 },
643 /* Tx AMP - 0x06 */
645 T1_AFE_PORT_CFG1_REG, 0x000C, 0 },
648 T1_INTERRUPT_SOURCE_REG, 0, 0 },
651 T1_INTERRUPT2_SOURCE_REG, 0, 0 },
654 T1_POWER_DOWN_CONTROL_REG, 0x0300, 0 },
660 if (rc < 0)
665 if (rc < 0)
678 if (rc < 0)
683 if (rc < 0)
691 int rc, val = 0;
696 if (rc < 0)
700 if (rc < 0)
706 if (rc < 0)
711 LAN87XX_INTERRUPT_SOURCE_2, 0);
712 if (rc < 0)
718 if (rc < 0)
727 if (rc < 0)
731 if (rc < 0)
737 if (rc < 0)
742 LAN87XX_INTERRUPT_SOURCE_2, 0);
745 return rc < 0 ? rc : 0;
754 LAN87XX_INTERRUPT_SOURCE_2, 0);
755 if (irq_status < 0) {
761 if (irq_status < 0) {
766 if (irq_status == 0)
778 return rc < 0 ? rc : 0;
789 if (bmcr < 0)
794 if (bmsr < 0)
798 ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
799 if (ret < 0)
802 if (ret < 0)
810 return 0;
818 0, 0},
821 10, 0},
824 90, 0},
827 60, 0},
830 31, 0},
833 0, 0x0038},
836 70, 0},
839 1, 0},
844 if (rc < 0)
850 0x00, 0);
851 if (rc < 0)
856 0x0A, 0);
857 if (rc < 0)
860 if ((rc & 0x4000) != 0x4000) {
863 0x0E, 0x5, 0x7);
864 if (rc < 0)
867 0x1A, 0x8, 0x8);
868 if (rc < 0)
873 0x10, 0x8, 0x40);
874 if (rc < 0)
878 for (i = 0; i < ARRAY_SIZE(cable_test); i++) {
893 if (rc < 0)
898 return 0;
918 int pos_peak_cycle = 0, pos_peak_in_phases = 0, pos_peak_phase = 0;
919 int neg_peak_cycle = 0, neg_peak_in_phases = 0, neg_peak_phase = 0;
923 int gain_idx = 0, pos_peak = 0, neg_peak = 0;
924 int pos_peak_time = 0, neg_peak_time = 0;
925 int pos_peak_in_phases_hybrid = 0;
929 PHYACC_ATTR_BANK_DSP, 151, 0);
932 PHYACC_ATTR_BANK_DSP, 153, 0);
934 PHYACC_ATTR_BANK_DSP, 154, 0);
936 PHYACC_ATTR_BANK_DSP, 156, 0);
938 PHYACC_ATTR_BANK_DSP, 157, 0);
940 pos_peak_cycle = (pos_peak_time >> 7) & 0x7F;
942 pos_peak_phase = pos_peak_time & 0x7F;
944 neg_peak_cycle = (neg_peak_time >> 7) & 0x7F;
945 neg_peak_phase = neg_peak_time & 0x7F;
966 gain_idx >= 0) {
972 detect = 0;
983 int rc = 0;
989 90, 0);
990 if (rc < 0)
997 90, 0);
998 if (rc < 0)
1006 return 0;
1011 int rc = 0;
1014 if (rc < 0)
1020 phydev->link = 0;
1024 phydev->pause = 0;
1025 phydev->asym_pause = 0;
1028 if (rc < 0)
1032 if (rc < 0)
1040 u16 ctl = 0;
1051 return 0;
1066 u8 sqi_value = 0;
1070 PHYACC_ATTR_BANK_DSP, T1_COEF_RW_CTL_CFG, 0x0301);
1071 if (rc < 0)
1075 PHYACC_ATTR_BANK_DSP, T1_DCQ_SQI_REG, 0x0);
1076 if (rc < 0)
1097 if (ret < 0)
1104 if (ret < 0)
1111 if (ret < 0)
1131 if (ret < 0)
1138 if (ret < 0)
1146 if (ret < 0)
1161 if (ret < 0)
1166 if (txc < 0)
1171 if (rxc < 0)
1202 return 0;
1208 if (ret < 0)
1224 if (ret < 0)
1266 if (ret < 0)
1277 return 0;
1308 if (ret < 0)
1318 if (ret < 0)
1330 for (int i = 0; i < cnt; i++) {
1333 if (ret < 0)
1337 return 0;
1344 {MDIO_MMD_PMAPMD, LAN887X_ZQCAL_CONTROL_1, 0x4008},
1345 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL2, 0x0000},
1346 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL6, 0x0040},
1348 {MDIO_MMD_PCS, LAN887X_IDLE_ERR_CNT_THRESH, 0x0008},
1349 {MDIO_MMD_PCS, LAN887X_IDLE_ERR_TIMER_WIN, 0x800d},
1351 {MDIO_MMD_VEND1, LAN887x_CDR_CONFIG1_100, 0x0ab1},
1352 {MDIO_MMD_VEND1, LAN887x_LOCK1_EQLSR_CONFIG_100, 0x5274},
1353 {MDIO_MMD_VEND1, LAN887x_SLV_HD_MUFAC_CONFIG_100, 0x0d74},
1354 {MDIO_MMD_VEND1, LAN887x_PLOCK_MUFAC_CONFIG_100, 0x0aea},
1355 {MDIO_MMD_VEND1, LAN887x_PROT_DISABLE_100, 0x0360},
1356 {MDIO_MMD_VEND1, LAN887x_KF_LOOP_SAT_CONFIG_100, 0x0c30},
1358 {MDIO_MMD_VEND1, LAN887X_LOCK1_EQLSR_CONFIG, 0x2a78},
1359 {MDIO_MMD_VEND1, LAN887X_LOCK3_EQLSR_CONFIG, 0x1368},
1360 {MDIO_MMD_VEND1, LAN887X_PROT_DISABLE, 0x1354},
1361 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN6, 0x3C84},
1362 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN7, 0x3ca5},
1363 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN8, 0x3ca5},
1364 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN9, 0x3ca5},
1365 {MDIO_MMD_VEND1, LAN887X_ECHO_DELAY_CONFIG, 0x0024},
1366 {MDIO_MMD_VEND1, LAN887X_FFE_MAX_CONFIG, 0x227f},
1368 {MDIO_MMD_PCS, LAN887X_SCR_CONFIG_3, 0x1e00},
1369 {MDIO_MMD_PCS, LAN887X_INFO_FLD_CONFIG_5, 0x0fa1},
1383 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x00b8},
1384 {MDIO_MMD_PMAPMD, LAN887X_TX_AMPLT_1000T1_REG, 0x0038},
1385 {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x000f},
1391 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x0038},
1392 {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x0014},
1397 if (ret < 0)
1407 {MDIO_MMD_PMAPMD, LAN887X_TX_AMPLT_1000T1_REG, 0x003f},
1408 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x00b8},
1414 if (ret < 0)
1443 if (ret < 0)
1449 if (ret < 0)
1455 if (ret < 0)
1460 if (ret < 0)
1475 if (ret < 0)
1489 if (ret < 0)
1521 if (val < 0) {
1535 for (int i = 0; i < ARRAY_SIZE(lan887x_hw_stats); i++)
1546 for (int i = 0; i < ARRAY_SIZE(lan887x_hw_stats); i++)
1558 if (rc < 0)
1566 GENMASK(15, 0));
1567 if (rc < 0)
1572 if (rc < 0)
1583 return 0;
1593 if (irq_status < 0) {
1618 if (rc < 0)
1626 if (rc < 0)
1632 if (rc < 0)
1636 if (rc < 0)
1640 if (rc < 0)
1644 if (rc < 0)
1648 return 0;
1655 {MDIO_MMD_VEND1, LAN887X_MAX_PGA_GAIN_100, 0x1f},
1656 {MDIO_MMD_VEND1, LAN887X_MIN_PGA_GAIN_100, 0x0},
1657 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_TDR_THRESH_100, 0x1},
1658 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_AGC_THRESH_100, 0x3c},
1659 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MIN_WAIT_CONFIG_100, 0x0},
1660 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100, 0x46},
1661 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_CYC_CONFIG_100, 0x5a},
1662 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_TX_PULSE_CONFIG_100, 0x44d5},
1663 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MIN_PGA_GAIN_100, 0x0},
1669 if (rc < 0)
1677 if (rc < 0)
1680 rc = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x80b0, 0x0038);
1681 if (rc < 0)
1685 LAN887X_CALIB_CONFIG_100, 0,
1687 if (rc < 0)
1690 for (int i = 0; i < ARRAY_SIZE(values); i++) {
1693 if (rc < 0)
1699 values[i].reg, 0xa);
1700 if (rc < 0)
1708 BIT(0), BIT(0));
1709 if (rc < 0)
1717 if (rc < 0)
1749 if (rc < 0)
1754 if (rc < 0)
1772 if (rc < 0) {
1774 if (ret < 0)
1780 return 0;
1801 if (gain_idx < 0) {
1808 if (pos_peak < 0) {
1815 if (neg_peak < 0) {
1822 if (pos_peak_time < 0) {
1829 if (neg_peak_time < 0) {
1835 pos_peak_cycle = (pos_peak_time >> 7) & 0x7f;
1836 pos_peak_in_phases = (pos_peak_cycle * 96) + (pos_peak_time & 0x7f);
1837 neg_peak_cycle = (neg_peak_time >> 7) & 0x7f;
1838 neg_peak_in_phases = (neg_peak_cycle * 96) + (neg_peak_time & 0x7f);
1842 neg_peak > MICROCHIP_CABLE_NOISE_MARGIN && gain_idx >= 0) {
1848 pos_peak_in_phases > 0) {
1855 neg_peak_in_phases > 0) {
1865 distance = 0;
1871 if (rc < 0)
1876 if (rc < 0)
1882 if (gain_idx_hybrid < 0) {
1889 if (pos_peak_time_hybrid < 0) {
1895 pos_peak_cycle_hybrid = (pos_peak_time_hybrid >> 7) & 0x7f;
1896 pos_peak_phase_hybrid = pos_peak_time_hybrid & 0x7f;
1916 distance = 0;
1921 if (rc < 0)
1924 length = ((u32)distance & GENMASK(15, 0));
1929 return 0;
1936 if (ret < 0)
1942 if (ret < 0)
1955 if (rc < 0) {
1958 return 0;
1978 u32 sqiavg = 0;
1979 u8 sqinum = 0;
1986 if (rc < 0)
1991 if (rc < 0)
2001 if (rc < 0)
2011 if (rc < 0)
2018 for (i = 0; i < SQI_SAMPLES; i++) {
2022 if (rc < 0)
2027 if (rc < 0)
2035 if (rc < 0)
2049 if (sqiavg != 0) {
2068 sqinum = 0;
2089 if (rc < 0)
2098 if (rc < 0)
2102 if (rc < 0)