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/linux/Documentation/devicetree/bindings/sound/
H A Dwlf,wm8962.yaml29 const: 0
74 within [0x0, 0xffff] are valid. Any other value is regarded as setting
75 the GPIO register to its reset value 0x0.
101 #size-cells = <0>;
105 reg = <0x1a>;
116 0x0000 /* 0:Default */
117 0x0000 /* 1:Default */
118 0x0013 /* 2:FN_DMICCLK */
119 0x0000 /* 3:Default */
120 0x8014 /* 4:FN_DMICCDAT */
[all …]
/linux/drivers/media/platform/nuvoton/
H A Dnpcm-regs.h12 #define VCD_DIFF_TBL 0x0000
13 #define VCD_FBA_ADR 0x8000
14 #define VCD_FBB_ADR 0x8004
16 #define VCD_FB_LP 0x8008
17 #define VCD_FBA_LP GENMASK(15, 0)
20 #define VCD_CAP_RES 0x800c
21 #define VCD_CAP_RES_VERT_RES GENMASK(10, 0)
24 #define VCD_MODE 0x8014
25 #define VCD_MODE_VCDE BIT(0)
30 #define VCD_CMD 0x8018
[all …]
/linux/arch/m68k/include/uapi/asm/
H A Dbootinfo-mac.h14 #define BI_MAC_MODEL 0x8000 /* Mac Gestalt ID (model type) */
15 #define BI_MAC_VADDR 0x8001 /* Mac video base address */
16 #define BI_MAC_VDEPTH 0x8002 /* Mac video depth */
17 #define BI_MAC_VROW 0x8003 /* Mac video rowbytes */
18 #define BI_MAC_VDIM 0x8004 /* Mac video dimensions */
19 #define BI_MAC_VLOGICAL 0x8005 /* Mac video logical base */
20 #define BI_MAC_SCCBASE 0x8006 /* Mac SCC base address */
21 #define BI_MAC_BTIME 0x8007 /* Mac boot time */
22 #define BI_MAC_GMTBIAS 0x8008 /* Mac GMT timezone offset */
23 #define BI_MAC_MEMSIZE 0x8009 /* Mac RAM size (sanity check) */
[all …]
/linux/drivers/media/usb/dvb-usb/
H A Ddibusb-common.c20 #define deb_info(args...) dprintk(debug,0x01,args)
28 if (st->ops.fifo_ctrl(adap->fe_adap[0].fe, onoff)) { in dibusb_streaming_ctrl()
33 return 0; in dibusb_streaming_ctrl()
42 st->ops.pid_ctrl(adap->fe_adap[0].fe, in dibusb_pid_filter()
45 return 0; in dibusb_pid_filter()
54 if (st->ops.pid_parse(adap->fe_adap[0].fe, onoff) < 0) in dibusb_pid_filter_ctrl()
57 return 0; in dibusb_pid_filter_ctrl()
70 b[0] = DIBUSB_REQ_SET_IOCTL; in dibusb_power_ctrl()
93 if ((ret = dibusb_streaming_ctrl(adap,onoff)) < 0) in dibusb2_0_streaming_ctrl()
97 b[0] = DIBUSB_REQ_SET_STREAMING_MODE; in dibusb2_0_streaming_ctrl()
[all …]
/linux/drivers/scsi/qla2xxx/
H A Dqla_mr.h14 #define PCI_DEVICE_ID_QLOGIC_ISPF001 0xF001
18 #define FX00_COMMAND_TYPE_7 0x07 /* Command Type 7 entry for 7XXX */
53 #define STATUS_TYPE_FX00 0x01 /* Status entry. */
80 #define MULTI_STATUS_TYPE_FX00 0x0D
91 #define TSK_MGMT_IOCB_TYPE_FX00 0x05
116 #define ABORT_IOCB_TYPE_FX00 0x08 /* Abort IOCB status. */
136 #define IOCTL_IOSB_TYPE_FX00 0x0C
159 #define STATUS_CONT_TYPE_FX00 0x04
161 #define FX00_IOCB_TYPE 0x0B
203 #define QLAFX00_LINK_STATUS_DOWN 0x10
[all …]
/linux/drivers/gpio/
H A Dgpio-pch.c14 #define PCH_EDGE_FALLING 0
19 #define PCH_IM_MASK GENMASK(2, 0)
40 #define PCI_DEVICE_ID_INTEL_EG20T_PCH 0x8803
41 #define PCI_DEVICE_ID_ROHM_ML7223m_IOH 0x8014
42 #define PCI_DEVICE_ID_ROHM_ML7223n_IOH 0x8043
43 #define PCI_DEVICE_ID_ROHM_EG20T_PCH 0x8803
150 return 0; in pch_gpio_direction_output()
166 return 0; in pch_gpio_direction_input()
239 im_pos = ch - 0; in pch_irq_type()
263 return 0; in pch_irq_type()
[all …]
/linux/include/linux/mfd/mt6332/
H A Dregisters.h10 #define MT6332_HWCID 0x8000
11 #define MT6332_SWCID 0x8002
12 #define MT6332_TOP_CON 0x8004
13 #define MT6332_DDR_VREF_AP_CON 0x8006
14 #define MT6332_DDR_VREF_DQ_CON 0x8008
15 #define MT6332_DDR_VREF_CA_CON 0x800A
16 #define MT6332_TEST_OUT 0x800C
17 #define MT6332_TEST_CON0 0x800E
18 #define MT6332_TEST_CON1 0x8010
19 #define MT6332_TESTMODE_SW 0x8012
[all …]
/linux/drivers/clk/qcom/
H A Ddispcc0-sa8775p.c59 { 249600000, 2020000000, 0 },
63 .l = 0x3a,
64 .alpha = 0x9800,
65 .config_ctl_val = 0x20485699,
66 .config_ctl_hi_val = 0x00182261,
67 .config_ctl_hi1_val = 0x32aa299c,
68 .user_ctl_val = 0x00000000,
69 .user_ctl_hi_val = 0x00400805,
73 .offset = 0x0,
90 .l = 0x1f,
[all …]
H A Ddispcc1-sa8775p.c59 { 249600000, 2020000000, 0 },
63 .l = 0x3a,
64 .alpha = 0x9800,
65 .config_ctl_val = 0x20485699,
66 .config_ctl_hi_val = 0x00182261,
67 .config_ctl_hi1_val = 0x32aa299c,
68 .user_ctl_val = 0x00000000,
69 .user_ctl_hi_val = 0x00400805,
73 .offset = 0x0,
90 .l = 0x1f,
[all …]
H A Ddispcc-sm8450.c52 #define DISP_CC_MISC_CMD 0xF000
75 { 249600000, 2000000000, 0 },
79 .l = 0xD,
80 .alpha = 0x6492,
81 .config_ctl_val = 0x20485699,
82 .config_ctl_hi_val = 0x00182261,
83 .config_ctl_hi1_val = 0x32AA299C,
84 .user_ctl_val = 0x00000000,
85 .user_ctl_hi_val = 0x00000805,
89 .l = 0xd,
[all …]
H A Decpricc-qdu1000.c46 { 249600000, 2020000000, 0 },
51 .l = 0x24,
52 .alpha = 0x7555,
53 .config_ctl_val = 0x20485699,
54 .config_ctl_hi_val = 0x00182261,
55 .config_ctl_hi1_val = 0x32aa299c,
56 .user_ctl_val = 0x00000000,
57 .user_ctl_hi_val = 0x00000805,
61 .offset = 0x0,
66 .enable_reg = 0x0,
[all …]
/linux/tools/perf/pmu-events/arch/arm64/
H A Dcommon-and-microarch.json4 "EventCode": "0x00",
10 "EventCode": "0x01",
16 "EventCode": "0x02",
22 "EventCode": "0x03",
28 "EventCode": "0x04",
34 "EventCode": "0x05",
40 "EventCode": "0x06",
46 "EventCode": "0x07",
52 "EventCode": "0x08",
58 "EventCode": "0x0
2 { global() object
[all...]
/linux/drivers/net/wireless/ath/ath10k/
H A Dhw.h24 #define QCA988X_2_0_DEVICE_ID_UBNT (0x11ac)
25 #define QCA988X_2_0_DEVICE_ID (0x003c)
26 #define QCA6164_2_1_DEVICE_ID (0x0041)
27 #define QCA6174_2_1_DEVICE_ID (0x003e)
28 #define QCA6174_3_2_DEVICE_ID (0x0042)
29 #define QCA99X0_2_0_DEVICE_ID (0x0040)
30 #define QCA9888_2_0_DEVICE_ID (0x0056)
31 #define QCA9984_1_0_DEVICE_ID (0x0046)
32 #define QCA9377_1_0_DEVICE_ID (0x0042)
33 #define QCA9887_1_0_DEVICE_ID (0x0050)
[all …]
/linux/drivers/net/ethernet/freescale/enetc/
H A Denetc_hw.h12 #define ENETC_DEV_ID_PF 0xe100
13 #define ENETC_DEV_ID_VF 0xef00
14 #define ENETC_DEV_ID_PTP 0xee02
17 #define ENETC_BAR_REGS 0
19 /** SI regs, offset: 0h */
20 #define ENETC_SIMR 0
22 #define ENETC_SIMR_RSSE BIT(0)
23 #define ENETC_SICTR0 0x18
24 #define ENETC_SICTR1 0x1c
25 #define ENETC_SIPCAPR0 0x20
[all …]
/linux/sound/usb/
H A Dmixer_scarlett.c45 * USB URB commands overview (bRequest = 0x01 = UAC2_CS_CUR)
47 * 0x01 Analog Input line/instrument impedance switch, wValue=0x0901 +
49 * pad (-10dB) switch, wValue=0x0b01 + channel, data=Off/On (2bytes)
50 * ?? wValue=0x0803/04, ?? (2bytes)
51 * 0x0a Master Volume, wValue=0x0200+bus[0:all + only 1..4?] data(2bytes)
52 * Bus Mute/Unmute wValue=0x0100+bus[0:all + only 1..4?], data(2bytes)
53 * 0x28 Clock source, wValue=0x0100, data={1:int,2:spdif,3:adat} (1byte)
54 * 0x29 Set Sample-rate, wValue=0x0100, data=sample-rate(4bytes)
55 * 0x32 Mixer mux, wValue=0x0600 + mixer-channel, data=input-to-connect(2bytes)
56 * 0x33 Output mux, wValue=bus, data=input-to-connect(2bytes)
[all …]
/linux/drivers/scsi/qla4xxx/
H A Dql4_init.c32 "ispControlStatus = 0x%x\n", ha->host_no, in ql4xxx_set_mac_number()
69 for (cnt = 0; cnt < RESPONSE_QUEUE_DEPTH; cnt++) { in qla4xxx_init_response_q_entries()
80 * The QLA4010 requires us to restart the queues at index 0.
85 unsigned long flags = 0; in qla4xxx_init_rings()
90 ha->request_out = 0; in qla4xxx_init_rings()
91 ha->request_in = 0; in qla4xxx_init_rings()
96 ha->response_in = 0; in qla4xxx_init_rings()
97 ha->response_out = 0; in qla4xxx_init_rings()
101 writel(0, in qla4xxx_init_rings()
103 writel(0, in qla4xxx_init_rings()
[all …]
H A Dql4_fw.h23 __le32 ext_hw_conf; /* 0x50 R/W */
24 __le32 rsrvd0; /* 0x54 */
25 __le32 port_ctrl; /* 0x58 */
26 __le32 port_status; /* 0x5c */
27 __le32 rsrvd1[32]; /* 0x60-0xdf */
28 __le32 gp_out; /* 0xe0 */
29 __le32 gp_in; /* 0xe4 */
30 __le32 rsrvd2[5]; /* 0xe8-0xfb */
31 __le32 port_err_status; /* 0xfc */
35 __le32 rsrvd0[12]; /* 0x50-0x79 */
[all …]
/linux/drivers/gpu/drm/radeon/
H A Drv770d.h35 #define R7XX_MAX_BACKENDS_MASK 0xff
37 #define R7XX_MAX_SIMDS_MASK 0xffff
39 #define R7XX_MAX_PIPES_MASK 0xff
42 #define CG_UPLL_FUNC_CNTL 0x718
43 # define UPLL_RESET_MASK 0x00000001
44 # define UPLL_SLEEP_MASK 0x00000002
45 # define UPLL_BYPASS_EN_MASK 0x00000004
46 # define UPLL_CTLREQ_MASK 0x00000008
48 # define UPLL_REF_DIV_MASK 0x003F0000
49 # define UPLL_CTLACK_MASK 0x40000000
[all …]
H A Dnid.h33 #define CAYMAN_MAX_BACKENDS_MASK 0xFF
34 #define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF
36 #define CAYMAN_MAX_SIMDS_MASK 0xFFFF
37 #define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF
39 #define CAYMAN_MAX_PIPES_MASK 0xFF
40 #define CAYMAN_MAX_LDS_NUM 0xFFFF
42 #define CAYMAN_MAX_TCC_MASK 0xFF
44 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
45 #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001
47 #define DMIF_ADDR_CONFIG 0xBD4
[all …]
H A Dr600d.h30 #define CP_PACKET2 0x80000000
31 #define PACKET2_PAD_SHIFT 0
32 #define PACKET2_PAD_MASK (0x3fffffff << 0)
41 #define R6XX_MAX_BACKENDS_MASK 0xff
43 #define R6XX_MAX_SIMDS_MASK 0xff
45 #define R6XX_MAX_PIPES_MASK 0xff
48 #define ARRAY_LINEAR_GENERAL 0x00000000
49 #define ARRAY_LINEAR_ALIGNED 0x00000001
50 #define ARRAY_1D_TILED_THIN1 0x00000002
51 #define ARRAY_2D_TILED_THIN1 0x00000004
[all …]
/linux/drivers/iommu/
H A Dexynos-iommu.c45 ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
52 #define lv2ent_fault(pent) ((*(pent) & 3) == 0)
58 * v5.0 introduced support for 36bit physical address space by shifting
62 * value (0 or 4).
65 #define SYSMMU_PG_ENT_SHIFT 0
70 ((0 << 15) | (0 << 10)), /* no access */
72 ((0 << 15) | (1 << 10)), /* IOMMU_WRITE not supported, use read/write */
73 ((0 << 15) | (1 << 10)), /* IOMMU_READ | IOMMU_WRITE */
76 (0 << 4), /* no access */
84 ((0 << 9) | (0 << 4)), /* no access */
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_SUP_DIG_IDCODE_LO 0x0000
33 …DPCSSYS_CR0_SUP_DIG_IDCODE_HI 0x0001
34 …DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN 0x0002
35 …DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003
36 …DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004
37 …DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005
38 …DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006
39 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 0x0007
40 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 0x0008
[all …]
H A Ddpcs_4_2_0_offset.h27 // base address: 0x0
28 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
30 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
35 // base address: 0x360
36 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
38 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
43 // base address: 0x6c0
44 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
46 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
51 // base address: 0xa20
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dreg.h22 #define AR_CR 0x0008
23 #define AR_CR_RXE(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x0000000c : 0x00000004)
24 #define AR_CR_RXD 0x00000020
25 #define AR_CR_SWI 0x00000040
27 #define AR_RXDP 0x000C
29 #define AR_CFG 0x0014
30 #define AR_CFG_SWTD 0x00000001
31 #define AR_CFG_SWTB 0x00000002
32 #define AR_CFG_SWRD 0x00000004
33 #define AR_CFG_SWRB 0x00000008
[all …]
/linux/drivers/gpu/drm/gma500/
H A Dpsb_intel_reg.h11 #define GPIOA 0x5010
12 #define GPIOB 0x5014
13 #define GPIOC 0x5018
14 #define GPIOD 0x501c
15 #define GPIOE 0x5020
16 #define GPIOF 0x5024
17 #define GPIOG 0x5028
18 #define GPIOH 0x502c
19 # define GPIO_CLOCK_DIR_MASK (1 << 0)
20 # define GPIO_CLOCK_DIR_IN (0 << 1)
[all …]

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