Lines Matching +full:0 +full:x8014
58 { 249600000, 2020000000, 0 },
62 .l = 0x3a,
63 .alpha = 0x9800,
64 .config_ctl_val = 0x20485699,
65 .config_ctl_hi_val = 0x00182261,
66 .config_ctl_hi1_val = 0x32aa299c,
67 .user_ctl_val = 0x00000000,
68 .user_ctl_hi_val = 0x00400805,
72 .offset = 0x0,
89 .l = 0x1f,
90 .alpha = 0x4000,
91 .config_ctl_val = 0x20485699,
92 .config_ctl_hi_val = 0x00182261,
93 .config_ctl_hi1_val = 0x32aa299c,
94 .user_ctl_val = 0x00000000,
95 .user_ctl_hi_val = 0x00400805,
99 .offset = 0x1000,
116 { P_BI_TCXO, 0 },
130 { P_BI_TCXO, 0 },
146 { P_BI_TCXO, 0 },
158 { P_BI_TCXO, 0 },
170 { P_BI_TCXO, 0 },
182 { P_BI_TCXO, 0 },
194 { P_BI_TCXO, 0 },
208 { P_SLEEP_CLK, 0 },
216 F(37500000, P_MDSS_1_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
217 F(75000000, P_MDSS_1_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
222 .cmd_rcgr = 0x824c,
223 .mnd_width = 0,
237 F(19200000, P_BI_TCXO, 1, 0, 0),
242 .cmd_rcgr = 0x80ec,
243 .mnd_width = 0,
257 .cmd_rcgr = 0x8108,
258 .mnd_width = 0,
272 .cmd_rcgr = 0x81b8,
273 .mnd_width = 0,
287 .cmd_rcgr = 0x8170,
288 .mnd_width = 0,
302 .cmd_rcgr = 0x8154,
303 .mnd_width = 0,
317 .cmd_rcgr = 0x8188,
332 .cmd_rcgr = 0x81a0,
347 .cmd_rcgr = 0x826c,
362 .cmd_rcgr = 0x8284,
377 .cmd_rcgr = 0x8234,
378 .mnd_width = 0,
392 .cmd_rcgr = 0x821c,
393 .mnd_width = 0,
407 .cmd_rcgr = 0x8200,
408 .mnd_width = 0,
422 .cmd_rcgr = 0x81d0,
437 .cmd_rcgr = 0x81e8,
452 .cmd_rcgr = 0x8124,
453 .mnd_width = 0,
467 .cmd_rcgr = 0x813c,
468 .mnd_width = 0,
482 F(375000000, P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
483 F(500000000, P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
484 F(575000000, P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
485 F(650000000, P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
490 .cmd_rcgr = 0x80bc,
491 .mnd_width = 0,
505 .cmd_rcgr = 0x808c,
520 .cmd_rcgr = 0x80a4,
535 .cmd_rcgr = 0x80d4,
536 .mnd_width = 0,
550 F(32000, P_SLEEP_CLK, 1, 0, 0),
555 .cmd_rcgr = 0xc058,
556 .mnd_width = 0,
570 .cmd_rcgr = 0xc03c,
571 .mnd_width = 0,
585 .reg = 0x8104,
586 .shift = 0,
600 .reg = 0x8120,
601 .shift = 0,
615 .reg = 0x816c,
616 .shift = 0,
630 .reg = 0x8218,
631 .shift = 0,
645 .halt_reg = 0x8088,
648 .enable_reg = 0x8088,
649 .enable_mask = BIT(0),
663 .halt_reg = 0x8084,
666 .enable_reg = 0x8084,
667 .enable_mask = BIT(0),
681 .halt_reg = 0x8034,
684 .enable_reg = 0x8034,
685 .enable_mask = BIT(0),
699 .halt_reg = 0x8038,
702 .enable_reg = 0x8038,
703 .enable_mask = BIT(0),
717 .halt_reg = 0x803c,
720 .enable_reg = 0x803c,
721 .enable_mask = BIT(0),
735 .halt_reg = 0x8040,
738 .enable_reg = 0x8040,
739 .enable_mask = BIT(0),
753 .halt_reg = 0x805c,
756 .enable_reg = 0x805c,
757 .enable_mask = BIT(0),
771 .halt_reg = 0x8058,
774 .enable_reg = 0x8058,
775 .enable_mask = BIT(0),
789 .halt_reg = 0x804c,
792 .enable_reg = 0x804c,
793 .enable_mask = BIT(0),
807 .halt_reg = 0x8050,
810 .enable_reg = 0x8050,
811 .enable_mask = BIT(0),
825 .halt_reg = 0x8060,
828 .enable_reg = 0x8060,
829 .enable_mask = BIT(0),
843 .halt_reg = 0x8064,
846 .enable_reg = 0x8064,
847 .enable_mask = BIT(0),
861 .halt_reg = 0x8264,
864 .enable_reg = 0x8264,
865 .enable_mask = BIT(0),
879 .halt_reg = 0x8268,
882 .enable_reg = 0x8268,
883 .enable_mask = BIT(0),
897 .halt_reg = 0x8054,
900 .enable_reg = 0x8054,
901 .enable_mask = BIT(0),
915 .halt_reg = 0x8080,
918 .enable_reg = 0x8080,
919 .enable_mask = BIT(0),
933 .halt_reg = 0x807c,
936 .enable_reg = 0x807c,
937 .enable_mask = BIT(0),
951 .halt_reg = 0x8070,
954 .enable_reg = 0x8070,
955 .enable_mask = BIT(0),
969 .halt_reg = 0x8074,
972 .enable_reg = 0x8074,
973 .enable_mask = BIT(0),
987 .halt_reg = 0x8068,
990 .enable_reg = 0x8068,
991 .enable_mask = BIT(0),
1005 .halt_reg = 0x806c,
1008 .enable_reg = 0x806c,
1009 .enable_mask = BIT(0),
1023 .halt_reg = 0x8078,
1026 .enable_reg = 0x8078,
1027 .enable_mask = BIT(0),
1041 .halt_reg = 0x8044,
1044 .enable_reg = 0x8044,
1045 .enable_mask = BIT(0),
1059 .halt_reg = 0x8048,
1062 .enable_reg = 0x8048,
1063 .enable_mask = BIT(0),
1077 .halt_reg = 0x8014,
1080 .enable_reg = 0x8014,
1081 .enable_mask = BIT(0),
1095 .halt_reg = 0x800c,
1098 .enable_reg = 0x800c,
1099 .enable_mask = BIT(0),
1113 .halt_reg = 0x8024,
1116 .enable_reg = 0x8024,
1117 .enable_mask = BIT(0),
1131 .halt_reg = 0x801c,
1134 .enable_reg = 0x801c,
1135 .enable_mask = BIT(0),
1149 .halt_reg = 0xa004,
1152 .enable_reg = 0xa004,
1153 .enable_mask = BIT(0),
1167 .halt_reg = 0x8004,
1170 .enable_reg = 0x8004,
1171 .enable_mask = BIT(0),
1185 .halt_reg = 0x8008,
1188 .enable_reg = 0x8008,
1189 .enable_mask = BIT(0),
1203 .halt_reg = 0xe000,
1206 .enable_reg = 0xe000,
1207 .enable_mask = BIT(0),
1221 .halt_reg = 0xa00c,
1224 .enable_reg = 0xa00c,
1225 .enable_mask = BIT(0),
1239 .halt_reg = 0xa008,
1242 .enable_reg = 0xa008,
1243 .enable_mask = BIT(0),
1257 .halt_reg = 0x8030,
1260 .enable_reg = 0x8030,
1261 .enable_mask = BIT(0),
1275 .halt_reg = 0x802c,
1278 .enable_reg = 0x802c,
1279 .enable_mask = BIT(0),
1293 .halt_reg = 0x11014,
1296 .enable_reg = 0x11014,
1297 .enable_mask = BIT(0),
1306 .gdscr = 0x9000,
1307 .en_rest_wait_val = 0x2,
1308 .en_few_wait_val = 0x2,
1309 .clk_dis_wait_val = 0xf,
1318 .gdscr = 0xd000,
1319 .en_rest_wait_val = 0x2,
1320 .en_few_wait_val = 0x2,
1321 .clk_dis_wait_val = 0xf,
1408 [MDSS_DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
1409 [MDSS_DISP_CC_MDSS_RSCC_BCR] = { 0xa000 },
1416 .max_register = 0x12414,
1459 qcom_branch_set_clk_en(regmap, 0xc070); /* MDSS_1_DISP_CC_SLEEP_CLK */
1460 qcom_branch_set_clk_en(regmap, 0xc054); /* MDSS_1_DISP_CC_XO_CLK */