46 			   ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
53 #define lv2ent_fault(pent) ((*(pent) & 3) == 0)
59  * v5.0 introduced support for 36bit physical address space by shifting
63  * value (0 or 4).
66 #define SYSMMU_PG_ENT_SHIFT 0
71 	((0 << 15) | (0 << 10)), /* no access */
73 	((0 << 15) | (1 << 10)), /* IOMMU_WRITE not supported, use read/write */
74 	((0 << 15) | (1 << 10)), /* IOMMU_READ | IOMMU_WRITE */
77 	(0 << 4), /* no access */
85 	((0 << 9) | (0 << 4)), /* no access */
87 	((0 << 9) | (1 << 4)), /* IOMMU_WRITE not supported, use read/write */
88 	((0 << 9) | (1 << 4)), /* IOMMU_READ | IOMMU_WRITE */
91 	(0 << 2), /* no access */
124 #define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0))
131 #define CTRL_ENABLE	0x5
132 #define CTRL_BLOCK	0x7
133 #define CTRL_DISABLE	0x0
135 #define CFG_LRU		0x1
137 #define CFG_QOS(n)	((n & 0xF) << 7)
142 #define CTRL_VM_ENABLE			BIT(0)
148 #define REG_MMU_CTRL		0x000
149 #define REG_MMU_CFG		0x004
150 #define REG_MMU_STATUS		0x008
151 #define REG_MMU_VERSION		0x034
154 #define MMU_MIN_VER(val)	((val) & 0x7F)
157 #define MAKE_MMU_VER(maj, min)	((((maj) & 0xF) << 7) | ((min) & 0x7F))
160 #define REG_PAGE_FAULT_ADDR	0x024
161 #define REG_AW_FAULT_ADDR	0x028
162 #define REG_AR_FAULT_ADDR	0x02C
163 #define REG_DEFAULT_SLAVE_ADDR	0x030
166 #define REG_V5_FAULT_AR_VA	0x070
167 #define REG_V5_FAULT_AW_VA	0x080
170 #define REG_V7_CAPA0		0x870
171 #define REG_V7_CAPA1		0x874
172 #define REG_V7_CTRL_VM		0x8000
215 /* SysMMU v5 has the same faults for AR (0..4 bits) and AW (16..20 bits) */
327 	return 0;  in exynos_sysmmu_v1_get_fault_info()
350 	return 0;  in exynos_sysmmu_v5_get_fault_info()
363 	return 0;  in exynos_sysmmu_v7_get_fault_info()
368 	.flush_all	= 0x0c,
369 	.flush_entry	= 0x10,
370 	.pt_base	= 0x14,
371 	.int_status	= 0x18,
372 	.int_clear	= 0x1c,
379 	.pt_base	= 0x0c,
380 	.flush_all	= 0x10,
381 	.flush_entry	= 0x14,
382 	.flush_range	= 0x18,
383 	.flush_start	= 0x20,
384 	.flush_end	= 0x24,
385 	.int_status	= 0x60,
386 	.int_clear	= 0x64,
393 	.pt_base	= 0x0c,
394 	.flush_all	= 0x10,
395 	.flush_entry	= 0x14,
396 	.flush_range	= 0x18,
397 	.flush_start	= 0x20,
398 	.flush_end	= 0x24,
399 	.int_status	= 0x60,
400 	.int_clear	= 0x64,
401 	.fault_va	= 0x70,
402 	.fault_info	= 0x78,
409 	.pt_base	= 0x800c,
410 	.flush_all	= 0x8010,
411 	.flush_entry	= 0x8014,
412 	.flush_range	= 0x8018,
413 	.flush_start	= 0x8020,
414 	.flush_end	= 0x8024,
415 	.int_status	= 0x60,
416 	.int_clear	= 0x64,
417 	.fault_va	= 0x1000,
418 	.fault_info	= 0x1004,
438 	while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1))  in sysmmu_block()
451 	writel(0x1, SYSMMU_REG(data, flush_all));  in __sysmmu_tlb_invalidate()
460 		for (i = 0; i < num_inv; i++) {  in __sysmmu_tlb_invalidate_entry()
469 		writel(0x1, SYSMMU_REG(data, flush_range));  in __sysmmu_tlb_invalidate_entry()
525 	if (ver == 0x80000001u)  in __sysmmu_get_version()
526 		data->version = MAKE_MMU_VER(1, 0);  in __sysmmu_get_version()
613 	writel(0, data->sfrbase + REG_MMU_CFG);  in __sysmmu_disable()
681 			if (data->version >= MAKE_MMU_VER(5, 0))  in sysmmu_tlb_invalidate_flpdcache()
738 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in exynos_sysmmu_probe()
743 	irq = platform_get_irq(pdev, 0);  in exynos_sysmmu_probe()
744 	if (irq <= 0)  in exynos_sysmmu_probe()
747 	ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0,  in exynos_sysmmu_probe()
787 	if (PG_ENT_SHIFT < 0) {  in exynos_sysmmu_probe()
820 	return 0;  in exynos_sysmmu_probe()
842 	return 0;  in exynos_sysmmu_suspend()
860 	return 0;  in exynos_sysmmu_resume()
900 	BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev);  in exynos_iommu_domain_alloc_paging()
915 	for (i = 0; i < NUM_LV1ENTRIES; i++)  in exynos_iommu_domain_alloc_paging()
931 	domain->domain.geometry.aperture_start = 0;  in exynos_iommu_domain_alloc_paging()
932 	domain->domain.geometry.aperture_end   = ~0UL;  in exynos_iommu_domain_alloc_paging()
960 		data->pgtable = 0;  in exynos_iommu_domain_free()
971 	for (i = 0; i < NUM_LV1ENTRIES; i++)  in exynos_iommu_domain_free()
996 		return 0;  in exynos_iommu_identity_attach()
1013 		data->pgtable = 0;  in exynos_iommu_identity_attach()
1025 	return 0;  in exynos_iommu_identity_attach()
1076 	return 0;  in exynos_iommu_attach_device()
1154 		kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));  in lv1set_section()
1155 		*pgcnt = 0;  in lv1set_section()
1172 	return 0;  in lv1set_section()
1191 		for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {  in lv2set_page()
1193 				if (i > 0)  in lv2set_page()
1194 					memset(pent - i, 0, sizeof(*pent) * i);  in lv2set_page()
1206 	return 0;  in lv2set_page()
1337 		exynos_iommu_set_pte(ent, 0);  in exynos_iommu_unmap()
1352 	memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);  in exynos_iommu_unmap()
1370 	return 0;  in exynos_iommu_unmap()
1379 	phys_addr_t phys = 0;  in exynos_iommu_iova_to_phys()
1469 			return 0;  in exynos_iommu_of_xlate()
1474 	return 0;  in exynos_iommu_of_xlate()
1501 		return 0;  in exynos_iommu_init()
1506 				LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);  in exynos_iommu_init()
1526 	return 0;  in exynos_iommu_init()