10af62b01SAlex Deucher /* 20af62b01SAlex Deucher * Copyright 2010 Advanced Micro Devices, Inc. 30af62b01SAlex Deucher * 40af62b01SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 50af62b01SAlex Deucher * copy of this software and associated documentation files (the "Software"), 60af62b01SAlex Deucher * to deal in the Software without restriction, including without limitation 70af62b01SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 80af62b01SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 90af62b01SAlex Deucher * Software is furnished to do so, subject to the following conditions: 100af62b01SAlex Deucher * 110af62b01SAlex Deucher * The above copyright notice and this permission notice shall be included in 120af62b01SAlex Deucher * all copies or substantial portions of the Software. 130af62b01SAlex Deucher * 140af62b01SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 150af62b01SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 160af62b01SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 170af62b01SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 180af62b01SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 190af62b01SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 200af62b01SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 210af62b01SAlex Deucher * 220af62b01SAlex Deucher * Authors: Alex Deucher 230af62b01SAlex Deucher */ 240af62b01SAlex Deucher #ifndef NI_H 250af62b01SAlex Deucher #define NI_H 260af62b01SAlex Deucher 27fecf1d07SAlex Deucher #define CAYMAN_MAX_SH_GPRS 256 28fecf1d07SAlex Deucher #define CAYMAN_MAX_TEMP_GPRS 16 29fecf1d07SAlex Deucher #define CAYMAN_MAX_SH_THREADS 256 30fecf1d07SAlex Deucher #define CAYMAN_MAX_SH_STACK_ENTRIES 4096 31fecf1d07SAlex Deucher #define CAYMAN_MAX_FRC_EOV_CNT 16384 32fecf1d07SAlex Deucher #define CAYMAN_MAX_BACKENDS 8 33fecf1d07SAlex Deucher #define CAYMAN_MAX_BACKENDS_MASK 0xFF 34fecf1d07SAlex Deucher #define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF 35fecf1d07SAlex Deucher #define CAYMAN_MAX_SIMDS 16 36fecf1d07SAlex Deucher #define CAYMAN_MAX_SIMDS_MASK 0xFFFF 37fecf1d07SAlex Deucher #define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF 38fecf1d07SAlex Deucher #define CAYMAN_MAX_PIPES 8 39fecf1d07SAlex Deucher #define CAYMAN_MAX_PIPES_MASK 0xFF 40fecf1d07SAlex Deucher #define CAYMAN_MAX_LDS_NUM 0xFFFF 41fecf1d07SAlex Deucher #define CAYMAN_MAX_TCC 16 42fecf1d07SAlex Deucher #define CAYMAN_MAX_TCC_MASK 0xFF 43fecf1d07SAlex Deucher 44416a2bd2SAlex Deucher #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 45416a2bd2SAlex Deucher #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001 46416a2bd2SAlex Deucher 47fecf1d07SAlex Deucher #define DMIF_ADDR_CONFIG 0xBD4 487c1c7c18SAlex Deucher 490fda42acSAlex Deucher /* fusion vce clocks */ 500fda42acSAlex Deucher #define CG_ECLK_CNTL 0x620 510fda42acSAlex Deucher # define ECLK_DIVIDER_MASK 0x7f 520fda42acSAlex Deucher # define ECLK_DIR_CNTL_EN (1 << 8) 530fda42acSAlex Deucher #define CG_ECLK_STATUS 0x624 540fda42acSAlex Deucher # define ECLK_STATUS (1 << 0) 550fda42acSAlex Deucher 567c1c7c18SAlex Deucher /* DCE6 only */ 577c1c7c18SAlex Deucher #define DMIF_ADDR_CALC 0xC00 587c1c7c18SAlex Deucher 591b37078bSAlex Deucher #define SRBM_GFX_CNTL 0x0E44 601b37078bSAlex Deucher #define RINGID(x) (((x) & 0x3) << 0) 611b37078bSAlex Deucher #define VMID(x) (((x) & 0x7) << 0) 62b9952a8aSAlex Deucher #define SRBM_STATUS 0x0E50 63168757eaSAlex Deucher #define RLC_RQ_PENDING (1 << 3) 64168757eaSAlex Deucher #define GRBM_RQ_PENDING (1 << 5) 65168757eaSAlex Deucher #define VMC_BUSY (1 << 8) 66168757eaSAlex Deucher #define MCB_BUSY (1 << 9) 67168757eaSAlex Deucher #define MCB_NON_DISPLAY_BUSY (1 << 10) 68168757eaSAlex Deucher #define MCC_BUSY (1 << 11) 69168757eaSAlex Deucher #define MCD_BUSY (1 << 12) 70168757eaSAlex Deucher #define SEM_BUSY (1 << 14) 71168757eaSAlex Deucher #define RLC_BUSY (1 << 15) 72168757eaSAlex Deucher #define IH_BUSY (1 << 17) 73fecf1d07SAlex Deucher 74f60cbd11SAlex Deucher #define SRBM_SOFT_RESET 0x0E60 75f60cbd11SAlex Deucher #define SOFT_RESET_BIF (1 << 1) 76f60cbd11SAlex Deucher #define SOFT_RESET_CG (1 << 2) 77f60cbd11SAlex Deucher #define SOFT_RESET_DC (1 << 5) 78f60cbd11SAlex Deucher #define SOFT_RESET_DMA1 (1 << 6) 79f60cbd11SAlex Deucher #define SOFT_RESET_GRBM (1 << 8) 80f60cbd11SAlex Deucher #define SOFT_RESET_HDP (1 << 9) 81f60cbd11SAlex Deucher #define SOFT_RESET_IH (1 << 10) 82f60cbd11SAlex Deucher #define SOFT_RESET_MC (1 << 11) 83f60cbd11SAlex Deucher #define SOFT_RESET_RLC (1 << 13) 84f60cbd11SAlex Deucher #define SOFT_RESET_ROM (1 << 14) 85f60cbd11SAlex Deucher #define SOFT_RESET_SEM (1 << 15) 86f60cbd11SAlex Deucher #define SOFT_RESET_VMC (1 << 17) 87f60cbd11SAlex Deucher #define SOFT_RESET_DMA (1 << 20) 88f60cbd11SAlex Deucher #define SOFT_RESET_TST (1 << 21) 89f60cbd11SAlex Deucher #define SOFT_RESET_REGBB (1 << 22) 90f60cbd11SAlex Deucher #define SOFT_RESET_ORB (1 << 23) 91f60cbd11SAlex Deucher 92acc1522aSChristian König #define SRBM_READ_ERROR 0xE98 93acc1522aSChristian König #define SRBM_INT_CNTL 0xEA0 94acc1522aSChristian König #define SRBM_INT_ACK 0xEA8 95acc1522aSChristian König 96168757eaSAlex Deucher #define SRBM_STATUS2 0x0EC4 97168757eaSAlex Deucher #define DMA_BUSY (1 << 5) 98168757eaSAlex Deucher #define DMA1_BUSY (1 << 6) 99168757eaSAlex Deucher 100fa8198eaSAlex Deucher #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 101fa8198eaSAlex Deucher #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 102fa8198eaSAlex Deucher #define RESPONSE_TYPE_MASK 0x000000F0 103fa8198eaSAlex Deucher #define RESPONSE_TYPE_SHIFT 4 104fa8198eaSAlex Deucher #define VM_L2_CNTL 0x1400 105fa8198eaSAlex Deucher #define ENABLE_L2_CACHE (1 << 0) 106fa8198eaSAlex Deucher #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 107fa8198eaSAlex Deucher #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 108fa8198eaSAlex Deucher #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 109fa8198eaSAlex Deucher #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 110fa8198eaSAlex Deucher #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18) 111fa8198eaSAlex Deucher /* CONTEXT1_IDENTITY_ACCESS_MODE 112fa8198eaSAlex Deucher * 0 physical = logical 113fa8198eaSAlex Deucher * 1 logical via context1 page table 114fa8198eaSAlex Deucher * 2 inside identity aperture use translation, outside physical = logical 115fa8198eaSAlex Deucher * 3 inside identity aperture physical = logical, outside use translation 116fa8198eaSAlex Deucher */ 117fa8198eaSAlex Deucher #define VM_L2_CNTL2 0x1404 118fa8198eaSAlex Deucher #define INVALIDATE_ALL_L1_TLBS (1 << 0) 119fa8198eaSAlex Deucher #define INVALIDATE_L2_CACHE (1 << 1) 120fa8198eaSAlex Deucher #define VM_L2_CNTL3 0x1408 121fa8198eaSAlex Deucher #define BANK_SELECT(x) ((x) << 0) 122fa8198eaSAlex Deucher #define CACHE_UPDATE_MODE(x) ((x) << 6) 123fa8198eaSAlex Deucher #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 124fa8198eaSAlex Deucher #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 125fa8198eaSAlex Deucher #define VM_L2_STATUS 0x140C 126fa8198eaSAlex Deucher #define L2_BUSY (1 << 0) 127fa8198eaSAlex Deucher #define VM_CONTEXT0_CNTL 0x1410 128fa8198eaSAlex Deucher #define ENABLE_CONTEXT (1 << 0) 129fa8198eaSAlex Deucher #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 130ae133a11SChristian König #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 131fa8198eaSAlex Deucher #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 132ae133a11SChristian König #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 133ae133a11SChristian König #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 134ae133a11SChristian König #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 135ae133a11SChristian König #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 136ae133a11SChristian König #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 137ae133a11SChristian König #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 138ae133a11SChristian König #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 139ae133a11SChristian König #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 140ae133a11SChristian König #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 141ae133a11SChristian König #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 1421c89d27fSChristian König #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) 143fa8198eaSAlex Deucher #define VM_CONTEXT1_CNTL 0x1414 144fa8198eaSAlex Deucher #define VM_CONTEXT0_CNTL2 0x1430 145fa8198eaSAlex Deucher #define VM_CONTEXT1_CNTL2 0x1434 146fa8198eaSAlex Deucher #define VM_INVALIDATE_REQUEST 0x1478 147fa8198eaSAlex Deucher #define VM_INVALIDATE_RESPONSE 0x147c 14854e2e49cSAlex Deucher #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 14954e2e49cSAlex Deucher #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 15054e2e49cSAlex Deucher #define PROTECTIONS_MASK (0xf << 0) 15154e2e49cSAlex Deucher #define PROTECTIONS_SHIFT 0 15254e2e49cSAlex Deucher /* bit 0: range 15354e2e49cSAlex Deucher * bit 2: pde0 15454e2e49cSAlex Deucher * bit 3: valid 15554e2e49cSAlex Deucher * bit 4: read 15654e2e49cSAlex Deucher * bit 5: write 15754e2e49cSAlex Deucher */ 15854e2e49cSAlex Deucher #define MEMORY_CLIENT_ID_MASK (0xff << 12) 15954e2e49cSAlex Deucher #define MEMORY_CLIENT_ID_SHIFT 12 16054e2e49cSAlex Deucher #define MEMORY_CLIENT_RW_MASK (1 << 24) 16154e2e49cSAlex Deucher #define MEMORY_CLIENT_RW_SHIFT 24 16254e2e49cSAlex Deucher #define FAULT_VMID_MASK (0x7 << 25) 16354e2e49cSAlex Deucher #define FAULT_VMID_SHIFT 25 164fa8198eaSAlex Deucher #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 165fa8198eaSAlex Deucher #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 166fa8198eaSAlex Deucher #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 167fa8198eaSAlex Deucher #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 168fa8198eaSAlex Deucher #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 169fa8198eaSAlex Deucher 170fecf1d07SAlex Deucher #define MC_SHARED_CHMAP 0x2004 171fecf1d07SAlex Deucher #define NOOFCHAN_SHIFT 12 172fecf1d07SAlex Deucher #define NOOFCHAN_MASK 0x00003000 173fecf1d07SAlex Deucher #define MC_SHARED_CHREMAP 0x2008 174fa8198eaSAlex Deucher 175fa8198eaSAlex Deucher #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 176fa8198eaSAlex Deucher #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 177fa8198eaSAlex Deucher #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 178fa8198eaSAlex Deucher #define MC_VM_MX_L1_TLB_CNTL 0x2064 179fa8198eaSAlex Deucher #define ENABLE_L1_TLB (1 << 0) 180fa8198eaSAlex Deucher #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 181fa8198eaSAlex Deucher #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 182fa8198eaSAlex Deucher #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 183fa8198eaSAlex Deucher #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 184fa8198eaSAlex Deucher #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 185fa8198eaSAlex Deucher #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 186fa8198eaSAlex Deucher #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 18705b3ef69SAlex Deucher #define FUS_MC_VM_FB_OFFSET 0x2068 188fa8198eaSAlex Deucher 1890af62b01SAlex Deucher #define MC_SHARED_BLACKOUT_CNTL 0x20ac 190fecf1d07SAlex Deucher #define MC_ARB_RAMCFG 0x2760 191fecf1d07SAlex Deucher #define NOOFBANK_SHIFT 0 192fecf1d07SAlex Deucher #define NOOFBANK_MASK 0x00000003 193fecf1d07SAlex Deucher #define NOOFRANK_SHIFT 2 194fecf1d07SAlex Deucher #define NOOFRANK_MASK 0x00000004 195fecf1d07SAlex Deucher #define NOOFROWS_SHIFT 3 196fecf1d07SAlex Deucher #define NOOFROWS_MASK 0x00000038 197fecf1d07SAlex Deucher #define NOOFCOLS_SHIFT 6 198fecf1d07SAlex Deucher #define NOOFCOLS_MASK 0x000000C0 199fecf1d07SAlex Deucher #define CHANSIZE_SHIFT 8 200fecf1d07SAlex Deucher #define CHANSIZE_MASK 0x00000100 201fecf1d07SAlex Deucher #define BURSTLENGTH_SHIFT 9 202fecf1d07SAlex Deucher #define BURSTLENGTH_MASK 0x00000200 203fecf1d07SAlex Deucher #define CHANSIZE_OVERRIDE (1 << 11) 2040af62b01SAlex Deucher #define MC_SEQ_SUP_CNTL 0x28c8 2050af62b01SAlex Deucher #define RUN_MASK (1 << 0) 2060af62b01SAlex Deucher #define MC_SEQ_SUP_PGM 0x28cc 2070af62b01SAlex Deucher #define MC_IO_PAD_CNTL_D0 0x29d0 2080af62b01SAlex Deucher #define MEM_FALL_OUT_CMD (1 << 8) 2090af62b01SAlex Deucher #define MC_SEQ_MISC0 0x2a00 2100af62b01SAlex Deucher #define MC_SEQ_MISC0_GDDR5_SHIFT 28 2110af62b01SAlex Deucher #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 2120af62b01SAlex Deucher #define MC_SEQ_MISC0_GDDR5_VALUE 5 2130af62b01SAlex Deucher #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 2140af62b01SAlex Deucher #define MC_SEQ_IO_DEBUG_DATA 0x2a48 2150af62b01SAlex Deucher 216fecf1d07SAlex Deucher #define HDP_HOST_PATH_CNTL 0x2C00 217fecf1d07SAlex Deucher #define HDP_NONSURFACE_BASE 0x2C04 218fecf1d07SAlex Deucher #define HDP_NONSURFACE_INFO 0x2C08 219fecf1d07SAlex Deucher #define HDP_NONSURFACE_SIZE 0x2C0C 220fecf1d07SAlex Deucher #define HDP_ADDR_CONFIG 0x2F48 2210b65f83fSDave Airlie #define HDP_MISC_CNTL 0x2F4C 2220b65f83fSDave Airlie #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 223fecf1d07SAlex Deucher 224fecf1d07SAlex Deucher #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 225fecf1d07SAlex Deucher #define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C 226fecf1d07SAlex Deucher #define CGTS_SYS_TCC_DISABLE 0x3F90 227fecf1d07SAlex Deucher #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 228fecf1d07SAlex Deucher 229416a2bd2SAlex Deucher #define RLC_GFX_INDEX 0x3FC4 230416a2bd2SAlex Deucher 231fecf1d07SAlex Deucher #define CONFIG_MEMSIZE 0x5428 232fecf1d07SAlex Deucher 233fa8198eaSAlex Deucher #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 234fecf1d07SAlex Deucher #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 235fecf1d07SAlex Deucher 236fecf1d07SAlex Deucher #define GRBM_CNTL 0x8000 237fecf1d07SAlex Deucher #define GRBM_READ_TIMEOUT(x) ((x) << 0) 238fecf1d07SAlex Deucher #define GRBM_STATUS 0x8010 239fecf1d07SAlex Deucher #define CMDFIFO_AVAIL_MASK 0x0000000F 240fecf1d07SAlex Deucher #define RING2_RQ_PENDING (1 << 4) 241fecf1d07SAlex Deucher #define SRBM_RQ_PENDING (1 << 5) 242fecf1d07SAlex Deucher #define RING1_RQ_PENDING (1 << 6) 243fecf1d07SAlex Deucher #define CF_RQ_PENDING (1 << 7) 244fecf1d07SAlex Deucher #define PF_RQ_PENDING (1 << 8) 245fecf1d07SAlex Deucher #define GDS_DMA_RQ_PENDING (1 << 9) 246fecf1d07SAlex Deucher #define GRBM_EE_BUSY (1 << 10) 247fecf1d07SAlex Deucher #define SX_CLEAN (1 << 11) 248fecf1d07SAlex Deucher #define DB_CLEAN (1 << 12) 249fecf1d07SAlex Deucher #define CB_CLEAN (1 << 13) 250fecf1d07SAlex Deucher #define TA_BUSY (1 << 14) 251fecf1d07SAlex Deucher #define GDS_BUSY (1 << 15) 252fecf1d07SAlex Deucher #define VGT_BUSY_NO_DMA (1 << 16) 253fecf1d07SAlex Deucher #define VGT_BUSY (1 << 17) 254fecf1d07SAlex Deucher #define IA_BUSY_NO_DMA (1 << 18) 255fecf1d07SAlex Deucher #define IA_BUSY (1 << 19) 256fecf1d07SAlex Deucher #define SX_BUSY (1 << 20) 257fecf1d07SAlex Deucher #define SH_BUSY (1 << 21) 258fecf1d07SAlex Deucher #define SPI_BUSY (1 << 22) 259fecf1d07SAlex Deucher #define SC_BUSY (1 << 24) 260fecf1d07SAlex Deucher #define PA_BUSY (1 << 25) 261fecf1d07SAlex Deucher #define DB_BUSY (1 << 26) 262fecf1d07SAlex Deucher #define CP_COHERENCY_BUSY (1 << 28) 263fecf1d07SAlex Deucher #define CP_BUSY (1 << 29) 264fecf1d07SAlex Deucher #define CB_BUSY (1 << 30) 265fecf1d07SAlex Deucher #define GUI_ACTIVE (1 << 31) 266fecf1d07SAlex Deucher #define GRBM_STATUS_SE0 0x8014 267fecf1d07SAlex Deucher #define GRBM_STATUS_SE1 0x8018 268fecf1d07SAlex Deucher #define SE_SX_CLEAN (1 << 0) 269fecf1d07SAlex Deucher #define SE_DB_CLEAN (1 << 1) 270fecf1d07SAlex Deucher #define SE_CB_CLEAN (1 << 2) 271fecf1d07SAlex Deucher #define SE_VGT_BUSY (1 << 23) 272fecf1d07SAlex Deucher #define SE_PA_BUSY (1 << 24) 273fecf1d07SAlex Deucher #define SE_TA_BUSY (1 << 25) 274fecf1d07SAlex Deucher #define SE_SX_BUSY (1 << 26) 275fecf1d07SAlex Deucher #define SE_SPI_BUSY (1 << 27) 276fecf1d07SAlex Deucher #define SE_SH_BUSY (1 << 28) 277fecf1d07SAlex Deucher #define SE_SC_BUSY (1 << 29) 278fecf1d07SAlex Deucher #define SE_DB_BUSY (1 << 30) 279fecf1d07SAlex Deucher #define SE_CB_BUSY (1 << 31) 280fecf1d07SAlex Deucher #define GRBM_SOFT_RESET 0x8020 281fecf1d07SAlex Deucher #define SOFT_RESET_CP (1 << 0) 282fecf1d07SAlex Deucher #define SOFT_RESET_CB (1 << 1) 283fecf1d07SAlex Deucher #define SOFT_RESET_DB (1 << 3) 284fecf1d07SAlex Deucher #define SOFT_RESET_GDS (1 << 4) 285fecf1d07SAlex Deucher #define SOFT_RESET_PA (1 << 5) 286fecf1d07SAlex Deucher #define SOFT_RESET_SC (1 << 6) 287fecf1d07SAlex Deucher #define SOFT_RESET_SPI (1 << 8) 288fecf1d07SAlex Deucher #define SOFT_RESET_SH (1 << 9) 289fecf1d07SAlex Deucher #define SOFT_RESET_SX (1 << 10) 290fecf1d07SAlex Deucher #define SOFT_RESET_TC (1 << 11) 291fecf1d07SAlex Deucher #define SOFT_RESET_TA (1 << 12) 292fecf1d07SAlex Deucher #define SOFT_RESET_VGT (1 << 14) 293fecf1d07SAlex Deucher #define SOFT_RESET_IA (1 << 15) 294fecf1d07SAlex Deucher 295416a2bd2SAlex Deucher #define GRBM_GFX_INDEX 0x802C 296416a2bd2SAlex Deucher #define INSTANCE_INDEX(x) ((x) << 0) 297416a2bd2SAlex Deucher #define SE_INDEX(x) ((x) << 16) 298416a2bd2SAlex Deucher #define INSTANCE_BROADCAST_WRITES (1 << 30) 299416a2bd2SAlex Deucher #define SE_BROADCAST_WRITES (1 << 31) 300416a2bd2SAlex Deucher 3010c88a02eSAlex Deucher #define SCRATCH_REG0 0x8500 3020c88a02eSAlex Deucher #define SCRATCH_REG1 0x8504 3030c88a02eSAlex Deucher #define SCRATCH_REG2 0x8508 3040c88a02eSAlex Deucher #define SCRATCH_REG3 0x850C 3050c88a02eSAlex Deucher #define SCRATCH_REG4 0x8510 3060c88a02eSAlex Deucher #define SCRATCH_REG5 0x8514 3070c88a02eSAlex Deucher #define SCRATCH_REG6 0x8518 3080c88a02eSAlex Deucher #define SCRATCH_REG7 0x851C 3090c88a02eSAlex Deucher #define SCRATCH_UMSK 0x8540 3100c88a02eSAlex Deucher #define SCRATCH_ADDR 0x8544 3110c88a02eSAlex Deucher #define CP_SEM_WAIT_TIMER 0x85BC 31211ef3f1fSAlex Deucher #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 313721604a1SJerome Glisse #define CP_COHER_CNTL2 0x85E8 314440a7cd8SJerome Glisse #define CP_STALLED_STAT1 0x8674 315440a7cd8SJerome Glisse #define CP_STALLED_STAT2 0x8678 316440a7cd8SJerome Glisse #define CP_BUSY_STAT 0x867C 317440a7cd8SJerome Glisse #define CP_STAT 0x8680 3180c88a02eSAlex Deucher #define CP_ME_CNTL 0x86D8 3190c88a02eSAlex Deucher #define CP_ME_HALT (1 << 28) 3200c88a02eSAlex Deucher #define CP_PFP_HALT (1 << 26) 3210c88a02eSAlex Deucher #define CP_RB2_RPTR 0x86f8 3220c88a02eSAlex Deucher #define CP_RB1_RPTR 0x86fc 3230c88a02eSAlex Deucher #define CP_RB0_RPTR 0x8700 3240c88a02eSAlex Deucher #define CP_RB_WPTR_DELAY 0x8704 325fecf1d07SAlex Deucher #define CP_MEQ_THRESHOLDS 0x8764 326fecf1d07SAlex Deucher #define MEQ1_START(x) ((x) << 0) 327fecf1d07SAlex Deucher #define MEQ2_START(x) ((x) << 8) 328fecf1d07SAlex Deucher #define CP_PERFMON_CNTL 0x87FC 329fecf1d07SAlex Deucher 330fecf1d07SAlex Deucher #define VGT_CACHE_INVALIDATION 0x88C4 331fecf1d07SAlex Deucher #define CACHE_INVALIDATION(x) ((x) << 0) 332fecf1d07SAlex Deucher #define VC_ONLY 0 333fecf1d07SAlex Deucher #define TC_ONLY 1 334fecf1d07SAlex Deucher #define VC_AND_TC 2 335fecf1d07SAlex Deucher #define AUTO_INVLD_EN(x) ((x) << 6) 336fecf1d07SAlex Deucher #define NO_AUTO 0 337fecf1d07SAlex Deucher #define ES_AUTO 1 338fecf1d07SAlex Deucher #define GS_AUTO 2 339fecf1d07SAlex Deucher #define ES_AND_GS_AUTO 3 340fecf1d07SAlex Deucher #define VGT_GS_VERTEX_REUSE 0x88D4 341fecf1d07SAlex Deucher 342fecf1d07SAlex Deucher #define CC_GC_SHADER_PIPE_CONFIG 0x8950 343fecf1d07SAlex Deucher #define GC_USER_SHADER_PIPE_CONFIG 0x8954 344fecf1d07SAlex Deucher #define INACTIVE_QD_PIPES(x) ((x) << 8) 345fecf1d07SAlex Deucher #define INACTIVE_QD_PIPES_MASK 0x0000FF00 346fecf1d07SAlex Deucher #define INACTIVE_QD_PIPES_SHIFT 8 347fecf1d07SAlex Deucher #define INACTIVE_SIMDS(x) ((x) << 16) 348fecf1d07SAlex Deucher #define INACTIVE_SIMDS_MASK 0xFFFF0000 349fecf1d07SAlex Deucher #define INACTIVE_SIMDS_SHIFT 16 350fecf1d07SAlex Deucher 351fecf1d07SAlex Deucher #define VGT_PRIMITIVE_TYPE 0x8958 352fecf1d07SAlex Deucher #define VGT_NUM_INSTANCES 0x8974 353fecf1d07SAlex Deucher #define VGT_TF_RING_SIZE 0x8988 354fecf1d07SAlex Deucher #define VGT_OFFCHIP_LDS_BASE 0x89b4 355fecf1d07SAlex Deucher 356fecf1d07SAlex Deucher #define PA_SC_LINE_STIPPLE_STATE 0x8B10 357fecf1d07SAlex Deucher #define PA_CL_ENHANCE 0x8A14 358fecf1d07SAlex Deucher #define CLIP_VTX_REORDER_ENA (1 << 0) 359fecf1d07SAlex Deucher #define NUM_CLIP_SEQ(x) ((x) << 1) 360fecf1d07SAlex Deucher #define PA_SC_FIFO_SIZE 0x8BCC 361fecf1d07SAlex Deucher #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 362fecf1d07SAlex Deucher #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 363fecf1d07SAlex Deucher #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 364fecf1d07SAlex Deucher #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 365fecf1d07SAlex Deucher #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 366fecf1d07SAlex Deucher #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 367fecf1d07SAlex Deucher 368fecf1d07SAlex Deucher #define SQ_CONFIG 0x8C00 369fecf1d07SAlex Deucher #define VC_ENABLE (1 << 0) 370fecf1d07SAlex Deucher #define EXPORT_SRC_C (1 << 1) 371fecf1d07SAlex Deucher #define GFX_PRIO(x) ((x) << 2) 372fecf1d07SAlex Deucher #define CS1_PRIO(x) ((x) << 4) 373fecf1d07SAlex Deucher #define CS2_PRIO(x) ((x) << 6) 374fecf1d07SAlex Deucher #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 375fecf1d07SAlex Deucher #define NUM_PS_GPRS(x) ((x) << 0) 376fecf1d07SAlex Deucher #define NUM_VS_GPRS(x) ((x) << 16) 377fecf1d07SAlex Deucher #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 378fecf1d07SAlex Deucher #define SQ_ESGS_RING_SIZE 0x8c44 379fecf1d07SAlex Deucher #define SQ_GSVS_RING_SIZE 0x8c4c 380fecf1d07SAlex Deucher #define SQ_ESTMP_RING_BASE 0x8c50 381fecf1d07SAlex Deucher #define SQ_ESTMP_RING_SIZE 0x8c54 382fecf1d07SAlex Deucher #define SQ_GSTMP_RING_BASE 0x8c58 383fecf1d07SAlex Deucher #define SQ_GSTMP_RING_SIZE 0x8c5c 384fecf1d07SAlex Deucher #define SQ_VSTMP_RING_BASE 0x8c60 385fecf1d07SAlex Deucher #define SQ_VSTMP_RING_SIZE 0x8c64 386fecf1d07SAlex Deucher #define SQ_PSTMP_RING_BASE 0x8c68 387fecf1d07SAlex Deucher #define SQ_PSTMP_RING_SIZE 0x8c6c 388fecf1d07SAlex Deucher #define SQ_MS_FIFO_SIZES 0x8CF0 389fecf1d07SAlex Deucher #define CACHE_FIFO_SIZE(x) ((x) << 0) 390fecf1d07SAlex Deucher #define FETCH_FIFO_HIWATER(x) ((x) << 8) 391fecf1d07SAlex Deucher #define DONE_FIFO_HIWATER(x) ((x) << 16) 392fecf1d07SAlex Deucher #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 393fecf1d07SAlex Deucher #define SQ_LSTMP_RING_BASE 0x8e10 394fecf1d07SAlex Deucher #define SQ_LSTMP_RING_SIZE 0x8e14 395fecf1d07SAlex Deucher #define SQ_HSTMP_RING_BASE 0x8e18 396fecf1d07SAlex Deucher #define SQ_HSTMP_RING_SIZE 0x8e1c 397fecf1d07SAlex Deucher #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 398fecf1d07SAlex Deucher #define DYN_GPR_ENABLE (1 << 8) 399fecf1d07SAlex Deucher #define SQ_CONST_MEM_BASE 0x8df8 400fecf1d07SAlex Deucher 401fecf1d07SAlex Deucher #define SX_EXPORT_BUFFER_SIZES 0x900C 402fecf1d07SAlex Deucher #define COLOR_BUFFER_SIZE(x) ((x) << 0) 403fecf1d07SAlex Deucher #define POSITION_BUFFER_SIZE(x) ((x) << 8) 404fecf1d07SAlex Deucher #define SMX_BUFFER_SIZE(x) ((x) << 16) 405fecf1d07SAlex Deucher #define SX_DEBUG_1 0x9058 406fecf1d07SAlex Deucher #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 407fecf1d07SAlex Deucher 408fecf1d07SAlex Deucher #define SPI_CONFIG_CNTL 0x9100 409fecf1d07SAlex Deucher #define GPR_WRITE_PRIORITY(x) ((x) << 0) 410fecf1d07SAlex Deucher #define SPI_CONFIG_CNTL_1 0x913C 411fecf1d07SAlex Deucher #define VTX_DONE_DELAY(x) ((x) << 0) 412fecf1d07SAlex Deucher #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 413fecf1d07SAlex Deucher #define CRC_SIMD_ID_WADDR_DISABLE (1 << 8) 414fecf1d07SAlex Deucher 415fecf1d07SAlex Deucher #define CGTS_TCC_DISABLE 0x9148 416fecf1d07SAlex Deucher #define CGTS_USER_TCC_DISABLE 0x914C 417fecf1d07SAlex Deucher #define TCC_DISABLE_MASK 0xFFFF0000 418fecf1d07SAlex Deucher #define TCC_DISABLE_SHIFT 16 4192498c41eSAlex Deucher #define CGTS_SM_CTRL_REG 0x9150 420fecf1d07SAlex Deucher #define OVERRIDE (1 << 21) 421fecf1d07SAlex Deucher 422fecf1d07SAlex Deucher #define TA_CNTL_AUX 0x9508 423fecf1d07SAlex Deucher #define DISABLE_CUBE_WRAP (1 << 0) 424fecf1d07SAlex Deucher #define DISABLE_CUBE_ANISO (1 << 1) 425fecf1d07SAlex Deucher 426fecf1d07SAlex Deucher #define TCP_CHAN_STEER_LO 0x960c 427fecf1d07SAlex Deucher #define TCP_CHAN_STEER_HI 0x9610 428fecf1d07SAlex Deucher 429fecf1d07SAlex Deucher #define CC_RB_BACKEND_DISABLE 0x98F4 430fecf1d07SAlex Deucher #define BACKEND_DISABLE(x) ((x) << 16) 431fecf1d07SAlex Deucher #define GB_ADDR_CONFIG 0x98F8 432fecf1d07SAlex Deucher #define NUM_PIPES(x) ((x) << 0) 433fecf1d07SAlex Deucher #define NUM_PIPES_MASK 0x00000007 434fecf1d07SAlex Deucher #define NUM_PIPES_SHIFT 0 435fecf1d07SAlex Deucher #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 436fecf1d07SAlex Deucher #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 437fecf1d07SAlex Deucher #define PIPE_INTERLEAVE_SIZE_SHIFT 4 438fecf1d07SAlex Deucher #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 439fecf1d07SAlex Deucher #define NUM_SHADER_ENGINES(x) ((x) << 12) 440fecf1d07SAlex Deucher #define NUM_SHADER_ENGINES_MASK 0x00003000 441fecf1d07SAlex Deucher #define NUM_SHADER_ENGINES_SHIFT 12 442fecf1d07SAlex Deucher #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 443fecf1d07SAlex Deucher #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 444fecf1d07SAlex Deucher #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 445fecf1d07SAlex Deucher #define NUM_GPUS(x) ((x) << 20) 446fecf1d07SAlex Deucher #define NUM_GPUS_MASK 0x00700000 447fecf1d07SAlex Deucher #define NUM_GPUS_SHIFT 20 448fecf1d07SAlex Deucher #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 449fecf1d07SAlex Deucher #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 450fecf1d07SAlex Deucher #define MULTI_GPU_TILE_SIZE_SHIFT 24 451fecf1d07SAlex Deucher #define ROW_SIZE(x) ((x) << 28) 452bb92091aSAlex Deucher #define ROW_SIZE_MASK 0x30000000 453fecf1d07SAlex Deucher #define ROW_SIZE_SHIFT 28 454fecf1d07SAlex Deucher #define NUM_LOWER_PIPES(x) ((x) << 30) 455fecf1d07SAlex Deucher #define NUM_LOWER_PIPES_MASK 0x40000000 456fecf1d07SAlex Deucher #define NUM_LOWER_PIPES_SHIFT 30 457fecf1d07SAlex Deucher #define GB_BACKEND_MAP 0x98FC 458fecf1d07SAlex Deucher 459fecf1d07SAlex Deucher #define CB_PERF_CTR0_SEL_0 0x9A20 460fecf1d07SAlex Deucher #define CB_PERF_CTR0_SEL_1 0x9A24 461fecf1d07SAlex Deucher #define CB_PERF_CTR1_SEL_0 0x9A28 462fecf1d07SAlex Deucher #define CB_PERF_CTR1_SEL_1 0x9A2C 463fecf1d07SAlex Deucher #define CB_PERF_CTR2_SEL_0 0x9A30 464fecf1d07SAlex Deucher #define CB_PERF_CTR2_SEL_1 0x9A34 465fecf1d07SAlex Deucher #define CB_PERF_CTR3_SEL_0 0x9A38 466fecf1d07SAlex Deucher #define CB_PERF_CTR3_SEL_1 0x9A3C 467fecf1d07SAlex Deucher 468fecf1d07SAlex Deucher #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 469fecf1d07SAlex Deucher #define BACKEND_DISABLE_MASK 0x00FF0000 470fecf1d07SAlex Deucher #define BACKEND_DISABLE_SHIFT 16 471fecf1d07SAlex Deucher 472fecf1d07SAlex Deucher #define SMX_DC_CTL0 0xA020 473fecf1d07SAlex Deucher #define USE_HASH_FUNCTION (1 << 0) 474fecf1d07SAlex Deucher #define NUMBER_OF_SETS(x) ((x) << 1) 475fecf1d07SAlex Deucher #define FLUSH_ALL_ON_EVENT (1 << 10) 476fecf1d07SAlex Deucher #define STALL_ON_EVENT (1 << 11) 477fecf1d07SAlex Deucher #define SMX_EVENT_CTL 0xA02C 478fecf1d07SAlex Deucher #define ES_FLUSH_CTL(x) ((x) << 0) 479fecf1d07SAlex Deucher #define GS_FLUSH_CTL(x) ((x) << 3) 480fecf1d07SAlex Deucher #define ACK_FLUSH_CTL(x) ((x) << 6) 481fecf1d07SAlex Deucher #define SYNC_FLUSH_CTL (1 << 8) 482fecf1d07SAlex Deucher 4830c88a02eSAlex Deucher #define CP_RB0_BASE 0xC100 4840c88a02eSAlex Deucher #define CP_RB0_CNTL 0xC104 4850c88a02eSAlex Deucher #define RB_BUFSZ(x) ((x) << 0) 4860c88a02eSAlex Deucher #define RB_BLKSZ(x) ((x) << 8) 4870c88a02eSAlex Deucher #define RB_NO_UPDATE (1 << 27) 4880c88a02eSAlex Deucher #define RB_RPTR_WR_ENA (1 << 31) 4890c88a02eSAlex Deucher #define BUF_SWAP_32BIT (2 << 16) 4900c88a02eSAlex Deucher #define CP_RB0_RPTR_ADDR 0xC10C 4910c88a02eSAlex Deucher #define CP_RB0_RPTR_ADDR_HI 0xC110 4920c88a02eSAlex Deucher #define CP_RB0_WPTR 0xC114 4931b37078bSAlex Deucher 4941b37078bSAlex Deucher #define CP_INT_CNTL 0xC124 4951b37078bSAlex Deucher # define CNTX_BUSY_INT_ENABLE (1 << 19) 4961b37078bSAlex Deucher # define CNTX_EMPTY_INT_ENABLE (1 << 20) 4971b37078bSAlex Deucher # define TIME_STAMP_INT_ENABLE (1 << 26) 4981b37078bSAlex Deucher 4990c88a02eSAlex Deucher #define CP_RB1_BASE 0xC180 5000c88a02eSAlex Deucher #define CP_RB1_CNTL 0xC184 5010c88a02eSAlex Deucher #define CP_RB1_RPTR_ADDR 0xC188 5020c88a02eSAlex Deucher #define CP_RB1_RPTR_ADDR_HI 0xC18C 5030c88a02eSAlex Deucher #define CP_RB1_WPTR 0xC190 5040c88a02eSAlex Deucher #define CP_RB2_BASE 0xC194 5050c88a02eSAlex Deucher #define CP_RB2_CNTL 0xC198 5060c88a02eSAlex Deucher #define CP_RB2_RPTR_ADDR 0xC19C 5070c88a02eSAlex Deucher #define CP_RB2_RPTR_ADDR_HI 0xC1A0 5080c88a02eSAlex Deucher #define CP_RB2_WPTR 0xC1A4 5090c88a02eSAlex Deucher #define CP_PFP_UCODE_ADDR 0xC150 5100c88a02eSAlex Deucher #define CP_PFP_UCODE_DATA 0xC154 5110c88a02eSAlex Deucher #define CP_ME_RAM_RADDR 0xC158 5120c88a02eSAlex Deucher #define CP_ME_RAM_WADDR 0xC15C 5130c88a02eSAlex Deucher #define CP_ME_RAM_DATA 0xC160 5140c88a02eSAlex Deucher #define CP_DEBUG 0xC1FC 5150c88a02eSAlex Deucher 516b40e7e16SAlex Deucher #define VGT_EVENT_INITIATOR 0x28a90 517b40e7e16SAlex Deucher # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) 518b40e7e16SAlex Deucher # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 519b40e7e16SAlex Deucher 52029a15221SAlex Deucher /* TN SMU registers */ 52129a15221SAlex Deucher #define TN_CURRENT_GNB_TEMP 0x1F390 52229a15221SAlex Deucher 52369e0b57aSAlex Deucher /* pm registers */ 52469e0b57aSAlex Deucher #define SMC_MSG 0x20c 52569e0b57aSAlex Deucher #define HOST_SMC_MSG(x) ((x) << 0) 52669e0b57aSAlex Deucher #define HOST_SMC_MSG_MASK (0xff << 0) 52769e0b57aSAlex Deucher #define HOST_SMC_MSG_SHIFT 0 52869e0b57aSAlex Deucher #define HOST_SMC_RESP(x) ((x) << 8) 52969e0b57aSAlex Deucher #define HOST_SMC_RESP_MASK (0xff << 8) 53069e0b57aSAlex Deucher #define HOST_SMC_RESP_SHIFT 8 53169e0b57aSAlex Deucher #define SMC_HOST_MSG(x) ((x) << 16) 53269e0b57aSAlex Deucher #define SMC_HOST_MSG_MASK (0xff << 16) 53369e0b57aSAlex Deucher #define SMC_HOST_MSG_SHIFT 16 53469e0b57aSAlex Deucher #define SMC_HOST_RESP(x) ((x) << 24) 53569e0b57aSAlex Deucher #define SMC_HOST_RESP_MASK (0xff << 24) 53669e0b57aSAlex Deucher #define SMC_HOST_RESP_SHIFT 24 53769e0b57aSAlex Deucher 53869e0b57aSAlex Deucher #define CG_SPLL_FUNC_CNTL 0x600 53969e0b57aSAlex Deucher #define SPLL_RESET (1 << 0) 54069e0b57aSAlex Deucher #define SPLL_SLEEP (1 << 1) 54169e0b57aSAlex Deucher #define SPLL_BYPASS_EN (1 << 3) 54269e0b57aSAlex Deucher #define SPLL_REF_DIV(x) ((x) << 4) 54369e0b57aSAlex Deucher #define SPLL_REF_DIV_MASK (0x3f << 4) 54469e0b57aSAlex Deucher #define SPLL_PDIV_A(x) ((x) << 20) 54569e0b57aSAlex Deucher #define SPLL_PDIV_A_MASK (0x7f << 20) 54669e0b57aSAlex Deucher #define SPLL_PDIV_A_SHIFT 20 54769e0b57aSAlex Deucher #define CG_SPLL_FUNC_CNTL_2 0x604 54869e0b57aSAlex Deucher #define SCLK_MUX_SEL(x) ((x) << 0) 54969e0b57aSAlex Deucher #define SCLK_MUX_SEL_MASK (0x1ff << 0) 55069e0b57aSAlex Deucher #define CG_SPLL_FUNC_CNTL_3 0x608 55169e0b57aSAlex Deucher #define SPLL_FB_DIV(x) ((x) << 0) 55269e0b57aSAlex Deucher #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 55369e0b57aSAlex Deucher #define SPLL_FB_DIV_SHIFT 0 55469e0b57aSAlex Deucher #define SPLL_DITHEN (1 << 28) 55569e0b57aSAlex Deucher 55669e0b57aSAlex Deucher #define MPLL_CNTL_MODE 0x61c 55769e0b57aSAlex Deucher # define SS_SSEN (1 << 24) 55869e0b57aSAlex Deucher # define SS_DSMODE_EN (1 << 25) 55969e0b57aSAlex Deucher 56069e0b57aSAlex Deucher #define MPLL_AD_FUNC_CNTL 0x624 56169e0b57aSAlex Deucher #define CLKF(x) ((x) << 0) 56269e0b57aSAlex Deucher #define CLKF_MASK (0x7f << 0) 56369e0b57aSAlex Deucher #define CLKR(x) ((x) << 7) 56469e0b57aSAlex Deucher #define CLKR_MASK (0x1f << 7) 56569e0b57aSAlex Deucher #define CLKFRAC(x) ((x) << 12) 56669e0b57aSAlex Deucher #define CLKFRAC_MASK (0x1f << 12) 56769e0b57aSAlex Deucher #define YCLK_POST_DIV(x) ((x) << 17) 56869e0b57aSAlex Deucher #define YCLK_POST_DIV_MASK (3 << 17) 56969e0b57aSAlex Deucher #define IBIAS(x) ((x) << 20) 57069e0b57aSAlex Deucher #define IBIAS_MASK (0x3ff << 20) 57169e0b57aSAlex Deucher #define RESET (1 << 30) 57269e0b57aSAlex Deucher #define PDNB (1 << 31) 57369e0b57aSAlex Deucher #define MPLL_AD_FUNC_CNTL_2 0x628 57469e0b57aSAlex Deucher #define BYPASS (1 << 19) 57569e0b57aSAlex Deucher #define BIAS_GEN_PDNB (1 << 24) 57669e0b57aSAlex Deucher #define RESET_EN (1 << 25) 57769e0b57aSAlex Deucher #define VCO_MODE (1 << 29) 57869e0b57aSAlex Deucher #define MPLL_DQ_FUNC_CNTL 0x62c 57969e0b57aSAlex Deucher #define MPLL_DQ_FUNC_CNTL_2 0x630 58069e0b57aSAlex Deucher 58169e0b57aSAlex Deucher #define GENERAL_PWRMGT 0x63c 58269e0b57aSAlex Deucher # define GLOBAL_PWRMGT_EN (1 << 0) 58369e0b57aSAlex Deucher # define STATIC_PM_EN (1 << 1) 58469e0b57aSAlex Deucher # define THERMAL_PROTECTION_DIS (1 << 2) 58569e0b57aSAlex Deucher # define THERMAL_PROTECTION_TYPE (1 << 3) 58669e0b57aSAlex Deucher # define ENABLE_GEN2PCIE (1 << 4) 58769e0b57aSAlex Deucher # define ENABLE_GEN2XSP (1 << 5) 58869e0b57aSAlex Deucher # define SW_SMIO_INDEX(x) ((x) << 6) 58969e0b57aSAlex Deucher # define SW_SMIO_INDEX_MASK (3 << 6) 59069e0b57aSAlex Deucher # define SW_SMIO_INDEX_SHIFT 6 59169e0b57aSAlex Deucher # define LOW_VOLT_D2_ACPI (1 << 8) 59269e0b57aSAlex Deucher # define LOW_VOLT_D3_ACPI (1 << 9) 59369e0b57aSAlex Deucher # define VOLT_PWRMGT_EN (1 << 10) 59469e0b57aSAlex Deucher # define BACKBIAS_PAD_EN (1 << 18) 59569e0b57aSAlex Deucher # define BACKBIAS_VALUE (1 << 19) 59669e0b57aSAlex Deucher # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 59769e0b57aSAlex Deucher # define AC_DC_SW (1 << 24) 59869e0b57aSAlex Deucher 59969e0b57aSAlex Deucher #define SCLK_PWRMGT_CNTL 0x644 60069e0b57aSAlex Deucher # define SCLK_PWRMGT_OFF (1 << 0) 60169e0b57aSAlex Deucher # define SCLK_LOW_D1 (1 << 1) 60269e0b57aSAlex Deucher # define FIR_RESET (1 << 4) 60369e0b57aSAlex Deucher # define FIR_FORCE_TREND_SEL (1 << 5) 60469e0b57aSAlex Deucher # define FIR_TREND_MODE (1 << 6) 60569e0b57aSAlex Deucher # define DYN_GFX_CLK_OFF_EN (1 << 7) 60669e0b57aSAlex Deucher # define GFX_CLK_FORCE_ON (1 << 8) 60769e0b57aSAlex Deucher # define GFX_CLK_REQUEST_OFF (1 << 9) 60869e0b57aSAlex Deucher # define GFX_CLK_FORCE_OFF (1 << 10) 60969e0b57aSAlex Deucher # define GFX_CLK_OFF_ACPI_D1 (1 << 11) 61069e0b57aSAlex Deucher # define GFX_CLK_OFF_ACPI_D2 (1 << 12) 61169e0b57aSAlex Deucher # define GFX_CLK_OFF_ACPI_D3 (1 << 13) 61269e0b57aSAlex Deucher # define DYN_LIGHT_SLEEP_EN (1 << 14) 61369e0b57aSAlex Deucher #define MCLK_PWRMGT_CNTL 0x648 61469e0b57aSAlex Deucher # define DLL_SPEED(x) ((x) << 0) 61569e0b57aSAlex Deucher # define DLL_SPEED_MASK (0x1f << 0) 61669e0b57aSAlex Deucher # define MPLL_PWRMGT_OFF (1 << 5) 61769e0b57aSAlex Deucher # define DLL_READY (1 << 6) 61869e0b57aSAlex Deucher # define MC_INT_CNTL (1 << 7) 61969e0b57aSAlex Deucher # define MRDCKA0_PDNB (1 << 8) 62069e0b57aSAlex Deucher # define MRDCKA1_PDNB (1 << 9) 62169e0b57aSAlex Deucher # define MRDCKB0_PDNB (1 << 10) 62269e0b57aSAlex Deucher # define MRDCKB1_PDNB (1 << 11) 62369e0b57aSAlex Deucher # define MRDCKC0_PDNB (1 << 12) 62469e0b57aSAlex Deucher # define MRDCKC1_PDNB (1 << 13) 62569e0b57aSAlex Deucher # define MRDCKD0_PDNB (1 << 14) 62669e0b57aSAlex Deucher # define MRDCKD1_PDNB (1 << 15) 62769e0b57aSAlex Deucher # define MRDCKA0_RESET (1 << 16) 62869e0b57aSAlex Deucher # define MRDCKA1_RESET (1 << 17) 62969e0b57aSAlex Deucher # define MRDCKB0_RESET (1 << 18) 63069e0b57aSAlex Deucher # define MRDCKB1_RESET (1 << 19) 63169e0b57aSAlex Deucher # define MRDCKC0_RESET (1 << 20) 63269e0b57aSAlex Deucher # define MRDCKC1_RESET (1 << 21) 63369e0b57aSAlex Deucher # define MRDCKD0_RESET (1 << 22) 63469e0b57aSAlex Deucher # define MRDCKD1_RESET (1 << 23) 63569e0b57aSAlex Deucher # define DLL_READY_READ (1 << 24) 63669e0b57aSAlex Deucher # define USE_DISPLAY_GAP (1 << 25) 63769e0b57aSAlex Deucher # define USE_DISPLAY_URGENT_NORMAL (1 << 26) 63869e0b57aSAlex Deucher # define MPLL_TURNOFF_D2 (1 << 28) 63969e0b57aSAlex Deucher #define DLL_CNTL 0x64c 64069e0b57aSAlex Deucher # define MRDCKA0_BYPASS (1 << 24) 64169e0b57aSAlex Deucher # define MRDCKA1_BYPASS (1 << 25) 64269e0b57aSAlex Deucher # define MRDCKB0_BYPASS (1 << 26) 64369e0b57aSAlex Deucher # define MRDCKB1_BYPASS (1 << 27) 64469e0b57aSAlex Deucher # define MRDCKC0_BYPASS (1 << 28) 64569e0b57aSAlex Deucher # define MRDCKC1_BYPASS (1 << 29) 64669e0b57aSAlex Deucher # define MRDCKD0_BYPASS (1 << 30) 64769e0b57aSAlex Deucher # define MRDCKD1_BYPASS (1 << 31) 64869e0b57aSAlex Deucher 649bdf0c4f0SAlex Deucher #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c 650bdf0c4f0SAlex Deucher # define CURRENT_STATE_INDEX_MASK (0xf << 4) 651bdf0c4f0SAlex Deucher # define CURRENT_STATE_INDEX_SHIFT 4 652bdf0c4f0SAlex Deucher 65369e0b57aSAlex Deucher #define CG_AT 0x6d4 65469e0b57aSAlex Deucher # define CG_R(x) ((x) << 0) 65569e0b57aSAlex Deucher # define CG_R_MASK (0xffff << 0) 65669e0b57aSAlex Deucher # define CG_L(x) ((x) << 16) 65769e0b57aSAlex Deucher # define CG_L_MASK (0xffff << 16) 65869e0b57aSAlex Deucher 65969e0b57aSAlex Deucher #define CG_BIF_REQ_AND_RSP 0x7f4 66069e0b57aSAlex Deucher #define CG_CLIENT_REQ(x) ((x) << 0) 66169e0b57aSAlex Deucher #define CG_CLIENT_REQ_MASK (0xff << 0) 66269e0b57aSAlex Deucher #define CG_CLIENT_REQ_SHIFT 0 66369e0b57aSAlex Deucher #define CG_CLIENT_RESP(x) ((x) << 8) 66469e0b57aSAlex Deucher #define CG_CLIENT_RESP_MASK (0xff << 8) 66569e0b57aSAlex Deucher #define CG_CLIENT_RESP_SHIFT 8 66669e0b57aSAlex Deucher #define CLIENT_CG_REQ(x) ((x) << 16) 66769e0b57aSAlex Deucher #define CLIENT_CG_REQ_MASK (0xff << 16) 66869e0b57aSAlex Deucher #define CLIENT_CG_REQ_SHIFT 16 66969e0b57aSAlex Deucher #define CLIENT_CG_RESP(x) ((x) << 24) 67069e0b57aSAlex Deucher #define CLIENT_CG_RESP_MASK (0xff << 24) 67169e0b57aSAlex Deucher #define CLIENT_CG_RESP_SHIFT 24 67269e0b57aSAlex Deucher 67369e0b57aSAlex Deucher #define CG_SPLL_SPREAD_SPECTRUM 0x790 67469e0b57aSAlex Deucher #define SSEN (1 << 0) 67569e0b57aSAlex Deucher #define CLK_S(x) ((x) << 4) 67669e0b57aSAlex Deucher #define CLK_S_MASK (0xfff << 4) 67769e0b57aSAlex Deucher #define CLK_S_SHIFT 4 67869e0b57aSAlex Deucher #define CG_SPLL_SPREAD_SPECTRUM_2 0x794 67969e0b57aSAlex Deucher #define CLK_V(x) ((x) << 0) 68069e0b57aSAlex Deucher #define CLK_V_MASK (0x3ffffff << 0) 68169e0b57aSAlex Deucher #define CLK_V_SHIFT 0 68269e0b57aSAlex Deucher 68369e0b57aSAlex Deucher #define SMC_SCRATCH0 0x81c 68469e0b57aSAlex Deucher 68569e0b57aSAlex Deucher #define CG_SPLL_FUNC_CNTL_4 0x850 68669e0b57aSAlex Deucher 68769e0b57aSAlex Deucher #define MPLL_SS1 0x85c 68869e0b57aSAlex Deucher #define CLKV(x) ((x) << 0) 68969e0b57aSAlex Deucher #define CLKV_MASK (0x3ffffff << 0) 69069e0b57aSAlex Deucher #define MPLL_SS2 0x860 69169e0b57aSAlex Deucher #define CLKS(x) ((x) << 0) 69269e0b57aSAlex Deucher #define CLKS_MASK (0xfff << 0) 69369e0b57aSAlex Deucher 69469e0b57aSAlex Deucher #define CG_CAC_CTRL 0x88c 69569e0b57aSAlex Deucher #define TID_CNT(x) ((x) << 0) 69669e0b57aSAlex Deucher #define TID_CNT_MASK (0x3fff << 0) 69769e0b57aSAlex Deucher #define TID_UNIT(x) ((x) << 14) 69869e0b57aSAlex Deucher #define TID_UNIT_MASK (0xf << 14) 69969e0b57aSAlex Deucher 7008ba10463SAlex Deucher #define CG_IND_ADDR 0x8f8 7018ba10463SAlex Deucher #define CG_IND_DATA 0x8fc 7028ba10463SAlex Deucher /* CGIND regs */ 7038ba10463SAlex Deucher #define CG_CGTT_LOCAL_0 0x00 7048ba10463SAlex Deucher #define CG_CGTT_LOCAL_1 0x01 7058ba10463SAlex Deucher 70669e0b57aSAlex Deucher #define MC_CG_CONFIG 0x25bc 70769e0b57aSAlex Deucher #define MCDW_WR_ENABLE (1 << 0) 70869e0b57aSAlex Deucher #define MCDX_WR_ENABLE (1 << 1) 70969e0b57aSAlex Deucher #define MCDY_WR_ENABLE (1 << 2) 71069e0b57aSAlex Deucher #define MCDZ_WR_ENABLE (1 << 3) 71169e0b57aSAlex Deucher #define MC_RD_ENABLE(x) ((x) << 4) 71269e0b57aSAlex Deucher #define MC_RD_ENABLE_MASK (3 << 4) 71369e0b57aSAlex Deucher #define INDEX(x) ((x) << 6) 71469e0b57aSAlex Deucher #define INDEX_MASK (0xfff << 6) 71569e0b57aSAlex Deucher #define INDEX_SHIFT 6 71669e0b57aSAlex Deucher 71769e0b57aSAlex Deucher #define MC_ARB_CAC_CNTL 0x2750 71869e0b57aSAlex Deucher #define ENABLE (1 << 0) 71969e0b57aSAlex Deucher #define READ_WEIGHT(x) ((x) << 1) 72069e0b57aSAlex Deucher #define READ_WEIGHT_MASK (0x3f << 1) 72169e0b57aSAlex Deucher #define READ_WEIGHT_SHIFT 1 72269e0b57aSAlex Deucher #define WRITE_WEIGHT(x) ((x) << 7) 72369e0b57aSAlex Deucher #define WRITE_WEIGHT_MASK (0x3f << 7) 72469e0b57aSAlex Deucher #define WRITE_WEIGHT_SHIFT 7 72569e0b57aSAlex Deucher #define ALLOW_OVERFLOW (1 << 13) 72669e0b57aSAlex Deucher 72769e0b57aSAlex Deucher #define MC_ARB_DRAM_TIMING 0x2774 72869e0b57aSAlex Deucher #define MC_ARB_DRAM_TIMING2 0x2778 72969e0b57aSAlex Deucher 73069e0b57aSAlex Deucher #define MC_ARB_RFSH_RATE 0x27b0 73169e0b57aSAlex Deucher #define POWERMODE0(x) ((x) << 0) 73269e0b57aSAlex Deucher #define POWERMODE0_MASK (0xff << 0) 73369e0b57aSAlex Deucher #define POWERMODE0_SHIFT 0 73469e0b57aSAlex Deucher #define POWERMODE1(x) ((x) << 8) 73569e0b57aSAlex Deucher #define POWERMODE1_MASK (0xff << 8) 73669e0b57aSAlex Deucher #define POWERMODE1_SHIFT 8 73769e0b57aSAlex Deucher #define POWERMODE2(x) ((x) << 16) 73869e0b57aSAlex Deucher #define POWERMODE2_MASK (0xff << 16) 73969e0b57aSAlex Deucher #define POWERMODE2_SHIFT 16 74069e0b57aSAlex Deucher #define POWERMODE3(x) ((x) << 24) 74169e0b57aSAlex Deucher #define POWERMODE3_MASK (0xff << 24) 74269e0b57aSAlex Deucher #define POWERMODE3_SHIFT 24 74369e0b57aSAlex Deucher 74469e0b57aSAlex Deucher #define MC_ARB_CG 0x27e8 74569e0b57aSAlex Deucher #define CG_ARB_REQ(x) ((x) << 0) 74669e0b57aSAlex Deucher #define CG_ARB_REQ_MASK (0xff << 0) 74769e0b57aSAlex Deucher #define CG_ARB_REQ_SHIFT 0 74869e0b57aSAlex Deucher #define CG_ARB_RESP(x) ((x) << 8) 74969e0b57aSAlex Deucher #define CG_ARB_RESP_MASK (0xff << 8) 75069e0b57aSAlex Deucher #define CG_ARB_RESP_SHIFT 8 75169e0b57aSAlex Deucher #define ARB_CG_REQ(x) ((x) << 16) 75269e0b57aSAlex Deucher #define ARB_CG_REQ_MASK (0xff << 16) 75369e0b57aSAlex Deucher #define ARB_CG_REQ_SHIFT 16 75469e0b57aSAlex Deucher #define ARB_CG_RESP(x) ((x) << 24) 75569e0b57aSAlex Deucher #define ARB_CG_RESP_MASK (0xff << 24) 75669e0b57aSAlex Deucher #define ARB_CG_RESP_SHIFT 24 75769e0b57aSAlex Deucher 75869e0b57aSAlex Deucher #define MC_ARB_DRAM_TIMING_1 0x27f0 75969e0b57aSAlex Deucher #define MC_ARB_DRAM_TIMING_2 0x27f4 76069e0b57aSAlex Deucher #define MC_ARB_DRAM_TIMING_3 0x27f8 76169e0b57aSAlex Deucher #define MC_ARB_DRAM_TIMING2_1 0x27fc 76269e0b57aSAlex Deucher #define MC_ARB_DRAM_TIMING2_2 0x2800 76369e0b57aSAlex Deucher #define MC_ARB_DRAM_TIMING2_3 0x2804 76469e0b57aSAlex Deucher #define MC_ARB_BURST_TIME 0x2808 76569e0b57aSAlex Deucher #define STATE0(x) ((x) << 0) 76669e0b57aSAlex Deucher #define STATE0_MASK (0x1f << 0) 76769e0b57aSAlex Deucher #define STATE0_SHIFT 0 76869e0b57aSAlex Deucher #define STATE1(x) ((x) << 5) 76969e0b57aSAlex Deucher #define STATE1_MASK (0x1f << 5) 77069e0b57aSAlex Deucher #define STATE1_SHIFT 5 77169e0b57aSAlex Deucher #define STATE2(x) ((x) << 10) 77269e0b57aSAlex Deucher #define STATE2_MASK (0x1f << 10) 77369e0b57aSAlex Deucher #define STATE2_SHIFT 10 77469e0b57aSAlex Deucher #define STATE3(x) ((x) << 15) 77569e0b57aSAlex Deucher #define STATE3_MASK (0x1f << 15) 77669e0b57aSAlex Deucher #define STATE3_SHIFT 15 77769e0b57aSAlex Deucher 77869e0b57aSAlex Deucher #define MC_CG_DATAPORT 0x2884 77969e0b57aSAlex Deucher 78069e0b57aSAlex Deucher #define MC_SEQ_RAS_TIMING 0x28a0 78169e0b57aSAlex Deucher #define MC_SEQ_CAS_TIMING 0x28a4 78269e0b57aSAlex Deucher #define MC_SEQ_MISC_TIMING 0x28a8 78369e0b57aSAlex Deucher #define MC_SEQ_MISC_TIMING2 0x28ac 78469e0b57aSAlex Deucher #define MC_SEQ_PMG_TIMING 0x28b0 78569e0b57aSAlex Deucher #define MC_SEQ_RD_CTL_D0 0x28b4 78669e0b57aSAlex Deucher #define MC_SEQ_RD_CTL_D1 0x28b8 78769e0b57aSAlex Deucher #define MC_SEQ_WR_CTL_D0 0x28bc 78869e0b57aSAlex Deucher #define MC_SEQ_WR_CTL_D1 0x28c0 78969e0b57aSAlex Deucher 79069e0b57aSAlex Deucher #define MC_SEQ_MISC0 0x2a00 79169e0b57aSAlex Deucher #define MC_SEQ_MISC0_GDDR5_SHIFT 28 79269e0b57aSAlex Deucher #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 79369e0b57aSAlex Deucher #define MC_SEQ_MISC0_GDDR5_VALUE 5 79469e0b57aSAlex Deucher #define MC_SEQ_MISC1 0x2a04 79569e0b57aSAlex Deucher #define MC_SEQ_RESERVE_M 0x2a08 79669e0b57aSAlex Deucher #define MC_PMG_CMD_EMRS 0x2a0c 79769e0b57aSAlex Deucher 79869e0b57aSAlex Deucher #define MC_SEQ_MISC3 0x2a2c 79969e0b57aSAlex Deucher 80069e0b57aSAlex Deucher #define MC_SEQ_MISC5 0x2a54 80169e0b57aSAlex Deucher #define MC_SEQ_MISC6 0x2a58 80269e0b57aSAlex Deucher 80369e0b57aSAlex Deucher #define MC_SEQ_MISC7 0x2a64 80469e0b57aSAlex Deucher 80569e0b57aSAlex Deucher #define MC_SEQ_RAS_TIMING_LP 0x2a6c 80669e0b57aSAlex Deucher #define MC_SEQ_CAS_TIMING_LP 0x2a70 80769e0b57aSAlex Deucher #define MC_SEQ_MISC_TIMING_LP 0x2a74 80869e0b57aSAlex Deucher #define MC_SEQ_MISC_TIMING2_LP 0x2a78 80969e0b57aSAlex Deucher #define MC_SEQ_WR_CTL_D0_LP 0x2a7c 81069e0b57aSAlex Deucher #define MC_SEQ_WR_CTL_D1_LP 0x2a80 81169e0b57aSAlex Deucher #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 81269e0b57aSAlex Deucher #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 81369e0b57aSAlex Deucher 81469e0b57aSAlex Deucher #define MC_PMG_CMD_MRS 0x2aac 81569e0b57aSAlex Deucher 81669e0b57aSAlex Deucher #define MC_SEQ_RD_CTL_D0_LP 0x2b1c 81769e0b57aSAlex Deucher #define MC_SEQ_RD_CTL_D1_LP 0x2b20 81869e0b57aSAlex Deucher 81969e0b57aSAlex Deucher #define MC_PMG_CMD_MRS1 0x2b44 82069e0b57aSAlex Deucher #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 82169e0b57aSAlex Deucher #define MC_SEQ_PMG_TIMING_LP 0x2b4c 82269e0b57aSAlex Deucher 82369e0b57aSAlex Deucher #define MC_PMG_CMD_MRS2 0x2b5c 82469e0b57aSAlex Deucher #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60 82569e0b57aSAlex Deucher 826875711f0SDave Airlie #define AUX_CONTROL 0x6200 827875711f0SDave Airlie #define AUX_EN (1 << 0) 828875711f0SDave Airlie #define AUX_LS_READ_EN (1 << 8) 829875711f0SDave Airlie #define AUX_LS_UPDATE_DISABLE(x) (((x) & 0x1) << 12) 830875711f0SDave Airlie #define AUX_HPD_DISCON(x) (((x) & 0x1) << 16) 831875711f0SDave Airlie #define AUX_DET_EN (1 << 18) 832875711f0SDave Airlie #define AUX_HPD_SEL(x) (((x) & 0x7) << 20) 833875711f0SDave Airlie #define AUX_IMPCAL_REQ_EN (1 << 24) 834875711f0SDave Airlie #define AUX_TEST_MODE (1 << 28) 835875711f0SDave Airlie #define AUX_DEGLITCH_EN (1 << 29) 836875711f0SDave Airlie #define AUX_SW_CONTROL 0x6204 837875711f0SDave Airlie #define AUX_SW_GO (1 << 0) 838875711f0SDave Airlie #define AUX_LS_READ_TRIG (1 << 2) 839875711f0SDave Airlie #define AUX_SW_START_DELAY(x) (((x) & 0xf) << 4) 840875711f0SDave Airlie #define AUX_SW_WR_BYTES(x) (((x) & 0x1f) << 16) 841875711f0SDave Airlie 842875711f0SDave Airlie #define AUX_SW_INTERRUPT_CONTROL 0x620c 843875711f0SDave Airlie #define AUX_SW_DONE_INT (1 << 0) 844875711f0SDave Airlie #define AUX_SW_DONE_ACK (1 << 1) 845875711f0SDave Airlie #define AUX_SW_DONE_MASK (1 << 2) 846875711f0SDave Airlie #define AUX_SW_LS_DONE_INT (1 << 4) 847875711f0SDave Airlie #define AUX_SW_LS_DONE_MASK (1 << 6) 848875711f0SDave Airlie #define AUX_SW_STATUS 0x6210 849875711f0SDave Airlie #define AUX_SW_DONE (1 << 0) 850875711f0SDave Airlie #define AUX_SW_REQ (1 << 1) 851875711f0SDave Airlie #define AUX_SW_RX_TIMEOUT_STATE(x) (((x) & 0x7) << 4) 852875711f0SDave Airlie #define AUX_SW_RX_TIMEOUT (1 << 7) 853875711f0SDave Airlie #define AUX_SW_RX_OVERFLOW (1 << 8) 854875711f0SDave Airlie #define AUX_SW_RX_HPD_DISCON (1 << 9) 855875711f0SDave Airlie #define AUX_SW_RX_PARTIAL_BYTE (1 << 10) 856875711f0SDave Airlie #define AUX_SW_NON_AUX_MODE (1 << 11) 857875711f0SDave Airlie #define AUX_SW_RX_MIN_COUNT_VIOL (1 << 12) 858875711f0SDave Airlie #define AUX_SW_RX_INVALID_STOP (1 << 14) 859875711f0SDave Airlie #define AUX_SW_RX_SYNC_INVALID_L (1 << 17) 860875711f0SDave Airlie #define AUX_SW_RX_SYNC_INVALID_H (1 << 18) 861875711f0SDave Airlie #define AUX_SW_RX_INVALID_START (1 << 19) 862875711f0SDave Airlie #define AUX_SW_RX_RECV_NO_DET (1 << 20) 863875711f0SDave Airlie #define AUX_SW_RX_RECV_INVALID_H (1 << 22) 864875711f0SDave Airlie #define AUX_SW_RX_RECV_INVALID_V (1 << 23) 865875711f0SDave Airlie 866875711f0SDave Airlie #define AUX_SW_DATA 0x6218 867875711f0SDave Airlie #define AUX_SW_DATA_RW (1 << 0) 868875711f0SDave Airlie #define AUX_SW_DATA_MASK(x) (((x) & 0xff) << 8) 869875711f0SDave Airlie #define AUX_SW_DATA_INDEX(x) (((x) & 0x1f) << 16) 870875711f0SDave Airlie #define AUX_SW_AUTOINCREMENT_DISABLE (1 << 31) 871875711f0SDave Airlie 87269e0b57aSAlex Deucher #define LB_SYNC_RESET_SEL 0x6b28 87369e0b57aSAlex Deucher #define LB_SYNC_RESET_SEL_MASK (3 << 0) 87469e0b57aSAlex Deucher #define LB_SYNC_RESET_SEL_SHIFT 0 87569e0b57aSAlex Deucher 87669e0b57aSAlex Deucher #define DC_STUTTER_CNTL 0x6b30 87769e0b57aSAlex Deucher #define DC_STUTTER_ENABLE_A (1 << 0) 87869e0b57aSAlex Deucher #define DC_STUTTER_ENABLE_B (1 << 1) 87969e0b57aSAlex Deucher 88069e0b57aSAlex Deucher #define SQ_CAC_THRESHOLD 0x8e4c 88169e0b57aSAlex Deucher #define VSP(x) ((x) << 0) 88269e0b57aSAlex Deucher #define VSP_MASK (0xff << 0) 88369e0b57aSAlex Deucher #define VSP_SHIFT 0 88469e0b57aSAlex Deucher #define VSP0(x) ((x) << 8) 88569e0b57aSAlex Deucher #define VSP0_MASK (0xff << 8) 88669e0b57aSAlex Deucher #define VSP0_SHIFT 8 88769e0b57aSAlex Deucher #define GPR(x) ((x) << 16) 88869e0b57aSAlex Deucher #define GPR_MASK (0xff << 16) 88969e0b57aSAlex Deucher #define GPR_SHIFT 16 89069e0b57aSAlex Deucher 89169e0b57aSAlex Deucher #define SQ_POWER_THROTTLE 0x8e58 89269e0b57aSAlex Deucher #define MIN_POWER(x) ((x) << 0) 89369e0b57aSAlex Deucher #define MIN_POWER_MASK (0x3fff << 0) 89469e0b57aSAlex Deucher #define MIN_POWER_SHIFT 0 89569e0b57aSAlex Deucher #define MAX_POWER(x) ((x) << 16) 89669e0b57aSAlex Deucher #define MAX_POWER_MASK (0x3fff << 16) 89769e0b57aSAlex Deucher #define MAX_POWER_SHIFT 0 89869e0b57aSAlex Deucher #define SQ_POWER_THROTTLE2 0x8e5c 89969e0b57aSAlex Deucher #define MAX_POWER_DELTA(x) ((x) << 0) 90069e0b57aSAlex Deucher #define MAX_POWER_DELTA_MASK (0x3fff << 0) 90169e0b57aSAlex Deucher #define MAX_POWER_DELTA_SHIFT 0 90269e0b57aSAlex Deucher #define STI_SIZE(x) ((x) << 16) 90369e0b57aSAlex Deucher #define STI_SIZE_MASK (0x3ff << 16) 90469e0b57aSAlex Deucher #define STI_SIZE_SHIFT 16 90569e0b57aSAlex Deucher #define LTI_RATIO(x) ((x) << 27) 90669e0b57aSAlex Deucher #define LTI_RATIO_MASK (0xf << 27) 90769e0b57aSAlex Deucher #define LTI_RATIO_SHIFT 27 90869e0b57aSAlex Deucher 90969e0b57aSAlex Deucher /* CG indirect registers */ 91069e0b57aSAlex Deucher #define CG_CAC_REGION_1_WEIGHT_0 0x83 91169e0b57aSAlex Deucher #define WEIGHT_TCP_SIG0(x) ((x) << 0) 91269e0b57aSAlex Deucher #define WEIGHT_TCP_SIG0_MASK (0x3f << 0) 91369e0b57aSAlex Deucher #define WEIGHT_TCP_SIG0_SHIFT 0 91469e0b57aSAlex Deucher #define WEIGHT_TCP_SIG1(x) ((x) << 6) 91569e0b57aSAlex Deucher #define WEIGHT_TCP_SIG1_MASK (0x3f << 6) 91669e0b57aSAlex Deucher #define WEIGHT_TCP_SIG1_SHIFT 6 91769e0b57aSAlex Deucher #define WEIGHT_TA_SIG(x) ((x) << 12) 91869e0b57aSAlex Deucher #define WEIGHT_TA_SIG_MASK (0x3f << 12) 91969e0b57aSAlex Deucher #define WEIGHT_TA_SIG_SHIFT 12 92069e0b57aSAlex Deucher #define CG_CAC_REGION_1_WEIGHT_1 0x84 92169e0b57aSAlex Deucher #define WEIGHT_TCC_EN0(x) ((x) << 0) 92269e0b57aSAlex Deucher #define WEIGHT_TCC_EN0_MASK (0x3f << 0) 92369e0b57aSAlex Deucher #define WEIGHT_TCC_EN0_SHIFT 0 92469e0b57aSAlex Deucher #define WEIGHT_TCC_EN1(x) ((x) << 6) 92569e0b57aSAlex Deucher #define WEIGHT_TCC_EN1_MASK (0x3f << 6) 92669e0b57aSAlex Deucher #define WEIGHT_TCC_EN1_SHIFT 6 92769e0b57aSAlex Deucher #define WEIGHT_TCC_EN2(x) ((x) << 12) 92869e0b57aSAlex Deucher #define WEIGHT_TCC_EN2_MASK (0x3f << 12) 92969e0b57aSAlex Deucher #define WEIGHT_TCC_EN2_SHIFT 12 93069e0b57aSAlex Deucher #define WEIGHT_TCC_EN3(x) ((x) << 18) 93169e0b57aSAlex Deucher #define WEIGHT_TCC_EN3_MASK (0x3f << 18) 93269e0b57aSAlex Deucher #define WEIGHT_TCC_EN3_SHIFT 18 93369e0b57aSAlex Deucher #define CG_CAC_REGION_2_WEIGHT_0 0x85 93469e0b57aSAlex Deucher #define WEIGHT_CB_EN0(x) ((x) << 0) 93569e0b57aSAlex Deucher #define WEIGHT_CB_EN0_MASK (0x3f << 0) 93669e0b57aSAlex Deucher #define WEIGHT_CB_EN0_SHIFT 0 93769e0b57aSAlex Deucher #define WEIGHT_CB_EN1(x) ((x) << 6) 93869e0b57aSAlex Deucher #define WEIGHT_CB_EN1_MASK (0x3f << 6) 93969e0b57aSAlex Deucher #define WEIGHT_CB_EN1_SHIFT 6 94069e0b57aSAlex Deucher #define WEIGHT_CB_EN2(x) ((x) << 12) 94169e0b57aSAlex Deucher #define WEIGHT_CB_EN2_MASK (0x3f << 12) 94269e0b57aSAlex Deucher #define WEIGHT_CB_EN2_SHIFT 12 94369e0b57aSAlex Deucher #define WEIGHT_CB_EN3(x) ((x) << 18) 94469e0b57aSAlex Deucher #define WEIGHT_CB_EN3_MASK (0x3f << 18) 94569e0b57aSAlex Deucher #define WEIGHT_CB_EN3_SHIFT 18 94669e0b57aSAlex Deucher #define CG_CAC_REGION_2_WEIGHT_1 0x86 94769e0b57aSAlex Deucher #define WEIGHT_DB_SIG0(x) ((x) << 0) 94869e0b57aSAlex Deucher #define WEIGHT_DB_SIG0_MASK (0x3f << 0) 94969e0b57aSAlex Deucher #define WEIGHT_DB_SIG0_SHIFT 0 95069e0b57aSAlex Deucher #define WEIGHT_DB_SIG1(x) ((x) << 6) 95169e0b57aSAlex Deucher #define WEIGHT_DB_SIG1_MASK (0x3f << 6) 95269e0b57aSAlex Deucher #define WEIGHT_DB_SIG1_SHIFT 6 95369e0b57aSAlex Deucher #define WEIGHT_DB_SIG2(x) ((x) << 12) 95469e0b57aSAlex Deucher #define WEIGHT_DB_SIG2_MASK (0x3f << 12) 95569e0b57aSAlex Deucher #define WEIGHT_DB_SIG2_SHIFT 12 95669e0b57aSAlex Deucher #define WEIGHT_DB_SIG3(x) ((x) << 18) 95769e0b57aSAlex Deucher #define WEIGHT_DB_SIG3_MASK (0x3f << 18) 95869e0b57aSAlex Deucher #define WEIGHT_DB_SIG3_SHIFT 18 95969e0b57aSAlex Deucher #define CG_CAC_REGION_2_WEIGHT_2 0x87 96069e0b57aSAlex Deucher #define WEIGHT_SXM_SIG0(x) ((x) << 0) 96169e0b57aSAlex Deucher #define WEIGHT_SXM_SIG0_MASK (0x3f << 0) 96269e0b57aSAlex Deucher #define WEIGHT_SXM_SIG0_SHIFT 0 96369e0b57aSAlex Deucher #define WEIGHT_SXM_SIG1(x) ((x) << 6) 96469e0b57aSAlex Deucher #define WEIGHT_SXM_SIG1_MASK (0x3f << 6) 96569e0b57aSAlex Deucher #define WEIGHT_SXM_SIG1_SHIFT 6 96669e0b57aSAlex Deucher #define WEIGHT_SXM_SIG2(x) ((x) << 12) 96769e0b57aSAlex Deucher #define WEIGHT_SXM_SIG2_MASK (0x3f << 12) 96869e0b57aSAlex Deucher #define WEIGHT_SXM_SIG2_SHIFT 12 96969e0b57aSAlex Deucher #define WEIGHT_SXS_SIG0(x) ((x) << 18) 97069e0b57aSAlex Deucher #define WEIGHT_SXS_SIG0_MASK (0x3f << 18) 97169e0b57aSAlex Deucher #define WEIGHT_SXS_SIG0_SHIFT 18 97269e0b57aSAlex Deucher #define WEIGHT_SXS_SIG1(x) ((x) << 24) 97369e0b57aSAlex Deucher #define WEIGHT_SXS_SIG1_MASK (0x3f << 24) 97469e0b57aSAlex Deucher #define WEIGHT_SXS_SIG1_SHIFT 24 97569e0b57aSAlex Deucher #define CG_CAC_REGION_3_WEIGHT_0 0x88 97669e0b57aSAlex Deucher #define WEIGHT_XBR_0(x) ((x) << 0) 97769e0b57aSAlex Deucher #define WEIGHT_XBR_0_MASK (0x3f << 0) 97869e0b57aSAlex Deucher #define WEIGHT_XBR_0_SHIFT 0 97969e0b57aSAlex Deucher #define WEIGHT_XBR_1(x) ((x) << 6) 98069e0b57aSAlex Deucher #define WEIGHT_XBR_1_MASK (0x3f << 6) 98169e0b57aSAlex Deucher #define WEIGHT_XBR_1_SHIFT 6 98269e0b57aSAlex Deucher #define WEIGHT_XBR_2(x) ((x) << 12) 98369e0b57aSAlex Deucher #define WEIGHT_XBR_2_MASK (0x3f << 12) 98469e0b57aSAlex Deucher #define WEIGHT_XBR_2_SHIFT 12 98569e0b57aSAlex Deucher #define WEIGHT_SPI_SIG0(x) ((x) << 18) 98669e0b57aSAlex Deucher #define WEIGHT_SPI_SIG0_MASK (0x3f << 18) 98769e0b57aSAlex Deucher #define WEIGHT_SPI_SIG0_SHIFT 18 98869e0b57aSAlex Deucher #define CG_CAC_REGION_3_WEIGHT_1 0x89 98969e0b57aSAlex Deucher #define WEIGHT_SPI_SIG1(x) ((x) << 0) 99069e0b57aSAlex Deucher #define WEIGHT_SPI_SIG1_MASK (0x3f << 0) 99169e0b57aSAlex Deucher #define WEIGHT_SPI_SIG1_SHIFT 0 99269e0b57aSAlex Deucher #define WEIGHT_SPI_SIG2(x) ((x) << 6) 99369e0b57aSAlex Deucher #define WEIGHT_SPI_SIG2_MASK (0x3f << 6) 99469e0b57aSAlex Deucher #define WEIGHT_SPI_SIG2_SHIFT 6 99569e0b57aSAlex Deucher #define WEIGHT_SPI_SIG3(x) ((x) << 12) 99669e0b57aSAlex Deucher #define WEIGHT_SPI_SIG3_MASK (0x3f << 12) 99769e0b57aSAlex Deucher #define WEIGHT_SPI_SIG3_SHIFT 12 99869e0b57aSAlex Deucher #define WEIGHT_SPI_SIG4(x) ((x) << 18) 99969e0b57aSAlex Deucher #define WEIGHT_SPI_SIG4_MASK (0x3f << 18) 100069e0b57aSAlex Deucher #define WEIGHT_SPI_SIG4_SHIFT 18 100169e0b57aSAlex Deucher #define WEIGHT_SPI_SIG5(x) ((x) << 24) 100269e0b57aSAlex Deucher #define WEIGHT_SPI_SIG5_MASK (0x3f << 24) 100369e0b57aSAlex Deucher #define WEIGHT_SPI_SIG5_SHIFT 24 100469e0b57aSAlex Deucher #define CG_CAC_REGION_4_WEIGHT_0 0x8a 100569e0b57aSAlex Deucher #define WEIGHT_LDS_SIG0(x) ((x) << 0) 100669e0b57aSAlex Deucher #define WEIGHT_LDS_SIG0_MASK (0x3f << 0) 100769e0b57aSAlex Deucher #define WEIGHT_LDS_SIG0_SHIFT 0 100869e0b57aSAlex Deucher #define WEIGHT_LDS_SIG1(x) ((x) << 6) 100969e0b57aSAlex Deucher #define WEIGHT_LDS_SIG1_MASK (0x3f << 6) 101069e0b57aSAlex Deucher #define WEIGHT_LDS_SIG1_SHIFT 6 101169e0b57aSAlex Deucher #define WEIGHT_SC(x) ((x) << 24) 101269e0b57aSAlex Deucher #define WEIGHT_SC_MASK (0x3f << 24) 101369e0b57aSAlex Deucher #define WEIGHT_SC_SHIFT 24 101469e0b57aSAlex Deucher #define CG_CAC_REGION_4_WEIGHT_1 0x8b 101569e0b57aSAlex Deucher #define WEIGHT_BIF(x) ((x) << 0) 101669e0b57aSAlex Deucher #define WEIGHT_BIF_MASK (0x3f << 0) 101769e0b57aSAlex Deucher #define WEIGHT_BIF_SHIFT 0 101869e0b57aSAlex Deucher #define WEIGHT_CP(x) ((x) << 6) 101969e0b57aSAlex Deucher #define WEIGHT_CP_MASK (0x3f << 6) 102069e0b57aSAlex Deucher #define WEIGHT_CP_SHIFT 6 102169e0b57aSAlex Deucher #define WEIGHT_PA_SIG0(x) ((x) << 12) 102269e0b57aSAlex Deucher #define WEIGHT_PA_SIG0_MASK (0x3f << 12) 102369e0b57aSAlex Deucher #define WEIGHT_PA_SIG0_SHIFT 12 102469e0b57aSAlex Deucher #define WEIGHT_PA_SIG1(x) ((x) << 18) 102569e0b57aSAlex Deucher #define WEIGHT_PA_SIG1_MASK (0x3f << 18) 102669e0b57aSAlex Deucher #define WEIGHT_PA_SIG1_SHIFT 18 102769e0b57aSAlex Deucher #define WEIGHT_VGT_SIG0(x) ((x) << 24) 102869e0b57aSAlex Deucher #define WEIGHT_VGT_SIG0_MASK (0x3f << 24) 102969e0b57aSAlex Deucher #define WEIGHT_VGT_SIG0_SHIFT 24 103069e0b57aSAlex Deucher #define CG_CAC_REGION_4_WEIGHT_2 0x8c 103169e0b57aSAlex Deucher #define WEIGHT_VGT_SIG1(x) ((x) << 0) 103269e0b57aSAlex Deucher #define WEIGHT_VGT_SIG1_MASK (0x3f << 0) 103369e0b57aSAlex Deucher #define WEIGHT_VGT_SIG1_SHIFT 0 103469e0b57aSAlex Deucher #define WEIGHT_VGT_SIG2(x) ((x) << 6) 103569e0b57aSAlex Deucher #define WEIGHT_VGT_SIG2_MASK (0x3f << 6) 103669e0b57aSAlex Deucher #define WEIGHT_VGT_SIG2_SHIFT 6 103769e0b57aSAlex Deucher #define WEIGHT_DC_SIG0(x) ((x) << 12) 103869e0b57aSAlex Deucher #define WEIGHT_DC_SIG0_MASK (0x3f << 12) 103969e0b57aSAlex Deucher #define WEIGHT_DC_SIG0_SHIFT 12 104069e0b57aSAlex Deucher #define WEIGHT_DC_SIG1(x) ((x) << 18) 104169e0b57aSAlex Deucher #define WEIGHT_DC_SIG1_MASK (0x3f << 18) 104269e0b57aSAlex Deucher #define WEIGHT_DC_SIG1_SHIFT 18 104369e0b57aSAlex Deucher #define WEIGHT_DC_SIG2(x) ((x) << 24) 104469e0b57aSAlex Deucher #define WEIGHT_DC_SIG2_MASK (0x3f << 24) 104569e0b57aSAlex Deucher #define WEIGHT_DC_SIG2_SHIFT 24 104669e0b57aSAlex Deucher #define CG_CAC_REGION_4_WEIGHT_3 0x8d 104769e0b57aSAlex Deucher #define WEIGHT_DC_SIG3(x) ((x) << 0) 104869e0b57aSAlex Deucher #define WEIGHT_DC_SIG3_MASK (0x3f << 0) 104969e0b57aSAlex Deucher #define WEIGHT_DC_SIG3_SHIFT 0 105069e0b57aSAlex Deucher #define WEIGHT_UVD_SIG0(x) ((x) << 6) 105169e0b57aSAlex Deucher #define WEIGHT_UVD_SIG0_MASK (0x3f << 6) 105269e0b57aSAlex Deucher #define WEIGHT_UVD_SIG0_SHIFT 6 105369e0b57aSAlex Deucher #define WEIGHT_UVD_SIG1(x) ((x) << 12) 105469e0b57aSAlex Deucher #define WEIGHT_UVD_SIG1_MASK (0x3f << 12) 105569e0b57aSAlex Deucher #define WEIGHT_UVD_SIG1_SHIFT 12 105669e0b57aSAlex Deucher #define WEIGHT_SPARE0(x) ((x) << 18) 105769e0b57aSAlex Deucher #define WEIGHT_SPARE0_MASK (0x3f << 18) 105869e0b57aSAlex Deucher #define WEIGHT_SPARE0_SHIFT 18 105969e0b57aSAlex Deucher #define WEIGHT_SPARE1(x) ((x) << 24) 106069e0b57aSAlex Deucher #define WEIGHT_SPARE1_MASK (0x3f << 24) 106169e0b57aSAlex Deucher #define WEIGHT_SPARE1_SHIFT 24 106269e0b57aSAlex Deucher #define CG_CAC_REGION_5_WEIGHT_0 0x8e 106369e0b57aSAlex Deucher #define WEIGHT_SQ_VSP(x) ((x) << 0) 106469e0b57aSAlex Deucher #define WEIGHT_SQ_VSP_MASK (0x3fff << 0) 106569e0b57aSAlex Deucher #define WEIGHT_SQ_VSP_SHIFT 0 106669e0b57aSAlex Deucher #define WEIGHT_SQ_VSP0(x) ((x) << 14) 106769e0b57aSAlex Deucher #define WEIGHT_SQ_VSP0_MASK (0x3fff << 14) 106869e0b57aSAlex Deucher #define WEIGHT_SQ_VSP0_SHIFT 14 106969e0b57aSAlex Deucher #define CG_CAC_REGION_4_OVERRIDE_4 0xab 107069e0b57aSAlex Deucher #define OVR_MODE_SPARE_0(x) ((x) << 16) 107169e0b57aSAlex Deucher #define OVR_MODE_SPARE_0_MASK (0x1 << 16) 107269e0b57aSAlex Deucher #define OVR_MODE_SPARE_0_SHIFT 16 107369e0b57aSAlex Deucher #define OVR_VAL_SPARE_0(x) ((x) << 17) 107469e0b57aSAlex Deucher #define OVR_VAL_SPARE_0_MASK (0x1 << 17) 107569e0b57aSAlex Deucher #define OVR_VAL_SPARE_0_SHIFT 17 107669e0b57aSAlex Deucher #define OVR_MODE_SPARE_1(x) ((x) << 18) 107769e0b57aSAlex Deucher #define OVR_MODE_SPARE_1_MASK (0x3f << 18) 107869e0b57aSAlex Deucher #define OVR_MODE_SPARE_1_SHIFT 18 107969e0b57aSAlex Deucher #define OVR_VAL_SPARE_1(x) ((x) << 19) 108069e0b57aSAlex Deucher #define OVR_VAL_SPARE_1_MASK (0x3f << 19) 108169e0b57aSAlex Deucher #define OVR_VAL_SPARE_1_SHIFT 19 108269e0b57aSAlex Deucher #define CG_CAC_REGION_5_WEIGHT_1 0xb7 108369e0b57aSAlex Deucher #define WEIGHT_SQ_GPR(x) ((x) << 0) 108469e0b57aSAlex Deucher #define WEIGHT_SQ_GPR_MASK (0x3fff << 0) 108569e0b57aSAlex Deucher #define WEIGHT_SQ_GPR_SHIFT 0 108669e0b57aSAlex Deucher #define WEIGHT_SQ_LDS(x) ((x) << 14) 108769e0b57aSAlex Deucher #define WEIGHT_SQ_LDS_MASK (0x3fff << 14) 108869e0b57aSAlex Deucher #define WEIGHT_SQ_LDS_SHIFT 14 108969e0b57aSAlex Deucher 109069e0b57aSAlex Deucher /* PCIE link stuff */ 109169e0b57aSAlex Deucher #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 109269e0b57aSAlex Deucher #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 109369e0b57aSAlex Deucher # define LC_LINK_WIDTH_SHIFT 0 109469e0b57aSAlex Deucher # define LC_LINK_WIDTH_MASK 0x7 109569e0b57aSAlex Deucher # define LC_LINK_WIDTH_X0 0 109669e0b57aSAlex Deucher # define LC_LINK_WIDTH_X1 1 109769e0b57aSAlex Deucher # define LC_LINK_WIDTH_X2 2 109869e0b57aSAlex Deucher # define LC_LINK_WIDTH_X4 3 109969e0b57aSAlex Deucher # define LC_LINK_WIDTH_X8 4 110069e0b57aSAlex Deucher # define LC_LINK_WIDTH_X16 6 110169e0b57aSAlex Deucher # define LC_LINK_WIDTH_RD_SHIFT 4 110269e0b57aSAlex Deucher # define LC_LINK_WIDTH_RD_MASK 0x70 110369e0b57aSAlex Deucher # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 110469e0b57aSAlex Deucher # define LC_RECONFIG_NOW (1 << 8) 110569e0b57aSAlex Deucher # define LC_RENEGOTIATION_SUPPORT (1 << 9) 110669e0b57aSAlex Deucher # define LC_RENEGOTIATE_EN (1 << 10) 110769e0b57aSAlex Deucher # define LC_SHORT_RECONFIG_EN (1 << 11) 110869e0b57aSAlex Deucher # define LC_UPCONFIGURE_SUPPORT (1 << 12) 110969e0b57aSAlex Deucher # define LC_UPCONFIGURE_DIS (1 << 13) 111069e0b57aSAlex Deucher #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 111169e0b57aSAlex Deucher # define LC_GEN2_EN_STRAP (1 << 0) 111269e0b57aSAlex Deucher # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 111369e0b57aSAlex Deucher # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 111469e0b57aSAlex Deucher # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 111569e0b57aSAlex Deucher # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 111669e0b57aSAlex Deucher # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 111769e0b57aSAlex Deucher # define LC_CURRENT_DATA_RATE (1 << 11) 111869e0b57aSAlex Deucher # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) 111969e0b57aSAlex Deucher # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) 112069e0b57aSAlex Deucher # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 112169e0b57aSAlex Deucher # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 112269e0b57aSAlex Deucher # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 112369e0b57aSAlex Deucher # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 112469e0b57aSAlex Deucher # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 112569e0b57aSAlex Deucher #define MM_CFGREGS_CNTL 0x544c 112669e0b57aSAlex Deucher # define MM_WR_TO_CFG_EN (1 << 3) 112769e0b57aSAlex Deucher #define LINK_CNTL2 0x88 /* F0 */ 112869e0b57aSAlex Deucher # define TARGET_LINK_SPEED_MASK (0xf << 0) 112969e0b57aSAlex Deucher # define SELECTABLE_DEEMPHASIS (1 << 6) 113069e0b57aSAlex Deucher 11310c88a02eSAlex Deucher /* 1132f2ba57b5SChristian König * UVD 1133f2ba57b5SChristian König */ 1134f2ba57b5SChristian König #define UVD_SEMA_ADDR_LOW 0xEF00 1135f2ba57b5SChristian König #define UVD_SEMA_ADDR_HIGH 0xEF04 1136f2ba57b5SChristian König #define UVD_SEMA_CMD 0xEF08 11379a21059dSChristian König #define UVD_UDEC_ADDR_CONFIG 0xEF4C 11389a21059dSChristian König #define UVD_UDEC_DB_ADDR_CONFIG 0xEF50 11399a21059dSChristian König #define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54 1140*70a033d2SAlex Deucher #define UVD_NO_OP 0xEFFC 1141f2ba57b5SChristian König #define UVD_RBC_RB_RPTR 0xF690 1142f2ba57b5SChristian König #define UVD_RBC_RB_WPTR 0xF694 1143e66582f9SAlex Deucher #define UVD_STATUS 0xf6bc 1144f2ba57b5SChristian König 1145f2ba57b5SChristian König /* 11460c88a02eSAlex Deucher * PM4 11470c88a02eSAlex Deucher */ 11484e872ae2SIlija Hadzic #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 11490c88a02eSAlex Deucher (((reg) >> 2) & 0xFFFF) | \ 11500c88a02eSAlex Deucher ((n) & 0x3FFF) << 16) 11510c88a02eSAlex Deucher #define CP_PACKET2 0x80000000 11520c88a02eSAlex Deucher #define PACKET2_PAD_SHIFT 0 11530c88a02eSAlex Deucher #define PACKET2_PAD_MASK (0x3fffffff << 0) 11540c88a02eSAlex Deucher 11550c88a02eSAlex Deucher #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 11560c88a02eSAlex Deucher 11574e872ae2SIlija Hadzic #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 11580c88a02eSAlex Deucher (((op) & 0xFF) << 8) | \ 11590c88a02eSAlex Deucher ((n) & 0x3FFF) << 16) 11600c88a02eSAlex Deucher 11610c88a02eSAlex Deucher /* Packet 3 types */ 11620c88a02eSAlex Deucher #define PACKET3_NOP 0x10 11630c88a02eSAlex Deucher #define PACKET3_SET_BASE 0x11 11640c88a02eSAlex Deucher #define PACKET3_CLEAR_STATE 0x12 11650c88a02eSAlex Deucher #define PACKET3_INDEX_BUFFER_SIZE 0x13 11660c88a02eSAlex Deucher #define PACKET3_DEALLOC_STATE 0x14 11670c88a02eSAlex Deucher #define PACKET3_DISPATCH_DIRECT 0x15 11680c88a02eSAlex Deucher #define PACKET3_DISPATCH_INDIRECT 0x16 11690c88a02eSAlex Deucher #define PACKET3_INDIRECT_BUFFER_END 0x17 1170721604a1SJerome Glisse #define PACKET3_MODE_CONTROL 0x18 11710c88a02eSAlex Deucher #define PACKET3_SET_PREDICATION 0x20 11720c88a02eSAlex Deucher #define PACKET3_REG_RMW 0x21 11730c88a02eSAlex Deucher #define PACKET3_COND_EXEC 0x22 11740c88a02eSAlex Deucher #define PACKET3_PRED_EXEC 0x23 11750c88a02eSAlex Deucher #define PACKET3_DRAW_INDIRECT 0x24 11760c88a02eSAlex Deucher #define PACKET3_DRAW_INDEX_INDIRECT 0x25 11770c88a02eSAlex Deucher #define PACKET3_INDEX_BASE 0x26 11780c88a02eSAlex Deucher #define PACKET3_DRAW_INDEX_2 0x27 11790c88a02eSAlex Deucher #define PACKET3_CONTEXT_CONTROL 0x28 11800c88a02eSAlex Deucher #define PACKET3_DRAW_INDEX_OFFSET 0x29 11810c88a02eSAlex Deucher #define PACKET3_INDEX_TYPE 0x2A 11820c88a02eSAlex Deucher #define PACKET3_DRAW_INDEX 0x2B 11830c88a02eSAlex Deucher #define PACKET3_DRAW_INDEX_AUTO 0x2D 11840c88a02eSAlex Deucher #define PACKET3_DRAW_INDEX_IMMD 0x2E 11850c88a02eSAlex Deucher #define PACKET3_NUM_INSTANCES 0x2F 11860c88a02eSAlex Deucher #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 11870c88a02eSAlex Deucher #define PACKET3_INDIRECT_BUFFER 0x32 11880c88a02eSAlex Deucher #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 11890c88a02eSAlex Deucher #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 11900c88a02eSAlex Deucher #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 11910c88a02eSAlex Deucher #define PACKET3_WRITE_DATA 0x37 11920c88a02eSAlex Deucher #define PACKET3_MEM_SEMAPHORE 0x39 11930c88a02eSAlex Deucher #define PACKET3_MPEG_INDEX 0x3A 11940c88a02eSAlex Deucher #define PACKET3_WAIT_REG_MEM 0x3C 1195cbfc35b9SAlex Deucher #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 1196cbfc35b9SAlex Deucher /* 0 - always 1197cbfc35b9SAlex Deucher * 1 - < 1198cbfc35b9SAlex Deucher * 2 - <= 1199cbfc35b9SAlex Deucher * 3 - == 1200cbfc35b9SAlex Deucher * 4 - != 1201cbfc35b9SAlex Deucher * 5 - >= 1202cbfc35b9SAlex Deucher * 6 - > 1203cbfc35b9SAlex Deucher */ 1204cbfc35b9SAlex Deucher #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 1205cbfc35b9SAlex Deucher /* 0 - reg 1206cbfc35b9SAlex Deucher * 1 - mem 1207cbfc35b9SAlex Deucher */ 1208cbfc35b9SAlex Deucher #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 1209cbfc35b9SAlex Deucher /* 0 - me 1210cbfc35b9SAlex Deucher * 1 - pfp 1211cbfc35b9SAlex Deucher */ 12120c88a02eSAlex Deucher #define PACKET3_MEM_WRITE 0x3D 121358f8cf56SChristian König #define PACKET3_PFP_SYNC_ME 0x42 12140c88a02eSAlex Deucher #define PACKET3_SURFACE_SYNC 0x43 12150c88a02eSAlex Deucher # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 12160c88a02eSAlex Deucher # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 12170c88a02eSAlex Deucher # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 12180c88a02eSAlex Deucher # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 12190c88a02eSAlex Deucher # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 12200c88a02eSAlex Deucher # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 12210c88a02eSAlex Deucher # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 12220c88a02eSAlex Deucher # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 12230c88a02eSAlex Deucher # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 12240c88a02eSAlex Deucher # define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 12250c88a02eSAlex Deucher # define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 12260c88a02eSAlex Deucher # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 12270c88a02eSAlex Deucher # define PACKET3_CB11_DEST_BASE_ENA (1 << 18) 12280c88a02eSAlex Deucher # define PACKET3_FULL_CACHE_ENA (1 << 20) 12290c88a02eSAlex Deucher # define PACKET3_TC_ACTION_ENA (1 << 23) 12300c88a02eSAlex Deucher # define PACKET3_CB_ACTION_ENA (1 << 25) 12310c88a02eSAlex Deucher # define PACKET3_DB_ACTION_ENA (1 << 26) 12320c88a02eSAlex Deucher # define PACKET3_SH_ACTION_ENA (1 << 27) 12330c88a02eSAlex Deucher # define PACKET3_SX_ACTION_ENA (1 << 28) 123410e9ffaeSAlex Deucher # define PACKET3_ENGINE_ME (1 << 31) 12350c88a02eSAlex Deucher #define PACKET3_ME_INITIALIZE 0x44 12360c88a02eSAlex Deucher #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 12370c88a02eSAlex Deucher #define PACKET3_COND_WRITE 0x45 12380c88a02eSAlex Deucher #define PACKET3_EVENT_WRITE 0x46 1239b40e7e16SAlex Deucher #define EVENT_TYPE(x) ((x) << 0) 1240b40e7e16SAlex Deucher #define EVENT_INDEX(x) ((x) << 8) 1241b40e7e16SAlex Deucher /* 0 - any non-TS event 1242b40e7e16SAlex Deucher * 1 - ZPASS_DONE 1243b40e7e16SAlex Deucher * 2 - SAMPLE_PIPELINESTAT 1244b40e7e16SAlex Deucher * 3 - SAMPLE_STREAMOUTSTAT* 1245b40e7e16SAlex Deucher * 4 - *S_PARTIAL_FLUSH 1246b40e7e16SAlex Deucher * 5 - TS events 1247b40e7e16SAlex Deucher */ 12480c88a02eSAlex Deucher #define PACKET3_EVENT_WRITE_EOP 0x47 1249b40e7e16SAlex Deucher #define DATA_SEL(x) ((x) << 29) 1250b40e7e16SAlex Deucher /* 0 - discard 1251b40e7e16SAlex Deucher * 1 - send low 32bit data 1252b40e7e16SAlex Deucher * 2 - send 64bit data 1253b40e7e16SAlex Deucher * 3 - send 64bit counter value 1254b40e7e16SAlex Deucher */ 1255b40e7e16SAlex Deucher #define INT_SEL(x) ((x) << 24) 1256b40e7e16SAlex Deucher /* 0 - none 1257b40e7e16SAlex Deucher * 1 - interrupt only (DATA_SEL = 0) 1258b40e7e16SAlex Deucher * 2 - interrupt when data write is confirmed 1259b40e7e16SAlex Deucher */ 12600c88a02eSAlex Deucher #define PACKET3_EVENT_WRITE_EOS 0x48 12610c88a02eSAlex Deucher #define PACKET3_PREAMBLE_CNTL 0x4A 12620c88a02eSAlex Deucher # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 12630c88a02eSAlex Deucher # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 12640c88a02eSAlex Deucher #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 12650c88a02eSAlex Deucher #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 12660c88a02eSAlex Deucher #define PACKET3_ALU_PS_CONST_UPDATE 0x4E 12670c88a02eSAlex Deucher #define PACKET3_ALU_VS_CONST_UPDATE 0x4F 12680c88a02eSAlex Deucher #define PACKET3_ONE_REG_WRITE 0x57 12690c88a02eSAlex Deucher #define PACKET3_SET_CONFIG_REG 0x68 12700c88a02eSAlex Deucher #define PACKET3_SET_CONFIG_REG_START 0x00008000 12710c88a02eSAlex Deucher #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 12720c88a02eSAlex Deucher #define PACKET3_SET_CONTEXT_REG 0x69 12730c88a02eSAlex Deucher #define PACKET3_SET_CONTEXT_REG_START 0x00028000 12740c88a02eSAlex Deucher #define PACKET3_SET_CONTEXT_REG_END 0x00029000 12750c88a02eSAlex Deucher #define PACKET3_SET_ALU_CONST 0x6A 12760c88a02eSAlex Deucher /* alu const buffers only; no reg file */ 12770c88a02eSAlex Deucher #define PACKET3_SET_BOOL_CONST 0x6B 12780c88a02eSAlex Deucher #define PACKET3_SET_BOOL_CONST_START 0x0003a500 12790c88a02eSAlex Deucher #define PACKET3_SET_BOOL_CONST_END 0x0003a518 12800c88a02eSAlex Deucher #define PACKET3_SET_LOOP_CONST 0x6C 12810c88a02eSAlex Deucher #define PACKET3_SET_LOOP_CONST_START 0x0003a200 12820c88a02eSAlex Deucher #define PACKET3_SET_LOOP_CONST_END 0x0003a500 12830c88a02eSAlex Deucher #define PACKET3_SET_RESOURCE 0x6D 12840c88a02eSAlex Deucher #define PACKET3_SET_RESOURCE_START 0x00030000 12850c88a02eSAlex Deucher #define PACKET3_SET_RESOURCE_END 0x00038000 12860c88a02eSAlex Deucher #define PACKET3_SET_SAMPLER 0x6E 12870c88a02eSAlex Deucher #define PACKET3_SET_SAMPLER_START 0x0003c000 12880c88a02eSAlex Deucher #define PACKET3_SET_SAMPLER_END 0x0003c600 12890c88a02eSAlex Deucher #define PACKET3_SET_CTL_CONST 0x6F 12900c88a02eSAlex Deucher #define PACKET3_SET_CTL_CONST_START 0x0003cff0 12910c88a02eSAlex Deucher #define PACKET3_SET_CTL_CONST_END 0x0003ff0c 12920c88a02eSAlex Deucher #define PACKET3_SET_RESOURCE_OFFSET 0x70 12930c88a02eSAlex Deucher #define PACKET3_SET_ALU_CONST_VS 0x71 12940c88a02eSAlex Deucher #define PACKET3_SET_ALU_CONST_DI 0x72 12950c88a02eSAlex Deucher #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 12960c88a02eSAlex Deucher #define PACKET3_SET_RESOURCE_INDIRECT 0x74 12970c88a02eSAlex Deucher #define PACKET3_SET_APPEND_CNT 0x75 12982a6f1abbSChristian König #define PACKET3_ME_WRITE 0x7A 12990c88a02eSAlex Deucher 1300f60cbd11SAlex Deucher /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 1301f60cbd11SAlex Deucher #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 1302f60cbd11SAlex Deucher #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ 1303f60cbd11SAlex Deucher 1304f60cbd11SAlex Deucher #define DMA_RB_CNTL 0xd000 1305f60cbd11SAlex Deucher # define DMA_RB_ENABLE (1 << 0) 1306f60cbd11SAlex Deucher # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 1307f60cbd11SAlex Deucher # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 1308f60cbd11SAlex Deucher # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 1309f60cbd11SAlex Deucher # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 1310f60cbd11SAlex Deucher # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 1311f60cbd11SAlex Deucher #define DMA_RB_BASE 0xd004 1312f60cbd11SAlex Deucher #define DMA_RB_RPTR 0xd008 1313f60cbd11SAlex Deucher #define DMA_RB_WPTR 0xd00c 1314f60cbd11SAlex Deucher 1315f60cbd11SAlex Deucher #define DMA_RB_RPTR_ADDR_HI 0xd01c 1316f60cbd11SAlex Deucher #define DMA_RB_RPTR_ADDR_LO 0xd020 1317f60cbd11SAlex Deucher 1318f60cbd11SAlex Deucher #define DMA_IB_CNTL 0xd024 1319f60cbd11SAlex Deucher # define DMA_IB_ENABLE (1 << 0) 1320f60cbd11SAlex Deucher # define DMA_IB_SWAP_ENABLE (1 << 4) 1321f60cbd11SAlex Deucher # define CMD_VMID_FORCE (1 << 31) 1322f60cbd11SAlex Deucher #define DMA_IB_RPTR 0xd028 1323f60cbd11SAlex Deucher #define DMA_CNTL 0xd02c 1324f60cbd11SAlex Deucher # define TRAP_ENABLE (1 << 0) 1325f60cbd11SAlex Deucher # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 1326f60cbd11SAlex Deucher # define SEM_WAIT_INT_ENABLE (1 << 2) 1327f60cbd11SAlex Deucher # define DATA_SWAP_ENABLE (1 << 3) 1328f60cbd11SAlex Deucher # define FENCE_SWAP_ENABLE (1 << 4) 1329f60cbd11SAlex Deucher # define CTXEMPTY_INT_ENABLE (1 << 28) 1330f60cbd11SAlex Deucher #define DMA_STATUS_REG 0xd034 1331f60cbd11SAlex Deucher # define DMA_IDLE (1 << 0) 1332f60cbd11SAlex Deucher #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044 1333f60cbd11SAlex Deucher #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048 1334f60cbd11SAlex Deucher #define DMA_TILING_CONFIG 0xd0b8 1335f60cbd11SAlex Deucher #define DMA_MODE 0xd0bc 1336f60cbd11SAlex Deucher 1337f60cbd11SAlex Deucher #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 1338f60cbd11SAlex Deucher (((t) & 0x1) << 23) | \ 1339f60cbd11SAlex Deucher (((s) & 0x1) << 22) | \ 1340f60cbd11SAlex Deucher (((n) & 0xFFFFF) << 0)) 1341f60cbd11SAlex Deucher 1342f60cbd11SAlex Deucher #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 1343f60cbd11SAlex Deucher (((vmid) & 0xF) << 20) | \ 1344f60cbd11SAlex Deucher (((n) & 0xFFFFF) << 0)) 1345f60cbd11SAlex Deucher 13462ab91adaSAlex Deucher #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ 13472ab91adaSAlex Deucher (1 << 26) | \ 13482ab91adaSAlex Deucher (1 << 21) | \ 13492ab91adaSAlex Deucher (((n) & 0xFFFFF) << 0)) 13502ab91adaSAlex Deucher 1351cbfc35b9SAlex Deucher #define DMA_SRBM_POLL_PACKET ((9 << 28) | \ 1352cbfc35b9SAlex Deucher (1 << 27) | \ 1353cbfc35b9SAlex Deucher (1 << 26)) 1354cbfc35b9SAlex Deucher 1355cbfc35b9SAlex Deucher #define DMA_SRBM_READ_PACKET ((9 << 28) | \ 1356cbfc35b9SAlex Deucher (1 << 27)) 1357cbfc35b9SAlex Deucher 1358f60cbd11SAlex Deucher /* async DMA Packet types */ 1359f60cbd11SAlex Deucher #define DMA_PACKET_WRITE 0x2 1360f60cbd11SAlex Deucher #define DMA_PACKET_COPY 0x3 1361f60cbd11SAlex Deucher #define DMA_PACKET_INDIRECT_BUFFER 0x4 1362f60cbd11SAlex Deucher #define DMA_PACKET_SEMAPHORE 0x5 1363f60cbd11SAlex Deucher #define DMA_PACKET_FENCE 0x6 1364f60cbd11SAlex Deucher #define DMA_PACKET_TRAP 0x7 1365f60cbd11SAlex Deucher #define DMA_PACKET_SRBM_WRITE 0x9 1366f60cbd11SAlex Deucher #define DMA_PACKET_CONSTANT_FILL 0xd 1367f60cbd11SAlex Deucher #define DMA_PACKET_NOP 0xf 1368f60cbd11SAlex Deucher 13690af62b01SAlex Deucher #endif 1370