Home
last modified time | relevance | path

Searched +full:0 +full:x6c (Results 1 – 25 of 756) sorted by relevance

12345678910>>...31

/linux/sound/drivers/opl4/
H A Dyrw801.c40 snd_opl4_read_memory(opl4, buf, 0x001200, 15); in snd_yrw801_detect()
43 snd_opl4_read_memory(opl4, buf, 0x1ffffe, 2); in snd_yrw801_detect()
44 if (buf[0] != 0x01) in snd_yrw801_detect()
46 dev_dbg(opl4->card->dev, "YRW801 ROM version %02x.%02x\n", buf[0], buf[1]); in snd_yrw801_detect()
47 return 0; in snd_yrw801_detect()
58 {0x14, 0x27, {0x12c,7474,100, 0,0,0x00,0xc8,0x20,0xf2,0x13,0x08,0x0}},
59 {0x28, 0x2d, {0x12d,6816,100, 0,0,0x00,0xc8,0x20,0xf2,0x14,0x08,0x0}},
60 {0x2e, 0x33, {0x12e,5899,100, 0,0,0x00,0xc8,0x20,0xf2,0x14,0x08,0x0}},
61 {0x34, 0x39, {0x12f,5290,100, 0,0,0x00,0xc8,0x20,0xf2,0x14,0x08,0x0}},
62 {0x3a, 0x3f, {0x130,4260,100, 0,0,0x0a,0xc8,0x20,0xf2,0x14,0x08,0x0}},
[all …]
/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2044.dtsi20 reg = <0x00000000 0x80000000 0x00000010 0x00000000>;
26 #clock-cells = <0>;
37 reg = <0x6c 0x00000000 0x0 0x00001000>,
38 <0x6c 0x00300000 0x0 0x00004000>,
39 <0x48 0x00000000 0x0 0x00001000>,
40 <0x6c 0x000c0000 0x0 0x00001000>;
48 interrupt-map-mask = <0 0 0 7>;
49 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
50 <0 0 0 2 &pcie_intc0 1>,
51 <0 0 0 3 &pcie_intc0 2>,
[all …]
/linux/drivers/scsi/aic7xxx/
H A Daic7xxx_seq.h_shipped9 0xb2, 0x00, 0x00, 0x08,
10 0xf7, 0x11, 0x22, 0x08,
11 0x00, 0x65, 0xee, 0x59,
12 0xf7, 0x01, 0x02, 0x08,
13 0xff, 0x6a, 0x24, 0x08,
14 0x40, 0x00, 0x40, 0x68,
15 0x08, 0x1f, 0x3e, 0x10,
16 0x40, 0x00, 0x40, 0x68,
17 0xff, 0x40, 0x3c, 0x60,
18 0x08, 0x1f, 0x3e, 0x10,
[all …]
H A Daic79xx_seq.h_shipped9 0xff, 0x02, 0x06, 0x78,
10 0x00, 0xea, 0x6e, 0x59,
11 0x01, 0xea, 0x04, 0x30,
12 0xff, 0x04, 0x0c, 0x78,
13 0x19, 0xea, 0x6e, 0x59,
14 0x19, 0xea, 0x04, 0x00,
15 0x33, 0xea, 0x68, 0x59,
16 0x33, 0xea, 0x00, 0x00,
17 0x60, 0x3a, 0x3a, 0x68,
18 0x04, 0x4d, 0x35, 0x78,
[all …]
/linux/drivers/regulator/
H A Dpv88080-regulator.h11 #define PV88080_REG_EVENT_A 0x04
12 #define PV88080_REG_MASK_A 0x09
13 #define PV88080_REG_MASK_B 0x0A
14 #define PV88080_REG_MASK_C 0x0B
17 #define PV88080AA_REG_HVBUCK_CONF1 0x2D
18 #define PV88080AA_REG_HVBUCK_CONF2 0x2E
19 #define PV88080AA_REG_BUCK1_CONF0 0x27
20 #define PV88080AA_REG_BUCK1_CONF1 0x28
21 #define PV88080AA_REG_BUCK1_CONF2 0x59
22 #define PV88080AA_REG_BUCK1_CONF5 0x5C
[all …]
/linux/kernel/bpf/preload/iterators/
H A Diterators.lskel-big-endian.h27 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_map__attach()
29 if (fd > 0) in iterators_bpf__dump_bpf_map__attach()
38 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_prog__attach()
40 if (fd > 0) in iterators_bpf__dump_bpf_prog__attach()
48 int ret = 0; in iterators_bpf__attach()
50 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_map__attach(skel); in iterators_bpf__attach()
51 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_prog__attach(skel); in iterators_bpf__attach()
52 return ret < 0 ? ret : 0; in iterators_bpf__attach()
93 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load()
94 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load()
[all …]
H A Diterators.lskel-little-endian.h27 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_map__attach()
29 if (fd > 0) in iterators_bpf__dump_bpf_map__attach()
38 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_prog__attach()
40 if (fd > 0) in iterators_bpf__dump_bpf_prog__attach()
48 int ret = 0; in iterators_bpf__attach()
50 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_map__attach(skel); in iterators_bpf__attach()
51 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_prog__attach(skel); in iterators_bpf__attach()
52 return ret < 0 ? ret : 0; in iterators_bpf__attach()
96 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load()
97 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load()
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx6sll.c19 #define CCM_ANALOG_PLL_BYPASS (0x1 << 16)
20 #define xPLL_CLR(offset) (offset + 0x8)
62 { .val = 0, .div = 4, },
67 { .val = 0, .div = 1, },
91 hws[IMX6SLL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6sll_clocks_init()
101 base = of_iomap(np, 0); in imx6sll_clocks_init()
106 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x0)); in imx6sll_clocks_init()
107 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x10)); in imx6sll_clocks_init()
108 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x20)); in imx6sll_clocks_init()
109 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x30)); in imx6sll_clocks_init()
[all …]
H A Dclk-imx6ul.c76 { .val = 0, .div = 20, },
86 { .val = 0, .div = 4, },
91 { .val = 0, .div = 1, },
100 IMX6UL_GPR1_ENET1_CLK_SEL, 0,
106 IMX6UL_GPR1_ENET2_CLK_SEL, 0,
140 hws[IMX6UL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6ul_clocks_init()
150 base = of_iomap(np, 0); in imx6ul_clocks_init()
154 …hws[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
155 …hws[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
156 …hws[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
[all …]
H A Dclk-imx6sx.c89 { .val = 0, .div = 20, },
99 { .val = 0, .div = 4, },
104 { .val = 0, .div = 1, },
133 hws[IMX6SX_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6sx_clocks_init()
147 base = of_iomap(np, 0); in imx6sx_clocks_init()
151 …hws[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
152 …hws[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
153 …hws[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
154 …hws[IMX6SX_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
155 …hws[IMX6SX_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
[all …]
H A Dclk-imx6sl.c18 #define CCSR 0xc
20 #define CACRR 0x10
21 #define CDHIPR 0x48
27 #define PLL_ARM 0x0
28 #define BM_PLL_ARM_DIV_SELECT 0x7f
73 { .val = 0, .div = 20, },
83 { .val = 0, .div = 4, },
88 { .val = 0, .div = 1, },
195 hws[IMX6SL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6sl_clocks_init()
196 hws[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock_hw("ckil", 0); in imx6sl_clocks_init()
[all …]
/linux/arch/x86/platform/olpc/
H A Dolpc.c54 return !!(inb(port) & 0x02); in ibf_status()
59 return inb(port) & 0x01; in obf_status()
114 int restarts = 0; in olpc_xo1_ec_cmd()
117 for (i = 0; i < 10 && (obf_status(0x6c) == 1); i++) in olpc_xo1_ec_cmd()
118 inb(0x68); in olpc_xo1_ec_cmd()
125 if (wait_on_ibf(0x6c, 0)) { in olpc_xo1_ec_cmd()
141 pr_devel("olpc-ec: running cmd 0x%x\n", cmd); in olpc_xo1_ec_cmd()
142 outb(cmd, 0x6c); in olpc_xo1_ec_cmd()
144 if (wait_on_ibf(0x6c, 0)) { in olpc_xo1_ec_cmd()
152 for (i = 0; i < inlen; i++) { in olpc_xo1_ec_cmd()
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dsophgo,sg2044-pcie.yaml53 const: 0
94 reg = <0x6c 0x00400000 0x0 0x00001000>,
95 <0x6c 0x00700000 0x0 0x00004000>,
96 <0x40 0x00000000 0x0 0x00001000>,
97 <0x6c 0x00780c00 0x0 0x00000400>;
101 bus-range = <0x00 0xff>;
102 clocks = <&clk 0>;
105 linux,pci-domain = <0>;
107 ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00200000>,
108 <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000000>,
[all …]
/linux/drivers/media/dvb-frontends/
H A Dcxd2820r.h14 #define CXD2820R_GPIO_D (0 << 0) /* disable */
15 #define CXD2820R_GPIO_E (1 << 0) /* enable */
16 #define CXD2820R_GPIO_O (0 << 1) /* output */
18 #define CXD2820R_GPIO_L (0 << 2) /* output low */
21 #define CXD2820R_TS_SERIAL 0x08
22 #define CXD2820R_TS_SERIAL_MSB 0x28
23 #define CXD2820R_TS_PARALLEL 0x30
24 #define CXD2820R_TS_PARALLEL_MSB 0x70
27 * I2C address: 0x6c, 0x6d
56 * Default: none, must set. Values: 0x6c, 0x6d.
[all …]
/linux/net/sunrpc/auth_gss/
H A Dgss_krb5_test.c63 KUNIT_ASSERT_EQ(test, err, 0); in kdf_case()
77 .head[0].iov_len = param->plaintext->len, in checksum_case()
95 KUNIT_ASSERT_EQ(test, err, 0); in checksum_case()
97 tfm = crypto_alloc_ahash(gk5e->cksum_name, 0, CRYPTO_ALG_ASYNC); in checksum_case()
100 KUNIT_ASSERT_EQ(test, err, 0); in checksum_case()
102 buf.head[0].iov_base = kunit_kzalloc(test, buf.head[0].iov_len, GFP_KERNEL); in checksum_case()
103 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf.head[0].iov_base); in checksum_case()
104 memcpy(buf.head[0].iov_base, param->plaintext->data, buf.head[0] in checksum_case()
[all...]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
H A Dfw.c28 if (rtlpriv->max_fw_size == 0 || !rtlhal->pfirmware) in rtl92d_download_fw()
48 if ((rtl_read_byte(rtlpriv, 0x1f) & BIT(5)) == BIT(5)) in rtl92d_download_fw()
57 for (count = 0; count < 5000; count++) { in rtl92d_download_fw()
61 if ((rtl_read_byte(rtlpriv, 0x1f) & BIT(5)) == BIT(5)) in rtl92d_download_fw()
76 value = rtl_read_byte(rtlpriv, 0x1f); in rtl92d_download_fw()
78 rtl_write_byte(rtlpriv, 0x1f, value); in rtl92d_download_fw()
81 value = rtl_read_byte(rtlpriv, 0x1f); in rtl92d_download_fw()
83 rtl_write_byte(rtlpriv, 0x1f, value); in rtl92d_download_fw()
93 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); in rtl92d_download_fw()
100 /* download fw over,clear 0x1f[5] */ in rtl92d_download_fw()
[all …]
/linux/drivers/staging/media/meson/vdec/
H A Dcodec_h264.c15 #define SIZE_WORKSPACE 0x1ee000
22 #define WORKSPACE_BUF_OFFSET 0x1000000
25 #define CMD_MASK GENMASK(7, 0)
43 #define PIC_STRUCT_MASK GENMASK(2, 0)
44 #define BUF_IDX_MASK GENMASK(4, 0)
47 #define OFFSET_MASK GENMASK(15, 0)
51 #define MB_TOTAL_MASK GENMASK(15, 0)
52 #define MB_WIDTH_MASK GENMASK(7, 0)
54 #define MAX_REF_MASK GENMASK(6, 0)
56 #define AR_IDC_MASK GENMASK(7, 0)
[all …]
/linux/drivers/clk/hisilicon/
H A Dcrg-hi3798cv200.c45 { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, },
46 { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, },
47 { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, },
48 { HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, },
49 { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, },
50 { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, },
51 { HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, },
52 { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, },
53 { HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, },
54 { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
[all …]
/linux/sound/soc/codecs/
H A Dda7213.h24 #define DA7213_STATUS1 0x02
25 #define DA7213_PLL_STATUS 0x03
26 #define DA7213_AUX_L_GAIN_STATUS 0x04
27 #define DA7213_AUX_R_GAIN_STATUS 0x05
28 #define DA7213_MIC_1_GAIN_STATUS 0x06
29 #define DA7213_MIC_2_GAIN_STATUS 0x07
30 #define DA7213_MIXIN_L_GAIN_STATUS 0x08
31 #define DA7213_MIXIN_R_GAIN_STATUS 0x09
32 #define DA7213_ADC_L_GAIN_STATUS 0x0A
33 #define DA7213_ADC_R_GAIN_STATUS 0x0B
[all …]
/linux/Documentation/devicetree/bindings/input/touchscreen/
H A Dhideep.txt5 - reg : I2C slave address, (e.g. 0x6C).
31 reg = <0x6c>;
36 reset-gpios = <&gpx1 5 0>;
/linux/lib/crypto/tests/
H A Dblake2b-testvecs.h9 .data_len = 0,
11 0x78, 0x6a, 0x02, 0xf7, 0x42, 0x01, 0x59, 0x03,
12 0xc6, 0xc6, 0xfd, 0x85, 0x25, 0x52, 0xd2, 0x72,
13 0x91, 0x2f, 0x47, 0x40, 0xe1, 0x58, 0x47, 0x61,
14 0x8a, 0x86, 0xe2, 0x17, 0xf7, 0x1f, 0x54, 0x19,
15 0xd2, 0x5e, 0x10, 0x31, 0xaf, 0xee, 0x58, 0x53,
16 0x13, 0x89, 0x64, 0x44, 0x93, 0x4e, 0xb0, 0x4b,
17 0x90, 0x3a, 0x68, 0x5b, 0x14, 0x48, 0xb7, 0x55,
18 0xd5, 0x6f, 0x70, 0x1a, 0xfe, 0x9b, 0xe2, 0xce,
24 0x6f, 0x2e, 0xcc, 0x83, 0x53, 0xa3, 0x20, 0x16,
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dfw.c23 if (((val_hmetfr >> boxnum) & BIT(0)) == 0 && val_mcutst_1 == 0) in _rtl8723e_check_fw_read_last_h2c()
34 u16 box_reg = 0, box_extreg = 0; in _rtl8723e_fill_h2c_command()
37 u8 buf_index = 0; in _rtl8723e_fill_h2c_command()
42 u32 h2c_waitcounter = 0; in _rtl8723e_fill_h2c_command()
79 if (wait_writeh2c_limmit == 0) { in _rtl8723e_fill_h2c_command()
86 case 0: in _rtl8723e_fill_h2c_command()
112 if (wait_h2c_limmit == 0) { in _rtl8723e_fill_h2c_command()
123 u1b_tmp = rtl_read_byte(rtlpriv, 0x1BF); in _rtl8723e_fill_h2c_command()
125 "Waiting for FW read clear HMEBox(%d)!!! 0x1BF = %2x\n", in _rtl8723e_fill_h2c_command()
136 memset(boxcontent, 0, sizeof(boxcontent)); in _rtl8723e_fill_h2c_command()
[all …]
/linux/drivers/tty/vt/
H A Ducs_fallback_table.h_shipped7 * Unicode Version: 16.0.0
16 { 0x00, 62, 0 },
17 { 0x01, 218, 62 },
18 { 0x02, 196, 280 },
19 { 0x03, 96, 476 },
20 { 0x04, 113, 572 },
21 { 0x05, 100, 685 },
22 { 0x06, 119, 785 },
23 { 0x07, 91, 904 },
24 { 0x09, 99, 995 },
[all …]
/linux/drivers/w1/slaves/
H A Dw1_ds2780.h16 #define W1_DS2780_READ_DATA 0x69
17 #define W1_DS2780_WRITE_DATA 0x6C
18 #define W1_DS2780_COPY_DATA 0x48
19 #define W1_DS2780_RECALL_DATA 0xB8
20 #define W1_DS2780_LOCK 0x6A
23 /* Register 0x00 Reserved */
24 #define DS2780_STATUS_REG 0x01
25 #define DS2780_RAAC_MSB_REG 0x02
26 #define DS2780_RAAC_LSB_REG 0x03
27 #define DS2780_RSAC_MSB_REG 0x04
[all …]
H A Dw1_ds2781.h14 #define W1_DS2781_READ_DATA 0x69
15 #define W1_DS2781_WRITE_DATA 0x6C
16 #define W1_DS2781_COPY_DATA 0x48
17 #define W1_DS2781_RECALL_DATA 0xB8
18 #define W1_DS2781_LOCK 0x6A
21 /* Register 0x00 Reserved */
22 #define DS2781_STATUS 0x01
23 #define DS2781_RAAC_MSB 0x02
24 #define DS2781_RAAC_LSB 0x03
25 #define DS2781_RSAC_MSB 0x04
[all …]

12345678910>>...31