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/linux/drivers/gpu/drm/amd/include/asic_reg/smuio/
H A Dsmuio_10_0_2_offset.h24 // base address: 0x5a000
25 …SMUIO_MCM_CONFIG 0x0023
26 …ne mmSMUIO_MCM_CONFIG_BASE_IDX 0
27 …IP_DISCOVERY_VERSION 0x0000
29 …IO_SMUIO_PINSTRAP 0x01b1
31 …SCRATCH_REGISTER0 0x01b2
33 …SCRATCH_REGISTER1 0x01b3
35 …SCRATCH_REGISTER2 0x01b4
37 …SCRATCH_REGISTER3 0x01b5
39 …SCRATCH_REGISTER4 0x01b6
[all …]
H A Dsmuio_11_0_6_offset.h27 // base address: 0x5a000
28 …CGTT_ROM_CLK_CTRL0 0x00e4
29 …ne mmCGTT_ROM_CLK_CTRL0_BASE_IDX 0
30 …ROM_INDEX 0x00e5
31 …ne mmROM_INDEX_BASE_IDX 0
32 …ROM_DATA 0x00e6
33 …ne mmROM_DATA_BASE_IDX 0
H A Dsmuio_13_0_3_offset.h29 // base address: 0x5a300
30 …SMUIO_MP_RESET_INTR 0x00c1
32 …SMUIO_SOC_HALT 0x00c2
37 // base address: 0x5a8a0
38 …PWROK_REFCLK_GAP_CYCLES 0x0028
40 …GOLDEN_TSC_INCREMENT_UPPER 0x002b
42 …GOLDEN_TSC_INCREMENT_LOWER 0x002c
44 …GOLDEN_TSC_COUNT_UPPER 0x002d
46 …GOLDEN_TSC_COUNT_LOWER 0x002e
48 …SOC_GOLDEN_TSC_SHADOW_UPPER 0x002f
[all …]
H A Dsmuio_9_0_offset.h27 // base address: 0x5a000
28 …ROM_CNTL 0x0024
29 …ne mmROM_CNTL_BASE_IDX 0
30 …ROM_STATUS 0x0026
31 …ne mmROM_STATUS_BASE_IDX 0
32 …CGTT_ROM_CLK_CTRL0 0x0027
33 …ne mmCGTT_ROM_CLK_CTRL0_BASE_IDX 0
34 …ROM_INDEX 0x0028
35 …ne mmROM_INDEX_BASE_IDX 0
36 …ROM_DATA 0x0029
[all …]
H A Dsmuio_13_0_2_offset.h30 // base address: 0x5a000
31 …SMUSVI0_TEL_PLANE0 0x0004
32 …e regSMUSVI0_TEL_PLANE0_BASE_IDX 0
33 …SMUSVI0_PLANE0_CURRENTVID 0x0014
34 …e regSMUSVI0_PLANE0_CURRENTVID_BASE_IDX 0
35 …SMUIO_MCM_CONFIG 0x0024
36 …e regSMUIO_MCM_CONFIG_BASE_IDX 0
37 …CKSVII2C_IC_CON 0x0040
38 …e regCKSVII2C_IC_CON_BASE_IDX 0
39 …CKSVII2C_IC_TAR 0x0041
[all …]
H A Dsmuio_11_0_0_offset.h27 // base address: 0x5a000
28 …SMUSVI0_TEL_PLANE0 0x0004
29 …ne mmSMUSVI0_TEL_PLANE0_BASE_IDX 0
30 …SMUIO_MCM_CONFIG 0x0024
31 …ne mmSMUIO_MCM_CONFIG_BASE_IDX 0
32 …CKSVII2C_IC_CON 0x0040
33 …ne mmCKSVII2C_IC_CON_BASE_IDX 0
34 …CKSVII2C_IC_TAR 0x0041
35 …ne mmCKSVII2C_IC_TAR_BASE_IDX 0
36 …CKSVII2C_IC_SAR 0x0042
[all …]
H A Dsmuio_13_0_6_offset.h29 // base address: 0x5a300
30 …SMUIO_MP_RESET_INTR 0x00c1
31 …e regSMUIO_MP_RESET_INTR_BASE_IDX 0
32 …SMUIO_SOC_HALT 0x00c2
33 …e regSMUIO_SOC_HALT_BASE_IDX 0
37 // base address: 0x5a8a0
38 …PWROK_REFCLK_GAP_CYCLES 0x0028
40 …GOLDEN_TSC_INCREMENT_UPPER 0x002b
42 …GOLDEN_TSC_INCREMENT_LOWER 0x002c
44 …GOLDEN_TSC_COUNT_UPPER 0x002d
[all …]
H A Dsmuio_14_0_2_offset.h29 // base address: 0x5a8a0
30 …PWROK_REFCLK_GAP_CYCLES 0x0028
32 …GOLDEN_TSC_INCREMENT_UPPER 0x002b
34 …GOLDEN_TSC_INCREMENT_LOWER 0x002c
36 …GOLDEN_TSC_COUNT_UPPER 0x002d
38 …GOLDEN_TSC_COUNT_LOWER 0x002e
40 …SOC_GOLDEN_TSC_SHADOW_UPPER 0x002f
42 …SOC_GOLDEN_TSC_SHADOW_LOWER 0x0030
44 …SOC_GAP_PWROK 0x0031
49 // base address: 0x5aca8
[all …]
/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,msm8996.yaml111 reg = <0x00408000 0x5a000>;
117 reg = <0x00543000 0x6000>;
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_4_0_sdm845.h12 .max_mixer_blendstages = 0xb,
25 .base = 0x0, .len = 0x45c,
28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_7_0_sm8350.h12 .max_mixer_blendstages = 0xb,
23 .base = 0x0, .len = 0x494,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_6_0_sm8250.h12 .max_mixer_blendstages = 0xb,
23 .base = 0x0, .len = 0x494,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_5_0_sm8150.h12 .max_mixer_blendstages = 0xb,
25 .base = 0x0, .len = 0x45c,
28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_9_0_sm8550.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
26 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
34 .base = 0x15000, .len = 0x290,
39 .base = 0x16000, .len = 0x290,
44 .base = 0x17000, .len = 0x290,
49 .base = 0x18000, .len = 0x290,
54 .base = 0x19000, .len = 0x290,
59 .base = 0x1a000, .len = 0x290,
68 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_10_0_sm8650.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
26 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
34 .base = 0x15000, .len = 0x1000,
39 .base = 0x16000, .len = 0x1000,
44 .base = 0x17000, .len = 0x1000,
49 .base = 0x18000, .len = 0x1000,
54 .base = 0x19000, .len = 0x1000,
59 .base = 0x1a000, .len = 0x1000,
68 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_5_1_sc8180x.h12 .max_mixer_blendstages = 0xb,
25 .base = 0x0, .len = 0x45c,
28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_8_1_sm8450.h12 .max_mixer_blendstages = 0xb,
23 .base = 0x0, .len = 0x494,
26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_8_0_sc8280xp.h23 .base = 0x0, .len = 0x494,
26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
34 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
[all …]
H A Ddpu_9_2_x1e80100.h11 .max_mixer_blendstages = 0xb,
22 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
33 .base = 0x15000, .len = 0x290,
38 .base = 0x16000, .len = 0x290,
43 .base = 0x17000, .len = 0x290,
48 .base = 0x18000, .len = 0x290,
53 .base = 0x19000, .len = 0x290,
58 .base = 0x1a000, .len = 0x290,
67 .base = 0x4000, .len = 0x344,
[all …]
/linux/drivers/soc/tegra/cbb/
H A Dtegra234-cbb.c8 * Error types supported by CBB2.0 are:
27 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
28 #define FABRIC_EN_CFG_STATUS_0_0 0x40
29 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
30 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80
31 #define FABRIC_EN_CFG_ADDR_HI_0 0x84
33 #define FABRIC_MN_MASTER_ERR_EN_0 0x200
34 #define FABRIC_MN_MASTER_ERR_FORCE_0 0x204
35 #define FABRIC_MN_MASTER_ERR_STATUS_0 0x208
36 #define FABRIC_MN_MASTER_ERR_OVERFLOW_STATUS_0 0x20c
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-s4.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0x0 0x0>;
30 reg = <0x0 0x1>;
37 reg = <0x0 0x2>;
44 reg = <0x0 0x3>;
66 #clock-cells = <0>;
89 #address-cells = <0>;
91 reg = <0x0 0xfff01000 0 0x1000>,
92 <0x0 0xfff02000 0 0x2000>,
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsdm850-lenovo-yoga-c630.dts44 pinctrl-0 = <&lid_pin_active>, <&mode_pin_active>;
64 reg = <0 0x8c400000 0 0x100000>;
69 reg = <0 0x8c515000 0 0x2000>;
74 reg = <0 0x8c517000 0 0x5a000>;
79 reg = <0 0x8c600000 0 0x1a00000>;
91 pinctrl-0 = <&sw_edp_1p2_en>;
102 #clock-cells = <0>;
139 regulators-0 {
376 reg = <0x70>;
381 pinctrl-0 = <&ec_int_state>;
[all …]
/linux/drivers/interconnect/qcom/
H A Dmsm8953.c105 .qos.prio_level = 0,
106 .qos.areq_prio = 0,
107 .qos.qos_port = 0,
123 .qos.prio_level = 0,
124 .qos.areq_prio = 0,
141 .qos.prio_level = 0,
142 .qos.areq_prio = 0,
159 .qos.prio_level = 0,
160 .qos.areq_prio = 0,
203 .slv_rpm_id = 0,
[all …]
H A Dmsm8937.c106 .mas_rpm_id = 0,
110 .qos.areq_prio = 0,
111 .qos.prio_level = 0,
112 .qos.qos_port = 0,
130 .qos.areq_prio = 0,
131 .qos.prio_level = 0,
150 .qos.areq_prio = 0,
151 .qos.prio_level = 0,
170 .qos.areq_prio = 0,
171 .qos.prio_level = 0,
[all …]
/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_cfg.c22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]

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