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Searched +full:0 +full:x5a000 (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/smuio/
H A Dsmuio_10_0_2_offset.h24 // base address: 0x5a000
25 …SMUIO_MCM_CONFIG 0x0023
26 …ne mmSMUIO_MCM_CONFIG_BASE_IDX 0
27 …IP_DISCOVERY_VERSION 0x0000
29 …IO_SMUIO_PINSTRAP 0x01b1
31 …SCRATCH_REGISTER0 0x01b2
33 …SCRATCH_REGISTER1 0x01b3
35 …SCRATCH_REGISTER2 0x01b4
37 …SCRATCH_REGISTER3 0x01b5
39 …SCRATCH_REGISTER4 0x01b6
[all …]
H A Dsmuio_11_0_6_offset.h27 // base address: 0x5a000
28 …CGTT_ROM_CLK_CTRL0 0x00e4
29 …ne mmCGTT_ROM_CLK_CTRL0_BASE_IDX 0
30 …ROM_INDEX 0x00e5
31 …ne mmROM_INDEX_BASE_IDX 0
32 …ROM_DATA 0x00e6
33 …ne mmROM_DATA_BASE_IDX 0
H A Dsmuio_13_0_3_offset.h29 // base address: 0x5a300
30 …SMUIO_MP_RESET_INTR 0x00c1
32 …SMUIO_SOC_HALT 0x00c2
37 // base address: 0x5a8a0
38 …PWROK_REFCLK_GAP_CYCLES 0x0028
40 …GOLDEN_TSC_INCREMENT_UPPER 0x002b
42 …GOLDEN_TSC_INCREMENT_LOWER 0x002c
44 …GOLDEN_TSC_COUNT_UPPER 0x002d
46 …GOLDEN_TSC_COUNT_LOWER 0x002e
48 …SOC_GOLDEN_TSC_SHADOW_UPPER 0x002f
[all …]
H A Dsmuio_9_0_offset.h27 // base address: 0x5a000
28 …ROM_CNTL 0x0024
29 …ne mmROM_CNTL_BASE_IDX 0
30 …ROM_STATUS 0x0026
31 …ne mmROM_STATUS_BASE_IDX 0
32 …CGTT_ROM_CLK_CTRL0 0x0027
33 …ne mmCGTT_ROM_CLK_CTRL0_BASE_IDX 0
34 …ROM_INDEX 0x0028
35 …ne mmROM_INDEX_BASE_IDX 0
36 …ROM_DATA 0x0029
[all …]
H A Dsmuio_13_0_2_offset.h30 // base address: 0x5a000
31 …SMUSVI0_TEL_PLANE0 0x0004
32 …e regSMUSVI0_TEL_PLANE0_BASE_IDX 0
33 …SMUSVI0_PLANE0_CURRENTVID 0x0014
34 …e regSMUSVI0_PLANE0_CURRENTVID_BASE_IDX 0
35 …SMUIO_MCM_CONFIG 0x0024
36 …e regSMUIO_MCM_CONFIG_BASE_IDX 0
37 …CKSVII2C_IC_CON 0x0040
38 …e regCKSVII2C_IC_CON_BASE_IDX 0
39 …CKSVII2C_IC_TAR 0x0041
[all …]
H A Dsmuio_11_0_0_offset.h27 // base address: 0x5a000
28 …SMUSVI0_TEL_PLANE0 0x0004
29 …ne mmSMUSVI0_TEL_PLANE0_BASE_IDX 0
30 …SMUIO_MCM_CONFIG 0x0024
31 …ne mmSMUIO_MCM_CONFIG_BASE_IDX 0
32 …CKSVII2C_IC_CON 0x0040
33 …ne mmCKSVII2C_IC_CON_BASE_IDX 0
34 …CKSVII2C_IC_TAR 0x0041
35 …ne mmCKSVII2C_IC_TAR_BASE_IDX 0
36 …CKSVII2C_IC_SAR 0x0042
[all …]
H A Dsmuio_13_0_6_offset.h29 // base address: 0x5a300
30 …SMUIO_MP_RESET_INTR 0x00c1
31 …e regSMUIO_MP_RESET_INTR_BASE_IDX 0
32 …SMUIO_SOC_HALT 0x00c2
33 …e regSMUIO_SOC_HALT_BASE_IDX 0
37 // base address: 0x5a8a0
38 …PWROK_REFCLK_GAP_CYCLES 0x0028
40 …GOLDEN_TSC_INCREMENT_UPPER 0x002b
42 …GOLDEN_TSC_INCREMENT_LOWER 0x002c
44 …GOLDEN_TSC_COUNT_UPPER 0x002d
[all …]
H A Dsmuio_14_0_2_offset.h29 // base address: 0x5a8a0
30 …PWROK_REFCLK_GAP_CYCLES 0x0028
32 …GOLDEN_TSC_INCREMENT_UPPER 0x002b
34 …GOLDEN_TSC_INCREMENT_LOWER 0x002c
36 …GOLDEN_TSC_COUNT_UPPER 0x002d
38 …GOLDEN_TSC_COUNT_LOWER 0x002e
40 …SOC_GOLDEN_TSC_SHADOW_UPPER 0x002f
42 …SOC_GOLDEN_TSC_SHADOW_LOWER 0x0030
44 …SOC_GAP_PWROK 0x0031
49 // base address: 0x5aca8
[all …]
/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,msm8996.yaml111 reg = <0x00408000 0x5a000>;
117 reg = <0x00543000 0x6000>;
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_8_1_sm8450.h12 .max_mixer_blendstages = 0xb,
23 .base = 0x0, .len = 0x494,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_9_1_sar2130p.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
32 .base = 0x15000, .len = 0x290,
36 .base = 0x16000, .len = 0x290,
40 .base = 0x17000, .len = 0x290,
44 .base = 0x18000, .len = 0x290,
48 .base = 0x19000, .len = 0x290,
52 .base = 0x1a000, .len = 0x290,
60 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_9_0_sm8550.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
32 .base = 0x15000, .len = 0x290,
36 .base = 0x16000, .len = 0x290,
40 .base = 0x17000, .len = 0x290,
44 .base = 0x18000, .len = 0x290,
48 .base = 0x19000, .len = 0x290,
52 .base = 0x1a000, .len = 0x290,
60 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_8_4_sa8775p.h11 .max_mixer_blendstages = 0xb,
22 .base = 0x0, .len = 0x494,
24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
25 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_8_0_sc8280xp.h23 .base = 0x0, .len = 0x494,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
[all …]
H A Ddpu_9_2_x1e80100.h11 .max_mixer_blendstages = 0xb,
22 .base = 0, .len = 0x494,
24 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
31 .base = 0x15000, .len = 0x290,
35 .base = 0x16000, .len = 0x290,
39 .base = 0x17000, .len = 0x290,
43 .base = 0x18000, .len = 0x290,
47 .base = 0x19000, .len = 0x290,
51 .base = 0x1a000, .len = 0x290,
59 .base = 0x4000, .len = 0x344,
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsdm850-lenovo-yoga-c630.dts44 pinctrl-0 = <&lid_pin_active>, <&mode_pin_active>;
64 reg = <0 0x8c400000 0 0x100000>;
69 reg = <0 0x8c515000 0 0x2000>;
74 reg = <0 0x8c517000 0 0x5a000>;
79 reg = <0 0x8c600000 0 0x1a00000>;
91 pinctrl-0 = <&sw_edp_1p2_en>;
102 #clock-cells = <0>;
139 regulators-0 {
371 reg = <0x70>;
376 pinctrl-0 = <&ec_int_state>;
[all …]
/linux/drivers/interconnect/qcom/
H A Dmsm8996.c50 .qos.qos_port = 0,
111 .qos.qos_port = 0,
124 .qos.areq_prio = 0,
125 .qos.prio_level = 0,
158 .qos.areq_prio = 0,
159 .qos.prio_level = 0,
190 .mas_rpm_id = 0,
194 .qos.areq_prio = 0,
195 .qos.prio_level = 0,
196 .qos.qos_port = 0,
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-msm8909.c52 { P_XO, 0 },
64 .offset = 0x21000,
67 .enable_reg = 0x45000,
68 .enable_mask = BIT(0),
80 .offset = 0x21000,
94 .l_reg = 0x20004,
95 .m_reg = 0x20008,
96 .n_reg = 0x2000c,
97 .config_reg = 0x20010,
98 .mode_reg = 0x20000,
[all …]
H A Dgcc-msm8916.c45 .l_reg = 0x21004,
46 .m_reg = 0x21008,
47 .n_reg = 0x2100c,
48 .config_reg = 0x21010,
49 .mode_reg = 0x21000,
50 .status_reg = 0x2101c,
63 .enable_reg = 0x45000,
64 .enable_mask = BIT(0),
76 .l_reg = 0x20004,
77 .m_reg = 0x20008,
[all …]
H A Dgcc-msm8976.c56 .l_reg = 0x21004,
57 .m_reg = 0x21008,
58 .n_reg = 0x2100c,
59 .config_reg = 0x21014,
60 .mode_reg = 0x21000,
61 .status_reg = 0x2101c,
74 .enable_reg = 0x45000,
75 .enable_mask = BIT(0),
89 .l_reg = 0x4a004,
90 .m_reg = 0x4a008,
[all …]
H A Dgcc-msm8939.c53 .l_reg = 0x21004,
54 .m_reg = 0x21008,
55 .n_reg = 0x2100c,
56 .config_reg = 0x21010,
57 .mode_reg = 0x21000,
58 .status_reg = 0x2101c,
71 .enable_reg = 0x45000,
72 .enable_mask = BIT(0),
84 .l_reg = 0x20004,
85 .m_reg = 0x20008,
[all …]
/linux/drivers/net/ethernet/adaptec/
H A Dstarfire.c78 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
105 static int rx_copybreak /* = 0 */;
172 module_param(max_interrupt_work, int, 0);
173 module_param(mtu, int, 0);
174 module_param(debug, int, 0);
175 module_param(rx_copybreak, int, 0);
176 module_param(intr_latency, int, 0);
177 module_param(small_frames, int, 0);
178 module_param(enable_hw_cksum, int, 0);
181 MODULE_PARM_DESC(debug, "Debug level (0-6)");
[all …]