Lines Matching +full:0 +full:x5a000
78 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
105 static int rx_copybreak /* = 0 */;
172 module_param(max_interrupt_work, int, 0);
173 module_param(mtu, int, 0);
174 module_param(debug, int, 0);
175 module_param(rx_copybreak, int, 0);
176 module_param(intr_latency, int, 0);
177 module_param(small_frames, int, 0);
178 module_param(enable_hw_cksum, int, 0);
181 MODULE_PARM_DESC(debug, "Debug level (0-6)");
184 MODULE_PARM_DESC(small_frames, "Maximum size of receive frames that bypass interrupt latency (0,64,…
185 MODULE_PARM_DESC(enable_hw_cksum, "Enable/disable hardware cksum support (0/1)");
216 For transmit this driver uses type 0/1 transmit descriptors (depending
277 CH_6915 = 0,
281 { PCI_VDEVICE(ADAPTEC, 0x6915), CH_6915 },
282 { 0, }
304 PCIDeviceConfig=0x50040, GenCtrl=0x50070, IntrTimerCtrl=0x50074,
305 IntrClear=0x50080, IntrStatus=0x50084, IntrEnable=0x50088,
306 MIICtrl=0x52000, TxStationAddr=0x50120, EEPROMCtrl=0x51000,
307 GPIOCtrl=0x5008C, TxDescCtrl=0x50090,
308 TxRingPtr=0x50098, HiPriTxRingPtr=0x50094, /* Low and High priority. */
309 TxRingHiAddr=0x5009C, /* 64 bit address extension. */
310 TxProducerIdx=0x500A0, TxConsumerIdx=0x500A4,
311 TxThreshold=0x500B0,
312 CompletionHiAddr=0x500B4, TxCompletionAddr=0x500B8,
313 RxCompletionAddr=0x500BC, RxCompletionQ2Addr=0x500C0,
314 CompletionQConsumerIdx=0x500C4, RxDMACtrl=0x500D0,
315 RxDescQCtrl=0x500D4, RxDescQHiAddr=0x500DC, RxDescQAddr=0x500E0,
316 RxDescQIdx=0x500E8, RxDMAStatus=0x500F0, RxFilterMode=0x500F4,
317 TxMode=0x55000, VlanType=0x55064,
318 PerfFilterTable=0x56000, HashTable=0x56100,
319 TxGfpMem=0x58000, RxGfpMem=0x5a000,
328 IntrLinkChange=0xf0000000, IntrStatsMax=0x08000000,
329 IntrAbnormalSummary=0x02000000, IntrGeneralTimer=0x01000000,
330 IntrSoftware=0x800000, IntrRxComplQ1Low=0x400000,
331 IntrTxComplQLow=0x200000, IntrPCI=0x100000,
332 IntrDMAErr=0x080000, IntrTxDataLow=0x040000,
333 IntrRxComplQ2Low=0x020000, IntrRxDescQ1Low=0x010000,
334 IntrNormalSummary=0x8000, IntrTxDone=0x4000,
335 IntrTxDMADone=0x2000, IntrTxEmpty=0x1000,
336 IntrEarlyRxQ2=0x0800, IntrEarlyRxQ1=0x0400,
337 IntrRxQ2Done=0x0200, IntrRxQ1Done=0x0100,
338 IntrRxGFPDead=0x80, IntrRxDescQ2Low=0x40,
339 IntrNoTxCsum=0x20, IntrTxBadID=0x10,
340 IntrHiPriTxBadID=0x08, IntrRxGfp=0x04,
341 IntrTxGfp=0x02, IntrPCIPad=0x01,
345 IntrNormalMask=0xff00, IntrAbnormalMask=0x3ff00fe,
350 AcceptBroadcast=0x04, AcceptAllMulticast=0x02, AcceptAll=0x01,
351 AcceptMulticast=0x10, PerfectFilter=0x40, HashFilter=0x30,
352 PerfectFilterVlan=0x80, MinVLANPrio=0xE000, VlanMode=0x0200,
353 WakeupOnGFP=0x0800,
358 MiiSoftReset=0x8000, MIILoopback=0x4000,
359 TxFlowEnable=0x0800, RxFlowEnable=0x0400,
360 PadEnable=0x04, FullDuplex=0x02, HugeFrame=0x01,
365 TxDescSpaceUnlim=0x00, TxDescSpace32=0x10, TxDescSpace64=0x20,
366 TxDescSpace128=0x30, TxDescSpace256=0x40,
367 TxDescType0=0x00, TxDescType1=0x01, TxDescType2=0x02,
368 TxDescType3=0x03, TxDescType4=0x04,
369 TxNoDMACompletion=0x08,
370 TxDescQAddr64bit=0x80, TxDescQAddr32bit=0,
377 RxBufferLenShift=16, RxMinDescrThreshShift=0,
378 RxPrefetchMode=0x8000, RxVariableQ=0x2000,
379 Rx2048QEntries=0x4000, Rx256QEntries=0,
380 RxDescAddr64bit=0x1000, RxDescAddr32bit=0,
381 RxDescQAddr64bit=0x0100, RxDescQAddr32bit=0,
382 RxDescSpace4=0x000, RxDescSpace8=0x100,
383 RxDescSpace16=0x200, RxDescSpace32=0x300,
384 RxDescSpace64=0x400, RxDescSpace128=0x500,
385 RxConsumerWrEn=0x80,
390 RxReportBadFrames=0x80000000, RxDMAShortFrames=0x40000000,
391 RxDMABadFrames=0x20000000, RxDMACrcErrorFrames=0x10000000,
392 RxDMAControlFrame=0x08000000, RxDMAPauseFrame=0x04000000,
393 RxChecksumIgnore=0, RxChecksumRejectTCPUDP=0x02000000,
394 RxChecksumRejectTCPOnly=0x01000000,
395 RxCompletionQ2Enable=0x800000,
396 RxDMAQ2Disable=0, RxDMAQ2FPOnly=0x100000,
397 RxDMAQ2SmallPkt=0x200000, RxDMAQ2HighPrio=0x300000,
398 RxDMAQ2NonIP=0x400000,
399 RxUseBackupQueue=0x080000, RxDMACRC=0x040000,
401 RxBurstSizeShift=0,
406 RxComplQAddr64bit=0x80, RxComplQAddr32bit=0,
407 RxComplProducerWrEn=0x40,
408 RxComplType0=0x00, RxComplType1=0x10,
409 RxComplType2=0x20, RxComplType3=0x30,
410 RxComplThreshShift=0,
415 TxComplQAddr64bit=0x80, TxComplQAddr32bit=0,
416 TxComplProducerWrEn=0x40,
417 TxComplIntrStatus=0x20,
418 CommonQueueMode=0x10,
419 TxComplThreshShift=0,
424 RxEnable=0x05, TxEnable=0x0a,
425 RxGFPEnable=0x10, TxGFPEnable=0x20,
430 Timer10X=0x800, EnableIntrMasking=0x60, SmallFrameBypass=0x100,
431 SmallFrame64=0, SmallFrame128=0x200, SmallFrame256=0x400, SmallFrame512=0x600,
432 IntrLatencyMask=0x1f,
467 RxOK=0x20000000, RxFIFOErr=0x10000000, RxBufQ2=0x08000000,
493 TxDescID=0xB0000000,
494 TxCRCEn=0x01000000, TxDescIntr=0x08000000,
495 TxRingWrap=0x04000000, TxCalTCP=0x02000000,
499 #if 0
593 return 0; in netdev_vlan_rx_add_vid()
608 return 0; in netdev_vlan_rx_kill_vid()
645 ioaddr = pci_resource_start(pdev, 0); in starfire_init_one()
646 io_size = pci_resource_len(pdev, 0); in starfire_init_one()
647 if (!ioaddr || ((pci_resource_flags(pdev, 0) & IORESOURCE_MEM) == 0)) { in starfire_init_one()
691 for (i = 0; i < 6; i++) in starfire_init_one()
697 for (i = 0; i < 0x20; i++) in starfire_init_one()
706 writel(0, base + TxMode); in starfire_init_one()
711 while (--boguscnt > 0) { in starfire_init_one()
713 if ((readl(base + PCIDeviceConfig) & 1) == 0) in starfire_init_one()
716 if (boguscnt == 0) in starfire_init_one()
732 np->mii_if.phy_id_mask = 0x1f; in starfire_init_one()
733 np->mii_if.reg_num_mask = 0x1f; in starfire_init_one()
743 if (small_frames > 0) { in starfire_init_one()
780 int phy, phy_idx = 0; in starfire_init_one()
782 for (phy = 0; phy < 32 && phy_idx < PHY_CNT; phy++) { in starfire_init_one()
786 while (--boguscnt > 0) in starfire_init_one()
787 if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0) in starfire_init_one()
789 if (boguscnt == 0) { in starfire_init_one()
794 if (mii_status != 0) { in starfire_init_one()
805 if (np->phy_cnt > 0) in starfire_init_one()
806 np->mii_if.phy_id = np->phys[0]; in starfire_init_one()
808 memset(&np->mii_if, 0, sizeof(np->mii_if)); in starfire_init_one()
813 return 0; in starfire_init_one()
834 } while ((result & 0xC0000000) != 0x80000000 && --boguscnt > 0); in mdio_read()
835 if (boguscnt == 0) in mdio_read()
836 return 0; in mdio_read()
837 if ((result & 0xffff) == 0xffff) in mdio_read()
838 return 0; in mdio_read()
839 return result & 0xffff; in mdio_read()
870 writel(0, ioaddr + GenCtrl); in netdev_open()
906 (0 << RxMinDescrThreshShift) | in netdev_open()
915 (0 << RxEarlyIntThreshShift) | in netdev_open()
922 (0 << TxPadLenShift) | in netdev_open()
937 (0 << RxComplThreshShift), in netdev_open()
944 for (i = 0; i < 6; i++) in netdev_open()
948 writew(0, ioaddr + PerfFilterTable); in netdev_open()
949 writew(0, ioaddr + PerfFilterTable + 4); in netdev_open()
950 writew(0, ioaddr + PerfFilterTable + 8); in netdev_open()
956 writew(be16_to_cpu(eaddrs[0]), setup_frm); setup_frm += 8; in netdev_open()
978 np->mii_if.advertising = mdio_read(dev, np->phys[0], MII_ADVERTISE); in netdev_open()
982 writel(0x0f00ff00, ioaddr + GPIOCtrl); in netdev_open()
990 writel(0x00800000 | readl(ioaddr + PCIDeviceConfig), in netdev_open()
1022 fw_rx_data = (const __be32 *)&fw_rx->data[0]; in netdev_open()
1023 fw_tx_data = (const __be32 *)&fw_tx->data[0]; in netdev_open()
1028 for (i = 0; i < rx_size; i++) in netdev_open()
1030 for (i = 0; i < tx_size; i++) in netdev_open()
1060 mdio_write(dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising); in check_duplex()
1061 mdio_write(dev, np->phys[0], MII_BMCR, BMCR_RESET); in check_duplex()
1063 while (--silly_count && mdio_read(dev, np->phys[0], MII_BMCR) & BMCR_RESET) in check_duplex()
1070 reg0 = mdio_read(dev, np->phys[0], MII_BMCR); in check_duplex()
1085 mdio_write(dev, np->phys[0], MII_BMCR, reg0); in check_duplex()
1124 np->cur_rx = np->cur_tx = np->reap_tx = 0; in init_ring()
1125 np->dirty_rx = np->dirty_tx = np->rx_done = np->tx_done = 0; in init_ring()
1130 for (i = 0; i < RX_RING_SIZE; i++) { in init_ring()
1152 np->rx_ring[i].rxaddr = 0; in init_ring()
1154 np->rx_info[i].mapping = 0; in init_ring()
1160 for (i = 0; i < DONE_Q_SIZE; i++) { in init_ring()
1161 np->rx_done_q[i].status = 0; in init_ring()
1162 np->tx_done_q[i].status = 0; in init_ring()
1165 for (i = 0; i < TX_RING_SIZE; i++) in init_ring()
1166 memset(&np->tx_info[i], 0, sizeof(np->tx_info[i])); in init_ring()
1196 for (i = 0; i < skb_num_frags(skb); i++) { in start_tx()
1197 int wrap_ring = 0; in start_tx()
1200 if (i == 0) { in start_tx()
1209 np->reap_tx = 0; in start_tx()
1244 entry = 0; in start_tx()
1251 if (np->cur_tx % (TX_RING_SIZE / 2) == 0) in start_tx()
1272 if (i > 0) { in start_tx()
1276 np->tx_info[entry].mapping = 0; in start_tx()
1301 int handled = 0; in intr_handler()
1310 if (intr_status == 0 || intr_status == (u32) -1) in intr_handler()
1346 while ((tx_status = le32_to_cpu(np->tx_done_q[np->tx_done].status)) != 0) { in intr_handler()
1350 if ((tx_status & 0xe0000000) == 0xa0000000) { in intr_handler()
1352 } else if ((tx_status & 0xe0000000) == 0x80000000) { in intr_handler()
1353 u16 entry = (tx_status & 0x7fff) / sizeof(starfire_tx_desc); in intr_handler()
1360 np->tx_info[entry].mapping = 0; in intr_handler()
1365 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in intr_handler()
1377 np->tx_done_q[np->tx_done].status = 0; in intr_handler()
1400 if (--boguscnt < 0) { in intr_handler()
1424 int retcode = 0; in __netdev_rx()
1427 while ((desc_status = le32_to_cpu(np->rx_done_q[np->rx_done].status)) != 0) { in __netdev_rx()
1445 if (*quota <= 0) { /* out of rx quota */ in __netdev_rx()
1452 entry = (desc_status >> 16) & 0x7ff; in __netdev_rx()
1476 np->rx_info[entry].mapping = 0; in __netdev_rx()
1492 if (le16_to_cpu(desc->status2) & 0x0100) { in __netdev_rx()
1505 else if (le16_to_cpu(desc->status2) & 0x0040) { in __netdev_rx()
1511 if (le16_to_cpu(desc->status2) & 0x0200) { in __netdev_rx()
1526 desc->status = 0; in __netdev_rx()
1530 if (*quota == 0) { /* out of rx quota */ in __netdev_rx()
1582 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) { in refill_rx_ring()
1603 if (entry >= 0) in refill_rx_ring()
1617 mdio_read(dev, np->phys[0], MII_BMCR); in netdev_media_change()
1618 mdio_read(dev, np->phys[0], MII_BMSR); in netdev_media_change()
1620 reg0 = mdio_read(dev, np->phys[0], MII_BMCR); in netdev_media_change()
1621 reg1 = mdio_read(dev, np->phys[0], MII_BMSR); in netdev_media_change()
1627 reg4 = mdio_read(dev, np->phys[0], MII_ADVERTISE); in netdev_media_change()
1628 reg5 = mdio_read(dev, np->phys[0], MII_LPA); in netdev_media_change()
1634 np->mii_if.full_duplex = 0; in netdev_media_change()
1636 np->speed100 = 0; in netdev_media_change()
1639 np->speed100 = 0; in netdev_media_change()
1640 np->mii_if.full_duplex = 0; in netdev_media_change()
1647 np->speed100 = 0; in netdev_media_change()
1651 np->mii_if.full_duplex = 0; in netdev_media_change()
1716 dev->stats.tx_bytes = readl(ioaddr + 0x57010); in get_stats()
1717 dev->stats.rx_bytes = readl(ioaddr + 0x57044); in get_stats()
1718 dev->stats.tx_packets = readl(ioaddr + 0x57000); in get_stats()
1720 readl(ioaddr + 0x57024) + readl(ioaddr + 0x57028); in get_stats()
1721 dev->stats.tx_window_errors = readl(ioaddr + 0x57018); in get_stats()
1723 readl(ioaddr + 0x57004) + readl(ioaddr + 0x57008); in get_stats()
1727 writew(0, ioaddr + RxDMAStatus); in get_stats()
1728 dev->stats.rx_crc_errors = readl(ioaddr + 0x5703C); in get_stats()
1729 dev->stats.rx_frame_errors = readl(ioaddr + 0x57040); in get_stats()
1730 dev->stats.rx_length_errors = readl(ioaddr + 0x57058); in get_stats()
1731 dev->stats.rx_missed_errors = readl(ioaddr + 0x5707C); in get_stats()
1742 int vlan_count = 0; in set_vlan_mode()
1754 writew(0, filter_addr); in set_vlan_mode()
1789 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 8; in set_rx_mode()
1794 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4; in set_rx_mode()
1805 memset(mc_filter, 0, sizeof(mc_filter)); in set_rx_mode()
1818 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4; in set_rx_mode()
1822 for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++) in set_rx_mode()
1833 return 0; in check_if_running()
1850 return 0; in get_link_ksettings()
1911 if ((cmd == SIOCSMIIREG) && (data->phy_id == np->phys[0])) in netdev_ioctl()
1936 writel(0, ioaddr + IntrEnable); in netdev_close()
1939 writel(0, ioaddr + GenCtrl); in netdev_close()
1945 for (i = 0; i < 8 /* TX_RING_SIZE is huge! */; i++) in netdev_close()
1953 for (i = 0; i < 8 /* RX_RING_SIZE */; i++) { in netdev_close()
1962 for (i = 0; i < RX_RING_SIZE; i++) { in netdev_close()
1963 np->rx_ring[i].rxaddr = cpu_to_dma(0xBADF00D0); /* An invalid address. */ in netdev_close()
1971 np->rx_info[i].mapping = 0; in netdev_close()
1973 for (i = 0; i < TX_RING_SIZE; i++) { in netdev_close()
1979 np->tx_info[i].mapping = 0; in netdev_close()
1984 return 0; in netdev_close()
1996 return 0; in starfire_suspend()
2008 return 0; in starfire_resume()